JP2006180260A - Image reader, image reading method, program making computer implement the method, and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image forming apparatus capable of reading an image of high picture quality. <P>SOLUTION: In the image reader, a system control unit 1 includes an SSCG section 140 which generates a spectrum spread clock and a timing circuit 112 which generates a reference clock to control the SSCG section 140. A read unit 2 includes a CCD 111 which converts the light image of a document into an electric signal, an A-D conversion section 119 which converts the analog information of the electric signal acquired by the CCD 111 into digital information, and a pulse motor 108 which moves the CCD 111 and an optical system in a vertical scanning direction. The pulse motor 108 is driven by a reference clock generated by the timing circuit 112 and the CCD 111 and the A-D conversion section 119 are driven by a spectrum spread clock generated by the SSCG section 140. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image reading apparatus, an image reading method, a program for causing a computer to execute the method, and an image forming apparatus.

  Conventionally, in an image reading apparatus, when a spread spectrum generator is provided and a CCD or analog processing drive clock is modulated by a spread spectrum clock (SSCG clock), periodic noise is generated in an image read by the waveform shape of a signal to be sampled. May occur. In order to solve this, a technique has been devised in which the timing circuit is divided into an analog part and a digital part, the digital part uses a spread clock, and the analog part uses a reference clock (non-SSCG clock). Reference 1).

JP-A-2001-094734

  However, according to the technique of Patent Document 1, since the clock input to the timing generation means of the digital signal processing system uses a spread spectrum clock, the resonance reduction peculiar to the motor drive is reduced by the low frequency fluctuation due to the SSCG modulation frequency. There was a problem that occurred.

  In addition, when the SSCG clock is used for the scanning drive means, a resonance phenomenon may occur due to a low frequency fluctuation caused by the SSCG modulation frequency. When a three-line CCD is used, there is a problem that the reading position accuracy deteriorates. there were.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an image reading apparatus capable of preventing the occurrence of a resonance phenomenon peculiar to motor driving due to low frequency fluctuations caused by the SSCG modulation frequency and reading a clear image. It is to be.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 is an image reading apparatus, which photoelectrically converts a light image generated by illuminating a document image by an optical system. A / D conversion means for converting the analog signal converted by the photoelectric conversion means into a digital signal, scan driving means for relatively moving the original and the optical system to scan in the sub-scanning direction, A first drive means for driving the photoelectric conversion means and the A / D conversion means with a clock, a second drive means for driving the scan drive means with a clock, and a spread spectrum clock to the first drive means Generating timing to drive the photoelectric conversion means and the A / D conversion means, and supply a reference clock to the second driving means to drive the scanning driving means; Characterized by comprising.

  According to a second aspect of the present invention, in the image reading apparatus according to the first aspect, the timing generating means has an internal PLL (Phase Locked Loop) circuit, and the spread spectrum is supplied to the first driving means. The clock is generated by a multiplied clock from the internal PLL circuit.

  According to a third aspect of the present invention, in the image reading apparatus according to the first or second aspect, a spread spectrum clock is externally provided on a clock supply route from the timing generating unit to the first driving unit. An external spread spectrum insertion means for insertion is provided.

  According to a fourth aspect of the present invention, in the image reading apparatus according to the second aspect, the timing generation unit further includes the timing on a clock supply route from the timing generation unit to the first driving unit. Before the input to the internal PLL circuit of the generating means, it has an output means for outputting to the outside, and an input means for inputting to the internal PLL circuit from the outside.

  According to a fifth aspect of the present invention, in the image reading apparatus according to any one of the first to fourth aspects, the timing generating means is controlled by serial data, and the second driving means is The reference clock generated by the timing generation means is supplied as the serial data.

  According to a sixth aspect of the present invention, in the image reading device according to any one of the first to fifth aspects, the first driving means is a CCD driver, and the second driving means is a motor. It is a driver 117.

  According to a seventh aspect of the present invention, in the image reading apparatus according to any one of the second to sixth aspects, the timing generating unit is set to the second driving unit after a power ON reset of the timing generating unit. The clock generation reset is released, and after the stable operation of the internal PLL circuit, the clock generation reset to the first driving means is released.

  According to an eighth aspect of the present invention, in the image reading apparatus according to the seventh aspect, the timing generation unit starts a spread spectrum modulation operation after releasing the reset to the first driving unit. To do.

  According to a ninth aspect of the present invention, in the image reading apparatus according to any one of the first to eighth aspects, the photoelectric conversion means has a plurality of line CCDs including a three-line color CCD. Features.

  The invention according to claim 10 is an image reading method, wherein a photoelectric conversion step of photoelectrically converting a light image generated by illuminating a document image by an optical system, and an analog signal converted by the photoelectric conversion step A / D conversion step for converting the signal into a digital signal, a scanning drive step for relatively moving the original and the optical system to scan in the sub-scanning direction, photoelectric conversion in the photoelectric conversion step, and the A / D A first driving step for driving A / D conversion in the D conversion step with a clock; a second driving step for driving scanning in the scan driving step with a clock; and the photoelectric conversion in the first driving step. And a timing signal generation step of supplying a spread spectrum clock for performing A / D conversion and supplying a reference clock to be scanned in the second driving step. .

  The invention according to claim 11 is a program that causes a computer to execute the image reading method according to claim 10.

  According to a twelfth aspect of the present invention, there is provided an image forming apparatus comprising: a photoelectric conversion unit that photoelectrically converts a light image generated by illuminating a document image by an optical system; and an analog signal converted by the photoelectric conversion unit. An A / D conversion means for converting the signal into a digital signal, a scanning drive means for relatively moving the original and the optical system to scan in the sub-scanning direction, the photoelectric conversion means and the A / D conversion means. A first driving means for driving with a clock; a second driving means for driving the scanning driving means with a clock; and a spread spectrum clock to the first driving means to supply the photoelectric conversion means and the A / A timing generating unit that drives a D conversion unit and supplies a reference clock to the second driving unit to drive the scanning driving unit; and the image reading unit Characterized in that and an image output means for outputting the image read by the location.

  According to the first aspect of the invention, in general, an image reading apparatus uses a number of clocks such as a transfer clock × 2, a reset clock, a clamp clock, and a final stage clock to drive a CCD as a photoelectric conversion means. Therefore, harmonics of the fundamental frequency component of the high-speed drive clock (several MHz to several tens of MHz) are generated. In the present invention, at least the photoelectric conversion means (CCD unit) and the A / D conversion means are driven with a spread spectrum clock (SSCG clock), thereby producing an effect of reducing EMI (electromagnetic interference). Further, since the level of the radiated electromagnetic wave is lowered, the risk of malfunction of other nearby devices can be reduced. In addition, since the optical system is driven as the scanning drive means, the clock to the second drive means (for example, the pulse motor driver 117) can be set to a low speed (several KHz to several tens KHz), and the fall can be blunted. The level of radiated electromagnetic waves can be made very low so as not to cause problems. In the present invention, since the reference clock (non-SSCG clock) is supplied to the scanning drive means, it is possible to prevent the resonance phenomenon peculiar to the motor drive from occurring due to the low frequency fluctuation caused by the SSCG modulation frequency. When the SSCG clock is used for the scanning drive means, when a three-line CCD is used due to a resonance phenomenon caused by a low frequency fluctuation due to the modulation frequency of the SSCG, the reading position accuracy deteriorates. The phenomenon can be prevented. In addition, regarding image processing, the position accuracy of determining areas for automatic document color determination (black determination, gray determination, etc.) and automatic image separation (character determination, halftone determination) may deteriorate, causing abnormal images due to poor determination. Can reduce sex. Further, the present invention can reduce the cost because the clock can be supplied to the signal processing unit including the photoelectric conversion means that requires the SSCG clock by one timing generation means and the scan driving means that requires the reference clock. There is an effect that can be.

  Further, according to the invention according to claim 2, since the multiplier circuit of the internal PLL circuit that is not a method of integrating the gate delay amount is used, accurate phase adjustment and pulse width adjustment of the drive clock to the photoelectric conversion means can be performed. There is an effect that it becomes possible.

  According to the invention of claim 3, there is an effect that an external SSCG device for supplying the SSCG clock to the first driving means can be connected.

  According to the fourth aspect of the present invention, there is an effect that the frequency range of SSCG is not increased by taking out the clock from the front of the internal PLL circuit.

  Further, according to the invention of claim 5, serial communication is possible without waiting for the lock time of the internal PLL circuit, so that the waiting time until the scanning operation after transmitting the motor speed profile data can be extremely shortened. There is an effect.

  According to the invention of claim 6, since the CCD is a high-capacity load, clocks are supplied by a plurality of CCD drivers. By using this clock as the SSCG clock, radiation noise can be greatly reduced. . In addition, since there is almost no radiation noise due to the drive clock of the motor driver 117, it is possible to increase the reading position accuracy and to prevent the resonance phenomenon by adopting a configuration that operates with the reference clock. .

  According to the seventh aspect of the invention, as a reset procedure after the power is turned on, the reset of the second driving means is reset by separating the reset of the clock of the first driving means and the clock of the second driving means. Since the serial communication that operates with the second drive means is possible without waiting for the lock time of the internal PLL circuit later, the speed profile data of the motor drive can be sent without waiting time. .

  According to the eighth aspect of the present invention, the reset release of the first driving means is after the maximum lock time of the internal PLL circuit, and the timing shift caused by the input of the spread clock by SSCG before the reset release. It is possible to prevent one clock shift generated in the above.

  According to the ninth aspect of the invention, in particular, the 3-line CCD has RGB line intervals and the reading position is different for each color. Therefore, the speed fluctuation level applied to each RGB image data at the same document position is different. Therefore, unlike reading when there is no speed fluctuation, an erroneous determination of document color determination or image separation occurs, but this phenomenon can be prevented.

  According to the tenth aspect of the present invention, EMI (electromagnetic interference) can be reduced by driving with a spread spectrum clock (SSCG) in the photoelectric conversion step and the A / D conversion step. Since the level is lowered, the risk of malfunction of other nearby devices can be reduced. Further, in the scanning driving process, it is possible to make the clock to the driving means for driving the optical system, for example, a pulse motor driver 117 slow, and to slow down the falling, so that the level of radiated electromagnetic waves is extremely low. The effect is that it can be lowered to prevent problems. In addition, since a reference clock (non-SSCG clock) is supplied in the scan driving process, it is possible to prevent a resonance phenomenon peculiar to motor driving from occurring due to a low-frequency fluctuation due to the modulation frequency of SSCG. When the SSCG clock is used in the scan driving process, the resonance phenomenon occurs due to the low frequency fluctuation due to the modulation frequency of the SSCG, so that the read position accuracy is deteriorated when the 3-line CCD is used. Deterioration phenomenon can be prevented. In addition, regarding image processing, the position accuracy of determining areas for automatic document color determination (black determination, gray determination, etc.) and automatic image separation (character determination, halftone determination) may deteriorate, causing abnormal images due to poor determination. There is an effect that the sex can be reduced.

  Further, according to the invention of claim 11, there is an effect that the computer can execute the image reading method described in claim 10.

  Further, according to the invention of claim 12, it is possible to provide an image forming apparatus provided with the image reading apparatus described in claim 1.

(1. Embodiment)
Exemplary embodiments of an image reading apparatus, an image reading method, a program for causing a computer to execute the method, and an image forming apparatus according to the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 1-1 is a functional block diagram of an image reading apparatus in the image forming apparatus according to the embodiment of the present invention. The image reading apparatus includes a system control unit 1 that controls the whole and a reading unit 2 that is controlled by the system control unit 1 and reads a document.

  The system control unit 1 includes an SSCG unit 140 that generates a spread spectrum clock and a timing circuit 112 that generates a reference clock and controls the SSCG unit 140.

  The reading unit 2 includes a CCD 111 that converts an optical image of a document irradiated by the optical system into analog information, an A / D conversion unit 119 that converts analog information acquired by the CCD 111 into digital information, and the CCD 111 and the optical system. And a pulse motor 108 that moves in the sub-scanning direction.

  In the image reading apparatus in the image forming apparatus according to the embodiment of the present invention, the pulse motor 108 is driven by the reference clock generated by the timing circuit 112, and the CCD 111 and the A / D converter 119 are driven by the spread spectrum clock generated by the SSCG unit 140. Is controlled by the timing circuit 112.

  With this configuration, at least the CCD portion and the A / D conversion portion are driven by the spread spectrum clock, so that EMI (electromagnetic interference) can be reduced. On the other hand, since a low-speed (several KHz to several tens KHz) reference clock is supplied to the pulse motor driver 117 as means for moving the optical system, the rise and fall can be blunted and the level of radiated electromagnetic waves is very high. In addition, it is possible to prevent the occurrence of a resonance phenomenon peculiar to motor driving due to low frequency fluctuations caused by the SSCG modulation frequency. When such a resonance phenomenon occurs when the motor is driven, the reading position accuracy of a commonly used three-line CCD deteriorates. However, in the present invention, this is prevented, and high-quality reading is possible. . Hereinafter, an image forming apparatus according to an embodiment will be described in detail.

  FIG. 1-2 is an explanatory diagram of the image forming apparatus according to the embodiment of the present invention. The image forming apparatus includes a system control unit 1, an image reading unit 2, an image processing unit 3, an image writing unit 4, an operation unit 5, a copier mechanism unit 6, an image display unit 7, a drum unit 8, an intermediate transfer unit 9, and a development unit. Unit 10, paper feeding unit 11, and fixing unit 12.

  In the image forming apparatus, the image reading unit 2 scans the original while irradiating the original with a light source, reads the image from the reflected light from the original with a three-line CCD sensor, and sends the image data to the image processing unit 3. In the image processing unit 3, image data subjected to image processing such as scanner γ correction, color conversion, main scanning scaling, image separation, processing, area processing, gradation correction processing, etc. is sent to the image writing unit 4. The image writing unit 4 modulates the driving of an LD (laser diode) according to the image data.

  In the drum unit 8, a latent image is written by a laser beam from an LD on a uniformly charged rotating photosensitive drum, and toner is attached by a developing unit 10 to be visualized. The image formed on the photosensitive drum is retransferred onto the transfer belt of the intermediate transfer unit 9. In the case of full-color copying, four colors (Bk, C, M, and Y) of toner are sequentially stacked on the intermediate transfer belt. In the case of full-color copying, when the four-color image formation and transfer processes of Bk, C, M, and Y are completed, the transfer sheet is fed from the sheet feeding unit 11 in synchronization with the intermediate transfer belt, and transferred. The toner is transferred from the intermediate transfer belt to the transfer paper at the same time on the transfer paper. The transfer paper onto which the toner has been transferred is sent to the fixing unit 12 through the conveying unit, and is thermally fixed by the fixing roller and the pressure roller and is discharged.

  For user settings such as copy mode, the operation unit 5 accepts input from the operator. An operation mode such as a copy mode that has received a setting input is sent to the system control unit 1, and the system control unit 1 performs a control process for executing the set copy mode. At this time, the system control unit 1 issues a control instruction to units such as the image reading unit 2, the image processing unit 3, the image writing unit 4, and the image display unit 7.

  In order to display the image read from the image reading unit 2 on the image display unit 7, the image reading unit 2 starts reading a document image according to a control instruction from the system control unit 1, and the image signal from the image reading unit 2 is displayed. On the other hand, the image processing unit 3 performs image processing suitable for display on the image display device, and then outputs the image data of the document to the image display device.

  FIG. 2 is a functional block diagram of the image display unit. The image display unit 7 includes a FIFO (line buffer) 21, DRAM 22, CPU 23, VRAM 24, LCD controller 25, LCD panel 26, ROM 27, SRAM 28, serial level conversion 29, image data level conversion 30, and a keyboard 31. The unit 1 and the image processing unit 3 are connected.

  The image data output from the image processing unit 3 is stored in the DRAM 22 for image data storage by the DMA controller built in the CPU 23 via the FIFO 21 shown in FIG. Since the image data control signal is sent to the image display unit 7 together with the image data, it is possible to capture only the effective image area. Valid image data stored in the DRAM 22 is DMA-transferred to the VRAM 24 by the CPU 23. At this time, the CPU 23 can transfer an arbitrary portion of the image data in the DRAM 22 and perform processing such as enlargement / reduction / decimation. The image data transferred to the VRAM 24 is displayed on the LCD panel 26 under the control of the LCD controller 25.

  FIG. 3 is an explanatory diagram of the screen and operation system of the image display unit. The image display unit 7 may also be used as a display editor for displaying an image on the LCD and performing editing / processing area designation / mode setting within the screen. Each setting key shown in FIG. 3 corresponds to the keyboard 31 in the functional block diagram of FIG. In the present embodiment, the reading key and the brightness adjustment key are particularly important.

  FIG. 4 is a schematic diagram illustrating an example of the operation unit. The operation unit 7 has various keys, that is, a numeric keypad 41, a mode clear / preheat key 42, an interrupt key 43, an image quality adjustment key 44, a program key 45, a print start key 46, a clear / stop key 47, an area processing key 48, A brightness adjustment knob 49, touch panel keys arranged on an LCD (liquid crystal panel) 50, and an initial setting key 51 are provided.

  The numeric keypad 41 is used when inputting numerical values such as the number of copies. The mode clear / preheat key 42 is used to cancel the set mode and return to the initial setting, or to set the preheat state by continuously pressing for a predetermined time or longer. The interrupt key 43 is used to interrupt during copying and to copy another document. The image quality adjustment key 44 is used when adjusting the image quality. The program key 45 is used to register or call a frequently used mode. The print start key 46 is a key for starting copying. The clear / stop key 47 is used to clear an input numerical value or to interrupt copying during copying. The area processing key 48 is used when a mode such as area processing / editing is used on the image display unit (display editor).

  The brightness adjustment knob 49 adjusts the brightness of the LCD panel screen. The touch panel key 50 sets a key area in the same range as the range of various keys displayed on the LCD panel, and when the touch panel detects a press within the set range, processing of the set key is performed. I do. The initial setting key 51 is pressed when the user can select each initial setting.

  FIG. 5 is a diagram illustrating an example of an LCD (liquid crystal display screen). As shown in FIG. 5, on the LCD screen, there are mode selection displays such as a color mode, automatic density, manual density, image quality mode, automatic paper selection, paper tray, automatic paper scaling, equal magnification, sorting, stack, etc. There are also sub-screen selection displays such as create, color processing, double-sided, and variable magnification. A key having the same size as each display is set on the touch panel.

  FIG. 6 is a diagram showing an example of screen development by pressing the scaling key in FIG. When the scaling key is pressed, the scaling setting screen is scrolled up from the bottom of the screen. On the scaling setting screen, a key for fixed scaling (a scaling mode in which a scaling ratio is set in advance) is set. For example, when the touch panel key of the 71% portion is pressed by the operator, an input by pressing is accepted and a scaling factor of 71% is selected. Also, on this screen, a zoom key, a size scaling key, and an independent scaling / enlarged continuous shooting key are set on the left side of the screen so that selection of a scaling mode other than the standard scaling is accepted.

  FIG. 7 is a diagram illustrating an example of the touch panel detection circuit. FIG. 8 is a diagram for explaining settings of the touch panel shown in FIG. The touch panel detection circuit receives an input from the touch panel 71 and includes an A-D converter 73 and a controller 72. The controller 72 sets the detection terminal to a high state and sets X1, X2, Y1, and Y2. FIG. 8 shows the setting states of X1, X2, Y1, and Y2. Since the Y1 and Y2 circuits are pulled up by resistors, Y1 becomes + 5V when the touch panel is OFF, and 0V when the touch panel is ON. Therefore, the ON / OFF state is confirmed from the output of the A / D converter 73. When the controller 72 detects the touch panel ON state, the controller 72 switches to the measurement mode. In the X direction, X1 is + 5V, X2 is 0V, and the potential at the input position is connected to the A / D converter through Y1 to calculate coordinates. The coordinates in the Y direction are also calculated in the same way by switching circuits. By such a detection circuit, the pressed position of the touch panel 71 is detected.

  FIG. 9 is a functional block diagram of the operation unit. In the operation unit 5, the address signal from the CPU 53 is taken into the address latch 54 and is controlled here by the signal from the CPU 53. A part of the address signal output from the address latch 54 enters the address decoder 56, where a chip select signal for each IC is generated and used to create a memory map. Further, the address enters the memory such as the ROM 63 and the RAM 64 and the LCD controller 55 and is used for address designation. On the other hand, a data bus from the CPU 53 is connected to a memory and an LCD controller 55 to perform bidirectional data communication. In addition to the address bus and data bus from the CPU 53, the LCD controller 55 is connected to an LED driver 59, a keyboard 60, an analog touch panel 61, an LCD module 62, a display data ROM 63, a RAM 62, and the like.

  The LCD controller 55 creates display data from the data in the ROM 63 and the RAM 64 by a signal from the keyboard 66 or a signal from the touch panel 61, and controls display on the LCD. In addition, an optical fiber connector 65 is connected to the CPU 53 to perform communication with the outside.

  FIG. 10 is a diagram for mainly explaining a reading portion in the entire block diagram of the image reading apparatus according to the embodiment. FIG. 11 is a diagram for mainly explaining an image processing portion in the entire block diagram of the image reading apparatus according to the embodiment. The shading correction 122 in FIG. 10 is connected to each unit as shown in FIG. FIG. 10 and FIG. 11 show the entire image reading apparatus in two parts. The CPU 101 on the scanner IPU control unit executes a program stored in the ROM 102 and controls the entire scanner / IPU unit by reading and writing data and the like in the RAM 103. The CPU 101 is connected to the system control unit 104 by serial communication, and performs an operation instructed by transmission / reception of commands and data. Further, the system control unit 104 is connected to the operation display unit 105 by serial communication, and can set an instruction such as an operation mode by a key input instruction from the user.

  The CPU 101 is connected to an original detection sensor, an HP sensor, a pressure plate opening / closing sensor, a cooling fan, and the like, which are I / O 106, and performs detection and ON / OFF control. The scanner motor driver 117107 is driven by the PWM method output from the timing circuit 112, generates an excitation pulse sequence, and drives the pulse motor 108 for scanning the document.

  An original image is imaged on a three-line CCD 111 by passing light signals through a plurality of mirrors and lenses by a light amount output of a xenon lamp 110 driven by a lamp inverter 109. The 3-line CCD 111 is supplied with respective drive clocks by a timing circuit 112 for controlling a scanner IPU (Image Processing Unit), and outputs odd, even analog image signals of RGB to the emitter followers 113 to 115. Signals input from the emitter followers 113 to 115 to the analog processing circuits 116 to 118 are subjected to subtraction CDS in the analog processing circuits 116 to 118, line clamped at the optical black portion of the CCD, and an output difference between odd and even. And adjust each amplifier gain. After gain adjustment, the signals are combined by a multiplexer, and finally input to A / D converters 119 to 121 after DC level offset adjustment.

  The analog signals input to the A / D converters 119 to 120 are digitized and input to the shading circuit 122. The shading circuit 122 has a function of correcting unevenness in the amount of light in the illumination system and variations in CCD pixel output. The shading-corrected image data is input to the inter-line correction memories 123 and 124, and the image data of the number of lines B and G of the 3-line CCD and the number of lines B and R is delayed in the memory, so that one or more lines of the read image of BGR Align and output to dot correction 125.

  In the dot correction 125, the image data output from the inter-line correction memory is corrected for a dot shift within one line of RGB data. In the scanner γ correction 126, the reflectance linear data is corrected by a look-up table method. The corrected image data is input to the RGB filter, the color conversion process, the scaling process, and the create 130 via the automatic document color determination circuit 128, the automatic image separation circuit 129, and the delay memory (127).

  The automatic document color determination circuit 128 performs ACS (chromatic / achromatic determination) processing and inputs it to the automatic image separation circuit 129 to perform character / halftone separation processing. In the ACS processing, black and gray are determined. In image area separation processing, edge determination (determined by the continuity of white and black pixels), halftone dot determination (determined by the repetitive pattern of peak / valley peak pixels in the image), photo determination (image data outside character / halftone dots) In some cases, the character, print (halftone) portion, and photographic portion are determined and transmitted to the CPU 101, and the parameters and coefficients are switched by the subsequent RGB filter, color conversion printer γ correction, YMCK filter, and gradation processing. used.

  The image data is input to the RGB filter 130. In the RGB filter 130, filter coefficients such as RGB MTF correction, smoothing, edge emphasis, and through are switched and set according to the previous determination area. In the color conversion process, YMCK conversion, UCR, and UCA processes are executed from RGB data. Enlargement / reduction processing is executed on the image data input to the scaling processing and subjected to main scanning. The branch of the image display unit 132 is performed after this processing. It is connected to the image display unit 132 via an interface (I / F). In create, create editing and color processing. In create editing, italics, mirroring, shadowing, hollowing processing, etc. are executed. In color processing, color conversion, specified color erasure, undercolor, etc. are executed.

  The printer γ correction / YMCK filter 131 sets printer γ conversion and filter coefficients based on the previous determination area. Dither processing is executed in gradation processing, writing timing setting, image area, white area setting, test pattern generation such as gray scale and color patch can be performed in video control, and final image data is written in LD by writing processing. It is processed so that it can be output to (laser diode) and output to LD. Each function process is connected to the CPU 101 and executes setting and operation of each process according to an instruction from the system control unit 1 by a program stored in the ROM 102.

  12 and 13-1 are diagrams illustrating an image reading procedure of the image reading apparatus according to the embodiment. In FIG. 12, the timing circuit 112 and the CCD driver driving unit 133 are mainly functionally shown. Here, the timing circuit 112 is connected to the shading correction circuit 122, the A / D converters 119 to 121, and the analog processing circuits 116 to 118 shown in FIGS. The CCD driving unit 133 is connected to a three-line CCD.

  The timing circuit 112, the 3-line CCD 111, and the CCD driving unit 133 that is not described in FIGS. In the timing circuit 112, an external oscillator input is supplied as a reference clock to a motor control circuit, a CPU_I / F drive clock, and a register setting unit control circuit via a clock generator.

  The motor control circuit supplies the PWM clock to the motor driver 117 as the second driving means by using the reference clock. Since the PWM clock does not use the SSCG modulation clock, accurate reading position accuracy can be obtained. In addition, it is possible to suppress the occurrence of a resonance phenomenon peculiar to the motor due to the SSCG modulation clock. Similarly, the serial communication unit of the CPU_I / F unit is configured to operate with a reference clock.

  Next, generation of the SSCG clock supplied to the CCD 111 and the A / D conversion unit 119 will be described. The reference clock is connected to the output pin of the timing circuit to supply the clock to the external SSCG. The SSCG clock of the external SSCG is captured by the input pin of the timing circuit. The SSCG clock generates a quadruple clock by setting a frequency divider by register setting via the CPU_I / F as an input to the internal PLL circuit. Various clocks are generated based on this clock. From the CCD clock generation circuit of this timing circuit, a first phase transfer clock, a second phase transfer clock, a final stage transfer clock, a reset clock, a clamp clock, and a shift gate clock for driving the CCD are generated as an SSCG clock. This clock is input to the pulse adjustment circuit at the subsequent stage, and the phase shift amount and the pulse width increase / decrease amount of each clock pulse are adjusted and output under the control of the register setting unit.

  This pulse phase shift amount has a function of adjusting the shift amount in half-cycle units of the quadruple clock described above. Further, the pulse width increase / decrease amount also has a function of increasing / decreasing the pulse width amount in half-cycle units of the quadruple clock. These outputs are input to the CCD drive unit 133.

  FIG. 13-2 is a flowchart for explaining the procedure of the image reading unit according to the embodiment. When document reading is started, the SSCG unit 140 drives the CCD 111 and the A / D conversion unit 119 with the spread spectrum clock (step S101). The CCD 11 reads the original image and photoelectrically converts it (step S102), and the A / D converter 119 converts the photoelectrically converted analog signal into a digital signal (step S103). The CCD 111 determines whether or not the final line has been read (step S104). If the final line has not been read (No in step S104), the timing circuit 112 drives the pulse motor 108 with the reference clock to perform the sub-scanning direction. Shift (step S105) and return to step S101. If it is read to the last line (Yes in step S104), the process is terminated as it is.

  FIG. 14 is a block diagram of a CCD drive unit and a 3-line CCD. FIG. 15 is a graph showing a CCD drive timing chart. In FIG. 14, the first and second phase transfer clocks of the 3-line CCD have 8 terminals each having an input capacity of MAX 150 pF and TYP 100 pF. In this example, ACT04 is used as the drive driver. As an example of the present invention, ACT04 with 6 circuits is shown as a CCD driver, but it can also be realized by using, for example, ACT240 with 8 circuits.

  FIG. 16 is a diagram for explaining the pulse adjustment function. The pulse phase shift amount adjustment function will be described with reference to FIG. For the phase shift amounts of XPH2B, XRS, and XCP, the timing chart shown in FIG. In the present embodiment, the amount of phase shift is in the range of -4 to +4, but any timing can be accommodated by adopting a configuration capable of shifting the phase by one period. In FIG. 16, the phase shift amount is indicated by a solid line with a phase shift of 0 based on a falling edge reference in units of half clocks of a quadruple clock generated by the PLL. Dotted lines indicate phase shifts -2, -1, +1, and +2. The phase shifts −4, −3, +3, and +4 are similarly phase-shifted, but are omitted in FIG. Although phase shift examples have been shown for XPH2B and XRS, they are the same for XCP, and will be omitted.

  FIG. 17 is a diagram illustrating the pulse width increase / decrease adjustment function. Each pulse width increase / decrease amount of XPH2B, XRS, and XCP has a default pulse width increase / decrease amount of 0 in the timing chart shown in FIG. In this embodiment, the pulse width increase / decrease amount is set to −3 to +3. However, XPH2B, XRS, and XCP are divided into 16 divisions in units of a half clock of 4 times, so that a maximum of 15 divisions from a pulse of a minimum of 1 division. It is also possible to adopt a configuration that can take up to the pulse width. If it is this structure, it can respond to all timings. FIG. 17 shows an example in which the pulse width increase / decrease amounts of XPH2B and XRS are −1 and +1. The pulse width is increased or decreased on the rising edge basis. The pulse width increase / decrease amounts of -3, -2, +2, and +3 increase and decrease in the same manner, but are omitted in FIG. Since XCP is the same, all of them are omitted.

  FIG. 18 is a diagram illustrating the configuration of the pulse adjustment function register. The phase shift amount adjustment function register has a 16-bit register configuration in which each default can be set to ± 4 with 0 being 4 bits. The pulse width increase / decrease adjustment function register has a 16-bit register configuration in which 3 bits can be set up to ± 3. Thus, the pulse adjustment circuit is operated by the multiplication circuit of the internal PLL circuit.

  Next, the reset operation of the timing circuit will be described. In FIG. 12, the reset signal of the external reset IC is input to the timing circuit 112. The input signal generates a reset signal of RST1 and RST2 to each block by an internal reset generation circuit in the timing circuit 112.

  RST2 is a reset signal to a circuit (motor driving circuit, CPU_I / F, register setting unit) that supplies a clock to the second driving means. RST1 is a reset signal to a circuit for supplying a clock to the first driving means (CCD clock generation circuit, A / D converter, clock generation circuit for each signal processing such as analog processing).

  The internal reset generation circuit generates an SSCG_ON signal for turning on the external SSCG. In the external SSCG, a modulation clock is output by an SSCG_ON signal, and a reference clock (non-SSCG clock) is generated in the OFF state.

  In this embodiment, this SSCG_ON signal after the power is turned on can prevent a malfunction (one clock shift generated due to a timing shift due to the modulation clock) by inputting a spread clock by the SSCG before the internal PLL circuit is locked.

  FIG. 19 is a timing chart for explaining a reset sequence after the power is turned on. After the power is turned on, the reset is released after the time A waiting for the rise time of the power by the external reset IC. This external reset signal is input to the timing circuit and generates a reset signal of RST2 after time B synchronized with at least three internal clocks. Thereafter, a reset signal for RST1 of the signal processing system is generated after time C (2.5 to 150 ms) after waiting for the lock time of the internal PLL circuit. As a result, the CPU_I / F serial communication can be performed after the reset of RST2 is released. Without waiting for reset release waiting for the lock time of the internal PLL circuit of RST1, for example, the motor speed profile data required by the motor drive circuit can be received from the CPU by serial communication, and the time until the scan operation can be shortened. .

  Although the case where the CPU_I / F is a serial communication has been described in this embodiment, a configuration in which a 16-bit or 32-bit bus connection interface operates similarly with a reference clock can be used. Further, an SSCG ON signal is generated after a time D after the reset release of RST2. In the present embodiment, the SSCG_ON signal is generated from the internal reset generation circuit of the timing circuit. However, any signal from another circuit block, an external circuit, or a CPU port may be generated as long as it can be generated after D time of RST2.

  In the image reading apparatus according to the embodiment, a large number of clocks such as a transfer clock, a reset clock, a clamp clock, and a final stage clock are used to drive the CCD as the photoelectric conversion means. Harmonics of fundamental frequency components (MHz to several tens of MHz) are generated, but EMI can be reduced by driving at least the CCD 111 and the A / D converter 119 with a spread spectrum clock (SSCG) as a minimum system. In addition, since the level of the radiated electromagnetic wave is lowered, it is possible to prevent a nearby device from malfunctioning.

  On the other hand, since the clock supply to the pulse motor driver 117 for driving the optical system as the scanning drive means is low speed (several KHz to several tens KHz), the rise and fall can be blunted, and the level of the radiated electromagnetic wave Can be kept very low. As described above, since the reference clock (non-SSCG clock) is supplied to the scanning drive means, it is possible to prevent the resonance phenomenon peculiar to the motor drive from occurring due to the low frequency fluctuation caused by the SSCG modulation frequency.

  When the SSCG clock is used for the scanning drive means, a resonance phenomenon may occur due to a low frequency fluctuation due to the modulation frequency of the SSCG. When a three-line CCD is used, the reading position accuracy deteriorates. In addition, the image processing unit determines the area accuracy for automatic document color determination (black determination, gray determination, etc.) and automatic image separation (character determination, halftone determination) in order to perform optimal image processing. Although there is a possibility of causing an abnormal image due to a defect, the present invention has an effect of preventing such a failure.

  Further, according to the image reading apparatus according to the present embodiment, the clock is supplied to the signal processing unit including the photoelectric conversion unit that requires the SSCG clock by one timing generation unit and the clock is supplied to the scan driving unit that requires the reference clock. Since it can be done, it has the effect of reducing costs.

  In addition, since the multiplier circuit of the internal PLL circuit that is not a method of integrating the gate delay amount is used, the phase adjustment and pulse width adjustment of the drive clock to the photoelectric conversion means can be performed accurately.

  Further, an external SSCG device for supplying the SSCG clock can be connected.

  Also, the SSCG frequency range can be suppressed by extracting the clock from the front of the internal PLL circuit.

  In addition, since serial communication is possible without waiting for the lock time of the internal PLL circuit, the waiting time until the scanning operation after transmitting the motor speed profile data can be shortened.

  In addition, since the CCD has a high capacity load, clocks are supplied by a plurality of CCD drivers. However, radiation noise can be greatly reduced by using the SSCG clock for this clock. Further, since there is almost no radiation noise due to the driving clock of the motor driver 117, it is possible to increase the reading position accuracy by operating with the reference clock and prevent the resonance phenomenon.

  As a reset procedure after the power is turned on, the reset of the clock of the CCD and A / D converter (first driving means) and the clock of the pulse motor driver 117 (second driving means) is separated. Sending motor-driven speed profile data without waiting time by enabling serial communication to operate with the second driving means without waiting for the lock time of the internal PLL circuit after resetting the second driving means Can do.

  Further, it is desirable that the reset release of the first drive means be performed after the maximum lock time of the internal PLL circuit. This is because it is possible to prevent one clock shift caused by a timing shift caused by the spread of the spread clock by SSCG before the reset release.

  In particular, the 3-line CCD has RGB line intervals and the reading position is different for each color. Therefore, a phenomenon in which the speed fluctuation level given to each RGB image data at the same original position is different easily occurs. Unlike reading when there is no change, document color determination and image separation misjudgment may occur, but the image reading apparatus according to the embodiment can prevent these phenomena.

  Further, the image forming apparatus according to the embodiment includes such an image reading apparatus and can form a high quality image by high quality reading.

(2. Hardware configuration)
FIG. 20 is a block diagram illustrating a hardware configuration of such an image forming apparatus. As shown in the figure, this image forming apparatus has a configuration in which a controller 910 and an engine unit 960 are connected via a PCI (Peripheral Component Interconnect) bus. A controller 910 is a controller that controls the entire image forming apparatus, image reading, image processing, and input from an operation unit (not shown). The engine unit 960 is an image processing engine that can be connected to a PCI bus, and includes, for example, an image processing part such as error diffusion and gamma conversion for acquired image data.

  The controller 910 includes a CPU 911, a north bridge (NB) 913, a system memory (MEM-P) 912, a south bridge (SB) 914, a local memory (MEM-C) 917, and an ASIC (Application Specific Integrated Circuit). 916 and a hard disk drive 918, and the North Bridge 913 and the ASIC 916 are connected by an AGP (Accelerated Graphics Port) bus 915. The MEM-P 912 further includes a ROM (Read Only Memory) 912a and a RAM (Random Access Memory) 912b.

  The CPU 911 performs overall control of the image forming apparatus, has a chip set including the NB 913, the MEM-P 912, and the SB 914, and is connected to other devices via the chip set.

  The NB 913 is a bridge for connecting the CPU 911, the MEM-P 912, the SB 914, and the AGP bus 915, and includes a memory controller that controls reading and writing to the MEM-P 912, a PCI master, and an AGP target.

  The MEM-P 912 is a system memory used as a memory for storing programs and data, a memory for developing programs and data, and the like, and includes a ROM 912a and a RAM 912b. The ROM 912a is a read-only memory used as a memory for storing programs and data. The RAM 912b is a writable and readable memory used as a memory for developing programs and data, an image drawing memory during image processing, and the like.

  The SB 914 is a bridge for connecting the NB 913 to a PCI device and peripheral devices. The SB 914 is connected to the NB 913 via a PCI bus, and a network interface (I / F) unit and the like are also connected to the PCI bus.

  The ASIC 916 is an IC (Integrated Circuit) for multimedia information processing having hardware elements for multimedia information processing, and has a role of a bridge for connecting the AGP bus 915, the PCI bus, the HDD 918, and the MEM-C 917, respectively. .

  The ASIC 916 includes a PCI target and an AGP master, an arbiter (ARB) that forms the core of the ASIC 916, a memory controller that controls the MEM-C 917, and a plurality of DMACs (Direct Memory) that perform image data rotation by hardware logic or the like. A Universal Serial Bus (USB) 940 and an IEEE (The Institute of Electrical and Engineering Engineers 1394) interface 950 are connected between the access controller and the engine unit 960 via a PCI bus.

  The MEM-C 917 is a local memory used as an image buffer for transmission and a code buffer, and the HDD 918 is a storage for storing image data, programs, font data, and forms.

  The AGP bus 915 is a bus interface for a graphics accelerator card that has been proposed in order to speed up graphic processing. The AGP bus 915 speeds up the graphics accelerator card by directly accessing the MEM-P 912 with high throughput.

  The keyboard 920 connected to the ASIC 916 receives an operation input from the operator, and transmits the operation input information received by the ASIC 916.

  The image reading program executed by the image reading apparatus of the present embodiment is a file in an installable format or an executable format, such as a CD-ROM, a flexible disk (FD), a CD-R, a DVD (Digital Versatile Disk), or the like. You may comprise so that it may record and provide on a computer-readable recording medium.

  Furthermore, the image reading program executed by the image reading apparatus of the present embodiment may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Further, the image reading program executed by the image reading apparatus of the present embodiment may be provided or distributed via a network such as the Internet.

  The image reading program executed by the image reading apparatus of the present embodiment has a module configuration including the above-described units (image processing unit, system control unit, A / D conversion unit, SSCG unit, timing circuit, etc.). As actual hardware, a CPU (processor) reads out and executes an image reading program from the ROM, and the above-described units are loaded onto the main storage device, and an image processing unit, a system control unit, an A / D conversion unit, An SSCG unit, a timing circuit, and the like are generated on the main storage device.

  The embodiment of the present invention described above is an example for description, and the present invention is not limited to these examples described here.

  As described above, the image reading apparatus, the image reading method, the program for causing the computer to execute the method, and the image forming apparatus according to the present invention are useful for the image reading apparatus, and in particular, photoelectric conversion and scanning in the image reading apparatus. This is useful for a technology that supplies a clock for driving.

1 is a functional block diagram of an image reading apparatus in an image forming apparatus according to an embodiment of the present invention. It is explanatory drawing of the image forming apparatus by embodiment of this invention. It is a functional block diagram of an image display unit. It is explanatory drawing of the screen and operation system of an image display unit. It is a schematic diagram which shows an example of an operation part unit. It is a figure which shows an example of LCD (liquid crystal display screen). It is a figure which shows an example of the screen expansion | deployment by pressing down the magnification key in FIG. It is a figure showing an example of a touch panel detection circuit. It is a figure explaining the setting of the touch panel shown in FIG. It is a functional block diagram of an operation part unit. It is a figure mainly explaining a reading part among the whole block diagrams of the image reading apparatus by embodiment. It is a figure mainly explaining an image processing part among the whole block diagrams of the image reading apparatus by embodiment. It is a figure explaining the image reading procedure of the image reading apparatus by embodiment. It is another figure explaining the image reading procedure of the image reading apparatus by embodiment. It is a flowchart explaining the procedure of the image reading means by embodiment. It is a block diagram of a CCD drive unit and a 3-line CCD. It is the graph which showed the CCD drive timing chart. It is a figure explaining a pulse adjustment function. It is a figure explaining a pulse width increase / decrease amount adjustment function. It is a figure explaining the structure of a pulse adjustment function register. It is a timing chart explaining the reset sequence after power ON. 2 is a block diagram illustrating a hardware configuration of the image forming apparatus. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 System control unit 2 Reading unit 3 Image processing unit 4 Image writing unit 5 Operation part unit 6 Copier mechanism part 7 Image display unit 108 Pulse motor 111 CCD
112 Timing Circuit 119 A / D Converter 140 SSCG

Claims (12)

Photoelectric conversion means for photoelectrically converting a light image generated by illuminating a document image by an optical system;
A / D conversion means for converting the analog signal converted by the photoelectric conversion means into a digital signal;
Scanning drive means for moving the original and the optical system relatively to scan in the sub-scanning direction;
First driving means for driving the photoelectric conversion means and the A / D conversion means with a clock;
Second driving means for driving the scanning driving means with a clock;
A spread spectrum clock is supplied to the first driving means to drive the photoelectric conversion means and the A / D conversion means, and a reference clock is supplied to the second driving means to drive the scan driving means. Timing generating means for
An image reading apparatus comprising:   The timing generating means has an internal PLL (Phase Locked Loop) circuit, and generates a spread spectrum clock to be supplied to the first driving means by a multiplied clock from the internal PLL circuit. The image reading apparatus according to claim 1.   The external spread spectrum insertion means for inserting a spread spectrum clock from the outside on a clock supply route from the timing generation means to the first drive means. Image reading device.   The timing generation means further includes an output means for outputting to the outside before input to the internal PLL circuit of the timing generation means on a clock supply route from the timing generation means to the first drive means; The image reading apparatus according to claim 2, further comprising an input unit configured to input to the internal PLL circuit. The timing generation means is controlled by serial data,
5. The image reading apparatus according to claim 1, wherein the second driving unit supplies the reference clock generated by the timing generation unit as the serial data. 6. . The first driving means is a CCD driver;
The image reading apparatus according to claim 1, wherein the second driving unit is a motor driver 117.   The timing generation means releases the reset of the clock generation to the second driving means after the power ON reset of the timing generation means, and the clock generation reset to the first driving means after the stable operation of the internal PLL circuit 7. The image reading apparatus according to claim 2, wherein the image reading apparatus cancels the image.   The image reading apparatus according to claim 7, wherein the timing generation unit starts a spread spectrum modulation operation after releasing the reset to the first driving unit.   The image reading apparatus according to claim 1, wherein the photoelectric conversion unit includes a plurality of line CCDs including a three-line color CCD. A photoelectric conversion step of photoelectrically converting a light image generated by illuminating a document image by an optical system;
An A / D conversion step of converting the analog signal converted by the photoelectric conversion step into a digital signal;
A scan driving step of relatively moving the original and the optical system to scan in the sub-scanning direction;
A first driving step for driving the photoelectric conversion in the photoelectric conversion step and the A / D conversion in the A / D conversion step with a clock;
A second driving step of driving scanning in the scanning driving step with a clock;
A timing signal generation step of supplying a spread spectrum clock for performing the photoelectric conversion and A / D conversion in the first driving step and a reference clock for scanning in the second driving step;
An image reading method comprising:   A program for causing a computer to execute the image reading method according to claim 10. Photoelectric conversion means for photoelectrically converting a light image generated by illuminating a document image by an optical system;
A / D conversion means for converting the analog signal converted by the photoelectric conversion means into a digital signal;
Scanning drive means for moving the original and the optical system relatively to scan in the sub-scanning direction;
First driving means for driving the photoelectric conversion means and the A / D conversion means with a clock;
Second driving means for driving the scanning driving means with a clock;
A spread spectrum clock is supplied to the first driving means to drive the photoelectric conversion means and the A / D conversion means, and a reference clock is supplied to the second driving means to drive the scan driving means. Timing generating means for
An image reading apparatus having
Image output means for outputting an image read by the image reading device;
An image forming apparatus comprising:

Images