JP2006180006A - Semiconductor integrated circuit and data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relieve the load of a central processing unit in the case of carrying out a color transformation of RGB data. <P>SOLUTION: A semiconductor integrated circuit (20) includes the central processing unit (23) and a data transfer control unit (26) formed onto a semiconductor substrate. The data transfer control unit converts RGB pixel data read from a first external memory (22) according to a first address into a second address, and reads data in a second external memory (22) by using the second address. Since the data transfer control unit caries out address conversion to read the data from the second external memory, the load of the central processing unit is relieved in the case of carrying out the color transformation of the RGB data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit capable of controlling conversion of RGB pixel data into other color data, and more particularly to a technique effective when applied to color conversion of a color printer, for example.

  In Patent Document 1, in DMA transfer, data read from a first memory at an address set by a CPU is stored in an address register, and an address generated using the data in the address register is written to the second memory. Use as an address is described.

JP 2000-112873 A

  The present inventor has studied control for converting RGB pixel data into other color data in a color printer or the like. In a color printer or the like, printing is performed by converting R (red), G (green), and B (blue), which are the three primary colors of light, into complementary colors C (cyan), M (magenta), Y (yellow), and K (black). . In order to perform this color conversion, a data table (lookup table) of color data corresponding to RGB data is prepared, RGB pixel data is read from the data buffer of RGB pixel data, and based on the read pixel data An address is generated, and a data table of color data is read using the generated address. Color calculation such as color interpolation is performed on the read data, and printing is performed using the color data.

  The inventor of the present invention directly performs the central access device for the read access to the data buffer, the read access to the data table of the color data, and the memory access for the write back of the color data to the data buffer in the operation such as color interpolation. Then, it discovered that the load of the central processing unit became too large. In view of this, the present invention has studied that the data transfer control device is burdened with access control required for color conversion as much as possible. In particular, in color conversion to a complementary color system, the number of colors and the data size per color vary depending on the printer manufacturer, and the range of color interpolation and the calculation method are also different, taking into account versatility. It has been made clear by the present inventors that this is important. In the above-mentioned patent document 1, the idea regarding the conversion of color data is not described.

  One of the typical objects of the present invention is to reduce the load on the central processing unit when performing color conversion of RGB data.

  Another representative object of the present invention is to improve versatility against differences in color conversion conditions when converting color of RGB data.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The semiconductor integrated circuit has a central processing unit and a data transfer control device on one semiconductor substrate, and the data transfer control device uses a first address according to transfer control information set by the central processing unit. The RGB pixel data read from the first external memory is converted into a second address, and the second external memory can be read using the second address. Since the data transfer control device performs address conversion for reading the second external memory, it is possible to reduce the load on the central processing unit during color conversion of RGB data.

  The second external memory stores a data table of color data of a plurality of colors corresponding to RGB data, for example.

  The color data of each color held in the data table is, for example, in a range that can be specified by the number of bits of the higher-order multiple bits of each RGB of the second address with respect to data in a range that can be expressed using the total number of bits of the second address. In this case, when the data transfer control device reads the second memory using the second address, the data transfer control device uses a plurality of higher-order bits of each of RGB of the second address as a base address. Lead representative data.

  The plurality of representative data read by using the higher-order multiple bits of each of the RGB of the second address as the base address are, for example, representative data of eight colors that exist around the color specified by the second address. .

  The data transfer control device includes, for example, a first control register in which the number of higher-order multiple bits of the first address is specified. Further, the data transfer control device has a second control register in which the number of colors of the color data of the plurality of colors is specified, for example. Furthermore, the data transfer control device has a third control register in which, for example, a data size per color of the color data of the plurality of colors is designated. When these registers are included, the data transfer control device calculates the data amount obtained by multiplying the product of the number of colors specified by the second control register and the data size specified by the third control register by eight. Read from the second external memory based on the second address. By adopting these registers, versatility can be improved with respect to differences in color conversion conditions during color conversion of RGB data.

  Further, when the semiconductor integrated circuit has an internal memory, the data transfer control device, for example, corresponds to a plurality of representative data corresponding to a plurality of representative data read for each color by using, as a base address, a plurality of higher-order bits of RGB of the second address. Transfer control of the lower-order multiple bits of two addresses to the internal memory is performed. At this time, the central processing unit, for example, sets the plurality of representative data read for each color using the plurality of upper bits of each RGB of the second address as the base address, and outputs the lower bits of the corresponding second address. And the color data corresponding to the second address is interpolated. The data transfer control device transfers the interpolated color data to the first external memory based on the first address.

  [2] A data processing system includes a data processor having a central processing unit and a data transfer control device on one semiconductor substrate, a first external memory storing RGB pixel data, and a plurality of colors corresponding to RGB data. A second external memory holding a data table of color data, and the data transfer control device reads data read from the first external memory by a first address in accordance with transfer control information set by the central processing unit. The second external memory can be read by converting to the second address and using the second address.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to reduce the load on the central processing unit when performing color conversion of RGB data.

  FIG. 1 illustrates a processing flow of image processing performed by a printer. The processing indicated by 3 is performed on the image information from the scanner (SCAN) 1 and the image information from the USB interface (USBIF) 2 to output print data to the printer head 4. Shading correction (SHDCR) 5 is performed on the output of the scanner 1. Shading correction is a process that corrects a portion where the image level is deviated from the ideal due to optical distortion of the lens (a signal with a higher level cannot be obtained at the end of an image of one line) or dirt on the lens. It is. Normally, one line image is captured before scanning, and correction is performed using this initial captured one line image simultaneously with scanning. A JPEG decoding process (JPEGCD) 6 is performed for the input from the USB interface 2. Data obtained by the JPEG decoding process is Y (luminance) CrCb (color difference) data, and an R / G / B conversion process (RGBCVT) 7 is performed on the data. In the resolution conversion process (RSLCVT) 8, since the resolution of the input image is different from the resolution of the printer head, the size is adjusted. Both inputs of the resolution conversion process 8 are RGB data. A color conversion process (CLRCVT) 9 and a color interpolation process (CLRITR) 10 are performed on the resolution conversion result.

  The color conversion process 9 is a process of performing color conversion after finishing the resolution conversion 8. The input image is represented by RGB or the like, but when the ink color on the print head side is, for example, four colors, C (cyan), M (magenta), Y (yellow), and K (black). This color conversion takes into account the image classification of the input image (text, natural image, outdoor indoor shot image), number of ink colors, ink ejection dot size, dot resolution, dot scan method, ink composition, paper quality to be printed, etc. It is common. Further, the number of ink colors is not limited to four, and there are six colors, seven colors, eight colors, and the like. In addition, some ink dots are classified into a plurality of sizes to realize a photographic image quality. Since such various conditions cannot be uniquely determined, a conversion data table (LUT: Look-up Table) of color data of a plurality of colors corresponding to RGB data is usually used. The conversion data table stores color data generated based on data accumulated in advance from experimental data. In short, RGB data is viewed as an address, and CMYK data to be converted is stored in advance at that address.

Focusing on the amount of data when the color conversion is performed, the type of color represented by 8 bits for each of R, G, and B is 2 ^{(8 × 3)} = 16777216≈16 mega (M). Since there are C, M, Y, and K 8-bit data for each color type, the data amount of the conversion data table is 16M × (8 bits × 4 colors) ≈512 Mbits. If such a storage capacity is consumed for the conversion data table, the cost increases. Therefore, since a certain level of image quality can be obtained without reproducing the 16M color stages in a non-linear manner, color conversion processing is performed using the thinned data, and then color interpolation is performed to fill in the gaps. Techniques can be employed. This interpolation is the color interpolation process 10.

  A binarization process 11 is performed on the result of the color interpolation process 10. In order to actually perform printing on the printer, it is necessary to express two states: dot strike (1) or no strike (0). The process of converting into these two states is the binarization process 11. One pixel is composed of a set of a plurality of dots, and a pseudo intermediate color is expressed by a combination of the color, size, etc. of dots to be formed on a plurality of dots constituting one pixel.

  Here, a specific example of color conversion will be described. For example, if there are 8-bit data for each of R, G, and B, the combination of each data can be considered as the memory address of the conversion data table. For example, address A [23:16] = R [7: 0], address A [15: 8] = G [7: 0], address A [7: 0] = B [7: 0] It is said. The data allocation is data D [31:24] = C [7: 0], data D [23:16] = M [7: 0], data D [15: 8] = Y [7: 0], Data D [7: 0] = K [7: 0].

In this case, if each of RGB is 8-bit data, the input address is 24 bits. If CMYK is also 8 bits, the required data amount is 2 ²⁴ × 8 bits × 4 colors = 536 Mbits. When color interpolation is not performed, the conversion data table requires such a storage capacity.

Therefore, the combination of each bit of R [7: 0], G [7: 0], and B [7: 0] has a large amount of data, so only the upper bits are considered. Here, assuming a 3 bit interval, the memory address of the conversion data table is A [8: 0] = R [7: 5] G [7: 5] B [7: 5]. Therefore, the data amount is 2 ^{(3 × 3)} = 512 types. Since each of these types has 8 bits for C, M, Y, and K, the data amount of the conversion data table is 512 × (8 bits × 4 colors) ≈16 k bits.

  In the above, for example, red R is 3 bits. Therefore, as shown in FIG. 2, if each 3 bits is a base address, 32 types of address ranges (RNG) for the lower 5 bits are provided for each base address. ). In the interpolation processing, data as a representative point designated by the upper 3 bits of each RGB is referred to, and interpolation is performed between the representative points using the lower 5 bits of each of RGB.

  FIG. 3 shows an example of interpolation processing. An address section specified by 8 bits for each of RGB is shown. When the address space is designated by 3 bits for each of RGB, the designated range is a cubic range indicated by 12. In the interpolation processing, conversion is performed using the address data of eight vertices of the cube. That is, the data of the surrounding 8 points for the pixels in the region selected by the upper 3 bits of RGB are extracted from the conversion data table. Based on the extracted data, the data at address position 13 specified by 8 bits for each of RGB in a cube composed of 8 target pixels is not used for reference to the RGB conversion data table. The calculation may be performed by weighting according to the distance from each vertex specified by the lower 5 bits of each RGB.

  In the conversion data table, several types of conversion data are stored according to the shooting conditions of the input image, the printing operation mode, the paper type, the ink type, the dot size, and the like. In this sense, a plurality of bits for designating conversion data according to characteristics is actually added above the address for accessing the conversion data table.

  FIG. 4 illustrates a main hardware configuration for performing the color conversion and color interpolation. A microcomputer (MCU) 20 performs at least the color conversion and color interpolation. A synchronous DRAM (SDRAM) 21 as a first external memory holds RGB image data whose resolution has been converted. A flash memory (FLASH) 22 as a second external memory holds a conversion data table (LUT). The microcomputer 20 includes a central processing unit (CPU) 23, a RAM 24 as an internal memory, a direct memory access controller (DMAC) 25 as a data transfer control device, and a bus state controller (external bus interface circuit). BSC) 26. An internal bus IBUS, a peripheral bus PBUS, and an external bus EXBUS are connected to the BSC 25. The CPU 23 and RAM 24 are connected via the internal bus IBUS, the DMAC 26 is connected to the peripheral bus PBUS, and the SDRAM 21 and FLASH 22 are connected to the external bus EXBUS. Although not shown, the SDRAM 21 and the FLASH 22 may be connected to individual external buses. The microcomputer 20, the SDRAM 21, and the flash memory 22 are configured as individual semiconductor integrated circuits, and are formed on a semiconductor substrate such as single crystal silicon using a CMOS integrated circuit manufacturing technique or the like.

  The CPU 23 includes an instruction control unit that fetches and decodes an instruction from a program memory (not shown), and an execution unit that executes an address operation and operand operation according to the instruction decoding result. The RAM 24 is used as a work area for the CPU 23 or a temporary storage area for data. The bus state controller 25 performs control of an access protocol according to access symmetry. The DMAC 26 controls data transfer to the SDRAM 21 and the FLASH 22 according to instructions from the CPU 23. In particular, the DMAC 26 bears processing for color conversion and color interpolation.

  FIG. 5 illustrates a data flow for color conversion and color interpolation when the DMAC 26 has an address conversion function for color conversion. After the CPU 23 sets the source address and the number of transfer words of the RGB pixel data in the DMAC 26, when the DMA transfer is started by the DMAC 26, the access address ADR1 is supplied to the SDRAM 21 (A), whereby the RGB pixel data DAT1 is transferred from the SDRAM 21. It is read and supplied to the DMAC 26 (B). The DMAC 26 converts the supplied RGB pixel data into corresponding color data addresses (C). The converted color data address is supplied to the flash memory 22 as the second address ADR2 (D). As a result, the corresponding color data DAT2 is read from the flash memory 22 to the DMAC 26 (E). The read color data is color-interpolated by the CPU 23 (F1), and the color-interpolated data is written back to the SDRAM 21 via the DMAC 26. The write-back destination address of the color-complemented data may be the same as or different from the original RGB image data address. As a result, the CPU 23 does not have to perform the process of generating the address of the corresponding color data of the LUT based on the RGB pixel data, so the burden on the CPU 23 can be reduced.

  FIG. 6 illustrates a data flow for color conversion and color interpolation when the DMAC 26 has an address conversion function for color conversion and an interpolation calculation function. After the CPU 23 sets the source address and the number of transfer words of the RGB pixel data in the DMAC 26, when the DMA transfer is started by the DMAC 26, the access address ADR1 is supplied to the SDRAM 21 (A), whereby the RGB pixel data DAT1 is transferred from the SDRAM 21. It is read and supplied to the DMAC 26 (B). The DMAC 26 converts the supplied RGB pixel data into corresponding color data addresses (C). The converted color data address is supplied to the flash memory 22 as the second address ADR2 (D). As a result, the corresponding color data DAT2 is read from the flash memory 22 to the DMAC 26 (E). The DMAC 26 performs color interpolation on the read color data (F2) and writes the color-interpolated data back to the SDRAM 21. The write-back destination address may be the same as or different from the address of the original RGB image data. As a result, the CPU 23 does not have to perform the process of generating the address of the corresponding color data of the LUT based on the RGB pixel data, and the CPU 23 does not have to perform the color interpolation process for the corresponding color data read from the LUT. The burden on the CPU 23 can be further reduced.

  FIG. 7 shows a timing chart of the processing according to FIG. First, the CPU 23 performs initial setting (INIT) for the DMAC 26. For example, the head address indicating the start position of input image data, the data size after color conversion, for example, a burst size setting such as 4 bytes for 4 colors, 6 bytes for 6 colors, an increment value of a transfer address, a transfer image Settings such as size are made. Thereafter, when the start of DMA transfer processing is instructed (REQ), an access address is issued from the top address to the SDRAM 21 (A). In the figure, a read command R is issued following the active command ACT as a command (CMD), and addresses A0, A1, A2,... Are sequentially issued as access addresses (ADR) in synchronization therewith. As a result, the data D0, D1, D2,... Are sequentially read from the SDRAM 21 through a predetermined latency (B). The data to be read may be a single target data, but if the burst function of the SDRAM 21 is used, the processing performance increases if several data are taken together. Data transferred from the SDRAM 21 is stored in a buffer such as a FIFO in the DMAC 26, and is sequentially subjected to address conversion for the color conversion (CLRCVT), thereby generating an address of color data corresponding to the LUT (C). The address of the corresponding color data in the LUT is issued to the FLASH 22 (D). Here, the address data converted in (C) has a one-to-one correspondence with the data acquired in (B), but this is for ease of explanation. A higher address is added according to the print condition, the number of colors, or the number of bytes for acquiring the color of the corresponding surrounding representative point. When color interpolation is performed, address conversion for LUT access is usually performed using only a part of the data read in (B), and the remaining several bits are used as data for interpolation calculation to be performed later. Specific examples thereof will be described later.

  The flash memory 22 outputs the color data FD0, FD1, FD2,... According to the address issued in the process (D) (E). In short, the address supplied to the flash memory 22 corresponds to RGB, and the data output from the flash memory 22 corresponds to the ink color CMYK. The CPU inputs the color data FD0, FD1, FD2,... To perform color interpolation (CLRITR) (F1), and the color-interpolated data Z0, Z1, Z2,... Are written back to the SDRAM 22 via the DMAC 26 (G ). As is apparent from the timing chart of FIG. 6, the DMAC 26 performs address conversion for color conversion, so that the CPU is free from the burden of address conversion. Meanwhile, the CPU 23 can perform another data processing using the internal bus IBUS.

  FIG. 8 shows an example of the DMAC 26. The DMAC 26 is representatively shown as an RGB data holding unit (RGBDL) 30, an RGB data distribution unit (RGBDD) 31, an address conversion unit (ADRCVT) 32, and lower-order data as circuit parts for realizing the functions shown in FIG. A holding unit (LOWDL) 33, a color data holding unit (CLRDL) 34, and an address generation unit (ADRG) 35 are included. Although not shown, the DMAC 26 also performs conventional data transfer using the RAM 24 on the internal bus IBUS as the transfer source or transfer destination in the data transfer control, or using the external SDRAM 21 and FLASH 22 as the transfer destination and transfer source. And a transfer control circuit unit for performing address generation and data buffering. Since such a transfer control circuit unit can be considered as the configuration of a DMAC that has been widely used in the past, a detailed description thereof is omitted here.

  The address generator 35 generates an address and an access control signal for read access to the SDRAM 21 based on the initial setting by the CPU 23. The RGB pixel data output from the SDRAM 21 is held in the RGB data holding unit 30. The RGB data held in the RGB data holding unit 30 is sorted by the RGB data sorting unit 31 into upper bits and lower bits. The higher-order bits are supplied to the address conversion unit 32, and a plurality of bits corresponding to the conversion conditions are added to the higher-order side to generate an address for referring to the LASH of the FLASH 22. The color data of the eight representative points corresponding to the one RGB data is read from the FLASH 22 by the generated address and held in the color data holding unit 34. The lower data holding unit 33 holds lower bits of RGB data. The FIFO buffer (FIFO) of the color data holding unit 34 so that the lower-order bits held in the lower data holding unit 33 and the color data of 8 units held in the color data holding unit 34 can be correlated with each other. 36. When the color data holding unit 34 detects the full state of the FIFO buffer 36, the control signal 37 suppresses the output operation of new RGB pixel data to the RGB data holding unit 30, and addresses based on the new RGB pixel data. The change operation and the lower data holding operation are stopped, and during that time, the pairs of color data and lower data stored in the FIFO buffer 36 are sequentially transferred to the RAM 24. Address control when transferring to the RAM 24 is performed by a transfer control circuit unit (not shown). The CPU 23 sequentially uses the pairs of color data and lower data transferred to the RAM 24 to perform interpolation processing, generate color data corresponding to the RGB pixel data, and the generated color data is stored in the RAM 24. The color data stored in the RAM 24 is written back to the SDRAM 21 at a predetermined timing using a transfer control circuit unit (not shown) of the DMAC 26. The write back address may be the same as or different from the storage address of the original RGB pixel data.

  FIG. 9 shows an example of the address generation unit 35. The address generator 35 includes a counter (COUNT) 40, an address calculator (ARTU) 41, a read start address register (RSAR) 42, a read address step register (MDBSR) 43, a read end address register (REAR) 44, and an end address decoder. (EADEC) 45 and an address generation control circuit (ADRCNT) 46.

  The read start address register (RSAR) 42 holds a read start address of RGB data. A read address step (MDBSR) 43 holds the number of steps of the read address. The number of steps of the read address depends on the data width and the like of the external bus. Based on the byte address, the number of steps is 4 when the data bus width is 32 bits and 2 when the data bus width is 16 bits. A read end address register (REAR) 44 holds a read end address of RGB data. The CPU 23 sets values for the registers 42, 43, and 44, for example. The counter 40 counts the clock signal CLK when the operation start is instructed by the enable signal 47. The clock signal CLK is synchronized with the operation clock signal of the SDRAM 21. An address computing unit (ARTU) 41 has a multiplier and an adder, multiplies the output of the counter 40 by the setting value of the register 43, and adds the setting value of the register 42 to this to generate an access address for the SDRAM 21. . The address generation control circuit 46 generates an enable signal 47 in response to an operation instruction from the CPU 23 or the like, generates an access control signal for the SDRAM 21, and holds RGB data read from the SDRAM 21 in the RGB data holding unit 30. A timing signal or the like necessary for the generation is generated. The end address decoder 45 determines whether the address output from the address calculator 41 has reached a value at the final address set in the register 44. When the end address is reached, in response to the output of the end address decoder 45, the address generation control circuit 46 inverts the enable signal 47 to the disable instruction state and stops the address generation operation. The RGB data holding unit 30 sequentially holds RGB pixel data output from the SDRAM 21 in synchronization with the access of the SDRAM 21. The data holding operation of the RGB data holding unit 30 is synchronized with the clock signal CLK, and start and stop are instructed by the control signal 48.

  FIG. 10 illustrates details of the RGB data distribution unit (RGBDD) 31, the address conversion unit (ADRCVT) 32, and the lower data holding unit (LOWDL) 33. An image data separate register (IDSR) 50 and an address translation data size register (ATDSR) 51 are arranged as control registers. Control data is set in the registers 50 and 51 by the CPU 23. The image data separate register (IDSR) 50 is a register for designating a storage pattern of RGB data constituting one pixel stored in the RGB data holding unit 30. For example, when the first control data (1stDAT) is set in the IDSR 50, RGB data is stored so that a 32-bit memory area is allocated to one pixel as shown in FIG. The output of pixel data is the first 24 bits for a 32-bit area per pixel. For example, when the second control data (2ndDAT) is set in the IDSR 50, RGB data is stored so that a 24-bit memory area is allocated to one pixel as shown in FIG. The output of pixel data is also made for every 24 bit area per pixel. The RGB data holding unit 30 outputs the stored RGB data sequentially to the RGB data distribution unit (RGBDD) 31 after the control signal 48 is instructed to stop storing the RGB data.

  The address translation data size register (ATDSR) 51 is a register for designating the number of upper bits of each R, G, B data used for address interpolation. For example, when address interpolation is performed, H′1 to H′7 are set as control data in the ATDSR 51 in accordance with the number of data used for interpolation. In the case where all the bit addresses of RGB data are converted, control data H′8 is set in the ATDSR 51.

  The RGB data distribution unit (RGBDD) 31 converts the 8-bit data of each RGB into the address conversion unit (ADRCVT) 32 with the higher-order bits (for example, 3 bits) in accordance with the setting of the address translation data size register (ATDSR) 51. Bits (for example, 5 bits) are distributed to the lower data holding unit (LOWDL) 33. The address conversion unit (ADRCVT) 32 includes a base address conversion unit (BACVT) 52 and an access address conversion unit (AACVT) 53.

  FIG. 12 shows an example of the address conversion unit (ADRCVT) 32. The base address conversion unit (BACVT) 52 performs 0 extension on the lower side of the RGB data, and a plurality of bits for designating the LUT corresponding to the conversion condition in accordance with the printing condition on the higher side. To be generated. For example, when the upper address is H'abc, 0 extension is performed on the lower side (H'abc... 0), a plurality of bits are added to the upper side, and the base address BADR (H'd. Generated. The access address generation unit 53 includes a peripheral address generation unit (MBAG) 54 that generates a peripheral address MADR, and an address adder (AAD) 55 that generates the access address AADR by adding the peripheral address MADR to the base address BADR. The set values of the LUT bus size register (LDBSR) 56, the color number register (CNR) 57, and the color data size register (CDDR) 58 are supplied to the peripheral address generation unit (MBAG). The LUT bus size register (LDBSR) 56 is a register that specifies the data bus width of the flash memory 22 that holds the LUT. A color number register (CNR) 57 is a register representing the number of colors after color conversion. A color data size register (CDDR) 58 is a register representing a data size per color. The registers 56 to 58 can be set with control data by the CPU 23. A peripheral address generation unit (MBAG) 54 sequentially generates lower addresses for accessing color data of a plurality of representative points necessary for color interpolation according to the set values of these registers. For example, if LDBSR56 specifies 32 bits, CNR57 specifies 8 colors, CDSR58 specifies 8 bits, and the number of surrounding pixels (number of surrounding representative points) is 8, output from LUT with one access The number of data that can be read out is 32 bits, and the number of data to be read from the LUT is 8 (: CNR) × 8 (: CDSR) × 8 (: number of surrounding representative points) = 512 bits, 16 times (512 bits / 32 bits) Need to access and capture data. As described above, the peripheral address generation unit 54 performs a process of issuing the number of addresses necessary for referring to the LUT of one pixel according to the data format.

  FIG. 13 illustrates a timing chart of the address addition operation. In the figure, the base address BADR is H'12304560. The surrounding address MADR is sequentially changed to H'0000000, H'0000004,. At this time, the access address AADR is sequentially set to H′12304560, H′12304564,.

FIG. 14 illustrates a flash memory access timing chart for color conversion and color interpolation. DAT [23: 0] is RGB data read from the SDRAM 21. DAT [23: 0] has the sequence R [7: 0] G [7: 0] B [7: 0]. Here, the upper 3 bits of each of RGB are used for the base address BADR [8: 0]. The breakdown is R [7: 5] G [7: 5] B [7: 5]. Here, in order to simplify the description, the upper 3 bits of each of RGB are set as a base address BADR [8: 0]. R [4: 0] G [4: 0] B [4: 0] is set to the lower address LADR [14: 0]. The lower address LADR [14: 0] is held in the LOWDL 33 for interpolation processing. Here, the number of surrounding pixels of the representative point is 8, and the surrounding address MADR is 7 toggle addresses of A, B, C, D, E, F, G, and H. The access address AADR is an address obtained by adding the surrounding address MADR to the base address BADR [8: 0]. The access address AADR is supplied to the flash memory 22 in synchronization with the read signal RD. As a result, color data of representative points is output from the flash memory 22. In FIG. 14, color data of eight representative points D _{1A to} D _1H corresponding to the pixel data of the first pixel FstPIC are output, and D _2A to D corresponding to the pixel data of the second pixel 2ndPIC. The color data of 8 representative points of _2H are output, and the color data of 8 representative points of D _{3A to} D _3H are output corresponding to the pixel data of the third pixel 3rdPIC.

  FIG. 15 illustrates the data arrangement of the LUT stored in the flash memory. For example, data is arranged so that color data of representative points of A, B, C, D, E, F, G, and H are continuous for each color of CMYK with respect to one RGB data. Assuming that memory addresses are mapped in units of A, B, C, D, E, F, G, and H for each color, and the leading address of the color data of the eight representative points is H'0000 The leading address of the color data of the next eight representative points is H′0020. Although not particularly illustrated, it should be noted that the color data of the eight representative points share four in the case of adjacent ones.

  FIG. 16 shows an example of the color data holding unit 34. The color data holding unit 34 includes a FIFOB 36 and a FIFO control circuit (FCNT) 60. The CMYK color data read from the LUT is stored in the FIFOB 36. A FIFO control circuit (FCNT) 60 inputs the set values of the registers ATDSR51, LDBSR56, CNR57, and CDSR58, and monitors the number of times data is transferred from the LUT to the FIFOOB 36. When the FIFOOB61 becomes full or the register 51 , 56, 57, and 58, when a predetermined number of times is reached, RGBDL30 issues a transfer stop request at signal 37, and LOWDL issues a lower address transfer request at signal 61 to FIFOOB36. Hold. When the FCNT 60 issues a transfer stop request, it outputs an interrupt signal 62 to the CPU 23 to transfer the data 63 held in the FIFOB 36 to the internal RAM 24. After the transfer, the transfer of color data from the LUT is resumed and the process is continued. The CPU 23 performs an interpolation process using the color data transferred to the internal RAM 24 and a plurality of bits on the lower side of the RGB data, and the color data for each pixel that has undergone the color conversion through the color interpolation process is sequentially stored in the internal RAM 24. When all the color conversions are completed, or when the transfer of RGB data from the SDRAM 21 by the DMAC 26 is completed, the CPU 23 instructs the DMAC 26 to perform an operation of transferring the color conversion completion data to the SDRAM 21.

  When converting the RGB data of the SDRAM 21 into the CMYK data by using the DMAC 26 described above, the CPU 23 may set the transfer condition in the DMAC 26 to indicate the start of the DMA transfer operation, and the DMAC 26 uses the LUT access address from the RGB data. It is sufficient to perform the process of generating the color and the process of acquiring the data for color complementation, and the burden on the CPU 23 can be reduced. In the meantime, the CPU 26 can be used for other data processing, which can eventually contribute to shortening the data processing time for printing by the printer.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the color type of color data to be converted to RGB data, the number of bits of each color data, and the like can be changed as appropriate. Further, the present invention is suitable for application to a low-cost ink jet printer, but the present invention is not limited to this, and can be applied to a laser printer or the like.

6 is a flowchart illustrating an example of a fixed order of image processing performed by a printer. It is explanatory drawing which illustrates the meaning as the data for interpolation of the upper side multiple bits in the data of each RGB color and the lower side bits. It is explanatory drawing which illustrates the principle of the calculation method of a color interpolation process. It is a system block diagram which illustrates the main hardware constitutions for performing color conversion and color interpolation. FIG. 10 is an operation explanatory diagram illustrating the flow of data for color conversion and color interpolation when the DMAC has an address conversion function for color conversion. FIG. 10 is an operation explanatory diagram illustrating the flow of data for color conversion and color interpolation when the DMAC has an address conversion function for color conversion and an interpolation calculation function. 6 is a timing chart of processing according to FIG. 5. It is a block diagram which shows an example of DMAC. It is a block diagram which shows an example of an address generation part. It is a block diagram which illustrates the detail of a RGB data distribution part (RGBDD), an address conversion part (ADRCVT), and a low-order data holding part (LOWDL). It is explanatory drawing which illustrates a control aspect with the control data which a register | resistor (IDSR) holds. It is a block diagram which shows an example of an address conversion part (ADRCVT). 6 is a timing chart illustrating an address addition operation. 6 is a timing chart of flash memory access for color conversion and color interpolation. It is explanatory drawing which illustrates the data arrangement | positioning of LUT stored in flash memory. It is a block diagram which shows an example of a color data holding part.

Explanation of symbols

9 Color conversion processing 10 Color interpolation processing 20 Microcomputer 21 SDRAM
22 Rush memory for storing LUT 23 CPU
24 Internal RAM
25 Bus state controller 26 DMAC

Claims (17)

Having a central processing unit and a data transfer control device on one semiconductor substrate,
The data transfer control device converts the RGB pixel data read from the first external memory by the first address into the second address according to the transfer control information set by the central processing unit, and uses the second address to convert the second pixel data. (2) A semiconductor integrated circuit capable of reading an external memory.   2. The semiconductor integrated circuit according to claim 1, wherein the second external memory stores a data table of color data of a plurality of colors corresponding to RGB data. The color data of each color held in the data table is representative of the range that can be specified by the number of bits of the higher-order multiple bits of each RGB of the second address, relative to the range of data that can be expressed using the total number of bits of the second address. Data,
The data transfer control device, when reading a second memory using the second address, reads a plurality of representative data for each color using a plurality of higher-order bits of RGB of the second address as base addresses. 3. The semiconductor integrated circuit according to 2.   The plurality of representative data that is read with the higher-order multiple bits of each RGB of the second address as a base address is representative data of eight colors for each color that exists around the color specified by the second address. Item 4. The semiconductor integrated circuit according to Item 3.   5. The semiconductor integrated circuit according to claim 4, wherein the data transfer control device includes a first control register in which the number of upper bits of the first address is designated.   6. The semiconductor integrated circuit according to claim 5, wherein the data transfer control device has a second control register in which the number of colors of the color data of the plurality of colors is designated.   7. The semiconductor integrated circuit according to claim 6, wherein the data transfer control device has a third control register in which a data size per color of the color data of the plurality of colors is designated.   The data transfer control device uses, as the second address, a data amount obtained by multiplying a product of the number of colors specified by the second control register and a data size specified by the third control register by eight. 8. The semiconductor integrated circuit according to claim 7, wherein reading is performed from the second external memory on the basis thereof. The semiconductor integrated circuit has an internal memory,
The data transfer control device controls transfer of a plurality of representative data read for each color using a plurality of upper bits of each RGB of the second address as a base address and a plurality of lower bits corresponding to the second address to an internal memory. The semiconductor integrated circuit according to claim 3, which can be performed.   The central processing unit uses the plurality of representative data read for each color using the plurality of upper bits of each of the RGB of the second address as a base address, using the lower bits of the corresponding second address, The semiconductor integrated circuit according to claim 9, wherein the color data corresponding to the second address is interpolated.   11. The semiconductor integrated circuit according to claim 10, wherein the data transfer control device transfers the interpolated color data to the first external memory based on a first address. A central processing unit and a data transfer control unit on one semiconductor substrate;
The data transfer device can output an address signal for accessing an external memory connected to the outside of the semiconductor substrate,
The data transfer device outputs a first address signal to the external memory, and the first data based on the first address signal is supplied from the external memory and is read using a part of the read first data. The second address for accessing the external memory can be output,
The central processing unit is a semiconductor integrated circuit capable of performing arithmetic processing on second data read based on the second address. A data processor having a central processing unit and a data transfer control device on one semiconductor substrate;
A first external memory for storing RGB pixel data;
A second external memory having a data table of color data of a plurality of colors corresponding to RGB data,
The data transfer control device converts the data read from the first external memory by the first address into the second address according to the transfer control information set by the central processing unit, and uses the second address to convert the second external Data processing system that can read memory. The color data of each color held in the data table is representative of the range that can be specified by the number of bits of the higher-order multiple bits of each RGB of the second address, relative to the range of data that can be expressed using the total number of bits of the second address. Data,
The data transfer control device, when reading a second memory using the second address, reads a plurality of representative data for each color using a plurality of higher-order bits of RGB of the second address as base addresses. 13. The data processing system according to 13. The data processor has an internal memory,
The data transfer control device controls transfer of a plurality of representative data read for each color using a plurality of upper bits of each RGB of the second address as a base address and a plurality of lower bits corresponding to the second address to an internal memory. The data processing system according to claim 14, which can be performed.   The central processing unit uses the plurality of representative data read for each color using the plurality of upper bits of each of the RGB of the second address as a base address, using the lower bits of the corresponding second address, 16. The data processing system according to claim 15, wherein the color data corresponding to the second address is interpolated.   The data processing system according to claim 16, wherein the data transfer control device transfers the interpolated color data to the first external memory based on a first address.

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