JP2006174497A - Image signal processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently detect a pixel defect included in a picture signal. <P>SOLUTION: A defect detection circuit 12 compares the picture signal of a target pixel with the picture signal of peripheral pixels, detects a pixel defect candidate and stores the address information of the pixel defect candidate in a position memory circuit 13. A defect judgement circuit 14 repeats the judgement of the pixel defect on the basis of address information stored in the position memory circuit 13, decides the address information of the pixel defect from the continuity of the judgement result and registers it in a defect registration circuit 15. A defect correction circuit 16 corrects a picture signal Y(n) in accordance with the address information of the registered pixel defect and generates a picture signal Y'(n). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image signal processing apparatus that detects a defect included in an image signal.

  In a solid-state imaging device such as a CCD image sensor, a so-called pixel defect may occur in which a constant charge is always accumulated and a fixed level is output regardless of the light reception level of the pixel. For this reason, in the process of signal processing on the image signal obtained from the solid-state imaging device, defect correction processing is performed so that pixel defects do not appear on the reproduction screen.

  FIG. 15 is a block diagram illustrating a configuration of an imaging apparatus configured to perform pixel defect correction processing.

  The CCD image sensor 1 has a plurality of light receiving pixels arranged in a matrix and accumulates information charges in each light receiving pixel in accordance with the received subject image. The CCD 1 is driven by a vertical drive signal φv and a horizontal drive signal φh, and information charges accumulated in each light receiving pixel are sequentially transferred and output in units of one line, and an image signal Y0 according to a predetermined format is output. The drive circuit 2 generates a vertical drive signal φv and a horizontal drive signal φh for driving the CCD 1 according to the vertical synchronization signal VD and the horizontal synchronization signal HD, and supplies them to the CCD 1.

  The timing control circuit 3 divides a reference clock having a fixed period, generates a vertical synchronization signal VD that determines the timing of vertical scanning and a horizontal synchronization signal HD that determines the timing of horizontal scanning, and supplies them to the drive circuit 2. For example, in the case of the NTSC format, the horizontal synchronizing signal HD is generated by dividing the reference clock of 14.32 MHz by 910, and the vertical synchronizing signal VD is generated by dividing the horizontal synchronizing signal by 525/2. Further, the timing control circuit 3 supplies a timing signal for synchronizing each operation timing to the operation timing of the CCD 1 to a signal processing circuit 4 and a defect correction circuit 5 described later.

  The signal processing circuit 4 subjects the image signal Y0 output from the CCD 1 to signal processing such as sample hold and level correction, and outputs the result as an image signal Y1. For example, in the sample and hold process, for the image signal Y0 that repeats the signal level and the reset level, the signal level is extracted after clamping the reset level to generate the image signal Y1 that continues the signal level. In the level correction process, gain feedback control is performed so that the average level of the output image signal Y1 falls within the target range. In the signal processing circuit 4, after the image signal Y 0 is sampled and held, the sample hold value is A / D converted, and thereafter digital processing tends to be adopted.

  The defect correction circuit 5 performs defect correction processing on the image signal Y1 based on the correction information stored in the correction information memory 6. For example, the pixel information in which the defect has occurred is configured to be replaced with an average value of information of pixels before and after the defect. The correction information memory 6 stores the position of the pixel defect of the CCD 1, for example, monitors the output of the CCD 1 in advance to detect the position of the pixel defect, and stores the detection result as correction address information.

Even if the CCD 1 is a chip manufactured in the same process, the position where the pixel defect occurs differs from chip to chip. Therefore, the CCD 1 used in the imaging device individually detects the position of the pixel defect and corrects the correction information memory 6. It is necessary to generate correction address information to be stored in. For this reason, the increase in the cost in the assembly process of an element and also the assembly process of the imaging device incorporating an element is caused.

  Further, the pixel defect of the CCD 1 may increase due to a change with time. When such a change with time occurs, the correction address information in the correction information memory 6 must be rewritten. However, since a general user of the imaging apparatus does not have means for rewriting the contents of the correction information memory 6, it is practically difficult to rewrite the correction information address in the correction information memory 6.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to make it possible to cope with changes in pixel defects due to changes in the elements over time without increasing the cost of the assembly process.

  The image signal processing apparatus of the present invention detects a pixel defect based on an image signal, and determines the level of the image signal corresponding to the target pixel as the level of the image signal corresponding to a plurality of peripheral pixels adjacent to the target pixel. A detection circuit that detects a defect candidate in comparison with a determination reference value set based on the determination circuit, a determination circuit that determines a pixel defect based on continuity over a plurality of screens of defect candidates detected by the detection circuit, A first memory section that temporarily stores defect information indicating the position of the pixel defect determined by the determination circuit; and a nonvolatile second memory that stores the position of the pixel defect from the first memory section. And a memory unit.

  And the said detection circuit of this invention can set the said determination reference value to multistep, and can detect a defect candidate for every step. In addition, the first memory unit or the second memory unit can store the defect information together with the defect information by leveling the degree of pixel defects, and can further store the first memory unit or the second memory. The part can also be preferentially stored in the order of high pixel defects.

  The determination circuit of the image signal processing apparatus according to the present invention can perform a defect determination operation for each area obtained by dividing one screen into a plurality of areas. The determination circuit can perform the defect determination operation repeatedly in a time division manner for each area obtained by dividing one screen into a plurality of areas.

  Further, the determination circuit may share a part of the detection circuit.

  According to the present invention, pixel defect information can be sequentially updated. Therefore, even when the number of pixel defects increases due to a change with time of the image sensor, it is possible to correct the pixel defects without particularly changing the setting.

  In addition, since the control information of the imaging device that generates the image signal is used as the criterion for determining the pixel defect, more accurate determination can be performed. Since the pixel defect is determined by dividing the screen, the capacity of the position memory circuit for storing the pixel defect information can be saved. Furthermore, by connecting an interface circuit capable of reading and writing each control information, the control information can be easily changed from an external computer device, and the versatility of the apparatus can be expanded.

  FIG. 1 is a block diagram showing a first embodiment of an image signal processing apparatus of the present invention.

The image signal processing apparatus of the present invention includes an image memory circuit 11, a defect detection circuit 12, a position memory circuit 13, a defect determination circuit 14, a defect registration circuit 15, and a defect correction circuit 16. In this image signal processing apparatus, predetermined processing is performed on the output of the image sensor, and pixel defect correction processing is performed on the image signal Y (n) that is A / D converted and supplied as digital data. Composed.

  The image memory circuit 11 includes a plurality of line memories and a plurality of latches, captures an image signal Y (n) that is continuously input in units of one row, and an image signal Y (P0) corresponding to the target pixel P0. The image signals Y (P1) to Y (P8) corresponding to the peripheral pixels P1 to P8 are output.

  The defect detection circuit 12 determines a determination reference value Lw and a black defect for determining a white defect based on the image signals Y (P1) to Y (P8) of the peripheral pixels P1 to P8 input from the image memory circuit 11. Determination reference value Lb is generated, and these determination reference values Lw and Lb are compared with the image signal Y (P0) of the target pixel P0 to detect a pixel defect. In this defect detection circuit 12, a true pixel defect caused by a physical defect of the solid-state imaging device that obtains the image signal Y (n) and an apparent pixel defect that is accidentally regarded as a pixel defect due to the convenience of the subject. Are detected without distinction, and all of them are defect candidates. In the detection operation of the defect detection circuit 12, the position of the pixel defect is output as address information. For example, the number of pixels is counted in synchronization with the input of the image signal Y (n), and the count value when a pixel defect is detected is output as address information.

  The position memory circuit 13 includes a volatile primary memory unit 13a that can support high-speed operation such as static memory (SRAM) and a non-volatile secondary memory unit 13b such as programmable memory (EEPROM). Address information output from the circuit 14 is stored as pixel defect position information. The primary memory unit 13a stores address information temporarily generated in the process of performing a pixel defect determination operation. The secondary memory unit 13b stores address information that is finally determined to be a pixel defect as a result of the pixel defect determination operation.

  The defect determination circuit 14 determines whether or not the pixel at the position indicated by each address information is a true pixel defect based on the continuity of pixel defects over a plurality of screens with respect to the address information stored in the position memory circuit 13. To do. In other words, if a pixel defect is detected accidentally due to the circumstances of the subject, it will not be detected as a pixel defect after a certain amount of time has passed, so only addresses that have been determined to be defective continuously for a certain period of time. Are determined to be true pixel defects. For example, for the pixel indicated by the address information stored in the position memory circuit 13, the same detection operation as the detection operation in the defect detection circuit 12 is repeated on a plurality of screens, or the defect detection circuit 12 is continuously displayed on a plurality of screens. While operating, it is configured to determine the continuity of pixel defects by comparing address information indicating pixel defects obtained for each screen. When the detection operation in the defect determination circuit 14 is the same as the detection operation of the defect detection circuit 12, a part of the detection circuit may be shared.

  The defect registration circuit 15 extracts the address information of the pixel determined to be a true pixel defect by the defect determination circuit 14 and stores it in the position memory circuit 13. Then, the defect correction circuit 16 replaces the image signal Y (P0) with the correction signal Y (c) based on the address information stored in the position memory circuit 13 by the defect registration circuit 15. Here, the correction signal Y (c) is generated, for example, by averaging the image signals of a plurality of peripheral pixels located around the target pixel P0. As a result, the image signal Y ′ (n) in which the white defect and the black defect are corrected is output from the defect correction circuit 16.

By the way, regarding the detection of pixel defects in the defect detection circuit 12, the determination reference values Lw and Lb may be set in multiple stages, and the pixel defect candidates may be weighted. That is, even if a pixel is determined as a defect, the degree of pixel defect is different depending on whether the pixel is greatly deviated from the predetermined determination reference values Lw and Lb and slightly deviated from the display screen. Is stored in the position memory circuit 13. If the degree of pixel defects is leveled and stored in the position memory circuit 13 in this way, when the number of pixel defects that can be registered in the position memory circuit 13 is limited, the defect registration circuit 15 determines the level of pixel defects. It is possible to configure so as to register with priority from the highest. Also, when there is no room for registering a new pixel defect in the position memory circuit 13, the defect level between the newly registered pixel defect and the already registered pixel defect is compared and rewritten according to the comparison result. By doing so, correction can be performed with priority given to pixel defects that are conspicuous on the screen.

  FIG. 2 is a block diagram illustrating an example of the image memory circuit 11. The memory circuit 11 includes first and second line memories 21 and 22 and first to sixth latches 23 to 28. As shown in FIG. 3, the memory circuit 11 is adjacent to the target pixel P0 and its periphery. Image signals Y (0) and Y (1) to Y (8) corresponding to the peripheral pixels P1 to P8 are simultaneously output.

  The first and second line memories 21 and 22 are connected in series with each other, and sequentially input image signals Y (n) are written into the first line memory 21 and sequentially read out from the first line memory 21. The image signal Y (n) to be written is written in the second line memory 22. As a result, the image signal Y (n) of the previous row is read from the first line memory 21 and the second line memory 22 receives the image signal Y (n) sequentially input. The image signal Y (n) two rows before is read out.

  The first and second latches 23 and 24 are connected in series with respect to the input of the image signal Y (n), and the image signal Y (n) one pixel before is held in the first latch 23, and the two pixels The previous image signal Y (n) is held in the second latch 24. As a result, the input image signal Y (n) is output as it is as the image signal Y (P8) corresponding to the peripheral pixel P8, and the image signal Y (n) held in the first and second latches 23, 24. ) Are output as image signals Y (P7) and Y (P6) corresponding to the peripheral pixels P7 and P6, respectively.

  The third and fourth latches 25 and 26 are connected in series to the input of the first line memory 21, and the image signal Y (n) one row before and one pixel before is supplied to the third latch 25. The image signal Y (n) two pixels before is held in the fourth latch 26. As a result, the image signal Y (n) read from the first line memory is output as the image signal Y (P5) corresponding to the peripheral pixel P5, and the image held in the third and fourth latches 25 and 26. The signal Y (n) is output as an image signal Y (P0) corresponding to the target pixel P0 and an image signal Y (P4) corresponding to the peripheral pixel P4.

  Similarly, the fifth and sixth latches 27 and 28 are connected in series to the input of the second line memory 22, and the image signal Y (n) two rows before and one pixel before is the fifth. The image signal Y (n) two pixels before is held in the latch 27 and held in the sixth latch 28. As a result, the image signal Y (n) read from the second line memory is output as the image signal Y (P3) corresponding to the peripheral pixel P3, and the image held in the fifth and sixth latches 27 and 28. The signal Y (n) is output as image signals Y (P2) and Y (P2) corresponding to the peripheral pixels P2 and P1, respectively.

  Accordingly, in the image memory circuit 11, the image signal Y (P0) of the target pixel P0 and the image signals Y (P1) to P8 of the surrounding pixels P1 to P8 located around the target pixel P0 while sequentially taking in the image signal Y (n). Y (P8) is output in parallel.

FIG. 4 is a block diagram showing a configuration of the defect detection circuit 12. The defect detection circuit 12
The average value calculating unit 31, the maximum value detecting unit 32, the minimum value detecting unit 33, first and second subtractors 34 and 35, an adder 36, and first and second comparators 37 and 38 are included.

  The average value calculation unit 31 takes in the image signals Y (P1) to Y (P8) of the peripheral pixels P1 to P8, respectively, and calculates their average level Lav. The maximum value detection unit 32 and the minimum value detection unit 33 detect the maximum level Lmax and the minimum level Lmin among the image signals Y (P1) to Y (P8), respectively.

  The first subtracter 34 subtracts the minimum level Lmin input from the minimum value detection unit 33 from the maximum level Lmax input from the maximum value detection unit 32, and calculates a difference ΔL therebetween. The adder 36 adds the difference ΔL to the average level Lav input from the average value calculation unit 31 to generate a determination reference value Lw for determining a white defect. The second subtracter 35 subtracts the difference ΔL input from the first subtractor 34 from the average level Lav input from the average value calculation unit 31 to determine a determination reference value Lb for determining a black defect. Is generated.

  The first comparator 37 compares the determination reference value Lb input from the second subtractor 35 with the image signal Y (P0) corresponding to the target pixel P0, and determines the level of the image signal Y (P0). When the reference value Lb has not been reached, that is, when it is determined that the target pixel P0 has a black defect, a detection output Db that is raised is generated. The second comparator 38 compares the determination reference value Lw input from the adder 36 with the image signal Y (P0) corresponding to the target pixel P0, and the level of the image signal Y (P0) is determined as the determination reference value Lw. When the target pixel P0 is determined to be a white defect, the detection output Dw that is raised is generated.

  FIG. 5 is a diagram showing a relationship between levels of image signals representing peripheral pixels and pixel defect determination levels calculated from these levels, and FIG. 6 is a flowchart showing operation steps of the defect determination operation. . In these drawings, as shown in FIG. 3, the pixel defect is determined for the target pixel P0 with reference to the eight peripheral pixels P1 to P8 adjacent to the target pixel P0.

  In the first step S1, the average value calculation circuit 31 calculates the average level Lav of the image signals Y (P1) to Y (P8) for eight pixels representing the peripheral pixels P1 to P8. In the second step S2, the maximum level detection unit 32 and the minimum value detection unit 33 use the maximum level Lmax and the minimum level Lmin of the image signals Y (P1) to Y (P8) for eight pixels representing the peripheral pixels P1 to P8. Is detected. The first step S1 and the second step S2 described above may be out of order.

  In the third step S3, the first subtracter 34 subtracts the minimum level Lmin from the maximum level Lmax to calculate a difference ΔL between the two levels. In the fourth step S4, the second subtracter 35 subtracts the difference ΔL from the average level Lav to generate a first determination reference value Lb for detecting a black defect, and the adder 36 generates an average level. A difference ΔL is added to Lav to generate a second determination reference value Lw for detecting a white defect. In the fifth step S5, the first and second comparators 37 and 38 compare the first and second determination reference values Lb and Lw with the image signal Y (P0) of the target pixel P0, thereby obtaining a pixel. A defect is determined and detection outputs Db and Dw are generated.

The first determination reference value Lb and the second determination reference value Lw generated by the first to fifth steps vary depending on the situation of the surrounding pixels, and are always maintained at optimum values. Here, the determination reference values Lb and Lw are values close to the average level Lav when the level difference between the peripheral pixels is small, and are values away from the average level Lav when the level difference between the peripheral pixels is large. Accordingly, the range of the determination reference values Lb and Lw is narrow in the region where the difference in shading is small on the screen, and conversely, the range of the determination reference values Lb and Lw is wide in the region where the difference in shading is large. Easily detect conspicuous pixel defects.

  FIG. 7 is a block diagram illustrating an example of a circuit for generating address information in the defect detection circuit 12. The circuit for generating the address information is composed of a horizontal counter 51, a vertical counter 52, a horizontal data latch 53, and a vertical data latch 54.

  The horizontal counter 51 is reset at a timing according to the horizontal synchronization signal HD1, and is counted up at a timing according to a clock CK1 having a fixed period synchronized with the detection operation of the defect detection circuit 12. Accordingly, the horizontal counter 51 repeats the counting operation for the number of pixels for one line during each horizontal scanning period, and counts the pixel numbers in the horizontal direction. The vertical counter 52 is reset at a timing according to the vertical synchronization signal VD1, and is counted up at a timing according to the horizontal synchronization signal HD1. Thus, the vertical counter 52 repeats the counting operation for the number of horizontal scanning lines for one screen in each vertical scanning period, and counts the pixel numbers in the vertical direction.

  The horizontal data latch 53 is connected to the horizontal counter 51, and takes in the count value of the horizontal counter 51 in response to one of the detection outputs Db and Dw. As a result, the horizontal address signal Fh indicating the timing of rising of the detection outputs Db and Dw, that is, the horizontal position of the pixel defect detected by the defect detection circuit 12, is extracted from the horizontal data latch 53. The vertical data latch 54 is connected to the vertical counter 52 and, like the horizontal data latch 53, takes in the count value of the vertical counter 52 in response to either of the detection outputs Db and Dw. Thereby, the vertical address signal Fv indicating the timing of rising of the detection outputs Db and Dw, that is, the vertical position of the pixel defect detected by the defect detection circuit 12 is extracted from the vertical data latch 54.

  For example, as shown in FIG. 8, when considering a screen of 6 rows × 8 columns, the horizontal counter 51 repeats counting in the range of “1” to “8”, and the vertical counter 52 is set to “1” to “8”. Repeat counting in the range of “6”. Therefore, if there is a pixel defect in the third row and the third column, when the count value of the horizontal counter 51 is taken into the horizontal data latch 53 at the rise of the detection outputs Db and Dw, “3” is output as the horizontal address signal Fh. The Then, when the count value of the vertical counter 52 is taken into the vertical data latch 54 at the rise of the detection outputs Db and Dw, “3” is output as the vertical address signal Fv. The address signals Fh and Fv output in this way indicate candidates including the possibility of pixel defects, and are supplied to the defect determination circuit 14.

  FIG. 9 is a block diagram illustrating an example of the configuration of the defect correction circuit 16. The defect correction circuit 16 includes first to fourth dividers 61 to 64, first to third adders 65 to 67, a selector 68, and a comparator 69. In the defect correction circuit 16, the image signals Y (P2) and Y (P7) of the peripheral pixels P2 and P7 positioned above and below the target pixel P0 and the image signals Y (P4) of the peripheral pixels P4 and P5 positioned above and below the target pixel P0. ), Y (P5) and the case where the correction signal Y (c) is generated.

  The first to fourth dividers 61 to 64 reduce the image signals Y (P2), Y (P7), Y (P4), and Y (P5) input from the memory circuit 11 to 1/4. The first adder 65 adds the division results of the first and second dividers 61 and 62, and the second adder 66 adds the division results of the third and fourth dividers 63 and 64. To do. Then, the third adder 67 adds the addition result of the first adder 65 and the addition result to the second adder 66 to generate a correction signal Y (c).

  The selector 68 selects either the image signal Y (P0) or the correction signal Y (c) of the target pixel P0 in response to the selection control signal S input from the comparator 69, and corrects the pixel defect. Output as signal Y ′ (P0).

  The comparator 69 compares the horizontal position information Fh and the vertical position information Fv based on the address information stored in the position memory circuit 13 with the horizontal reference information Rh and the vertical reference information Rv that change in the horizontal scanning period, A selection control signal S that is raised when they coincide is generated. The horizontal reference information Rh and the vertical reference information Rv used here can be generated using the horizontal counter 51 and the vertical counter 52 of the address generation circuit shown in FIG.

  Therefore, the selector 68 receives the image signal Y () of the target pixel P0 at the timing when the position information Fh, Fv according to the address information indicating the position of the pixel defect stored in the position memory circuit 13 and the reference information Rh, Rv match. P0) is replaced with the correction signal Y (c). As a result, the pixel defect is corrected by the information on the surrounding pixels.

  FIG. 10 is a block diagram showing a second embodiment of the image signal processing apparatus of the present invention. In this embodiment, when the defect determination circuit 14 ′ determines the defect of the target pixel, in addition to the continuity of the pixel defect, the imaging condition of the imaging device that obtains the image signal Y (n) is used. ing. The components other than the defect determination circuit 14 'are the same as those in the image signal processing apparatus according to the first embodiment shown in FIG.

  The defect determination circuit 14 ′ repeats the determination of defective pixels based on the defect candidate address information stored in the position memory circuit 13 and updates the address information. In the determination of the defective pixel, determination similar to the determination of the pixel defect in the defect detection circuit 12 is performed, and information indicating the operation state of the imaging apparatus that obtains the image signal Y (n) is received, and the contents of each information are included. Accordingly, the determination criterion is changed accordingly. That is, when the luminance of the subject image is high, the white defect is not conspicuous, and conversely, when the luminance of the subject image is low, the black defect is not conspicuous. Therefore, the pixel defect is simply determined only by the level of the image signal Y (n). If this is done, the true defect may not be determined as a defect. Therefore, based on exposure control information E (m) and gain control information G (m) indicating the operation state of the imaging device that obtains the image signal Y (n), the pixel defect determination criteria are changed, or the subject state In some cases, the pixel defect determination operation itself is temporarily stopped. For example, when the subject brightness estimated by the exposure control information E (m) and the gain control information G (m) exceeds a certain standard, the white defect determination operation is stopped, and when the certain standard is not reached, the black defect is detected. The determination operation is configured to stop.

  In addition to the exposure control information E (m) and the gain control information G (m), any information used for imaging control in the imaging apparatus can be used for the determination operation. For example, the focus control information for controlling the focus of the optical system of the image pickup apparatus is used, and the defect determination is performed before the focus is determined. If it is a true pixel defect, even when the focus of the optical system of the imaging device is not fixed, there is a clear difference from the surrounding pixels, so if the defect is determined before the focus is determined, a more accurate determination can be made. It becomes possible to do.

  Further, the defect determination circuit 14 ′ determines a pixel defect based only on the level of the image signal Y (n), and the address information obtained from the determination result includes exposure control information E (m), gain control information G (m), and the like. The control information may be added. That is, by adding imaging control information to address information indicating a pixel defect, it is selected whether or not correction processing as a pixel defect is performed on the pixel indicated by the address information at the time of defect correction. Will be able to.

FIG. 11 is a block diagram showing a third embodiment of the image signal processing apparatus of the present invention. In this embodiment, in addition to the configuration of the image signal processing apparatus of the first embodiment shown in FIG. 1, an area specifying circuit 17 is provided to limit the detection operation of the defect detection circuit 12 for each specific area of the image. I have to. Here, the defect determination circuit 14 uses the image signal Y (n) in addition to the level of the image signal Y (n) when determining the pixel defect as in the second embodiment shown in FIG. It is also possible to use imaging information of the obtained imaging apparatus.

  The area designation circuit 17 gives an instruction to the defect detection circuit 12 so as to divide one screen into a plurality of areas in synchronization with the timing of the horizontal scanning and vertical scanning of the image signal Y (n). For example, by dividing the horizontal scanning period into four and dividing the vertical scanning period into three, one screen is divided into 12 regions each consisting of 3 rows × 4 columns, and the defect detection circuit 12 is divided into only one of the divided regions. It is configured to allow the defect detection operation. Then, the area designating circuit 17 determines the pixel defect when the instruction from the defect registering circuit 15, that is, the address of the pixel defect in one divided region is fixed and the defect registering circuit 15 completes the registration of the pixel defect address information. The divided area where the detection is performed is changed. Even if no pixel defect is detected in the divided area and the defect registration circuit 15 does not register the pixel defect, the divided area where the pixel defect is detected is changed when the predetermined defect detection operation is completed. Is done. As a result, the defect detection circuit 12 sequentially detects pixel defects in a time division manner for a plurality of divided regions on the screen.

  If the defect detection circuit 12 is operated in time division for each divided region, the capacity of the position memory 13 for storing defect candidates detected by the defect detection circuit 12 can be saved. That is, since the defect detection circuit 12 detects more pixels than the pixels that are finally registered as pixel defects, in order to temporarily store the addresses of the pixels, the position memory circuit 13, In particular, the capacity of the primary memory unit 13a must be set large. Therefore, if the defect detection circuit 12 is operated in a time-sharing manner, the capacity of the primary memory unit 13a can be saved and an increase in circuit scale can be prevented.

  FIG. 12 is a block diagram showing a fourth embodiment of the image signal processing apparatus of the present invention. In this embodiment, an interface circuit 18 is provided in addition to the configuration of the image signal processing apparatus of the first embodiment shown in FIG. Here, the defect determination circuit 14 uses the image signal Y (n) in addition to the level of the image signal Y (n) when determining the pixel defect as in the second embodiment shown in FIG. It is also possible to use imaging information of the obtained imaging apparatus. Furthermore, similarly to the third embodiment shown in FIG. 11, an area designation circuit 17 may be provided and the defect detection circuit 12 may be operated for each divided region on the screen.

  The interface circuit 18 is connected to a serial bus 19 so that the image signal processing apparatus can be connected to an external computer device via the serial bus 19. As a result, it is possible to change the address information of the position memory circuit 13 and the determination criteria setting of the defect determination circuit 14 from a computer device connected to the serial bus 19. For example, in the second embodiment, whether or not to use the exposure control information E (m) and the gain control information G (m) given to the defect determination circuit 14 for the determination, and any information in the case of using it. It is possible to set from a computer device via the serial bus and the interface circuit 18 or the like. In the third embodiment, the division range of the area designating circuit 17 can be changed by being supplied from a computer device via the serial bus and interface circuit 18.

  By the way, the interface circuit 18 may be directly connected to the defect determination circuit 14 and the defect registration circuit 15 in addition to being connected to each part via a bus line.

FIG. 13 is a flowchart showing a first method for detecting an image defect according to the present invention. This detection method is executed by the defect detection circuit 12, the position memory circuit 13, the defect determination circuit 14, the defect registration circuit 15, and the defect correction circuit 16 shown in FIG. 1 (or any one of FIGS. 10, 11, and 12). The

  In the first step S1, the defect detection circuit 12 detects whether or not to be a pixel defect candidate, and stores address information indicating the position in the position memory circuit 13 only for those that may have pixel defects. In the subsequent second step S2, the defect determination circuit 14 performs the same detection process as the defect detection circuit 12 on the image signal Y (n) of the pixel specified by the address information stored in the position memory circuit 13. It is determined whether the pixel defect candidate is a true pixel defect. In the third step S3, the determination result is stored for the pixel determined to be a pixel defect.

  In the fourth step S4, it is determined how many times the defect candidate is determined, and if it is within the preset number of times set, the defect candidate determination is repeated by returning to the second step S2, and the specified number of times has been reached. If so, the process proceeds to a fifth step S5. When the process returns to the second step S2, the determination for the pixel defect candidate is performed again, and the determination result is stored in the subsequent third step S3. The determination result is stored in the third step S3 so as to be sequentially added by the number of times the determination is repeated in the second step S2.

  In the fifth step S5, it is determined whether or not a predetermined reference value is exceeded in the pixel defect candidate determination that is repeated a specified number of times. In other words, pixel defect candidates are determined a specified number of times, and among those, the number of times that the pixel defect is determined to be true (true) exceeds the number set as the reference value as a true pixel defect. The address to which the defect registration circuit 15 should perform correction processing is stored in the position memory circuit 13. In the sixth step S6, the defect correction circuit 16 performs correction processing on the pixel at the address registered in the position memory circuit 13, and an image signal Y ′ (n) in which the pixel defect is corrected is generated. The

  According to the first step S1 to the sixth step S6 described above, the pixel defect can be determined not only from the pixel state of one screen but also from the pixel state over a plurality of screens. Pixel defects can be distinguished.

  Here, with regard to the number of repetitions of defect candidate determination, the time required for determination becomes longer as the number is increased, but a more accurate determination result can be obtained. Further, in the defect registration operation in the fifth step S5, in addition to determining whether the pixel defect is true from the number of determinations, the exposure control information E (m) as obtained in the second embodiment shown in FIG. ), Gain control information information G (m), and various control information such as focus control information, the determination system can be further improved.

  FIG. 14 is a flowchart showing a second method for detecting an image defect according to the present invention. As in the case of FIG. 13, this detection method is the same as the defect detection circuit 12, the position memory circuit 13, the defect determination circuit 14, the defect registration circuit 15 and the defect registration circuit 15 shown in FIG. 1 (or any one of FIGS. 10, 11, and 12). This is executed by the defect correction circuit 16.

  In the first step S1, the defect detection circuit 12 detects pixel defect candidates on the initial screen, and stores address information indicating all pixel defect candidates on one screen (or divided area) in the position memory circuit 13. In the second step S2, the defect determination circuit 14 detects a pixel defect candidate on the next screen, and in the subsequent third step S3, the pixel defect candidate detected in the second step S2 is detected in the first step S1. It is determined whether or not the address information of the pixel defect of the first screen stored in the position memory circuit 13 matches.

In the fourth step S4, the address information for which the match is confirmed in the third step S3 is left, and the address information for which the match could not be confirmed is discarded, and the defect information, that is, the information in the position memory circuit 13 is updated. To do. Alternatively, in the third step S3, only the address information for which a match has been confirmed for a predetermined number of times (number of screens) is left, or only the address information for which a match has not been confirmed for a predetermined number of times (number of screens). Discard. The selection of whether to leave or discard this address information is also made depending on whether or not the information in the position memory circuit 13 is rewritten.

  In the fifth step S5, it is determined how many times defect information is updated, and if it is within a predetermined number of times set in advance, the process returns to the second step S2 to repeat detection of defect candidates, and the predetermined number of times has been reached. If so, the process proceeds to a sixth step S6. In the sixth step S6, the address information stored in the position memory circuit 13 is taken into the defect registration circuit 15 and registered as a true pixel defect. In a seventh step S7, the pixel at the address registered in the defect registration circuit 15 is subjected to correction processing by the defect correction circuit 16, and an image signal Y ′ (n) in which the pixel defect is corrected is generated. Is done.

  According to the first step S1 to the seventh step S7 described above, pixel defects can be determined not only from the state of pixels on one screen but also from the state of pixels across a plurality of screens, as in the detection method shown in FIG. Accidental pixel defects caused by the state of the subject can be distinguished.

  In the above embodiment, the case where the determination reference value is determined based on the level of a total of eight neighboring pixels of 3 rows × 3 columns adjacent to the target pixel is exemplified, but more than that, for example, 3 rows × 5 The determination reference value may be set based on the levels of 14 peripheral pixels in a column and 24 peripheral pixels in 5 rows × 5 columns.

  As described above, the present invention is an image signal processing device that detects a pixel defect on a screen based on an image signal for displaying a screen, and the level of the image signal corresponding to the target pixel is adjacent to the target pixel. A detection circuit that detects a defect candidate in comparison with a determination reference value that is set based on the levels of image signals corresponding to a plurality of peripheral pixels, and a continuity of defect candidates detected by the detection circuit over a plurality of screens And a memory circuit that stores defect information indicating the position of the pixel defect determined by the determination circuit, and corrects the target pixel according to the defect information stored in the memory circuit. An image signal processing apparatus. The detection circuit sets a determination reference value by adding or subtracting the difference between the maximum value and the minimum value of the signal levels of the plurality of peripheral pixels to the average value of the signal levels of the plurality of peripheral pixels. The detection circuit sets determination reference values in multiple stages and detects defect candidates at each stage. The determination circuit continues the defect determination operation in a plurality of fields to determine the position of the pixel defect, and then stops the operation together with the detection circuit. The determination circuit repeats the defect determination operation at a predetermined cycle. The memory circuit includes a first memory unit that temporarily stores defect information together with a detection result of the detection circuit, a non-volatile second memory unit that captures and stores the position of the pixel defect from the first memory unit, Have

  The determination circuit receives imaging control information of an imaging device that obtains an image signal, and determines a pixel defect based on the imaging control information and a determination reference value. The determination circuit receives imaging control information of an imaging apparatus that obtains an image signal, and determines a pixel defect based on a determination reference value when the luminance of the subject estimated from the imaging control information is within a predetermined range. The determination circuit performs a defect determination operation for each area obtained by dividing one screen into a plurality of areas. The determination circuit repeatedly performs a defect determination operation in time division for each area obtained by dividing one screen into a plurality of areas. At least one of the determination circuit and the memory circuit is connected to a bus to which an external device can be connected, and the pixel defect determination condition is changed from the external device.

Further, the present invention is a detection method for detecting a pixel defect included in a plurality of pixels constituting a screen based on an image signal for displaying one screen, and the signal level of the target pixel is set adjacent to the target pixel. A first step of detecting a defect candidate in comparison with a determination reference value set based on a signal level of peripheral pixels of the pixel and storing the position of the defect candidate; and a target pixel at the position stored in the first step A second step of comparing again the signal level with the criterion value, and a third step of storing the comparison result of the second step, and obtained by repeating the second and third steps a plurality of times. This is a pixel defect detection method for detecting a pixel defect according to a plurality of comparison results. The determination reference value is set by adding or subtracting the difference between the maximum value and the minimum value of the signal levels of the plurality of peripheral pixels to the average value of the signal levels of the plurality of peripheral pixels. Pixel defects are detected according to the imaging conditions of the imaging device that obtains an image signal together with a plurality of comparison results obtained by repeating the second and third steps a plurality of times.

  The present invention also provides a detection method for detecting a pixel defect included in a plurality of pixels constituting a screen from an image signal displaying one screen, wherein the signal level of the target pixel is set to a plurality of peripherals adjacent to the target pixel. A first step of detecting a first defect candidate by comparing with a determination reference value set based on a signal level of the pixel and storing a position of the first defect candidate; and a signal level of the target pixel A second step of detecting a second defect candidate in comparison with a determination reference value set based on signal levels of a plurality of neighboring pixels adjacent to the first pixel defect position, and a second defect A third step for determining coincidence with the position of the candidate and a fourth step for updating the position of the first defect candidate stored in the first step, leaving the position determined to coincide in the third step. And the second to second steps A method of detecting a pixel defect to repeat the steps. The determination reference value is set by adding or subtracting the difference between the maximum value and the minimum value of the signal levels of the plurality of peripheral pixels to the average value of the signal levels of the plurality of peripheral pixels.

1 is a block diagram showing a first embodiment of an image signal processing apparatus of the present invention. It is a block diagram which shows the structure of a memory circuit. It is a top view which shows the positional relationship of a target pixel and a surrounding pixel. It is a block diagram which shows the structure of a defect detection circuit. It is a figure which shows the relationship between the determination reference value and the level of a surrounding pixel. It is a flowchart explaining operation | movement of a defect determination circuit. It is a block diagram which shows the structure of an address generation circuit. It is a top view explaining the address of the pixel defect on a screen. It is a block diagram which shows the structure of a defect correction circuit. It is a block diagram which shows 2nd Embodiment of the image signal processing apparatus of this invention. It is a block diagram which shows 3rd Embodiment of the image signal processing apparatus of this invention. It is a block diagram which shows 4th Embodiment of the image signal processing apparatus of this invention. It is a flowchart explaining the 1st detection method of the pixel defect of this invention. It is a flowchart explaining the 2nd detection method of the pixel defect of this invention. It is a block diagram which shows the structure of a solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 CCD image sensor 2 Drive circuit 3 Timing control circuit 4 Signal processing circuit 5 Defect correction circuit 6 Correction information memory 11 Image memory circuit 12 Defect detection circuit 13 Position memory circuit 14, 14 'Defect determination circuit 15 Defect registration circuit 16 Defect correction circuit 17 area designating circuit 18 interface circuit 21 and 22 line memory 23 to 28 latch 31 average value calculating unit 32 maximum value detecting unit 33 minimum value detecting unit 34 and 35 subtractor 36 adder 37 and 38 comparator 51 horizontal counter 52 vertical counter 53 horizontal data latch 54 vertical data latch 61-64 divider 65-67 adder 68 selector 69 comparator

Claims (7)

An image signal processing apparatus for detecting a pixel defect based on an image signal, wherein the level of the image signal corresponding to the target pixel is set based on the level of the image signal corresponding to a plurality of peripheral pixels adjacent to the target pixel A detection circuit that detects a defect candidate in comparison with a determination reference value, a determination circuit that determines a pixel defect based on continuity over a plurality of screens of the defect candidate detected by the detection circuit, and the determination circuit A first memory unit that temporarily stores defect information indicating the position of the pixel defect, and a non-volatile second memory unit that captures and stores the position of the pixel defect from the first memory unit. An image signal processing apparatus comprising: The image signal processing apparatus according to claim 1, wherein the detection circuit sets the determination reference value in multiple stages and detects a defect candidate for each stage. The image signal processing apparatus according to claim 2, wherein the first memory unit or the second memory unit stores a level of a pixel defect along with the defect information. The image signal processing apparatus according to claim 3, wherein the first memory unit or the second memory unit stores in priority from the one having a high degree of pixel defects. The image signal processing apparatus according to claim 1, wherein the determination circuit performs a defect determination operation for each area obtained by dividing one screen into a plurality of areas. 6. The image signal processing apparatus according to claim 5, wherein the determination circuit repeatedly performs a defect determination operation in a time division manner for each area obtained by dividing one screen into a plurality of areas. The image signal processing apparatus according to claim 1, wherein the determination circuit shares a part of the detection circuit.

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