JP2006171022A - Display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce flicker in right and left faces by lessening a difference ΔV between the neighborhood of and a great distance from an input end of a gate voltage without shortening a charging time. <P>SOLUTION: A display device firstly sets gate off potential VGL to the potential of a first off signal V1 higher than inherent off potential and changes over the potential to that of a first off signal V2 being inherent off potential lower than it after an arbitrary constant period. Thereby a gate signal change amount is ▵VGH-V1 during gate-off in the neighborhood of a gate input end, and a gate signal change amount is ▵Vth-V2 during gate-off at the great distance of the gate input end. It is therefore possible to approximate them. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is used in, for example, a television device or a graphics display device, and a display device such as a liquid crystal display device that displays an image by supplying a display signal to each of a plurality of two-dimensionally arranged pixel units, and a display device thereof The present invention relates to a driving method.

  Conventionally, liquid crystal display devices are actively used in display devices such as television devices and graphics display devices. Among them, the active matrix liquid crystal display device (TFT-LCD) is particularly noticeable because a good display image without crosstalk between adjacent display pixel portions can be obtained even when the number of display pixels is increased. Collecting.

  In this active matrix driving type liquid crystal display device, a switching element such as a TFT is provided for each display pixel portion, and the switching element is turned on and off (switched to each switching element via each scanning signal line). OFF) A scanning signal for selecting a state is supplied and selectively driven, and a display signal (data signal) is supplied to each pixel electrode from each video signal line via each switch element. An image is displayed on the screen.

  FIG. 5 is an equivalent circuit diagram showing a configuration example of a main part of one pixel portion in a conventional active matrix liquid crystal display device.

  In FIG. 5, a pixel portion 20 of a conventional liquid crystal display device is provided with a video signal line (source bus line) 21 and a scanning signal line (gate bus line) 22 intersecting each other. A thin film transistor (TFT) 23 is provided as a switching element having a gate connected to the gate bus line 22 near the area, a source connected to the source bus line 21 near the intersection, and a drain connected to the pixel electrode 24. Yes. A liquid crystal material Clc is formed by sandwiching a liquid crystal material as a display medium between the pixel electrode 24 and the counter electrode 25. In addition, an auxiliary capacitor Ccs is provided in parallel with the liquid crystal capacitor Clc. One auxiliary capacitance electrode of the auxiliary capacitance Ccs is connected to the pixel electrode 24, and a counter voltage potential VCOM is applied to the other counter electrode. Furthermore, a parasitic capacitance Cgd is generated between the gate and drain of the TFT 23.

  Although only one pixel portion is shown in FIG. 5, a plurality of source bus lines 21 and gate bus lines 22 are provided, and each pixel portion 20 is provided for each region surrounded by both signal lines. It has been. Further, a display signal (data signal) corresponding to the display state of each pixel unit is supplied to each source bus line 21 from a video signal line driving means (source driver) (not shown), and each gate bus line 22 is scanned not shown. A scanning signal (gate signal) for turning on / off the TFT 21 is supplied from a line driving means (gate driver). As a result, an image is displayed by the entire pixel portion arranged in a matrix on the display screen.

  6A is a signal waveform diagram showing a gate driver output voltage signal (scanning signal) supplied to the gate of the TFT 23 in FIG. 5, and FIG. 6B is a liquid crystal supplied to the pixel electrode 24 in FIG. It is a signal waveform diagram which shows an applied voltage (data signal).

  As shown in FIG. 6A, each gate bus line 22 has a gate ON voltage (gate high voltage) that turns on the TFT 23 from the gate driver during the selection period in which all TFTs 21 connected to the line are turned on. VGH) is supplied. Further, in the next non-selection period in which all TFTs 21 connected to the line are turned off, a gate OFF voltage (gate low voltage VGL) for turning off the TFTs 23 is supplied from the gate driver. Thus, the gate driver output voltage signal (scanning signal) is configured by repeating the gate high voltage VGH and the gate low voltage VGL.

  As shown in FIG. 6B, the display voltage (liquid crystal applied potential; data signal voltage) applied to each display pixel portion (pixel electrode 24) via the TFT 23 is not selected (not selected). (Period; output period of the gate low voltage VGL), as shown in the following equation (1), the shift is shifted downward by the pull-in voltage ΔV. This is because a parasitic capacitance Cgd exists between the gate and drain of the TFT 23.

ΔV = (VGH−VGL) × Cgd / (Cgd + Clc + Ccs) (1)
VGH: gate high voltage VGL: gate low voltage Cgd: parasitic capacitance between gate and drain Clc: liquid crystal capacitance Ccs: auxiliary capacitance Actually, a plurality of pixel electrodes 24 and a liquid crystal capacitance Clc are connected to each TFT 23 on the gate bus line 22, respectively. As shown in FIG. 7, the input gate voltage (input scanning signal voltage) is delayed far from the vicinity of the gate input end by the resistance component 22a and the parasitic capacitance component 22b of the gate bus line 22 as shown in FIG. Occurs. For this reason, the gate voltage (scanning signal voltage) supplied to each TFT 23 differs greatly between the vicinity of the gate signal input end and the distance in the gate bus line 22.

  As shown in FIG. 8, the farther from the scanning line input end of the gate signal (scanning signal; gate driver output voltage signal), the longer the delay of the gate voltage and the smaller the gate voltage change amount when the gate is OFF. From the formula (1), the pull-in voltage ΔV decreases. Therefore, even if the counter potential is adjusted with an arbitrary VCOM common voltage so as to reduce the pull-in voltage ΔV, in-plane flicker occurs at the left and right positions of the display screen. Further, when the panel size of a liquid crystal display device (TFT-LCD) using the TFT 23 as a switch element is increased, flicker tends to be conspicuous in the left and right positions of the screen.

  In order to solve this problem, for example, in Patent Document 1, it is avoided that the gate input waveform (gate voltage waveform) becomes dull as shown in FIG. 8 from the vicinity of the gate input end of the gate signal (near the scanning line input end). Therefore, the in-plane flicker is reduced by the following method.

  As shown in FIG. 9, the gate signal waveform is forcibly blunted by the gate waveform control signal immediately before the gate OFF timing during the charging period in which the gate pixel (scanning signal voltage) is set to the high state to charge the display pixel portion. The gate signal waveform is smoothly inclined so as to gradually become the OFF level. As a result, the gate voltage change amount when the gate is turned off according to the above equation (1) is made substantially the same in the vicinity of the gate signal input end (near the gate input end) and in the distance, thereby reducing the difference in the pull-in voltage ΔV. In-plane flicker can be reduced.

  As another conventional technique, for example, in Patent Document 2, the cause of hindering the improvement of the screen display quality in driving the TFT-LCD is the above-described pull-in voltage ΔV. Therefore, the display quality is improved by reducing the pull-in voltage ΔV. Is planned. Instead of the conventional method of designing the auxiliary capacitance Ccs of the above formula (1) to be large in process in order to reduce the pull-in voltage ΔV value, here, specifically, the following two methods are disclosed. .

  First, as a first method, the pull-in voltage ΔV is reduced as a whole by forcibly blunting the gate voltage waveform of the TFT. This overlaps with Patent Document 1 described above, but (1) In Patent Document 1, the gate waveform is forcibly blunted to approximate the value of the pull-in voltage ΔV near and far from the gate signal input end. (2) In Patent Document 1, the falling waveform of the gate signal voltage is not smoothly inclined as in Patent Document 2, but from the ON state. It differs from Patent Document 2 in that the slope is blunted only at the beginning of switching to the off state, and the normal off waveform is maintained thereafter.

  Next, the second method is a method in which the gate-on voltage is once fixed to an intermediate potential at the time of gate-off and then switched to the original gate-off potential.

In Patent Document 2, these methods reduce the ΔV value as a whole without increasing the auxiliary capacitance Ccs of the above formula (1), leading to improved display quality.
Japanese Patent No. 3406508 Japanese Patent Laid-Open No. 6-3647

  However, in Patent Document 1, as shown in FIG. 7, the gate waveform is forcibly started to be inclined to the gate-off voltage from the timing immediately before the gate-off, which is originally the gate-on voltage period (scan line selection period). There is a problem that the charging time (scanning line selection period) is shortened. Further, as long as the parasitic capacitance Cgd exists in the TFT, the pull-in voltage ΔV cannot be eradicated.

  In Patent Document 2, immediately before the transition from the scanning line selection period to the non-selection period, that is, within the gate ON voltage period (scanning line selection period), the gate voltage is once lowered to an intermediate level, thereby writing the written video signal. The pull-in voltage ΔV is suppressed. In this case as well, similarly to Patent Document 1, there is a problem that the charging time (scanning line selection period) by the gate-on voltage is shortened. Moreover, in Patent Document 2, the variation in the pull-in voltage ΔV is considered to be due to the variation in the parasitic capacitance Cgd of each display pixel unit, and the concept of the vicinity of the gate signal input end and the distance is not particularly considered.

  The present invention solves the above-described conventional problem, and reduces the difference in the pull-in voltage ΔV between the position near and far from the input terminal of the gate signal without shortening the charging time (scan line selection period). An object of the present invention is to provide a display device that can reduce flicker in the left and right planes and a driving method thereof.

  The display device of the present invention provides a screen display by supplying a display signal to each pixel unit arranged two-dimensionally on a display screen via a switch element that is controlled to be turned on or off based on a scanning signal. In the display device that performs the above, when the switch element is controlled to be off, the first off potential and the second off potential that is the original off potential lower than the first off potential are output to each switch element as the scanning signal. The above-mentioned object is achieved by the switch element driving means.

  Preferably, the switch element driving means in the display device of the present invention includes voltage generating means for generating the first off potential and the second off potential, and switching timing of the first off potential and the second off potential. Timing control means for controlling the first off potential, and supplies the first off potential to the switch element for a predetermined period.

  In the display device of the present invention, a plurality of scanning signal lines and a plurality of video signal lines intersect, a control terminal is connected to the scanning signal line near the intersection, and one drive terminal is connected to the video signal line near the intersection. A plurality of pixel portions each having a switch element connected to each other and a pixel electrode connected to the other drive end of the switch element are arranged in a matrix, and an image for selectively supplying a video signal to the plurality of video signal lines Signal line driving means is provided, and has scanning signal line driving means for selectively supplying a scanning signal to the plurality of scanning signal lines, and the original off potential of the scanning signal during the non-selection period of the scanning signal line The first off potential set to a higher potential is supplied to the scanning signal line, and after the elapse of a predetermined period, the second off potential set to the original off potential is supplied via the scanning signal line driving means. Switch element driver for supplying to the scanning signal line Is provided, the object is achieved.

  Still preferably, in a display device according to the present invention, the switch element driving means includes voltage generating means for generating the first off potential and the second off potential, and switching timing of the first off potential and the second off potential. Timing control means for controlling the first off potential, and the first off potential is supplied to the scanning signal line through the scanning signal line driving means for a predetermined period.

  Still preferably, in a display device according to the present invention, the switch element driving unit is a signal selection unit that switches between the first off potential and the second off potential based on a switching timing control signal from the timing control unit. It has further.

  Still preferably, in a display device according to the present invention, the switch element driving unit is a signal selection unit that switches between the first off potential and the second off potential based on a switching timing control signal from the timing control unit. Is provided inside or outside the scanning signal line driving means, and the selection output from the signal selection means is the scanning signal low voltage.

  Further preferably, the timing control means in the display device of the present invention outputs a start signal defining a vertical period and a clock signal defining one horizontal on period of the scanning signal to the scanning signal line driving means, The voltage generating means outputs a scanning signal high voltage to the scanning signal line driving means, and the scanning signal line driving means uses the start signal, the clock signal, the scanning signal high voltage, and the scanning signal low voltage. A scanning signal is generated.

  Further preferably, the timing control means in the display device of the present invention is capable of setting the switching timing to an arbitrary value.

  Still preferably, in a display device according to the present invention, the timing control means includes a plurality of the switch elements connected from a position near the input end of the scanning signal line to which the scanning signal is supplied to a position far from the input end of the scanning signal line. The switching timing is set so that the change amount of the scanning signal voltage is the same between the position near the input end and the far position when the switch element is turned off.

  Further preferably, the timing control means in the display device of the present invention selects the switching timing according to at least one of display resolution and screen size by selecting data in a lookup table provided inside or outside. Can be set.

  Further preferably, the voltage generating means in the display device of the present invention is configured such that the first off-potential is a scanning signal voltage when the switch element is turned off at a position near the input end of each scanning signal line and a remote position thereof. The amount of change is set to be approximately the same.

  Further preferably, the voltage generating means in the display device of the present invention can set the first off potential to an arbitrary value.

  Further preferably, the voltage generating means in the display device of the present invention sets the first off potential according to at least one of display resolution and screen size.

  Further, preferably, the switch element in the display device of the present invention has a parasitic capacitance.

  Further preferably, the switch element in the display device of the present invention is a thin film transistor.

  Further preferably, the original off potential in the display device of the present invention is a voltage for controlling the switch element to be off.

  Further preferably, the amount of change in the scanning signal voltage in the display device of the present invention is such that the difference between the scanning signal high voltage for turning on the switching element and the scanning signal low voltage for turning off the switching element is With respect to the voltage value to which the pull-in voltage ΔV resulting from the parasitic capacitance of the element is added, this is the amount of change that changes between the position near the input end of the scanning signal line and its distant position. The parasitic capacitance of this switch element will be described. Since a plurality of switch elements are connected from a position near the input end of the scanning signal line to a position far away from the scanning signal line, the longer the scanning signal line length, the more the number of switch elements connected together with the resistance and capacitance of the scanning signal line. The capacity increases.

  According to the display device driving method of the present invention, the scanning signal in which a scanning signal high voltage for turning on the switching element is supplied to the switching element for each pixel unit arranged in a matrix form via the scanning signal line. In a method for driving a display device that displays an image on a display screen by supplying a video signal from a video signal line to a pixel electrode of each pixel unit via a switch element during a line selection period, the switch element is turned off. In the non-selection period of the scanning signal line for supplying the scanning signal low voltage to the scanning signal line, first, the first off potential set to a potential higher than the original off potential is supplied, and the predetermined period has elapsed. Later, a second off-potential set to the original off-potential is supplied, whereby the above object is achieved.

  Preferably, in the display device driving method of the present invention, at least one of the switching timing between the first off-potential and the second off-potential and the first off-potential is set as an input terminal of the scanning signal line. The amount of change in the scanning signal voltage is set to be approximately the same when the switch element is turned off between near and far.

  More preferably, the original off potential in the display device driving method of the present invention is a voltage for controlling the switching element to be off.

  More preferably, the amount of change in the scanning signal voltage in the driving method of the display device of the present invention is a difference between a scanning signal high voltage for turning on the switching element and a scanning signal low voltage for turning off the switching element. The voltage value to which the pull-in voltage ΔV resulting from the parasitic capacitance of the switch element is added is a change amount that changes between the position near the input end of the scanning signal line and its distant position.

  The operation of the present invention will be described below with the above configuration.

  Conventionally, in a display device using a switching element such as a TFT, the display voltage applied to each pixel portion is shifted downward by the pull-in voltage ΔV when the scanning signal voltage is turned off. In addition, the actual gate voltage (scanning signal voltage) varies greatly depending on the resistance and parasitic capacitance components of the scanning signal line (gate bus line) near and far from the input end, and the ΔV value differs at each location. When the panel is enlarged, flicker tends to be noticeable on the left and right sides of the screen.

  In the present invention, during the non-selection period, first, the scanning signal off voltage (gate low voltage VGL) is set to a first off potential higher than the original off potential, and an arbitrary constant at which the first off potential is output. After the period, the second off potential which is an original off potential lower than that potential is switched to. This makes it possible to reduce the difference in the pull-in voltage ΔV between near and far from the scanning signal input end, and to reduce left-right flicker. Since the scanning signal off voltage (gate low voltage VGL) is changed during the non-selection period of the scanning signal line, the charging time is not shortened as in Patent Document 1.

  The switching timing between the first off potential and the second off potential can be controlled by a dedicated switching timing control signal from timing control means such as a timing controller. In addition, this timing is set to an arbitrary value by referring to a lookup table (LUT) such as an EEPROM (Electrically Erasable Programmable ROM) provided in, for example, an ASIC (Application Specific Integrated Circuit) or outside the ASIC. Is possible. Furthermore, the first off potential can be set to an arbitrary value by voltage supply means such as a DC / DC converter.

  At least one of the switching timing between the first off potential and the second off potential and the first off potential is optimally adjusted according to each resolution of the display device, the screen size of the display panel, and the like, and the scanning signal (gate The amount of change in the scanning signal voltage (gate voltage) (gate high voltage VGH−gate low voltage VGL) is substantially the same in the non-selection period of the scanning signal line (when the gate is OFF), near and far from the signal input end. By setting so as to become, it becomes possible to reduce in-plane flicker on the left and right sides of the screen.

  As described above, according to the present invention, the change in the scanning signal voltage (gate voltage) during the non-selection period (when the gate is OFF) of the scanning signal line between the position close to and the distance from the input end (gate input end) of the scanning signal line. The amount can be approximated to reduce in-plane flicker on the left and right sides of the screen. In particular, the display quality can be improved in a display device such as a TFT-LCD having a large size and high definition.

Hereinafter, a case where the first and second embodiments of the display device of the present invention are applied to an active matrix liquid crystal display device (TFT-LCD) will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of a main part of an active matrix driving type liquid crystal display device according to a first embodiment of the present invention.

  In FIG. 1, a switch element driving unit 1A in an active matrix liquid crystal display device is a scanning signal line driving unit that selectively supplies a scanning signal (gate voltage signal) to a gate bus line 111 that is a scanning signal line. And a liquid crystal driving circuit substrate provided with a driver driving circuit 12 for timing driving the gate driver 11, and during the non-selection period (gate off period) of the gate bus line 111. A first off-potential set to a potential higher than the original off-potential is selectively supplied to the gate bus line 111, and after a predetermined period during which the first off-potential is supplied, the first off-potential set to the original off-potential is set. The 2 off potential is supplied to the gate bus line 111 via the gate driver 11.

  The driver drive circuit 12 includes a timing controller 121 as a timing control unit that outputs a gate start pulse that defines a vertical period of one screen and a gate clock that defines a scanning signal high voltage period (one horizontal period) to the gate driver 11. EEPROM 122 as storage means storing timing data used by the timing controller 121, gate high voltage VGH as a scanning signal high voltage for turning on the TFT in the gate driver 11, and two types of scanning for turning off the TFT. A DC / DC converter 123 as voltage generating means for outputting a gate low voltage VGL (first off signal V1 and second off signal V2) as a signal low voltage, and a control input terminal are connected to the timing controller 121 for signal selection. Signal input terminal Two VGL voltage output from the DC / DC converter 123 and a selector 124 as a connected signal selection means (gate low voltage VGL).

  The timing controller 121 outputs a VGL switching timing control signal for controlling the switching timing between the first off signal V1 and the second off signal V2 to the control terminal of the selector 124. This switching timing (output timing of the VGL switching timing control signal) is appropriately selected at the time of product shipment by selecting a look-up table (LUT) or other storage means (ROM) data set in the EEPROM 12 by the timing controller 121. It can be arbitrarily set by referring to the selected data.

  In the DC / DC converter 123, as the gate low voltage VGL, the first off signal V1 set to a potential higher than the original off potential and the second off signal set to an original off potential lower than the first off signal V1. A signal V2 and a gate high voltage VGH are generated and output. The first off signal V1 and the second off signal V2 can be set to arbitrary values by the DC / DC converter 123. That is, if two DC / DC converters are provided in the DC / DC converter 123, two voltages can be generated.

  The selector 124 selects (switches) one of the first off signal V1 and the second off signal V2 from the DC / DC converter 123 based on the VGL switching timing control signal from the timing controller 121, and the gate low voltage. Output to the gate driver 11 as VGL.

  Hereinafter, a driving method of the switch element driving unit 1A in the liquid crystal display device according to the first embodiment will be described.

  In the vicinity of the scanning signal line input end of the gate voltage signal (scanning signal), the gate voltage waveform is hardly dulled, and the voltage change amount (VGH−VGL) at the time of gate OFF shown in the above equation (1) increases. As shown in FIG. 2A, first, the gate low voltage VGL is set to a higher first OFF signal V1, and then, after an arbitrary fixed time, the second OFF which is the original OFF potential lower than that. Switch to signal V2. The switching timing is controlled by the output timing of the VGL switching timing control signal output from the timing controller 121 as shown in FIG.

  As a result, as shown in FIG. 2B, the gate signal change amount when the gate is off is approximated to a value of “VGH−V1” at a position near the input end of the gate voltage signal (scanning signal).

  On the other hand, as shown in FIG. 2 (c), at the position far from the input end of the gate voltage signal (scanning signal), the gate voltage waveform approaches the off potential (second off signal V2) while being dull. The potential of the first off signal V1 is not reached immediately. Since the gate low voltage VGL is switched to a lower potential (second off signal V2) while the potential of the first off signal V1 has not yet been reached, the gate voltage waveform becomes steeper with the second off signal V2 as the arrival point. Will drop. As a result, even if the gate low potential VGL is once fixed at the potential of the first off signal V1, the influence of the gate voltage signal at the far end of the scanning signal line input end is almost unchanged, and the potential of the second off signal V2 is maintained. Drop towards you.

  As a result, at the far end of the scanning signal line input end of the gate voltage signal, the gate voltage waveform is originally dull as shown in FIG. 2C, compared with the vicinity of the scanning voltage line input end of the gate voltage signal. By changing the gate low voltage VGL from a high potential (first off signal V1) to a low potential (second off signal V2) in the middle of the change amount of the signal, the vicinity of the scanning signal line input end of the gate voltage signal It is possible to adjust almost the same.

  That is, an approximate expression such as the following expression (2) is established.

Change amount ΔVG of gate voltage signal when gate is OFF (near input end) (VGH−V1)
≒ ΔVG (far from the input end) (Vth-V2) (2)
In the above formula (2), Vth indicates the actual threshold potential of the TFT (the TFT is turned off when the threshold voltage is equal to or lower than the Vth value), and VGH> Vth and V1> V2 are set.

  FIG. 3 is a waveform diagram showing the result of simulating the gate voltage waveform for the equivalent circuit of the gate bus line shown in FIG. By outputting the gate voltage waveform as shown in FIG. 2A from the gate driver 11, the gate voltage waveform as shown in FIG. 2B is supplied to the gate of the TFT at a position near the gate input end, and the gate input. At the far end position, a dull gate voltage waveform as shown in FIG. 2C is supplied to the gate of the TFT.

  In the switch element driving unit 1A in the liquid crystal display device of Embodiment 1, the potential value of the first off signal V1 and the timing of switching from the first off signal V1 to the second off signal V2 are the resolution and display of each liquid crystal display device. By finely adjusting according to the screen size of the panel, it is possible to further reduce the left and right in-plane flicker.

The switching timing from the first off signal V1 to the second off signal V2 can be freely changed by referring to an LUT preset in the EEPROM 12 connected to the timing controller 11.
(Embodiment 2)
FIG. 4 is a block diagram showing a configuration example of a main part of an active matrix liquid crystal display device according to Embodiment 2 of the present invention.

  In FIG. 4, in the switch element driving means 1B in the active matrix driving type liquid crystal display device, the EEPROM 122 on the driver driving circuit 12B side of the liquid crystal driving circuit substrate is built in the timing controller 121B. A selector 124 that selects the first off signal V1 and the second off signal V2 is built in the gate driver 11B. As a result, the circuit configuration can be further simplified and the manufacturing cost can be reduced as compared with the circuit configuration in the first embodiment.

  On the other hand, the DC / DC converter 123 can arbitrarily set at least the potential of the first off signal V1. Accordingly, it is possible to flexibly support display panels having various sizes and resolutions.

  As described above, according to the first and second embodiments, the gate off potential VGL (scanning signal low voltage) is first set to the potential of the first off signal V1 higher than the original off potential, and the first off signal V1 is After an arbitrary period of time to be supplied, the potential is switched to the potential of the second off signal V2, which is an original off potential lower than that. As a result, the amount of change in the gate signal when the gate is off in the vicinity of the gate input end is reduced to “ΔVGH−V1”, and the amount of change in the gate signal when the gate is off at the far end of the gate input end is “ΔVth−V2”. Can be approximated. As a result, the difference in the pull-in voltage ΔV generated between the vicinity of the input terminal of the gate voltage and the distant place is reduced without shortening the charging time itself as in the prior art, and the left and right plane flicker of the display screen is reduced. be able to.

  In the first and second embodiments, unlike the prior art disclosed in Patent Document 2, the purpose is not to reduce the pull-in voltage ΔV when the gate is OFF over the entire LCD screen. In the TFT LCD, the pull-in voltage ΔV The amount of change ΔVG of the gate signal that cannot be made uniform on the left and right of the screen due to the influence of the wiring delay of the gate bus line is made to be almost uniform on the left and right by switching the gate off potential, and flickers in the left and right planes It aims at reducing. Therefore, the technique of Patent Document 2 which aims to reduce the ΔV value of the entire screen by switching the gate-off potential instead of increasing the value of the auxiliary capacitor Ccs is a technique different from the present invention.

  In the prior art disclosed in Patent Document 1, the gate voltage waveform is forcibly blunted and gradually turned off during the charging period, so that the charging time is reduced. For this reason, when high-frequency driving is required as in a high-definition LCD, the display pixels cannot be sufficiently charged, and the application is often difficult. On the other hand, according to the present invention, it is possible to obtain the same effect as the conventional one without reducing the charging time as in Patent Document 1, and it is possible to cope with higher definition.

  Furthermore, in the first and second embodiments, the switching timing between the potential of the first off signal V1 and the potential of the second off signal V2 and the potential of the first off signal V1 are close to the input end of the scanning signal line 111. However, the present invention is not limited to this, and the potential of the first off signal V1 and the second off signal V2 are set so that the amount of change in the gate signal voltage is substantially the same when the TFT as the switching element is turned off. The change amount of the gate signal voltage is almost the same as the switching timing of the TFT as a switching element between the position close to and far from the input end of the scanning signal line 111. You may make it set so that it may become the same.

  Further, in the first and second embodiments, the plurality of scanning signal lines 111 and the plurality of video signal lines intersect, the control end is connected to the scanning signal line 111 near the intersection, and the video signal line near the intersection is connected to the video signal line. The present invention was applied to an active matrix liquid crystal display device in which a plurality of pixel portions each having a TFT having one driving end connected and a pixel electrode connected to a drain end serving as the other driving end of the TFT are arranged in a matrix. Although the case has been described, the present invention is not limited to this.

  As described above, in the case of an active matrix driving type liquid crystal display device, a source driver is provided as a video signal line driving means for selectively supplying video signals to a plurality of video signal lines, and a plurality of scanning signal lines 111 are provided. The gate driver 11 as a scanning signal line driving means for selectively supplying a scanning signal to the first signal is set to a potential higher than the original off potential of the scanning signal during the non-selection period of the scanning signal line 111. A switch element driving unit 1A for supplying an off potential to the scanning signal line 111 and supplying a second off potential set to the original off potential to the scanning signal line 111 via the gate driver 11 after a predetermined period of time. 1B is provided.

  As mentioned above, although this invention was illustrated using preferable Embodiment 1, 2 of this invention, this invention should not be limited and limited to this Embodiment 1,2. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of the specific preferred embodiments 1 and 2 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention is used in, for example, a television device or a graphics display device, and displays a liquid crystal display device that displays an image by supplying a display data signal to each of a plurality of two-dimensionally arranged pixel portions. In the field of the device and its driving method, it is possible to reduce the in-plane flicker on the left and right sides of the display screen by approximating the amount of change in the gate voltage when the gate is OFF near and far from the gate voltage input end. In particular, the display quality can be improved in a display device such as a liquid crystal display device (TFT-LCD) of an active matrix driving system that has been increased in size and definition.

1 is a block diagram illustrating a configuration example of a main part of an active matrix liquid crystal display device according to Embodiment 1 of the present invention. FIG. 4A and 4B are signal waveform diagrams for explaining a driving method of the display device according to the first embodiment of the present invention, in which FIG. 5A is a gate voltage waveform diagram at a driver output terminal, and FIG. (C) is a gate voltage waveform diagram far from the gate input end. FIG. 8 is a signal waveform diagram showing a result of simulating a gate voltage waveform for the equivalent circuit of the gate bus line shown in FIG. 7. It is a block diagram which shows the principal part structural example of the liquid crystal display device of the active matrix drive system which concerns on Embodiment 2 of this invention. It is an equivalent circuit diagram showing an example of a main part configuration of one pixel portion in a conventional active matrix driving type liquid crystal display device. (A) is a signal waveform diagram showing a gate driver output voltage signal (scanning signal) supplied to the gate of the TFT of FIG. 5, and (b) is a liquid crystal applied voltage (data signal) supplied to the pixel electrode of FIG. FIG. It is the equivalent circuit schematic of the gate bus line in the conventional TFT-LCD. FIG. 8 is a signal waveform diagram showing a comparison between gate voltage waveforms near and far from an input end of a gate voltage signal in the gate bus line of FIG. 7. It is a signal waveform diagram for demonstrating the conventional in-plane flicker reduction method currently disclosed by patent document 1. FIG.

Explanation of symbols

1A, 1B Switch element drive means 12, 12B Driver drive circuit 121, 121B Timing controller 122 EEPROM
123, 123B DC / DC converter 124 Selector 11, 11B Gate driver

Claims (21)

In a display device that performs screen display by supplying a display signal to each pixel unit arranged in a two-dimensional manner on a display screen through a switch element that is controlled to be turned on or off based on a scanning signal.
As the scanning signal, there is provided switch element driving means for outputting a first off potential and a second off potential which is an original off potential lower than the first off potential to each switch element when the switch element is controlled to be off. Display device. The switch element driving means includes
Voltage generating means for generating the first off potential and the second off potential;
Timing control means for controlling the switching timing of the first off potential and the second off potential;
The display device according to claim 1, wherein the first off potential is supplied to the switch element for a predetermined period. A plurality of scanning signal lines and a plurality of video signal lines intersect, a switching element having a control end connected to the scanning signal line in the vicinity of the intersection, and one drive end connected to the video signal line in the vicinity of the intersection; A plurality of pixel portions each having a pixel electrode connected to the other drive end of the switch element are arranged in a matrix,
Video signal line driving means for selectively supplying video signals to the plurality of video signal lines is provided,
Scanning signal line driving means for selectively supplying a scanning signal to the plurality of scanning signal lines, and set to a potential higher than the original off potential of the scanning signal during a non-selection period of the scanning signal line; A switch for supplying a first off potential to the scanning signal line, and supplying a second off potential set to the original off potential to the scanning signal line via the scanning signal line driving means after a predetermined period of time. A display device provided with element driving means. The switch element driving means includes
Voltage generating means for generating the first off potential and the second off potential;
Timing control means for controlling the switching timing of the first off potential and the second off potential;
4. The display device according to claim 3, wherein the first off potential is supplied to the scanning signal line through the scanning signal line driving unit for a predetermined period.   The switch element driving means further comprises signal selection means for switching between the first off potential and the second off potential based on a switching timing control signal from the timing control means. Display device.   The switch element driving unit includes a signal selection unit configured to switch between the first off potential and the second off potential based on a switching timing control signal from the timing control unit. The display device according to claim 4, wherein the display device is provided externally and the selection output from the signal selection means is a scanning signal low voltage. The timing control means outputs a start signal defining one vertical period and a clock signal defining one horizontal on period of the scanning signal to the scanning signal line driving means,
The voltage generating means outputs a scanning signal high voltage to the scanning signal line driving means,
The display device according to claim 6, wherein the scanning signal line driving unit generates the scanning signal using the start signal, the clock signal, the scanning signal high voltage, and the scanning signal low voltage.   The display device according to claim 2, wherein the timing control unit can set the switching timing to an arbitrary value.   The timing control means includes a plurality of switch elements connected from a position near the input end of the scanning signal line to which the scanning signal is supplied to a position far from the input end of the scanning signal line. The display device according to claim 2, wherein the switching timing is set so that a change amount of a scanning signal voltage becomes the same when the switch element is turned off.   The timing control means can set the switching timing according to at least one of display resolution and screen size by selecting data in a lookup table provided inside or outside. The display device described in 1.   The display device according to claim 2, wherein the voltage generation unit is capable of setting the first off potential to an arbitrary value.   The voltage generating means sets the first off potential so that the amount of change in the scanning signal voltage is substantially the same when the switch element is turned off at a position near the input end of each scanning signal line and a position far from the input terminal. The display device according to claim 2, wherein the display device is set.   The display device according to claim 2, wherein the voltage generation unit sets the first off potential according to at least one of display resolution and screen size.   The display device according to claim 1, wherein the switch element has a parasitic capacitance.   The display device according to claim 1, wherein the switch element is a thin film transistor.   The display device according to claim 1, wherein the original off potential is a voltage for controlling the switch element to be off.   The amount of change in the scanning signal voltage is the difference between the scanning signal high voltage for turning on the switching element and the scanning signal low voltage for turning off the switching element, and the pull-in voltage ΔV due to the parasitic capacitance of the switching element. 13. The display device according to claim 9, wherein the voltage value is a change amount that changes between a position near the input end of the scanning signal line and a position far from the position of the scanning signal line. A scanning signal high voltage for turning on the switching element is supplied to the switching element for each pixel unit arranged in a matrix form through the scanning signal line, during the selection period of the scanning signal line. In a driving method of a display device that displays an image on a display screen by supplying a video signal to a pixel electrode for each pixel unit via the switch element,
In a non-selection period of the scanning signal line for supplying the scanning signal line with the scanning signal low voltage for turning off the switch element, first, a first off potential set to a potential higher than the original off potential is supplied. A driving method of a display device that supplies a second off potential set to the original off potential after the predetermined period has elapsed.   The switching timing between the first off-potential and the second off-potential and at least one of the first off-potential is set at a position close to and far from the input end of the scanning signal line when the switch element is turned off. The method for driving a display device according to claim 15, wherein the change amount of the scanning signal voltage is set to be substantially the same.   The method of driving a display device according to claim 18, wherein the original off potential is a voltage for controlling the switching element to be off.   The amount of change in the scanning signal voltage is the difference between the scanning signal high voltage for turning on the switching element and the scanning signal low voltage for turning off the switching element, and the pull-in voltage ΔV due to the parasitic capacitance of the switching element. The driving method of the display device according to claim 19, wherein the voltage value is a change amount that varies between a position near the input end of the scanning signal line and a distant position thereof.

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