JP2006166256A - Image conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image conversion apparatus which obtains an interlace image of a high image updating speed from an interlace image of a low image updating speed. <P>SOLUTION: An image input unit 110 inputs image data of which one frame is constituted of a plurality of field images. An image signal arithmetic unit 111 generates a plurality of different field images from each of field images constituting the image data. Images of both fields are calculated from an interlaced image signal of one field. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image conversion apparatus, and more particularly to an image conversion apparatus that performs conversion processing of an image update speed and the number of pixels.

  The demand for higher definition of images is increasing, and a moving image camera having about 1 million pixels per frame has been put into practical use.

  A CCD (Charge Coupled Device), which is a general solid-state imaging device, cannot increase the driving speed indefinitely. Therefore, when the number of pixels of an image is increased, the image update speed must be decreased. If it is about 480,000 pixels, it is possible to output at an image update speed according to the current television (hereinafter referred to as TV) standard, but it is difficult if the number of pixels exceeds 1 million pixels. Although it is possible to improve the image update speed by increasing the signal readout path of the CCD, it is a trade-off with the circuit amount and the like.

  In addition, although the resolution of the imaging system is increasing, there is a demand that the display system does not increase in resolution at the same time, and it is desired to use a display device compliant with the current TV standard.

  The number of lines and the frame rate are determined by TV standards such as NTSC and PAL. Therefore, for example, when displaying an image having a larger number of pixels constituting one frame than the TV standard but a slower image update speed on a display device compliant with the current TV standard, the number of pixels of the image and the image update speed. Must be converted to meet the TV standard.

  An example of a conventional image conversion apparatus is disclosed in Patent Document 1. FIG. 8 shows a conventional image conversion apparatus disclosed in the document.

  8 includes a CCD 12, an A / D conversion unit 14, a signal processing unit 16, a compression / decompression unit 18, a clock 19, a built-in memory 20, a memory control circuit 22, a memory card 24, a video encoder 26, a D / D A conversion unit 28, switch 30, built-in monitor (NTSC) 32, time axis conversion unit 33, terminal 34, connection cable 35, external monitor (PAL) 36, camera control circuit 38, CPU 40, system controller 42 and operation switch 44 I have.

  The CCD 12 is controlled by the camera control circuit 38, and converts the light from the subject into an electrical signal, thereby recording one frame image signal at 30 frames (30 fps) or 15 frames per second (15 fps). Output at the rate. Although the camera has PAL specifications, the camera control circuit 38 operates according to NTSC.

  The output frame image signal is converted into a digital signal by the A / D conversion circuit 14 for each frame, subjected to white balance and gamma correction by the signal processing circuit 16, and controlled by the memory control circuit 22. The image data is temporarily stored in the built-in memory 20 as frame image data.

  The built-in memory 20 includes data recording areas (A) and (B), a compressed data storage area (C), and other areas (D).

  The frame image data stored in the data recording area (A) is compressed by the compression / decompression circuit 18 and stored in the compressed data recording area (C) of the built-in memory 20. By repeating the above operation and recording data to the memory card 24 sequentially from the compressed data recording area (C) while storing a plurality of frame compressed image data in the compressed data recording area C) of the built-in memory 20. , 30 fps or 15 fps frame compressed image data is obtained.

  The memory control circuit 22 is driven based on the clock signal from the clock 19. The frequency of the clock signal is switched between 30 fps and 15 fps so that a desired recording frame rate can be obtained in the memory control circuit 22.

When a moving image file recorded at 15 fps is output at 50 fields per second, 4 frames are obtained from one frame image data according to the remainder obtained by dividing the value of the counter N indicating the order of the frame image data to be reproduced by 3. Conversion of the image update rate is realized by selecting whether to generate one field image data or three field image data.
JP 2001-313896 A (page 2-3, FIG. 1)

  However, in the conventional image conversion apparatus, the original image is a frame image. Therefore, when an interlaced image is used as an input, the conventional image conversion apparatus cannot cope.

  The present invention has been made to solve the conventional problems, and an object thereof is to provide an image conversion apparatus capable of obtaining an interlaced image having a high image update speed from an interlaced image having a low image update speed. is there.

  The image conversion apparatus according to the present invention includes an image input means for inputting image data in which one frame is composed of a plurality of field images, and an image for generating a plurality of different field images from each field image constituting the image data. Signal calculating means.

  With this configuration, both input and output image data are image data in which one frame is composed of a plurality of fields, and a plurality of different field images are generated from one field image of the input image. An interlaced image with a high image update rate can be obtained from the image.

  In the image conversion apparatus of the present invention, the image signal calculation means includes an FIR filter, and calculates the image signals of both fields from the image signals of one of the fields constituting the interlaced image signal. With this configuration, an interlaced image with a high image update rate can be suitably obtained from an interlaced image with a low image update rate.

  Furthermore, the image conversion apparatus according to the present invention provides an effective image for n lines in the m line period including blanking so that the number of input lines versus the number of output lines in one input field is m: n. A scheduler is provided for performing processing scheduling that is calculated and output by the signal calculation means.

  With this configuration, even when image input is continuous and the number of lines created by image conversion is somewhat larger than the number of input image lines, an interlaced image with a high update rate can be obtained without increasing the processing speed of computation and memory access. Obtainable.

  Also, the image conversion processing method of the present invention acquires an interlaced image signal, and calculates an image signal of both fields from an image signal of one field constituting the acquired image signal. With this method, an interlaced image with a high image update rate can be obtained from an interlaced image with a low image update rate, as in the above-described aspect of the image conversion apparatus.

  Another aspect of the present invention is a program. The program acquires an interlaced image signal, and calculates an image signal of both fields from an image signal of one field constituting the acquired image signal. Is executed on the computer. With this program, the image conversion function of the present invention can be realized by an MPU, DSP, or the like.

  Another aspect of the present invention is a computer-readable recording medium, which acquires an interlaced image signal, and from both of the image signals of one field constituting the acquired image signal. Is recorded. With this recording medium, the program of the recording medium is read and executed by a computer, whereby the image conversion function of the present invention can be realized by an MPU, DSP, or the like.

  According to the present invention, both the input and output image data are image data in which one frame is composed of a plurality of fields, and a plurality of different field images are generated from one field image of the input image. An effect is obtained that an interlaced image having a high image update speed can be obtained from a slow interlaced image.

  Hereinafter, an image conversion apparatus according to an embodiment of the present invention will be described with reference to the drawings.

  An image conversion apparatus according to a first embodiment of the present invention is shown in FIG. In FIG. 1, the image conversion apparatus 100 includes an image input unit 110, an image signal calculation unit 111, and an image storage unit 112.

  The image input unit 110 inputs interlaced image data. The input image data is, for example, data generated by a CCD. In the input interlaced image data, one frame is composed of a plurality of field images.

  The image signal calculation unit 111 generates a plurality of different field images from each field image constituting the input image data. That is, the image signal calculation unit 111 calculates the images of both fields from the image signal of one field. The image signal calculation unit 111 is configured by a dedicated LSI, ASIC, or the like. The processing of the image signal calculation unit 111 will be described in detail later.

  The image storage unit 112 stores the data output from the image signal calculation unit 111. The image storage unit 112 has a function of rearranging the data calculated by the image signal calculation unit 111. That is, the image storage unit 112 is controlled by the memory control unit, stores the image data of the calculation result of the image signal calculation unit 111, and outputs the image data in a different order. Thereby, image data is output for each field. The image storage unit 112 is composed of a frame memory.

  The image conversion apparatus 100 may be realized by an MPU, DSP, or the like executing a program. In this case, a program that realizes the function of the image conversion apparatus 100 is executed by the MPU or the like. This program may be read by a computer from a computer-readable recording medium.

  Next, image conversion processing by the image conversion apparatus 100 will be described with reference to FIGS. 1, 2, and 3. Here, for the sake of easy understanding, the following specific example is used.

In the specific example of the present embodiment, the input image has the following format.
Total number of pixels 1525.3 horizontal x 1575 vertical Effective number of pixels 1280 horizontal x 960 vertical Pixel aspect ratio 1: 1
Image aspect ratio 4: 3
Image update rate 29.97 fields per second Sampling rate 1525.3 × 787.5 × 29.97≈36.00 MHz

The output image is assumed to be NTSC and has the following format.
Total number of pixels 910 horizontal x 525 vertical Effective number of pixels 768 horizontal x 480 vertical Pixel aspect ratio 1: 1
Image aspect ratio 4: 3
Image update rate 59.94 fields per second Sampling rate 910 × 525 × 29.97≈14.32 MHz

At this time, the following image conversion is required.
(1) The vertical direction is converted into effective pixels (1/2). (2) The horizontal direction is converted into effective pixels (3/5). (3) The image update speed is set to (2/1). First, (1) and (3) will be described in detail. The image signal obtained by the image input unit 110 conforms to the input image format shown above.

  The input image is in an interlace format. If two fields constituting one frame are an A field and a B field, the positional relationship between the two fields is as shown in the input signal 150 of FIG. In the input signal 150, the A / B field is mixed. The portion where "A" and "B" are written is image data, and the portion where "-" is written is dummy data inserted for up-sampling of sampling rate conversion, which will be described later. Is 0. Input line numbers 1, 3, 5, 7, 9, 11, and 13 are A fields, and input line numbers 2, 4, 6, 8, 10, 12, and 14 are B fields. The first frame image is obtained. Since the field readout format is used, the A field and the B field are alternately input from the image input unit 110 every (1 / 29.97) seconds. That is, the A field input signal 151 and the B field input signal 154 in FIG. 2 are alternately input.

  When the number of pixels in the vertical direction of the input image, that is, the number of lines and the image update speed are converted into the number of lines of the output image and the image update speed in the specific example of this embodiment, the number of lines is (1/2). In other words, it is required to be halved. The image update speed is double, that is, two fields are created from one input field. Therefore, the number of lines created from the input 1 field is (2/2), that is, equal magnification. The number of lines of an image created as one field image is half, but since a total of two fields are created, the number of output lines is equal to the number of input lines.

  Generally, enlargement / reduction of an image is given as a conversion of a sampling rate. When performing reduction with a magnification of m / n (m, n is an integer, m <n), the sampling rate is increased by inserting (m−1) zeros between sample points representing image data. (Up-sampling), band reduction at half the output frequency so that aliasing distortion does not occur after image reduction, and re-sampling (down-sampling) the band-limited sample sequence every n pieces to reduce the magnification m / n It can be performed.

  Here, the band limiting filter is a low-pass filter. Coefficients and the like are determined by a trade-off between the frequency characteristics and the processing amount / circuit amount.

  In image signal filtering, an FIR filter is preferably used because of the stability of the linear phase and system. In an FIR filter, it is effective to use a multi-tap configuration in order to achieve both a steep attenuation characteristic and passband flatness at a high level. However, in the image signal processing, the number of taps of the FIR filter in the vertical direction means the necessity of the same number of line memories. From the viewpoint of circuit amount, the line memory cannot be increased without limit.

  It is assumed that the image signal necessary for the filtering described above is input from the image signal input unit 110. It may be realized by a line memory or a frame memory. In the present embodiment, it is assumed that 4-line data is obtained from the image input unit 110. And the process of the image signal calculating part 111 is performed as follows.

  The input image as the number of effective pixels is field image data of 1280 × 480 pixels, and is updated every (1 / 29.97) seconds. The spatial phase of the image is shown in FIG. 2 by an A field input signal 151 and a B field input signal 154.

  Here, in this specification, the field of the input signal is appropriately referred to as an input field, the input A field, the input B field, and the like, and the field of the output signal is referred to as an output field, an output A field, and an output B field.

  In the present embodiment, two fields of output A / B are generated from the input signal 151 of the input A field and the input signal 154 of the input B field.

  The output A / B field generated from the input signal 151 in the input A field is the output signal 152 in the output A field and the output signal 153 in the output B field shown in FIG. In the specific example in the present embodiment, the spatial phase of the output A field and the output B field generated from the input A field is set at a distance of 3: 1 when viewed from two input lines.

  On the other hand, the output A / B fields generated from the input signal 154 in the input B field are the output signal 155 in the output A field and the output signal 156 in the output B field shown in FIG. In the specific example in the present embodiment, the spatial phase of the output A field and the output B field generated from the input B field is set at a position of a distance 1: 3 when viewed from two input lines.

  The input A / B fields have different spatial phases, but the output signal 152 of the output A field generated from the input signal 151 of the input A field and the output signal of the output A field generated from the input signal 154 of the input B field The spatial phase of 155 is equal. Similarly, the spatial phase of the output signal 153 of the output B field generated from the input signal 151 of the input A field and the output signal 156 of the output B field generated from the input signal 154 of the input B field are also equal. The relative spatial phase of the input / output signals is not limited to the above.

As a specific example in the present embodiment, it is considered to use a 17-tap FIR filter designed to have an appropriate cut-off frequency in order to limit the band by sampling rate conversion in the line direction. Filter coefficient FIRcoef
FIRcoef = (K0, K1, K2, K3, K4, K5
K6, K7, K8, K9, K10, K11,
(K12, K13, K14, K15, K16)
And The coefficient corresponding to the center tap is K8. At this time, if the A field data in the output line number 3 of the output signal 152 in FIG. 2 is the output A3 (A), the output A3 (A) is the A in the input line numbers 3, 5, 7, and 9 of the input signal 151. Using field data A3, A5, A7, A9 and FIRcoef, calculation is performed as follows.

  Output A3 (A) = K1 * A3 + K5 * A5 + K9 * A7 + K13 * A9

  As is apparent from the calculation contents, the dummy data inserted between the signals for up-sampling does not appear in the actual calculation because the value is 0.

  Similarly, assuming that the A field data in the output line number 3 of the output signal 155 in FIG. 2 is the output A3 (B), the output A3 (B) is in the input line numbers 4, 6, 8, and 10 of the input signal 154. It is calculated as follows using B field data B4, B6, B8, B10 and FIRcoef.

  Output A3 (B) = K3 * B4 + K7 * B6 + K11 * B8 + K15 * B10

  This is also clear from the calculation contents, but the dummy data inserted between the signals for upsampling has a value of 0, so it does not appear in the actual calculation. However, it is necessary to switch the coefficient depending on the field of the input image signal.

  The image data of the calculation result of the image signal calculation unit 111 is supplied to the image storage unit 112, and is output as image data with the image update speed converted through the image storage in the image storage unit 112. As described above, the image storage unit 112 is a frame memory or the like, and stores images in units of frames.

  An outline of the processing of the image storage unit 112 is shown in FIG. In FIG. 3, the number of lines is omitted, and one input field is 10 lines and one output field is 5 lines.

  In FIG. 3, the input signal 162 and the output signal 163 of the image storage unit 112 are divided into an input signal vertical synchronization signal (VD) 160, an input signal horizontal synchronization signal (HD) 161, and an output signal vertical synchronization signal (VD). 164, together with an output signal horizontal synchronizing signal (HD) 165.

  The input signal 162 of the image storage unit 112 is an output signal of the image signal calculation unit 111. In the data output from the image signal calculation unit 111, the output for the A field and the output for the B field appear alternately. As a result, in the input signal 162, (a, f, b, g, c, h, d , i, e) in this order (a, b, c... are data for one line).

  On the other hand, in the output signal 163, the A field data is (a, b, c, d, e), and the B field data is (f, g, h, i). In order to realize such processing, the image data is temporarily stored in the frame memory, and the rearranged image data is output. Thereby, an image signal is obtained for each forward data frame of the A field and the B field. Regarding the rearrangement output, the output signal 163 in FIG. 3 is output after one frame of input, but is not limited to this timing.

  In the present embodiment, the above-described image storage unit has been described on the assumption that the frame memory is located at the last stage of processing. However, by increasing the capacity at the front stage and doubling the image output speed, The target effect of the present case can also be obtained by performing processing for outputting different fields in the input image twice, that is, in the first time and the second time. Such an image storage unit may be provided as a part of the image signal calculation unit 111 so as to perform a storage process before the calculation process. When the image signal calculation unit 111 is a circuit such as an LSI, a part of the circuit may be an image storage unit.

  In the above description, the image conversion in the vertical direction has been described. For horizontal image conversion, reduction from 1280 pixels, which are effective pixels in the horizontal direction, to 768 pixels may be performed at any point in the signal processing. Processing immediately after the image input unit 110 is preferable from the viewpoint of overall processing speed. In this case, the horizontal image conversion unit may be a part of the image signal calculation unit 111. When the image signal calculation unit 111 is a circuit such as an LSI, a part of the circuit may be a horizontal image conversion unit. The horizontal reduction process may be a thinning process. In this case, acceptance of image quality deterioration is required. Further, reduction processing may be performed by sampling rate conversion using a plurality of horizontal pixels, aiming at high image quality. Thus, the reduction process is a trade-off between image quality and processing amount.

  In this embodiment, specific numerical values are given for the size of the input image, the number of filter taps, etc., but the present invention is not limited to these values.

  The image conversion apparatus according to the first embodiment of the present invention has been described above. As described above, according to the present embodiment, both input and output image data is image data in which one frame is composed of a plurality of fields, and a plurality of different field images are generated from one field image of the input image. Therefore, an interlaced image with a high image update speed can be obtained with sufficiently good image quality from an interlaced image with a low image update speed.

  Next, an image conversion apparatus according to a second embodiment of the present invention is shown in FIG. 4 has substantially the same configuration as that of the image conversion apparatus 100 according to the first embodiment shown in FIG. 1, that is, the image input unit 210 and the image signal of the image conversion apparatus 200. The calculation unit 211 and the image storage unit 212 have the same configurations as the image input unit 110, the image signal calculation unit 111, and the image storage unit 112 of the image conversion apparatus 100 in FIG. In the following description, description of matters overlapping with those of the first embodiment will be omitted as appropriate.

  As shown in FIG. 4, the image conversion apparatus 200 according to the second embodiment includes a scheduler 215 as a difference from the image conversion apparatus 100 according to the first embodiment. . The scheduler 215 generates an execution timing signal for image signal calculation in the image signal calculation unit 211, and supplies the timing signal to the image signal calculation unit 211. More specifically, the scheduler 215 performs processing for the image signal calculation unit 211 to calculate and output an effective image for n lines in an m line period including blanking, as will be described below using a specific example. Thus, the number of input lines versus the number of output lines in one input field becomes m: n.

  Next, image conversion processing by the image conversion apparatus 200 will be described with reference to FIGS. 4, 5, 6, and 7. In the description of this embodiment, the following specific example is used.

First, the input image in the present embodiment has the following format.
Total number of pixels 1536 horizontal x 1875 vertical Effective number of pixels 1280 horizontal x 960 vertical Pixel aspect ratio 1: 1
Image aspect ratio 4: 3
Image update rate 25 fields per second Sampling rate 1536 x 1875 x 12.5 = 36.00 MHz

The output image is assumed to be PAL, and has the following format.
Total number of pixels 908 horizontal x 625 vertical Effective number of pixels 768 horizontal x 576 vertical Pixel aspect ratio 1: 1
Image aspect ratio 4: 3
Image update rate 50 fields per second Sampling rate 908 × 625 × 25 = 14.1875 MHz

At this time, the following image conversion is required.
(1) The vertical direction is converted into effective pixels (3/5). (2) The horizontal direction is converted into effective pixels (3/5). (3) The image update speed is set to (2/1). First, (1) and (3) will be described in detail.

  The input image is in an interlace format. If two fields constituting one frame are an A field and a B field, the positional relationship between both fields is as shown in the input signal 250 of FIG. In the input signal 250, the A / B field is mixed. The portion where “A” and “B” are written is image data, and the portion where “−” is written is dummy data inserted for up-sampling of sampling rate conversion, and the value is 0 It is. Input line numbers 1, 3, 5, 7, 9, 11, and 13 are the A field, and input line numbers 2, 4, 6, 8, 10, and 12 are the B field. It becomes a frame image. Since the field readout format is used, the A field and the B field are alternately input from the image input unit 210 every (1/25) seconds. That is, the A field input signal 251 and the B field input signal 254 in FIG. 5 are alternately input.

  When the number of pixels in the vertical direction of the input image, that is, the number of lines and the image update speed are converted into the number of lines of the output image and the image update speed in the specific example of this embodiment, the number of lines is (3/5). Is required. The image update rate is double, that is, two fields A and B are created from one input field. Therefore, the number of lines created from the input 1 field is (6/5). It must cope with the number of lines to be created being larger than the number of input lines. The calculation process for converting the input image data is performed by the image signal calculation unit 211 as follows.

  The input image as the number of effective pixels is field data of 1280 × 480 pixels and is updated every (1/25) seconds. The spatial phase of the image is shown in FIG. 5 by the A field input signal 251 and the B field input signal 254.

  As in the first embodiment, in this embodiment, the input signal field is appropriately referred to as an input field, an input A field, an input B field, and the like, and the output signal field is an output field and an output A field. This is called an output B field.

  In the present embodiment, two fields of output A / B are generated from the input signal 251 in the input A field and the input signal 254 in the input B field.

  The output A / B fields generated from the input signal 251 in the input A field are the output signal 252 in the output A field and the output signal 253 in the output B field shown in FIG.

  The output A / B field generated from the input signal 254 in the input B field is the output signal 255 in the output A field and the output signal 256 in the output B field shown in FIG.

  The input A / B fields have different spatial phases, but the output signal 252 of the output A field generated from the input signal 251 of the input A field and the output signal of the output A field generated from the input signal 254 of the input B field The spatial phase with 255 is equal. Similarly, the spatial phase of the output signal 253 of the output B field generated from the input signal 251 of the input A field and the output signal 256 of the output B field generated from the input signal 254 of the input B field are also equal.

Spatial phase adjustment is realized by applying a band-limiting filter used for sampling rate conversion. Consider using a 23-tap FIR filter to limit the bandwidth with sampling rate conversion. Filter coefficient FIRcoef
FIRcoef = (K0, K1, K2, K3, K4, K5
K6, K7, K8, K9, K10, K11,
K12, K13, K14, K15, K16,
(K17, K18, K19, K20, K21, K22)
And The coefficient corresponding to the center tap is K11. At this time, the output A field data of the output line numbers A3, A5, and A7 shown in the output signal 252 of FIG. If the output B field data of the output line numbers 4, 6, and 8 shown are output B4 (A), output B6 (A), and output B8 (A), these data are the input A field data of the input signal 251 and the FIRcoef. Is calculated as follows (inputs after A13 are not shown). A3, A5, A7,... Are input A field data in input line numbers 3, 5, 7,.

Output A3 (A) = K5 * A3 + K11 * A5 + K17 * A7
Output A5 (A) = K1 * A5 + K7 * A7 + K13 * A9 + K19 * A11
Output A7 (A) = K3 * A9 + K9 * A11 + K15 * A13 + K21 * A15
Output B4 (A) = K0 * A3 + K6 * A5 + K12 * A7 + K18 * A9
Output B6 (A) = K2 * A7 + K8 * A9 + K14 * A11 + K20 * A13
Output B8 (A) = K4 * A11 + K10 * A13 + K16 * A15 + K22 * A17

  As is apparent from the calculation contents, the dummy data inserted between the signals for up-sampling does not appear in the actual calculation because the value is 0.

  Similarly, the output A field data of output line numbers 3, 5, and 7 shown in the output signal 255 of FIG. 5 are output A3 (B), output A5 (B), and output A7 (B). If the output B field data of output line numbers 4, 6, and 8 shown in FIG. 5 are output B4 (B), output B6 (B), and output B8 (B), these data are the same as the input B field data of the input signal 254. It is calculated as follows using FIRcoef. B2, B4, B6,... Are input B field data in input line numbers 2, 4, 6,.

Output A3 (B) = K2 * B2 + K8 * B4 + K12 * B6 + K18 * B8
Output A5 (B) = K4 * B6 + K10 * B8 + K16 * B10 + K22 * B12
Output A7 (B) = K0 * B8 + K6 * B10 + K12 * B12 + K18 * B14
Output B4 (B) = K3 * B4 + K9 * B6 + K15 * B8 + K21 * B10
Output B6 (B) = K5 * B8 + K11 * B10 + K17 * B12
Output B8 (B) = K1 * B10 + K7 * B12 + K13 * B14 + K19 * B16

  This is also clear from the calculation contents, but the dummy data inserted between the signals for upsampling has a value of 0, so it does not appear in the actual calculation.

  Here, as shown in the above equation, three kinds of combinations of coefficients are generated in order to obtain a certain field output. That is, the coefficients need to be switched according to the field and line number of the input image signal.

  Next, the function of the scheduler 215 will be described. In the present embodiment, the number of lines created from one input field is (6/5), and the number of output lines created is larger than the number of input lines. That is, it may be necessary to create two lines for one input line. An outline of the processing will be described with reference to FIGS.

  First, in FIG. 6, the input signals 262 and 263 and the output signal 264 of the image storage unit 212 are converted into an input signal vertical synchronization signal (VD) 260, an input signal horizontal synchronization signal (HD) 261, and an output signal vertical synchronization signal. (VD) 265 and an output signal horizontal synchronizing signal (HD) 266 are shown. In FIG. 6, the number of lines is omitted, and the input 1 field is 12 lines and the output 1 field is 6 lines.

  The image storage unit 212 is a frame memory that stores images in units of frames, and data is output from the image signal calculation unit 211 to the image storage unit 212. As shown in FIG. 6, the input signal 262 of the image storage unit 212 is (a, b, c, d, e, f), and the input signal 263 is (g, h, i, j, k). The input signals 262 and 263 are output signals of the image signal calculation unit 211, and the generation timings of b and h and e and j are simultaneous as shown in the figure.

  In order to realize such processing, the timing of outputting data to the image storage unit 212 is adjusted. As shown in FIG. 7, an image signal calculation execution timing signal 273 (or output image processing execution timing signal) different from the horizontal synchronization signal 270 is provided, and the image input unit 210 inputs data at the timing of the image signal calculation execution timing 273. At the same timing, the image signal calculation unit 211 captures data and switches the filter coefficient.

  Based on this timing signal, the image signal calculation unit 211 performs calculation over one or more horizontal effective periods and horizontal blanking periods.

  The input signal 262 and the input signal 263 in FIG. 6 are data generated by the image signal calculation unit 211 as described above. The illustrated data is processed at the timing of the output image signal 272 in FIG. 7, stored in the frame memory, and output in the order of the output signal 264 in FIG. The output for the A field and the output for the B field appear alternately, and thus the image update speed is converted through the accumulation of frame images.

  In the present embodiment, the description has been made assuming that the frame memory is located at the last stage of the processing. However, the present invention is not limited to this, and this point is as described in the first embodiment. is there.

  In the above description, the image conversion in the vertical direction has been described. For horizontal image conversion, reduction from 1280 pixels, which are effective pixels in the horizontal direction, to 768 pixels may be performed at any point in the signal processing. The processing in the horizontal direction is as described in the first embodiment.

  In the present embodiment, specific numerical values are given for the size of the input image, the number of filter taps, and the like. However, the present invention is not limited to these values, and this point is also the first embodiment. As explained in.

  The image conversion apparatus 200 according to the second embodiment of the present invention has been described above. According to the present embodiment, the effects of the first embodiment can be obtained, and even when the image input is continuous and the number of lines created by image conversion is somewhat larger than the number of input image lines, the calculation is performed. In addition, an interlaced image with a high update rate can be obtained without increasing the processing speed of memory access.

  In the first and second embodiments described above, the function of the image conversion apparatus can be recorded as a program on a recording medium such as a magnetic disk, a magneto-optical disk, or a ROM. Therefore, the function of the image conversion apparatus can be realized by reading this recording medium with a computer and executing it with an MPU, DSP, or the like.

  In addition, this invention is not limited to the above-mentioned embodiment, Of course, those skilled in the art can modify the above-mentioned embodiment within the scope of the present invention.

  As described above, the image conversion apparatus according to the present invention has an effect that an interlace image with a high image update speed can be suitably obtained from an interlace image with a low image update speed, and is an image conversion apparatus such as an imaging apparatus. Useful.

1 is a block diagram showing an image conversion apparatus according to a first embodiment of the present invention. Schematic diagram showing image conversion processing using spatial phase Schematic diagram showing image conversion processing in time series The block diagram which shows the image converter in the 2nd Embodiment of this invention Schematic diagram showing image transformation processing using spatial phase Schematic diagram showing image conversion processing in time series Schematic diagram of processing timing The figure which shows the conventional image converter

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image converter 110 Image input part 111 Image signal calculating part 112 Image storage part

Claims (6)

  Image input means for inputting image data in which one frame is composed of a plurality of field images, and image signal calculation means for generating a plurality of different field images from each field image constituting the image data An image conversion apparatus characterized by the above.   2. The image conversion apparatus according to claim 1, wherein the image signal calculation unit includes an FIR filter and calculates an image signal of both fields from each one of the image signals constituting the interlaced image signal. .   Processing for calculating and outputting effective images for n lines by the image signal calculation means in an m line period including blanking so that the number of input lines versus the number of output lines in one input field is m: n. The image conversion apparatus according to claim 1, further comprising a scheduler for performing scheduling.   An image conversion processing method comprising: obtaining an interlaced image signal, and calculating an image signal of both fields from an image signal of one field constituting the acquired image signal.   A program that acquires an interlaced image signal and causes a computer to execute image conversion processing for calculating an image signal of both fields from an image signal of one field constituting the acquired image signal.   A computer-readable recording medium having recorded thereon an image conversion processing program for acquiring an interlaced image signal and calculating an image signal of both fields from an image signal of one field constituting the acquired image signal.

Images