JP2006162492A - Semiconductor testing apparatus and test system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus and a test system for improving the stability in test quality by self-compensating the noise superimposed on a voltage applied to a device under test. <P>SOLUTION: A detection circuit 5 is provided for detecting the electrical load factors, affecting test results occurring at testing of a semiconductor device 4 from the electrical signal applied to input/output terminals of the semiconductor device 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor test apparatus and a test system. In particular, the present invention relates to self-compensation for noise and spike voltage generated in a test system constituting an IC / LSI tester for performing an IC / LSI electrical characteristic test and a function test. The present invention relates to a semiconductor test apparatus and a test system characterized by the configuration for the above.

  With the recent increase in integration and functionality of IC / LSIs (devices), customer requirements for device performance testing have become increasingly severe, and the competitive relationship of “device performance vs. tester performance” has been established. In order to guarantee the performance of the device, it is necessary to improve the test quality (test quality).

  In a conventional device test, first, a primary test of the device is performed on the probe card, then a final test is performed with the device in the actual usage environment to determine whether the device is good or not, and only good products are used as products. Ships.

In such final tests, in general,
1) Dedicated IC / LSI tester 2) Test fixture having circuit functions necessary for device testing 3) Test is performed with a configuration of a test program written in a dedicated language of the IC / LSI tester.

  This test fixture is generally a test jig in which a device under test (DUT: Device Under Test) is detachably mounted and is connected in advance to a dedicated IC / LSI tester. A load circuit for setting the actual usage environment state for each test device is provided (see, for example, Patent Document 1).

  In such a test fixture, the layout of the wiring and the routing of the ground line vary depending on the type of device under test. However, crosstalk between wirings may occur as the operating frequency increases in recent years. Alternatively, since the pad pitch is narrowed, the contact probe becomes unstable, the current is reduced, and noise is generated. This situation will be described with reference to FIGS. .

See FIG.
FIG. 2 is a conceptual configuration diagram of a conventional test system, in which a device under measurement 60 is mounted on a test fixture 53 that is a test jig, and the device under measurement 60 includes a test apparatus main body, that is, a tester 51. An electrical signal for testing is applied from the generated waveform generator (pattern generator) 52.

See FIG.
FIG. 7 is an explanatory diagram of the waveform of the electrical signal applied to the device under measurement, the right diagram shows the expected pulse voltage waveform generated by the waveform generator, and the left diagram shows the input of the device under test. The voltage waveform in a terminal part is shown.

  Due to the internal circuit configuration of the test fixture, the voltage waveform at the input terminal of this device under test has spike noise superimposed on the rising and falling parts of the pulse voltage waveform. The waveform is distorted.

  Therefore, in order to reduce such noise and spike voltage (high voltage noise in a short time), a capacitor is attached to each test circuit of each device based on the experience, theory, and experimental results of test engineers. Yes.

See FIG.
FIG. 8 is a conceptual configuration diagram when a capacitor for noise reduction is attached to the test system. The capacitor 54 is attached to a test system 50 having a tester, a test fixture, and the like, and a voltage supply unit 55 and a driver 56 are provided. The distortion of the voltage waveform applied from the comparator 57 and the GND / reference level 58 is compensated by the capacitor 54.

  However, this act of attaching a capacitor is uniquely fixed from the viewpoint of a tester as a hardware configuration, and the characteristics of the product lot often fluctuate, so the capacitor must be changed and tuned. May be.

  In order to change or tune the capacitor, the waveform actually applied from the tester is confirmed using an oscilloscope after the capacitor is attached.

Also, in the conventional semiconductor test apparatus, the voltage applied to the DUT is fed back to the control circuit side to automatically compensate for the voltage setting error due to the voltage drop of the control element, and the control element is installed in the vicinity of the DUT. Thus, it has also been proposed to suppress degradation of frequency characteristics and noise superposition caused by wiring pattern routing (see, for example, Patent Document 2).
JP 2002-243793 A JP 2002-040090 A

  However, in the past, since the test circuit function is unique for each device under test, the method for suppressing noise and spike voltage is also for each device under test, so the device manufacturing stage (wafer process) If there are some characteristic fluctuations in the test, for example, if the test results show a so-called marginless state that the test results have a limit on the PASS and FAIL judgments due to the influence of noise, the test results will be It is reflected as a Tome.

  Even if an existing tester manufactured by a device manufacturer has noise or spike voltage, it does not have a warning function or self-compensation function. For example, a spike voltage was generated. However, since the tester (test system) does not generate a warning, in the worst case, stress is applied to the device with overvoltage applied, and the test is continued as it is, and the test result is determined to be PASS. There are cases where it will end up.

That is, even if the device is operating normally in a certain test item, in the subsequent test of other items, the overvoltage was originally applied and spike noise was superimposed to destroy the inspected part of the device However, since the inspection result of the destroyed portion has already been determined to be normal, it is determined as PASS as a whole.
In actuality, when a product that should be determined as FAIL is shipped and leaked to the market, the effect is significant.

  In addition, the self-compensation in the above-mentioned Patent Document 2 is about the applied voltage value. When spike noise is superimposed on the applied voltage, there is no warning or self-compensation, and the defective product is still a product. There is a risk of shipping.

  Accordingly, an object of the present invention is to improve the stability of test quality by self-compensating for noise caused by a test jig superimposed on a voltage applied to a device under test.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In order to solve the above-described problem, the present invention applies an electrical load factor that affects a test result generated during a test of the semiconductor device 4 to an input / output terminal of the semiconductor device 4 in the semiconductor test apparatus. It is characterized by comprising at least a detection circuit 5 for detecting from an electrical signal.

  As described above, the semiconductor test apparatus includes the detection circuit 5 that detects electrical load factors such as noise, spike voltage, and overcurrent generated during the test of the semiconductor device 4 from the electric signal applied to the input / output terminal of the semiconductor device 4. As a result, it becomes possible to self-compensate the electrical load factor caused by the test fixture 3 having a different configuration for each semiconductor device 4 to be measured without requiring software, and the capacitors and the like are adjusted for each semiconductor device to be measured. There is no need to do it.

  In this case, it is desirable to use the detection circuit 5 that detects an electrical load factor in real time as the detection circuit 5 and to include a test peripheral circuit 6 that optimizes and corrects the electrical load factor, thereby stabilizing the test quality. Can be dramatically improved.

  In this case, as a component constituting the test peripheral circuit 6, a waveform correction circuit 7 and a waveform synthesis circuit 8 are typical.

  Further, according to the present invention, in the test system 1 including the tester 2 and the test fixture 3, the electrical load factor that affects the test result generated during the test of the electronic device to be measured is represented by the input / output terminals of the electronic device to be measured. It has the function to detect from the electric signal applied to.

  In this way, not only detecting the appropriateness / incorrectness of the applied voltage, but also detecting electrical load factors that affect test results such as noise and spike voltage, which is short-time, high-voltage noise. The electrical signal actually applied to the electronic device to be measured can be close to the ideal to be expected.

  In this case, it is not necessary to change the software for each type of electronic device to be measured by configuring the function of detecting the electrical load factor with hardware that does not require software depending on the electronic device to be measured. .

  In addition, it is desirable to detect the electrical load factor in real time by the function of detecting the electrical load factor, and to optimize and correct the electrical signal applied to the input / output terminal of the electronic device under measurement based on the detection result. , Test quality stability can be improved dramatically.

  In the present invention, it becomes possible to suppress noise and spike voltage without requiring software or hardware changes for each type of device under test, thereby dramatically improving test quality. .

  The present invention compares an ideal PG waveform generated in a test apparatus main body with a detected waveform detected by a waveform detecting means provided in a test jig, and cancels noise and spike voltage in the detected waveform by a test peripheral circuit. Generate a corrected waveform pattern, generate a combined waveform pattern by superimposing the generated corrected waveform pattern on the ideal PG waveform, and input the input terminal of the device under test via the waveform detection means attached to the test jig At the time of application to the unit, the noise and spike voltage caused by the test fixture are canceled and a voltage having a waveform close to ideal that should be expected is applied.

Here, with reference to FIG. 2 thru | or FIG. 5, the test system of the Example of this invention is demonstrated.
See Figure 2
FIG. 2 is a conceptual configuration diagram of a test system according to an embodiment of the present invention, and shows a circuit configuration for testing the test apparatus main body, that is, the tester 10 and the device under test 30 under the same conditions as the actual use state. The tester 10 includes a pattern generator 11 that generates an electrical signal and a power supply voltage to be applied to the test device 30 and a waveform state information analyzer 12.

  The test fixture 20 includes a signal line 21 for applying an electric signal to the device under measurement 30, a power supply line 22 for applying a power supply voltage to the device under measurement 30, and a GND line 23 for applying a ground potential to the device under measurement 30. The signal line 21, the power line 22, and the ground line 23 are provided with waveform detection circuits 24, 25, and 26, respectively.

See Figure 3
FIG. 3 is a conceptual diagram showing the principle of applied voltage waveform self-compensation in the test system of the embodiment of the present invention. The device under measurement 30 is a waveform detection circuit 24, 25, 26 attached to the test fixture 20. Is connected to a pattern generator 11 provided in the tester 10.

  In this case, the noise and spike voltage at the input terminal portion of the device under test 30 detected by the waveform detection circuits 24, 25, and 26 are caused by the waveform correction circuit 13 constituting the waveform state information analysis device 12 provided in the tester 10. Compensated by the generated correction waveform pattern.

See Figure 4
FIG. 4 is an explanatory diagram of a correction pattern generation method in the test system according to the embodiment of the present invention, which is detected by the ideal PG waveform and the waveform detection circuits 24, 25 and 26 by the comparison circuit 15 constituting the waveform state information analysis device 12. The detected waveforms are compared, noise and spike voltages in the detected waveforms are extracted by the limiter circuit 16 in which the maximum and minimum limits are set in advance, and a corrected waveform pattern is generated by the waveform correction circuit 23.
In each voltage waveform in the figure, the upper stage shows the voltage waveform before correction, and the lower stage shows the voltage waveform after correction.

Again see Figure 3
The corrected waveform pattern generated in this manner is superimposed on the ideal PG waveform in the waveform synthesis circuit 14 constituting the waveform state information analysis device 12 to synthesize the waveform pattern, and this synthesized waveform pattern is generated by the pattern generator 11. The voltage is applied to the device under measurement 30 via the waveform detection circuits 24, 25, and 26 attached to the test fixture 20.

  At this time, the voltage waveform applied to the test fixture 20 is corrected (pre-enhanced) so as to cancel out noise and spike voltage caused by the test fixture 20, and therefore applied to the input terminal portion of the device under test 30. At this time, the noise and spike voltage caused by the test fixture 20 are canceled out, and a voltage having a waveform close to ideal to be expected is applied.

See Figure 5
FIG. 5 is an explanatory diagram of the waveform of the electrical signal applied to the device under measurement, the right diagram shows the pre-enhanced pulse voltage waveform generated by the pattern generator, and the left diagram is the input terminal of the device under test. 6 shows a pulse voltage waveform applied in the section, and a voltage having a waveform close to an ideal to be expected is applied.

  The calculation result of the pulse voltage waveform generated from the pattern generator 11 and the waveform applied to the device under measurement 30 is accumulated by being fed back to the tester 10.

  That is, once the pulse voltage waveform generated by the pattern generator is pre-enhanced, the output of the waveform correction circuit is superimposed on the pre-enhanced pulse voltage waveform already stored.

  Therefore, after the pulse voltage waveform is pre-enhanced, the result of comparing the ideal PG waveform with the detected waveform is as shown in the waveform diagram of FIG. 3 as long as no noise or spike voltage is generated for some other reason. Since the output becomes 0, the pulse voltage waveform generated by the pattern generator does not change and becomes a pre-enhanced waveform.

  On the other hand, if noise or spike voltage occurs due to some other cause, the output of the waveform correction circuit does not become 0, so this output is superimposed on the pre-enhanced pulse voltage waveform that has already been accumulated and a new pre- An enhanced pulse voltage waveform is generated, the new pre-enhanced pulse voltage waveform is accumulated, and used as a subsequent superposition target voltage.

  As described above, in the embodiment of the present invention, the voltage waveform generated by the pattern generator is pre-enhanced so as to cancel out noise and spike voltage caused by the test fixture. A voltage having a waveform that is close to the ideal that should be expected after noise and spike voltage are canceled is applied to it, thereby dramatically improving the test quality and its stability.

  In the embodiment of the present invention, since only hardware having a self-compensation function is incorporated into the test system, software for each type of device to be measured and each production lot is not required. Since there is no need to adjust the hardware part for each type of measurement device or production lot, the throughput is improved, which in turn greatly contributes to the reduction of the manufacturing cost.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Additional remark 1) A semiconductor test apparatus comprising at least a detection circuit 5 for detecting an electrical load factor generated during a test of the semiconductor device 4 from an electric signal applied to an input / output terminal of the semiconductor device 4.
(Supplementary note 2) The detection circuit 5 comprises a detection circuit 5 for detecting the electrical load factor in real time, and further includes a test peripheral circuit 6 for optimizing and correcting the electrical load factor. The semiconductor test apparatus according to 1.
(Additional remark 3) The said test peripheral circuit 6 is provided with the waveform correction circuit 7 and the waveform synthesis circuit 8, The semiconductor test apparatus of Additional remark 2 characterized by the above-mentioned.
(Additional remark 4) In the test system 1 provided with the tester 2 and the test fixture 3, the electrical load factor generated at the time of the test of the electronic device to be measured is detected from the electric signal applied to the input / output terminal of the electronic device to be measured. A test system characterized by having functions.
(Supplementary Note 5) The test system according to Supplementary Note 4, wherein the function of detecting the electrical load factor is configured by hardware that does not require software dependent on the electronic device to be measured.
(Additional remark 6) While detecting an electrical load factor in real time by the function which detects the said electrical load factor, the electric signal applied to the input / output terminal of the said to-be-measured electronic device is optimized and corrected based on the said detection result The test system according to appendix 3 or 4, characterized by having a function.

  As a practical example of the present invention, a test process of a semiconductor device such as an IC or LSI is typical. However, the test process is not limited to a test of a semiconductor device. The present invention is also applied to test measurement of other electronic devices such as test measurement of conductive devices.

It is explanatory drawing of the fundamental structure of this invention. 1 is a conceptual configuration diagram of a test system according to an embodiment of the present invention. It is a conceptual block diagram which shows the applied voltage waveform self-compensation principle in the test system of the Example of this invention. It is explanatory drawing of the correction pattern generation method in the test system of the Example of this invention. It is explanatory drawing of the waveform of the electric signal applied to a to-be-measured device. It is a notional block diagram of the conventional test system. It is explanatory drawing of the waveform of the electric signal applied to a to-be-measured device. It is a conceptual block diagram at the time of attaching the capacitor for noise reduction to a test system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Test system 2 Tester 3 Test fixture 4 Semiconductor device 5 Detection circuit 6 Test peripheral circuit 7 Waveform correction circuit 8 Waveform synthesis circuit 10 Tester 11 Pattern generator 12 Waveform state information analysis device 13 Waveform correction circuit 14 Waveform synthesis circuit 15 Comparison circuit 16 Limiter circuit 20 Test fixture 21 Signal line 22 Power line 23 GND line 24 Waveform detection circuit 25 Waveform detection circuit 26 Waveform detection circuit 30 Device under test 50 Test system 51 Tester 52 Waveform generator 53 Test fixture 54 Capacitor 55 Voltage supply unit 56 Driver 57 Comparator 58 GND / Reference Level 60 Device Under Test

Claims (5)

A semiconductor test apparatus comprising at least a detection circuit for detecting an electrical load factor generated during a test of a semiconductor device from an electric signal applied to an input / output terminal of the semiconductor device. 2. The semiconductor test apparatus according to claim 1, wherein the detection circuit comprises a detection circuit that detects the electrical load factor in real time, and further includes a test peripheral circuit that optimizes and corrects the electrical load factor. A test system equipped with a tester and a test fixture has a function of detecting an electrical load factor generated during a test of an electronic device under measurement from an electric signal applied to an input / output terminal of the electronic device under measurement. And test system. 4. The test system according to claim 3, wherein the function of detecting the electrical load factor is constituted by hardware that does not require software depending on the electronic device to be measured. The function of detecting an electrical load factor in real time by the function of detecting the electrical load factor, and a function of optimizing and correcting an electrical signal applied to an input / output terminal of the electronic device to be measured based on the detection result The test system according to claim 3 or 4, characterized in that:

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