JP2006157983A - Radio communications system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time for frequency pull-in time at switching of a VCO, in a radio communications system provided with a PLL circuit having a plurality of VCOs. <P>SOLUTION: The frequency of a local oscillation signal, supplied from an oscillation system circuit, is varied according to the output voltage from a filter. The radio communications system comprises a receiving system circuit, combining the signal received from an antenna with the local oscillation signal, a set means of setting the predetermined voltage to the filter, in response to a second control signal, and a control means of generating a first control signal and generating the second control signal, according to the change in the local oscillation signal supplied from the oscillation system circuit and changed from a first frequency to a second frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique effectively applied to a PLL (Phase Locked Loop) circuit having a plurality of VCOs (Voltage Controlled Oscillators) and capable of switching an oscillation frequency. The present invention relates to a PLL circuit as a local oscillator that generates an oscillation signal having a predetermined frequency to be combined with a reception signal or a transmission signal in a wireless communication device such as the above, and a technology that is effective when used in a wireless communication system using the PLL circuit.

  In a mobile system such as a cellular phone, a dual band system that can handle signals in two frequency bands such as GSM (Group Special Mobile) of 880 to 915 MHz band and DCS (Digital Cellular System) of 1710 to 1785 MHz band, for example. There is a mobile phone. In a cellular phone, a PLL circuit is used as a local oscillator that generates an oscillation signal having a predetermined frequency to be combined with a reception signal or a transmission signal. However, as described above, signals of two different frequency bands are handled. In a cellular phone, it is difficult to cover two frequency bands with one VCO because of circuit characteristics. VCOs corresponding to the respective frequencies are provided and VCOs are switched according to the frequency band to be used. Yes. FIG. 5 shows a configuration example of a conventional PLL circuit used in a dual-band mobile phone. This PLL circuit divides a reference frequency signal TCXO such as 13 MHz into a signal R (hereinafter referred to as a reference side pulse) of about 200 KHz substantially equal to the channel interval, and a feedback signal F from the VCO as described above. A frequency divider 11B that divides the frequency into a pulse N having the same frequency of 200 KHz as the reference side pulse R (hereinafter referred to as a feedback side pulse) and a phase difference between the feedback side pulse N and the reference side pulse R are compared. A phase comparator 12 for detecting, a charge pump circuit 13 for sending and extracting charges according to the detected phase difference, and a loop filter 14 for generating a voltage according to the charges supplied from the charge pump. Two voltage controlled oscillators (VCO) 15A and 15B that oscillate at a frequency according to the voltage, and oscillation of these voltage controlled oscillators 15A and 15B It is constituted by a changeover switch 16 for feeding back selected force.

  In the PLL circuit used in the cellular phone, the channel (frequency band) interval is 200 KHz, and the same frequency as the selected channel combined with the transmission / reception signal is selected to select a desired channel from the plurality of channels. In order to generate the local oscillation signal by the PLL circuit, a variable frequency divider capable of changing the frequency division ratio is used as the feedback side frequency divider 11B. When the channel is switched, the variable frequency divider is controlled by a control signal from the system controller. The frequency division ratio of 11B is switched.

  Further, when the band to be used is switched from the GSM band to the DCS band or from the DCS band to the GSM band, the voltage controlled oscillation circuit by the switch 16 is switched together with the switching of the frequency division ratio of the variable frequency divider 11B by the control signal from the system controller. (VCO) The outputs of 15A and 15B are switched almost simultaneously. At this time, since the time until the VCO output is stabilized by switching the switch 16 is longer than the response time of the divided output by switching the frequency dividing ratio of the variable frequency divider 11B, switching of the VCO is generally more effective. Done first.

  However, it has been clarified that the PLL circuit in the conventional dual-band mobile phone has a problem that the pull-in time of the PLL circuit becomes long at the time of band switching for the reason described below. .

  FIG. 6A shows the outputs of the frequency dividers 11A and 11B and the output of the charge pump 13 when the PLL circuit is locked. As shown in the figure, the output of the frequency divider 11A (reference side pulse R) and the output of the variable frequency divider 11B (feedback side pulse N) are in phase, and the output CP of the charge pump 13 is 0V. It is constant. In this state, if the frequency division ratio n of the variable frequency divider 11B is lowered in order to lower the oscillation frequency of the PLL circuit, the period of the output (feedback side pulse N) of the variable frequency divider 11B is as shown in FIG. Since it becomes shorter than the cycle of the output of the frequency divider 11A (reference side pulse R), the negative current pulse CP is output from the charge pump 13 and acts to lower the frequency of the VCO. At this time, the channel interval is 200 KHz within the same band and the frequency division ratio does not change greatly. Therefore, the period of the feedback signal F becomes long, and the locked state as shown in FIG.

  On the other hand, if the frequency division ratio n of the variable frequency divider 11B is increased in order to increase the oscillation frequency of the PLL circuit, the output (feedback side pulse N) of the variable frequency divider 11B is contrary to the above, the frequency of the frequency divider 11A. Becomes longer than the period of the output (reference side pulse R). For this reason, a positive current pulse CP is output from the charge pump 13 to increase the frequency of the VCO, and the period of the feedback signal F is shortened so that the lock state is quickly achieved if the same band is used. As described above, when the frequency division ratio n of the variable frequency divider 11B is changed due to channel switching within the same band, the frequency is quickly stabilized.

  However, since the switch 16 is switched when the band is switched from the GSM band to the DCS band, the variable frequency divider 11B starts from the cycle T1 at which the VCO is switched as shown in the timing t1 of FIG. The cycle of the output (feedback side pulse N) is abruptly shortened. Therefore, a long negative current pulse CP is output from the charge pump 13 and acts to lower the frequency of the VCO. Moreover, even if two pulses from the other frequency divider (variable frequency divider B) are input in one period of the output of one frequency divider (here, reference side 11A) as in period T3, the phase comparator. Since 12 does not perform the comparison operation for the second pulse, the negative current pulse CP output from the charge pump 13 is considerably long. As a result, the output of the VCO on the selection side sticks to the lowest frequency side of the frequency variation range.

  In such a state, if the frequency division ratio of the variable frequency divider 11B is switched at the timing t2 of the period T4, the cycle of the output (feedback side pulse N) of the variable frequency divider 11B becomes longer. Depending on the switching timing, the rise of the output of the variable frequency divider 11B (feedback side pulse N) becomes faster than the rise of the output of the reference side frequency divider 11A (reference side pulse R) as in the period T5. The negative current pulse CP is output where the positive current pulse CP is desired to be output from the charge pump 13. As a result, the PLL circuit starts from an open state, and the phase lockup, that is, the frequency pull-in time may be increased.

  Contrary to the above, when the band is switched from the DCS band to the GSM band, the cycle of the output of the variable frequency divider 11B (feedback side pulse N) is abruptly increased. Current pulse CP is output to increase the frequency of the VCO, and the output of the VCO on the selection side sticks to the highest frequency side in the frequency variation range. In such a state, when the frequency dividing ratio of the variable frequency divider 11B is switched, the positive current pulse CP is output from the charge pump that originally wants to output the negative current pulse CP. The frequency pull-in time may become long.

  As described above, in the conventional PLL circuit, the first rise of the output of the variable frequency divider 11B (feedback side pulse N) after switching of the frequency division ratio is the output of the reference side frequency divider 11A (reference side pulse R). Whether it is earlier or later than the rise of the signal is not uniquely determined, and depends on the switching timing of the division ratio, and there is a problem that the frequency pull-in time varies. The fluctuation of the frequency pull-in time at the time of switching the VCO and the frequency division ratio is in a range that does not cause a problem in a wireless communication system of a mobile phone that handles only a voice signal. It has become clear that the amount of fluctuation in the frequency pull-in time exceeds the allowable range.

  SUMMARY OF THE INVENTION An object of the present invention is to make it possible to shorten a frequency pull-in time when switching a VCO in a wireless communication system including a PLL circuit having a plurality of VCOs.

An object of the present invention is to enable frequency acquisition to be completed within a predetermined time when switching a VCO in a wireless communication system including a PLL circuit having a plurality of VCOs.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

  That is, when switching the oscillation circuit in a wireless communication system that includes a PLL circuit having a plurality of oscillation circuits and is capable of processing two or more transmission signals and reception signals having different frequency bands by switching the oscillation circuit In addition, reset means for resetting the voltage of the filter capacitor to a predetermined voltage based on a signal from the control means is provided.

  According to the above-described means, when the oscillation circuit is switched, the oscillation circuit oscillates without being affected by the control voltage before switching, so that the frequency pull-in time of the PLL circuit can be shortened.

  The PLL circuit includes a variable frequency dividing circuit for frequency-dividing the feedback signal from any of the oscillation circuits whose phase is compared with a reference frequency signal by the phase comparator. The frequency of the reception signal and the transmission signal is selected by changing the frequency dividing ratio in the variable frequency dividing circuit based on the above signal. As a result, the band of the signal to be transmitted / received is switched by switching the oscillation circuit, and a desired frequency in each band can be selected by changing the frequency dividing ratio of the variable frequency dividing circuit.

  The resetting of the filter capacitance performed by the resetting means can be set to any fixed potential, but is preferably reset to the ground potential. This is because it is the most stable potential and can be easily obtained.

  The change of the frequency dividing ratio in the variable frequency dividing circuit is performed after switching the oscillation circuit, the variable frequency dividing circuit is reset to the initial state after the frequency dividing ratio is changed, and the resetting of the filter capacitance by the resetting means is performed. It may be configured to be performed in conjunction with the reset of the variable frequency dividing circuit. Since the time until the frequency stabilizes after changing the division ratio in the variable frequency divider is shorter than the time until the frequency stabilizes after switching the oscillation circuit, the total frequency pull-in time can be shortened. Because it can.

  The change of the frequency dividing ratio in the variable frequency dividing circuit is performed after switching the oscillation circuit, and the reset of the variable frequency dividing circuit and the filter capacitor is started simultaneously after the frequency dividing ratio in the variable frequency dividing circuit is changed, It is desirable that the reset of the filter capacitor is released after the reset of the variable frequency dividing circuit is released. As a result, it is possible to avoid malfunction by comparing the phase of the reference signal and the edge of the feedback signal immediately after the reset of the phase comparison circuit is released.

  Reset signal generating means for generating a control signal for resetting the variable frequency dividing circuit, and the reset signal generating means is based on a frequency division ratio setting signal in the variable frequency dividing circuit and the reference frequency signal. It is preferable to generate a reset signal that is set to an effective level during the period of the first pulse and the next pulse of the reference frequency signal after changing the frequency division ratio. By generating a reset signal based on the division ratio setting signal, the reset timing of the variable frequency divider circuit can be set accurately and easily, and by releasing the reset signal based on the reference frequency signal, the reset is released It is possible to uniquely determine the phase of the signal obtained by dividing the feedback signal with respect to the frequency signal to be a reference later.

  It is desirable that the operation of the phase comparator and the charge pump is stopped or transmission of the output of the phase comparator to the charge pump is interrupted while the filter capacitor is being reset by the reset means. As a result, the influence of the voltage of the filter capacitor due to the charge pump output can be completely eliminated, and the operation of the oscillation circuit can be prevented from becoming unstable during reset.

  Based on the reset control signal generated by the reset signal generating means, the effective level is changed in synchronization with the change of the reset control signal to the effective level, and the reference is more than the change of the reset control signal to the invalid level. Stop signal generating means for generating a stop signal that changes to an invalid level with a delay time equal to or greater than the pulse width of the frequency signal, and the stop signal generating means resets the filter capacitor and the phase comparator and the charge pump. It is preferable that the operation stop or the control to cut off the transmission of the output of the phase comparator to the charge pump is performed. As a result, it is possible to more reliably avoid malfunctions due to phase comparison between the reference signal and the edge of the feedback signal immediately after the reset of the phase comparison circuit is released.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, in a wireless communication system equipped with a PLL circuit having a plurality of VCOs, the frequency pull-in time when switching the VCO can be shortened, and the frequency pull-in can always be completed within a certain time when switching the VCO. There is an effect that can be made.

  Next, embodiments of the present invention will be described with reference to the drawings.

  In FIG. 1, the present invention is used as a local oscillator that generates an oscillation signal of a predetermined frequency to be combined with a reception signal or a transmission signal in a mobile phone that can handle signals of two frequency bands such as GSM and DCS. An embodiment when applied to a PLL circuit is shown.

  As shown in FIG. 1, the PLL circuit 10 of this embodiment divides a reference frequency signal TCXO such as 13 MHz to generate a reference side pulse R of 200 KHz, for example, and a feedback signal. A variable frequency divider 11B that divides F into pulses N having the same frequency of 200 KHz as the reference side pulse R, and a phase comparator that compares the phase of the divided feedback side pulse N and the reference side pulse R to make a phase difference. 12, a charge pump circuit 13 for sending and extracting charges according to the detected phase difference, and capacitors C0, C1, and a resistor R1, and generates a voltage according to the charge supplied from the charge pump circuit 2 The next loop filter 14, two voltage controlled oscillation circuits (VCO) 15A and 15B that oscillate at a frequency corresponding to the voltage generated by the filter, and these voltage controlled oscillation circuits 15A, is composed of a changeover switch 16 for selecting the oscillation output 15B.

  The voltage controlled oscillation circuit 15A can oscillate in a frequency range 5 to 10% wider than the GSM 880 to 915 MHz frequency band, and the voltage controlled oscillation circuit 15B can operate above and below the DCS 1710 to 1785 MHz frequency band. It is configured to be able to oscillate in a wide frequency range of 5 to 10%.

  The phase comparator 12 compares the phase of the feedback side pulse N divided by the variable frequency divider 11B with the phase of the reference side pulse R divided by the frequency divider 11A, and the phase of the feedback side pulse N is delayed. The up signal UP is output when the feedback side pulse N is advanced, and the down signal DOWN is output when the phase of the feedback side pulse N is advanced. The up signal UP and the down signal DOWN are supplied to the charge pump circuit 13 for sending and extracting charges.

  The charge pump circuit 13 includes a current source for current supply and a current source for current extraction. The charge pump circuit 13 generates a positive current pulse CP when the up signal UP is supplied, and is negative when the down signal DOWN is supplied. Current pulse CP is generated and supplied to the loop filter 14. The loop filter 14 is a secondary low-pass filter, which increases the charge charges of the capacitors C0 and C1 when a positive current pulse CP is supplied, and charges the capacitors C0 and C1 when a negative current pulse CP is supplied. Operates to reduce charge. As a result, when the phase of the feedback side pulse N is delayed, the output voltage of the loop filter 14 is increased to increase the oscillation frequency of the voltage controlled oscillation circuit 15A or 15B, and the phase of the feedback side pulse N is advanced. Decreases the output voltage of the loop filter 14 and lowers the oscillation frequency of the voltage controlled oscillation circuit 15A or 15B.

  The loop filter 14 is composed of a second-order filter, and its frequency response characteristic, that is, the loop band, is 1/10 or less of the frequency of the signal compared by the phase comparator 12 (200 KHz in this embodiment). Thus, the time constant of the loop filter 14 is set. If the response characteristic is higher than this, every time an output pulse is output from the phase comparator 12, the output voltage of the loop filter 14 fluctuates up and down, and the oscillation operation of the voltage controlled oscillation circuit 15A or 15B in the next stage becomes unstable. It is because it ends. In this embodiment, a switch 17 connected between the input node of the loop filter 14 and a constant voltage terminal such as the ground potential GND for resetting the charge charges of the filter capacitors C0 and C1, and a reference-side frequency division. A reset signal generating circuit 18 for generating a reset signal / RES for the variable frequency dividing circuit 11B based on the pulse R divided by the generator 11A, and a stop signal for delaying the rising edge based on the generated reset signal / RES. A delay circuit 19 for generating / STOP is provided.

  The stop signal / STOP is supplied to the phase comparator 12 and the charge pump circuit 13 to stop the operation of these circuits, and is supplied as a control signal to the reset switch 17 to charge the filter capacitors C0 and C1. It is comprised so that it can pull out. The delay time tpd of the stop signal / STOP in the delay circuit 19 is preferably longer than the pulse width of the reference side pulse R. This is to reliably prevent the phase comparator 12 from comparing the phase of the reference side pulse R to which the reset release timing is given and the edge of the feedback side pulse N that comes after that.

  The reset signal generation circuit 18 detects a change in the division ratio setting signal n supplied from the system controller or the like to the variable frequency divider 11B, and outputs the output (reference side pulse) of the reference side frequency divider 11A after the detection. The reset signal / RES is generated so as to fall in synchronization with the rise of the first pulse of R) and rise in synchronization with the rise of the next pulse. Specifically, the reset signal generation circuit 18 detects a change in the division ratio setting signal n, and an enable signal EN () that becomes an effective level for one cycle of the reference side pulse R after the detection. 2) and a circuit that generates a reset signal that changes in synchronization with the rising edge of the first pulse and the next pulse while the enable signal EN is at an effective level. can do. As a specific configuration for stopping the operations of the phase comparator 12 and the charge pump circuit 13 by the stop signal / STOP, for example, the current of the current source in the phase comparator 12 or the charge pump circuit 13 is cut off. Various methods are conceivable, such as providing a switch or providing a logic gate for preventing the outputs UP and DOWN of the phase comparator 12 from being transmitted to the charge pump circuit 13.

  Next, in the PLL circuit, the operation when the frequency division ratio of the variable frequency divider 11B is switched and the voltage controlled oscillation circuits 15A and 15B are switched will be described with reference to the timing chart of FIG. FIG. 2 shows the timing when the band is switched from the GSM band of 880 to 915 MHz to the DCS band of 1710 to 1785 MHz.

  When the voltage controlled oscillation circuit is switched at the timing t1 of the cycle T1 in FIG. 2, the cycle of the output of the variable frequency divider 11B that divides the feedback signal F (feedback side pulse N) is abruptly shortened. Therefore, a negative current pulse CP is output from the charge pump 13 and acts to lower the frequency of the voltage controlled oscillation circuit. Moreover, even if two output pulses from the other frequency divider (variable frequency divider B) are input during one period of the output from one frequency divider (here, reference side 11A) as in period T3, Since the comparator 12 does not perform a comparison operation for the second pulse, the negative current pulse CP output from the charge pump 13 is considerably long. As a result, the output of the voltage-controlled oscillation circuit on the selection side sticks to the lowest frequency side of the frequency variation range.

  In such a state, when the frequency division ratio of the variable frequency divider 11B is switched by the frequency division ratio setting signal n from the system controller or the like at a timing such as t2, the reset signal generation circuit 18 After detecting the change of the division ratio setting signal n, it falls in synchronization with the rise of the first pulse (timing t3) of the output pulse R of the reference side frequency divider 11A, and the rise of the next pulse ( A reset signal / RES that rises in synchronization with the timing t4) is generated. As a result, the variable frequency divider 11B is kept in a reset state while the reset signal / RES is at a low level.

  In addition, the stop signal / STOP changes to a low level in synchronization with the falling edge of the reset signal / RES, whereby the reset switch 17 is turned on and the charge charges of the capacitors C0 and C1 of the loop filter 14 are extracted to control the voltage. The control voltage to the oscillator 15B is fixed to the ground potential (0V). In addition, the operations of the phase comparator 12 and the charge pump circuit 13 are stopped by the stop signal / STOP. Therefore, the voltage controlled oscillator 15B is controlled so as to oscillate at the lower limit frequency of the fluctuation range.

  After that, at the next rising timing t4 of the reference side pulse R, the reset signal / RES changes to high level, the reset of the variable frequency divider 11B is released, and the variable frequency divider 11B starts frequency division again from this time point. To do. Then, when the stop signal / STOP is changed to a high level at a timing t5 after a while, the operation stop state of the phase comparator 12 and the charge pump circuit 13 is released, so that the phase comparison is started. At this time, the voltage-controlled oscillator 15B oscillates at the lower limit frequency of the fluctuation range, and the reset signal / RES is formed based on the reference side pulse R, so that its rise is delayed by the gate delay. Therefore, even if the oscillation frequency determined by the frequency division ratio n is close to the lower limit of the VCO fluctuation range, the period of the feedback side pulse N divided by the variable frequency divider 11B is always the period of the reference side pulse R. Longer than.

  Therefore, the phase comparator 12 detects the phase delay of the feedback side pulse N at the next rising timing t6 of the reference side pulse R, and the positive current pulse CP corresponding to the phase difference is output from the charge pump circuit 13. At this time, since the voltage controlled oscillator 15B oscillates at the lower frequency limit of the fluctuation range, the PLL circuit starts from the closed state, and the phase delay of the feedback side pulse N is 1710 MHz at maximum. Since the phase difference is only about 1785 MHz, the pull-in is completed with one positive current pulse CP from the charge pump circuit 13, and the PLL is locked up from the next cycle.

  Contrary to the above, at the time of band switching from the DCS band of 1710 to 1785 MHz to the GSM band of 880 to 915 MHz, the relationship between the output (reference side pulse R) and N in FIG. The period of the output (feedback-side pulse N) of the variable frequency divider 11B that divides the frequency of the output signal is rapidly increased. Therefore, a positive current pulse CP is output from the charge pump 13 and acts to increase the frequency of the voltage controlled oscillation circuit. Therefore, the voltage controlled oscillator 15A sticks to the upper limit frequency of the fluctuation range.

  However, also in this case, when the frequency division ratio of the variable frequency divider 11B is switched by the frequency division ratio setting signal n from the system controller or the like at the timing t2, the reset signal generation circuit 18 causes the low active reset signal. / RES is generated (timing t3). As a result, the variable frequency divider 11B is kept in the reset state during the low level period of the reset signal / RES, and the stop signal / STOP changes to the low level, thereby turning on the reset switch 17 and the capacitance C0 of the loop filter 14 , C1 charge charge is extracted. Further, the operations of the phase comparator 12 and the charge pump circuit 13 are stopped by the stop signal / STOP. Therefore, the voltage controlled oscillator 15A is controlled to oscillate at the lower limit frequency of the fluctuation range.

  Therefore, thereafter, as in the case of band switching from the GSM band to the DCS band, the reset signal / RES changes to high level at the next rising timing t4 of the reference side pulse R, and the variable frequency divider 11B is reset. Is released, and the variable frequency divider 11B starts frequency division again from this point. When the stop signal / STOP is changed to a high level at timing t5, the operation stop state of the phase comparator 12 and the charge pump circuit 13 is released, but the voltage controlled oscillator 15A oscillates at the lower limit frequency of the fluctuation range. In operation, the PLL circuit starts from a closed state. In addition, since the reset signal / RES is formed based on the reference side pulse R and its rising edge is delayed by the gate delay, the period of the feedback side pulse N divided by the variable frequency divider 11B is always the period of the reference side pulse R. Longer than.

  Therefore, the phase comparator 12 detects the phase delay of the feedback side pulse N at the next rising timing t6 of the reference side pulse R, and the positive current pulse CP corresponding to the phase difference is output from the charge pump circuit 13. Since the phase delay of the feedback side pulse N at this time is relatively small, the voltage controlled oscillator 15A completes the pull-in with one positive current pulse CP from the charge pump circuit 13, and the PLL starts from the next cycle. Locked up.

  FIG. 3 shows a second embodiment of the PLL circuit according to the present invention.

  In this embodiment, the switch 17 for resetting the filter capacitors C0 and C1 connected between the input node of the loop filter 14 and the ground potential GND in the embodiment of FIG. 1 is replaced with the input node of the loop filter 14 and the power supply voltage Vcc. And the filter capacitance is reset to Vcc. In this case, in either case of band switching from the GSM band to the DCS band or band switching from the DCS band to the GSM band, the voltage-controlled oscillation circuit 15A or 15B is reset to the upper limit frequency of the fluctuation range. Will oscillate. That is, during the reset period, the voltage controlled oscillation circuit 15A or 15B oscillates in the state where the oscillation frequency is the highest, contrary to the first embodiment.

  Therefore, in this embodiment, a reset signal generation circuit 18 that generates a reset signal / RES based on the output (feedback side pulse N) of the variable frequency divider 11B is provided, and the reference side frequency divider 11A is generated by the reset signal / RES. And a stop signal / STOP in which the falling edge of the reset signal / RES is delayed is generated by the delay circuit 19 to stop the phase comparator 12 and the charge pump 13.

  As a result, even if the oscillation frequency determined by the frequency division ratio n is close to the upper limit of the VCO fluctuation range, the reset signal / RES is formed based on the feedback side pulse N, so that its rise is delayed by the gate delay. Therefore, as for the first pulse after reset release, the output of the variable frequency divider 11B (feedback side pulse N) is always the output of the reference side frequency divider 11A (reference side pulse) contrary to the first embodiment. The timing is earlier than R). As a result, the phase comparator 12 determines that the phase of the feedback signal F is advanced and outputs a down signal, and the charge pump 13 receives it and outputs a negative current pulse CP. Therefore, the voltage controlled oscillation circuit 15A Or 15B operates to lower the oscillation frequency. Moreover, the voltage controlled oscillation circuit 15A or 15B oscillates at the upper limit of the fluctuation range during the reset period, and the PLL circuit starts from a closed state, so that the frequency pull-in is completed with one current pulse CP. Thus, the PLL can be brought into a lock-up state.

  FIG. 4 shows a configuration example of a radio communication system of a dual-band mobile phone using the PLL circuit of the above embodiment. Although not particularly limited, the system of this embodiment is a so-called single superheterodyne system.

  In FIG. 4, reference numeral 100 denotes an antenna for transmitting / receiving signal radio waves, 101 denotes a switch for transmission / reception switching, 110 denotes a reception system circuit for amplifying and demodulating a signal received by the antenna 100, and 120 modulates a signal transmitted from the antenna 100. A transmission system circuit for frequency conversion, 130 is an oscillation system circuit for generating a local oscillation signal required for the reception system circuit 110 and the transmission system circuit 120, and 140 extracts audio data from the reception signal or converts the audio data into a voltage. A baseband signal processing circuit 150 for converting into a pulse train is a system controller composed of a microcomputer or the like that comprehensively controls the entire system. The PLL circuit of the above embodiment is used in the oscillation system circuit 130.

  The reception system circuit 110 includes a band limiting filter (FLT) 111 including a SAW filter that removes unnecessary waves from a signal received from the antenna 100, and a low noise amplification circuit (LNA) that amplifies the signal that has passed through the filter 111. 112, a mixer (MIX) 113 that down-converts the amplified reception signal and the local oscillation signal from the oscillation system circuit 130 into an intermediate frequency signal, and corresponds to a frequency difference between the reception signal and the local oscillation signal. A band-pass filter (BPF) 114 for passing a signal having a frequency to be controlled, a programmable gain amplifier (PGA) 115 capable of amplifying the signal to a desired level, and a signal adjusted to a desired amplitude as a baseband It comprises a demodulator (DeMOD) that demodulates the signal (I / Q).

  The transmission system circuit 120 includes a modulator (MOD) 121 that modulates the transmission signal input as a baseband signal (I / Q) from the baseband signal processing circuit 140 into an RF signal, and the modulated signal as an oscillation system circuit. A mixer (UP-MIX) 122 that performs up-conversion to a signal of a desired transmission frequency by combining with the oscillation signal from 130, and a power amplifier (PA) that amplifies the frequency-converted transmission signal and transmits it from the antenna 100 Etc.

  The oscillation system circuit 130 includes an RF signal voltage controlled oscillation circuit (RFVCO) 131 and a voltage controlled oscillation circuit (IFVCO) 132 that generates an intermediate frequency signal (constant frequency) required by the demodulator 116 and the modulator 121. Are compared with the reference signal TCXO supplied from an oscillation circuit having a high frequency accuracy and no temperature dependency using a feedback signal from the VCOs 131 and 132, and a control voltage for each VCO. And a buffer (BFF) 134 that distributes and supplies the oscillation signal generated by the RFVCO 131 to the mixer 113 on the reception side and the mixer 122 on the transmission side.

  Here, the voltage controlled oscillation circuits 15A and 15B and the changeover switch 16 shown in FIGS. 1 and 3 correspond to the VCOs 131 and 132 in FIG. 4, and the RFVCO 131 and the IFVCO 132 have two voltage controlled oscillation circuits 15A and 15B. Are provided. Further, the frequency dividing circuits 11A and 11B, the phase comparator 12, the charge pump 13, and the loop filter 14 shown in FIGS. 1 and 3 are shown as a synthesizer (SYN) 133 in FIG. A reset switch 17, a reset signal generation circuit 18, and a delay circuit 19 are provided therein.

  In the system of this embodiment, when the system controller 150 attempts to change the channel, the frequency division ratio setting signal n supplied to the variable frequency divider in the synthesizer 133 is changed, and the RFVCO 131 and the IFVCO 132 are also changed. The VCO switching control signal FC is changed. The system controller 150 performs control to change the transmission / reception switching control signal TX / RX for the changeover switch 101 when switching between transmission and reception.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments. For example, in the embodiments, two voltage-controlled oscillation conversion circuits are provided in the subsequent stage of the charge pump circuit 13. Although described as a PLL circuit having 15A and 15B, the present invention can be applied to a case where there are three or more voltage-controlled oscillation circuits as well as two cases as in the embodiment. Also, the same effect as in the embodiment can be obtained.

  The terminal to which the reset switch 17 is connected is not limited to the ground point GND or the power supply voltage terminal Vcc, and can be any fixed potential terminal. Further, the loop filter 14 is not limited to the secondary filter composed of the capacitors C0, C1, R1 as shown in FIGS. 1 and 3, but the primary filter composed of one capacitor as shown in FIG. It may be a filter. In the embodiment, the frequency divider 11A that divides the reference signal is provided. However, this frequency divider is not always necessary, and may be omitted depending on the frequency of the reference signal.

  Furthermore, in the application example described above, the wireless communication system of the cellular phone called the single superheterodyne method has been described. However, the second downconverting the signal further downconverted after the mixer 113 on the receiving side in the single superheterodyne method. A direct conversion system called a double superheterodyne system called a double superheterodyne system that is provided with a mixer and a direct conversion system that directly inputs a received signal that has been amplified and passed through a predetermined bandpass filter by omitting a mixer on the receiving side. Needless to say, the present invention can also be applied to a wireless communication system of a cellular phone called.

  In the above description, the case where the invention made mainly by the present inventor is applied to a PLL circuit used in a radio communication system of a cellular phone, which is a field of use behind the present invention, has been described, but the present invention is not limited thereto. In addition, the present invention can be widely used in general for a PLL circuit including two or more VCOs and operating by switching frequencies and a system having the PLL circuit.

1 is a block diagram showing a first embodiment of a PLL circuit according to the present invention. 6 is a timing chart showing a frequency division ratio of the PLL circuit of the embodiment and an operation waveform at the time of VCO switching. It is a block diagram which shows the 2nd Example of the PLL circuit which concerns on this invention. 1 is a block diagram illustrating a configuration example of a dual-band mobile phone system as an example of a system to which a PLL circuit according to the present invention is applied. It is a block diagram which shows the structural example of the conventional PLL circuit. It is a timing chart which shows the operation waveform at the time of the lock state of a conventional PLL circuit, and frequency division ratio switching. It is a timing chart which shows the frequency division ratio of the conventional PLL circuit, and the operation waveform at the time of VCO switching.

Explanation of symbols

11A Reference Side Divider 11B Variable Divider 12 Phase Comparator 13 Charge Pump 14 Loop Filter 15A, 15B Voltage Control Oscillator 16 VCO Switch 17 Reset Switch 18 Reset Signal Generator 19 Delay Circuit TCXO Reference Signal F Feedback Signal R A signal obtained by dividing the reference signal N A signal obtained by dividing the feedback signal

Claims (9)

An oscillation system circuit that receives a first control signal and outputs a local oscillation signal having a first frequency and a second frequency different from the first frequency in accordance with the first control signal,
A phase comparator for detecting a phase difference between a reference signal and a signal based on the local oscillation signal;
A charge pump circuit for generating a voltage according to the phase difference detected by the phase comparator;
A filter having a capacitor and receiving a voltage output from the charge pump circuit;
Comprising
The frequency of the local oscillation signal supplied from the oscillation system circuit is changed according to the output voltage from the filter,
A receiving circuit for combining a signal received from an antenna and the local oscillation signal;
Setting means for setting a predetermined voltage to the filter in response to a second control signal;
Control for generating the first control signal and generating the second control signal in response to a change in the local oscillation signal supplied from the oscillation system circuit and changed from the first frequency to the second frequency Means,
A wireless communication system, further comprising: The oscillation circuit is
2. The frequency dividing circuit according to claim 1, further comprising a frequency dividing circuit that divides the local oscillation signal and supplies the divided local oscillation signal to the phase comparator as a signal based on the local oscillation signal. Wireless communication system. The frequency dividing circuit is a variable frequency dividing circuit that divides the local oscillation signal according to a frequency dividing ratio.
The control means includes
A first circuit for generating information indicating a frequency division ratio to be supplied to the variable frequency dividing circuit after changing the first control signal;
A second circuit for generating the second control signal in response to generation of information indicating the frequency division ratio;
The wireless communication system according to claim 2, comprising: The oscillation circuit is
A first voltage controlled oscillation circuit for generating a local oscillation signal of the first frequency;
A second voltage controlled oscillation circuit for generating a local oscillation signal of the second frequency,
4. The wireless communication system according to claim 3, wherein the voltage output from the filter is supplied as a control voltage to the first voltage controlled oscillation circuit and the second voltage controlled oscillation circuit. An oscillation system circuit that receives a first control signal and outputs a local oscillation signal having a first frequency and a second frequency different from the first frequency according to the first control signal,
A phase comparator for detecting a phase difference between a reference signal and a signal based on the local oscillation signal;
A charge pump circuit for generating a voltage according to the phase difference detected by the phase comparator;
A filter having a capacitor and receiving a voltage output from the charge pump circuit;
Comprising
The frequency of the local oscillation signal supplied from the oscillation system circuit is changed according to the output voltage from the filter,
A transmission system circuit that synthesizes a signal transmitted from an antenna and the local oscillation signal;
Setting means for setting a predetermined voltage to the filter in response to a second control signal;
Control for generating the first control signal and generating the second control signal in response to a change in the local oscillation signal supplied from the oscillation system circuit and changed from the first frequency to the second frequency Means,
A wireless communication system, further comprising: The oscillation circuit is
6. The frequency dividing circuit according to claim 5, further comprising a frequency dividing circuit that divides the local oscillation signal and supplies the divided local oscillation signal to the phase comparator as a signal based on the local oscillation signal. Wireless communication system. The frequency dividing circuit is a variable frequency dividing circuit that divides the local oscillation signal according to a frequency dividing ratio.
The control means includes
A first circuit for generating information indicating a frequency division ratio to be supplied to the variable frequency dividing circuit after changing the first control signal;
A second circuit for generating the second control signal in response to generation of information indicating the frequency division ratio;
The wireless communication system according to claim 6, comprising: The oscillation circuit is
A first voltage controlled oscillation circuit for generating a local oscillation signal of the first frequency;
A second voltage controlled oscillation circuit for generating a local oscillation signal of the second frequency,
8. The wireless communication system according to claim 7, wherein the voltage output from the filter is supplied as a control voltage to the first voltage controlled oscillation circuit and the second voltage controlled oscillation circuit. 6. The wireless communication system according to claim 5, further comprising a reception system circuit that combines a signal received from an antenna and the local oscillation signal.

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