JP2006157871A - Information processing apparatus and method, recording medium, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of realizing a reverse-direction fast playback operation without performing complicated band control. <P>SOLUTION: In the case of a reverse double speed playback operation, banks No. 0 to No. 5 are occupied by I and P pictures, which are stored in the decode order. In a timing next to it when I2 pictures are stored in the bank No. 5, B1 pictures are stored in a bank No. 6, B12 pictures are stored in a bank No. 7 in a timing next to it when a display timing of the B1 pictures, and the bank No. 6 is released. B pictures not omitted are alternately stored in the banks No. 6 and 7 in such a way that the display timing of the B pictures is delayed by one frame with respect to the decode timing and the banks are released after display of the B pictures. The banks No. 0 to 5 are released in any slower timing between both the cases when the display of the I, P pictures is finished and the use of the stored I and P pictures as a reference image is completed. The technology is applicable to playback devices. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to an information processing apparatus, an information processing method, a recording medium, and a program.
In particular, the present invention relates to an information processing apparatus, an information processing method, a recording medium, and a program that can reproduce compressed encoded data without controlling complicated bank memory.

  MPEG (Moving Picture Coding Experts Group / Moving Picture Experts Group) is widely used as a video compression technique.

  When decoding and reproducing stream data compressed and encoded by MPEG, there is a technique for executing high-speed reproduction or reproducing in the reverse direction in addition to normal reproduction.

  For example, in MPEG LongGOP which constitutes 1 GOP with 15 pictures, the B picture is thinned out at the input to the decoder, so that it is -3 to 3 times (minus the speed indicates reverse playback, and so on). High-speed reproduction can be performed (see, for example, Patent Document 1). Further, by having a table of picture information to be displayed for each reproduction speed, it is possible to perform reproduction at the speed of the prepared table.

JP-A-8-98142

  Also, for example, a compression-coded signal is acquired intermittently for 10 frames at intervals of 5 frames, and all the acquired compressed-coded signals are demodulated and then alternately supplied to the two decoding units for 5 frames. There is a technique in which, after each decoding process is executed, the decoded data is written in a memory and read out every other frame so that a double-speed reproduction signal can be obtained (for example, Patent Document 2). reference).

JP-A-8-56334

  Also, MPEG streams are convenient for playback in the forward direction. For example, the arrangement of pictures in the coding order of 1 GOP in MPEG Long GOP that constitutes 1 GOP with 15 pictures is I (2) B (0) B (1), P (5), B (3), B (4), P (8), B (6), B (7), P (11), B (9), B (10), P (14), B (12), B (13) (however, in parentheses The number indicates the order when the coding order is rearranged into the display order), and the picture referred to by the P picture is the previous I picture or P picture, and the picture referenced by the B picture is The previous I picture or P picture in the coding order and the second previous I picture or P picture. As a result, by reserving two reference picture memories (two banks), both the P picture and the B picture can be decoded, and the memory can be used efficiently.

  In this way, in order to reversely play back an MPEG stream that is convenient for playback in the forward direction, a decoding process is executed using a plurality of decoders, and a GOP immediately preceding the GOP to be decoded is added. There is a technique in which a reference image of a picture to be reproduced can be used correctly even in backward reproduction by supplying the data to a decoder (for example, Patent Document 3).

JP-A-10-150635

  For example, in MPEG LongGOP which constitutes 1 GOP with 15 pictures, the B picture is thinned out at the input to the decoder, so that it is -3 to 3 times (minus the speed indicates reverse playback, and so on). High-speed playback is possible, but the display interval of pictures becomes irregular, resulting in an unnatural display.

  In addition, when decoding is performed using a plurality of decoder chips, by combining with a process of thinning out B pictures that are not to be displayed at the input stage, even higher-speed playback (for example, 2 times with 2 chips, 4 times with 3 chips, 5 times with 4 chips, 7 times with 5 chips), but in the output processing, it is necessary to thin out I pictures or P pictures, Control of the baseband memory and processing for selecting data to be displayed from decoded data become complicated. For this reason, it has been difficult to reproduce and display by dynamically changing the speed using the conventional technique.

  Further, as described above, by having a table of picture information to be displayed for each reproduction speed, it is possible to reproduce at a speed corresponding to the prepared table. However, in such processing, the change of speed becomes a table unit, and moreover, complicated control is required to perform display at the time of switching without delay.

  As described above, the MPEG stream can be conveniently reproduced in the forward direction. However, when playback in the reverse direction is performed in the input order of the streams, if playback is performed in the reverse direction after decoding for 1 GOP is completed, a frame that can record data of at least 1 GOP (for example, 15 frames) can be recorded. Since a memory is provided and a large number of banks for reference image data must be reserved, a large memory capacity is required.

  The present invention has been made in view of such a situation, and enables high-speed reproduction, reverse reproduction, and high-speed reverse reproduction of compression-encoded data without performing complicated bank memory control. It is.

  An information processing apparatus according to a first aspect of the present invention includes a decoding unit that decodes compressed encoded video data, a supply control unit that controls supply of compressed encoded video data to the decoding unit, a supply control unit, and a decoding unit. Control means for controlling the processing executed by the decoding means, and the decoding means comprises a number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding processing is executed, and holds the decoded picture data. The control means holds the I picture and the P picture in a fixed position determined by the picture type in the bank memory, and the decoded picture data held in the bank memory is used as a reference picture if necessary. The decoding process by the decoding means is controlled so as to be used as

  The decoding means may be provided with a bank memory capable of holding a number of pictures obtained by adding 2 to the number of I and P pictures included in the processing unit.

  Three decoding means can be provided, and the decoding means can each be provided with a bank memory capable of holding 8 pictures.

  The control means may determine the order of decoding processing for each picture so that an I picture and a P picture among a plurality of pictures included in a processing unit are decoded before a B picture. it can.

  The control means may further include a playback speed command means for commanding the playback speed, and the control means may include a picture included in the processing unit based on the playback speed commanded by the playback speed command means. The picture output from the decoding means can be selected, and the decoding means includes a decoding processing execution means for executing decoding processing, and a picture supply control means for controlling the supply of pictures to the decoding processing execution means The picture supply control means, based on the control of the control means, out of the pictures included in the processing unit, and the picture output from the decoding means The B picture selected as the picture can be supplied to the decoding processing means. Based on the control of the control means, as well as decoding of each picture supplied by the picture supply control means may be adapted to output the pictures selected as pictures to be output from the decode means.

  A plurality of decoding means may be provided, and an output switching means for receiving the supply of uncompressed data output from the plurality of decoding means and selectively outputting the supplied uncompressed data by switching. The control means can further control the processing by the output switching means.

  When the picture outputted at the head of the processing unit among the decoded pictures outputted from the decoding means is an I picture or a P picture, the control means outputs the decoding start timing by the decoding means and the decoding means. The decoding means can be controlled so that the timing at which the output of the decoded picture is started is shifted by the first predetermined number of pictures.

  The first predetermined number may be a number obtained by adding 1 to the total number of I pictures and P pictures.

  When the picture output at the head of the processing unit among the decoded pictures output from the decoding means is a B picture, the control means outputs the decoding start timing by the decoding means and the decoded picture from the decoding means. The decoding means can be controlled so that the timing at which picture output is started is shifted by a second predetermined number of pictures.

  The second predetermined number may be a number obtained by adding 2 to the total number of I pictures and P pictures.

  When the playback speed and the playback direction commanded by the playback speed command means for commanding the playback speed and playback direction to the control means are the normal playback speed and the playback direction is the positive direction, the control means The decoding means can be controlled such that the decoding start timing and the timing at which the decoding means starts outputting the decoded picture are shifted by the first predetermined number of pictures.

  The first predetermined number may be a number obtained by adding 1 to the total number of I pictures and P pictures.

  When the playback speed and playback direction instructed by the playback speed command means are the normal playback speed and the playback direction is the reverse direction, the control means has the decoding start timing by the decoding means and the decoding means already decoded. The decoding means can be controlled so that the timing at which the output of the current picture starts is shifted by a second predetermined number of pictures.

  The second predetermined number may be a number obtained by adding 2 to the total number of I pictures and P pictures.

  The control means determines the order of decoding processing for each picture by the decoding means so that the timing at which the B picture is decoded by the decoding means is one picture before the timing of decoding and output by the decoding means. Can be.

  The decoding means includes, as the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed, a number of bank memories smaller than the number of pictures included in the processing unit in which the decoding process is executed. be able to.

  The compression-encoded video data may be composed of GOPs, and the control means is supplied with GOPs including more I pictures or P pictures than the number of bank memories minus 3. When received, the supplied GOP is divided to form a decoding processing unit including a number of I pictures or P pictures less than the value obtained by subtracting 2 from the number of bank memories, and the supply control means is controlled, and the decoding means Can be supplied with compressed encoded video data in units of decoding processing.

  In the control means, the sum of the number of I pictures or P pictures included in the decoded processing unit generated by division is the I picture included in the GOP or decoding processing unit immediately before the decoding processing unit or The decoding unit can be configured so as not to exceed a predetermined number more than the total number of P pictures.

  The compression-coded video data may be composed of GOPs, and the control means includes a first GOP including a smaller number of I pictures or P pictures than a value obtained by subtracting 3 from the number of bank memories. , The configuration of the second GOP that is temporally continuous with the first GOP is detected, and the total number of I pictures or P pictures included in the first GOP and the second GOP is detected. When the number is less than the value obtained by subtracting 3 from the number of bank memories, the first GOP and the second GOP are combined to form a decoding processing unit, the supply control means is controlled, and the decoding means decodes It is possible to supply compressed encoded video data in units of processing.

  The control means is configured such that the total number of I pictures or P pictures included in the decoding processing unit is a predetermined amount higher than the total number of I pictures or P pictures included in the GOP immediately before the decoding processing unit. The decoding unit can be configured so as not to exceed a number.

  The compression-encoded video data may be composed of GOPs, and the control means detects the configuration of the first GOP and the second GOP that is temporally continuous with the first GOP. When the total number of I pictures or P pictures included in the first GOP and the second GOP is less than twice the value obtained by subtracting 3 from the number of bank memories, A first decoding processing unit and a second decoding processing unit including a number of I pictures or P pictures smaller than a value obtained by subtracting 2 from the number of bank memories are combined after being combined with the second GOP. The supply control means can be controlled to cause the decoding means to individually supply the compressed encoded video data of the first decoding processing unit and the second decoding processing unit.

  In the control means, the total number of I pictures or P pictures included in the decoding processing unit is the number of I processing pictures or P pictures included in the decoding processing unit that is one time earlier than the decoding processing unit or GOP. The decoding unit can be configured so as not to exceed a predetermined number more than the total.

  An information processing method according to the first aspect of the present invention, a program recorded on a recording medium, and a program are subjected to a supply control step for controlling the supply of compressed encoded video data to a plurality of decoders and a decoding process. A decoding step of decoding compressed encoded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit. The I picture and the P picture are held at fixed positions determined by the picture type, and in the decoding step processing, the decoded picture data held in the bank memory is used as a reference image as necessary. Decoding is performed.

  In the first aspect of the present invention, compressed encoded video data is supplied to a plurality of decoders, and the compressed encoded video data is used by the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed. The data is decoded, and in the bank memory, the I picture and the P picture are held at fixed positions determined by the picture type, and the decoded picture data held in the bank memory is used as a reference image as necessary. Used to perform decoding.

  An information processing apparatus according to a second aspect of the present invention includes a storage unit that stores compressed encoded video data, a read unit that reads and outputs the compressed encoded video data stored in the storage unit, and a compressed encoded video Decoding means for decoding data, supply control means for controlling the supply of compressed encoded video data to the decoding means, control means for controlling processing executed by the supply control means and the decoding means, and a playback speed for the control means A playback speed command means for commanding, and the decoding means includes a number of bank memories corresponding to the number of pictures included in a processing unit in which decoding processing is executed, holds decoded picture data, and control means The I picture and P picture are held in fixed positions determined by the picture type in the bank memory, Decoding the processed picture data held in the, to be utilized as a reference image as needed, to control the decoding processing by the decoding means.

  An information processing method according to the second aspect of the present invention, a program recorded on a recording medium, and a program for reading out compressed encoded video data stored in a storage unit and a playback speed command A speed command supply step, a playback speed command acquisition step for acquiring a playback speed command supplied by the processing of the playback speed command supply step, and a supply control step for controlling the supply of compressed encoded video data to a plurality of decoders. A decoding step for decoding the compression-coded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed. In the bank memory, the I picture and the P picture have fixed positions determined by the picture type. Is held, the process of decoding steps are used as the reference image picture data of the decoded processed held in the bank memory is needed, the decoding is performed.

  In the second aspect of the present invention, compressed encoded video data is stored, and the stored compressed encoded video data is read and output. The compressed encoded video data is supplied to a plurality of decoders, and the compressed encoded video data is decoded using a number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed. The I picture and the P picture are held at fixed positions determined by the picture type, and the decoded picture data held in the bank memory is used as a reference picture as necessary, and decoding is executed. The

  An information processing apparatus according to a third aspect of the present invention includes a decoding unit that decodes compressed encoded video data, a supply control unit that controls the supply of compressed encoded video data to the decoding unit, a supply control unit, and a decoding unit. Control means for controlling the processing executed by the decoding means, the decoding means comprises a predetermined number of bank memories, holds the decoded picture data, and the compression-coded video data is composed of GOP, The control means divides or combines the GOPs by comparing the number of I-pictures or P-pictures included in 1 GOP compression-encoded video data with the number of bank memories to form a decoding processing unit, and supply control By controlling the means, it is possible to supply the decoding means with compressed encoded video data in units of decoding processing.

  When the control means receives a GOP including a larger number of I or P pictures than the number obtained by subtracting 3 from the number of bank memories, the supplied GOP is divided and 2 is subtracted from the number of bank memories. It is possible to configure a decoding processing unit including a smaller number of I pictures or P pictures, and to control the supply control means so that the decoding means supplies compressed encoded video data of the decoding processing unit.

  In the control means, the sum of the number of I pictures or P pictures included in the decoded processing unit generated by division is the I picture included in the GOP or decoding processing unit immediately before the decoding processing unit or The decoding unit can be configured so as not to exceed a predetermined number more than the total number of P pictures.

  When receiving the first GOP including the number of I pictures or P pictures smaller than the value obtained by subtracting 3 from the number of bank memories, the control means receives the second GOP that is temporally continuous with the first GOP. If the GOP configuration is detected and the total number of I or P pictures included in the first GOP and the second GOP is less than the value obtained by subtracting 3 from the number of bank memories, the first The GOP and the second GOP can be combined to form a decoding processing unit, and the supply control means can be controlled to cause the decoding means to supply compressed encoded video data in the decoding processing unit.

  The control means is configured such that the total number of I pictures or P pictures included in the decoding processing unit is a predetermined amount higher than the total number of I pictures or P pictures included in the GOP immediately before the decoding processing unit. The decoding unit can be configured so as not to exceed a number.

  The control means detects the configuration of the first GOP and the second GOP that is temporally continuous with the first GOP, and includes an I picture or a P picture included in the first GOP and the second GOP. When the sum of the numbers is less than twice the value obtained by subtracting 3 from the number of bank memories, the first GOP and the second GOP are combined and then divided to obtain 2 from the number of bank memories. The first decoding processing unit and the second decoding processing unit including a smaller number of I pictures or P pictures than the subtracted value are configured, the supply control means is controlled, and the first decoding processing unit and the second decoding processing unit are controlled by the decoding means. It is possible to individually supply the compression encoded video data of two decoding processing units.

  In the control means, the total number of I pictures or P pictures included in the decoding processing unit is the number of I processing pictures or P pictures included in the decoding processing unit that is one time earlier than the decoding processing unit or GOP. The decoding unit can be configured so as not to exceed a predetermined number more than the total.

  When the picture outputted at the head of the processing unit among the decoded pictures outputted from the decoding means is an I picture or a P picture, the control means outputs the decoding start timing by the decoding means and the decoding means. The decoding means can be controlled so that the timing at which the output of the decoded picture is started is shifted by the first predetermined number of pictures.

  The first predetermined number may be a number obtained by adding 1 to the total number of I pictures and P pictures.

  When the picture output at the head of the processing unit among the decoded pictures output from the decoding means is a B picture, the control means outputs the decoding start timing by the decoding means and the decoded picture from the decoding means. The decoding means can be controlled so that the timing at which picture output is started is shifted by a second predetermined number of pictures.

  The second predetermined number may be a number obtained by adding 2 to the total number of I pictures and P pictures.

  When the playback speed and the playback direction commanded by the playback speed command means for commanding the playback speed and playback direction to the control means are the normal playback speed and the playback direction is the positive direction, the control means The decoding means can be controlled such that the decoding start timing and the timing at which the decoding means starts outputting the decoded picture are shifted by the first predetermined number of pictures.

  The first predetermined number may be a number obtained by adding 1 to the total number of I pictures and P pictures.

  When the playback speed and playback direction instructed by the playback speed command means are the normal playback speed and the playback direction is the reverse direction, the control means has the decoding start timing by the decoding means and the decoding means already decoded. The decoding means can be controlled so that the timing at which the output of the current picture starts is shifted by a second predetermined number of pictures.

  The second predetermined number may be a number obtained by adding 2 to the total number of I pictures and P pictures.

  An information processing method according to a third aspect of the present invention, a program recorded on a recording medium, and a program comprising: a detection step for detecting a configuration of a GOP included in compressed encoded video data; and a compressed encoded video data of 1 GOP A comparison step for comparing the number of I-pictures or P-pictures included in the image and the number of bank memories for holding the decoded picture data, and dividing the GOP based on the comparison result of the processing of the comparison step The decoding processing unit configuration step is combined to form a decoding processing unit, and the decoding processing step is performed to perform decoding processing for each decoding processing unit configured by the processing of the decoding processing unit configuration step.

  In the third aspect of the present invention, the configuration of the GOP included in the compression encoded video data is detected, and the number of I pictures or P pictures included in the compression encoded video data of 1 GOP and the decoded picture data Are compared with the number of bank memories for holding the GOP, and based on the comparison result, the GOP is divided or combined to form a decoding processing unit, and the decoding processing is executed for each decoding processing unit.

  According to the first aspect or the second aspect of the present invention, high-speed reproduction, reverse reproduction, and high-speed reverse reproduction of compressed and encoded data can be performed. In particular, the I picture and the P picture are held at fixed positions determined by the number of picture types of the bank memory corresponding to the number of pictures, so that compression coding can be performed without performing complicated bank memory control. High-speed playback, reverse playback, and high-speed reverse playback of data can be performed.

  According to the third aspect of the present invention, compression-encoded data can be decoded. In particular, a GOP is divided or combined based on the number of bank memories to form a decoding processing unit. When using this decoder, it is possible to prevent the occurrence of decoding delay and undecoded pictures.

  Embodiments of the present invention will be described below. Correspondences between the configuration requirements of the present invention and the embodiments described in the detailed description of the present invention are exemplified as follows. This description is to confirm that the embodiments supporting the present invention are described in the detailed description of the invention. Accordingly, although there are embodiments that are described in the detailed description of the invention but are not described here as embodiments corresponding to the constituent elements of the present invention, It does not mean that the embodiment does not correspond to the configuration requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  The information processing apparatus according to the first aspect of the present invention (for example, the playback apparatus in FIG. 1) includes a decoding unit (for example, the decoder 22 to the decoder 24 in FIG. 1) for decoding the compression-encoded video data and a decoding unit. Supply control means (for example, the PCI bridge 17 in FIG. 1) for controlling the supply of compressed encoded video data, and control means (for example, the CPU 20 in FIG. 1) for controlling processing executed by the supply control means and the decoding means. The decoding means includes a processing unit in which decoding processing is executed (for example, in forward reproduction, in coding order, 13 pictures other than the first two B pictures of the first GOP, and the second picture after the second picture. 16 pictures in total with 3 pictures of the first IBB of the GOP, and in reverse playback, 13 pictures other than the first 2 B pictures of the second GOP And the number of bank memories (for example, the video bank of FIG. 2) corresponding to the number of pictures included in the first GBB of the first IBB of the third GOP displayed in the reverse display order. A memory 82) for holding the decoded picture data, and the control means holds the I picture and the P picture in a fixed position determined by the picture type in the bank memory and held in the bank memory. The decoding process by the decoding means is controlled so that the decoded picture data is used as a reference image as necessary.

  The control means can be further provided with a playback speed command means (for example, the CPU 11 in FIG. 1) for instructing the playback speed, and the control means is included in the processing unit based on the playback speed commanded by the playback speed command means. The picture output from the decoding means can be selected from among the pictures to be decoded. The decoding means performs decoding processing execution means (decoding processing unit 77 in FIG. 2) for executing decoding processing, and pictures to the decoding processing execution means. Picture supply control means (for example, the elementary stream address determination unit 73 in FIG. 2) for controlling the supply of the picture, and the picture supply control means is a picture included in the processing unit based on the control of the control means. Of these, the I picture and the P picture, and the B picture selected as the picture output from the decoding means. The decoding processing means decodes each picture supplied by the picture supply control means and selects it as a picture output from the decoding means based on the control of the control means. Can be output.

  A plurality of decoding means can be provided. The output switching means (for example, as shown in FIG. 1) receives supply of uncompressed data output from the plurality of decoding means, and selectively outputs the supplied uncompressed data. A selector 25) can be further provided, and the control means can further control the processing by the output switching means.

  The information processing method according to the first aspect of the present invention, the program recorded on the recording medium, and the program supply the compressed encoded video data to a plurality of decoders (for example, the decoder 22 to the decoder 24 in FIG. 1). Supply control step to be controlled (for example, the process of step S105 in FIG. 15) and a processing unit in which the decoding process is executed (for example, in forward reproduction, in the coding order, the first two B pictures of the first GOP) 16 pictures in total, including 13 pictures other than the first 3 pictures of the IBB at the beginning of the second GOP, and in reverse playback, 13 pictures other than the first 2 B pictures in the second GOP are reversed. According to the number of pictures included in a total of 16 pictures including the first three IBB pictures of the third GOP displayed in the display order of A decoding step (for example, step S192 in FIG. 18) for decoding the compressed encoded video data whose supply to the decoder is controlled by the processing in the supply control step using a number of bank memories (for example, the video bank memory 82 in FIG. 2). Or the processing in step S193), and the bank memory holds the I picture and the P picture at fixed positions determined by the picture type. In the decoding step processing, the decoded processing has been held in the bank memory. The picture data is used as a reference image as necessary, and decoding is executed.

  An information processing apparatus according to the second aspect of the present invention (for example, the playback apparatus in FIG. 1) is stored in a storage unit (for example, HDD 16 in FIG. 1) for storing compression-encoded video data and the storage unit. Reading means (for example, the south bridge 15 in FIG. 1) that reads and outputs the compression-encoded video data, decoding means (for example, the decoders 22 to 24 in FIG. 1) for decoding the compression-encoded video data, and decoding means Control means (for example, PCI bridge 17 in FIG. 1) for controlling the supply of compression-encoded video data to the computer, and control means (for example, CPU 20 in FIG. 1) for controlling processing executed by the supply control means and the decoding means. And a playback speed command means (for example, the CPU 11 in FIG. 1) for commanding the playback speed to the control means. Processing unit (for example, in forward reproduction, in coding order, the total of 13 pictures other than the first two B pictures of the first GOP and the three pictures of the first IBB of the second GOP after that) In 16-picture reverse playback, 13 pictures other than the first two B pictures of the second GOP and three pictures of the first IBB of the third GOP displayed before in the reverse display order The number of bank memories (for example, the video bank memory 82 in FIG. 2) corresponding to the number of pictures included in the total 16 pictures) is held, and the decoded picture data is held. Is held in a fixed position determined by the picture type in the bank memory, and the decoded-processed pin held in the bank memory. Cha data is to be utilized as a reference image as needed, to control the decoding processing by the decoding means.

  An information processing method according to the second aspect of the present invention, a program recorded on a recording medium, and a program read out the compressed encoded video data stored in the storage unit (for example, in step S1 of FIG. 3). Processing), a playback speed command supply step for supplying a playback speed command (for example, the process of step S5 or step S11 in FIG. 3), and a playback speed command acquisition step for acquiring the playback speed command (for example, FIG. 15). Processing in step S101), a supply control step (for example, processing in step S105 in FIG. 15) for controlling the supply of compressed encoded video data to a plurality of decoders (for example, the decoder 22 to the decoder 24 in FIG. 1), The processing unit in which the decoding process is executed (for example, in forward reproduction, in the coding order, at the head of the first GOP A total of 16 pictures including 13 pictures other than the B picture and 3 pictures of the IBB at the beginning of the second GOP behind the 13 pictures. In reverse playback, 13 pictures other than the 2 B pictures at the beginning of the second GOP And the number of bank memories (for example, the video bank of FIG. 2) corresponding to the number of pictures included in the first GBB of the first IBB of the third GOP displayed in the reverse display order. And a decoding step (for example, the processing in step S192 or step S193 in FIG. 18) for decoding the compressed encoded video data whose supply to the decoder is controlled by the processing in the supply control step using the memory 82) The I picture and P picture are held at fixed positions determined by the picture type. Tsu in processing flop is used as a reference image picture data of the decoded processed held in the bank memory is needed, the decoding is performed.

  An information processing apparatus (for example, the reproduction apparatus in FIG. 1) according to the third aspect of the present invention is an information processing apparatus that decodes compression-encoded video data, and includes decoding means (for example, a decoding unit that decodes compression-encoded video data). Decoder 22 through decoder 24) in FIG. 1, supply control means (for example, PCI bridge 17 in FIG. 1) for controlling the supply of compressed encoded video data to the decode means, and processing executed by the supply control means and the decode means Control means (for example, CPU 20 in FIG. 1), and the decoding means has a predetermined number of bank memories (for example, video bank memory 82 in FIG. 2) to hold the decoded picture data. The compression-encoded video data is composed of GOPs, and the control means controls the I picture or P picture included in the 1 GOP compression-encoded video data. The GOP is divided or combined by comparing the number of data and the number of bank memories to form a decoding processing unit, the supply control unit is controlled, and the decoding unit is supplied with compressed encoded video data. To supply.

  An information processing method according to the third aspect of the present invention, a program recorded on a recording medium, and a program detecting step (for example, step S603 in FIG. 60) for detecting the configuration of a GOP included in compression-encoded video data And a comparison step (for example, step S604 in FIG. 60) for comparing the number of I pictures or P pictures included in 1 GOP compression-encoded video data with the number of bank memories for holding decoded picture data. , Step S605, step S607, or step S609) and a decoding processing unit configuration step (for example, FIG. 60) that divides or combines GOPs to form a decoding processing unit based on the comparison result by the processing of the comparison step. Step S606, Step S608, Step S610, or Step Including the S611), and decoding processing step of performing a decoding process for each decoding processing unit constituted by the processing of the decoding processing unit configured step (e.g., step S612 in FIG. 60).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a hardware configuration of a playback apparatus 1 to which the present invention is applied.

  A CPU (Central Processing Unit) 11 is connected to the north bridge 12 and controls processing such as reading of data stored in an HDD (Hard disk Drive) 16, scheduling of decoding executed by the CPU 20, decoding In addition, a command for instructing start, change, or end of processing such as display output control is generated and output. The north bridge 12 is connected to a PCI bus (Peripheral Component Interconnect / Interface) 14. For example, under the control of the CPU 11, the north bridge 12 receives supply of data stored in the HDD 16 via the south bridge 15 and receives the PCI bus. 14, and supplied to the memory 18 via the PCI bridge 17. The north bridge 12 is also connected to the memory 13, and exchanges data necessary for the processing of the CPU 11.

  The memory 13 is a storage memory that can store data necessary for processing executed by the CPU 11 and that can be accessed at high speed, such as DDR (Double Data Rate). The south bridge 15 controls writing and reading of data in the HDD 16. The HDD 16 stores compressed and encoded stream data.

  The PCI bridge 17 includes a command buffer 31 and a result buffer 32 therein, and is connected to a memory 18 that buffers stream data read from the HDD 16 under the control of the CPU 11. The PCI bridge 17 can supply stream data read from the HDD 16 based on the control of the CPU 11 to the memory 18 and store the stream data, and stream data stored in the memory 18 based on the control of the CPU 20. Is supplied to the decoders 22 to 24. The PCI bridge 17 controls transmission / reception of a control signal corresponding to a command or a result via the PCI bus 14 or the control bus 19.

  The command buffer 31 receives commands written from the CPU 11 via the north bridge 12 and the PCI bus 14, and reads written commands from the CPU 20 via the control bus 19. The result buffer 32 receives a result written to the command by the CPU 20 via the control bus 19 and reads the written result from the CPU 11 via the north bridge 12 and the PCI bus 14. ing.

  The memory 18 stores compression-encoded stream data read by the HDD 16 based on the control of the PCI bridge 17 and is configured by, for example, SDRAM (Synchronous Dynamic Random Access Memory). .

  The CPU 20 reads a command written in the command buffer 31 of the PCI bridge 17 by the CPU 11 via the control bus 19, and processes executed by the PCI bridge 17, the decoders 22 to 24, and the selector 25 according to this command. To control. The memory 21 stores data necessary for the processing of the CPU 20.

  The decoders 22 to 24 decode the supplied compressed and encoded stream data based on the control of the CPU 20 and output an uncompressed video signal. The decoder 22 has a memory 41 therein, the decoder 23 has a memory 42 therein, and the decoder 24 has a memory 43 therein, and the compressed and encoded stream data supplied as necessary. Alternatively, the decoded uncompressed video signal can be held. The decoders 22 to 24 may be provided as independent devices that are not included in the playback device 1.

  The selector 25 can switch the output of uncompressed SDI (Serial Digital Interface) data output by the decoder 22 to the decoder 24 with frame accuracy based on the setting by the CPU 20.

  Note that the playback device 1 in FIG. 1 may be configured as a single device or may be configured by a plurality of devices. For example, in the playback device of FIG. 1, the CPU 11, the north bridge 12, the memory 13, the south bridge 15, and the HDD 16 are assumed to be a part of the configuration of the personal computer. An expansion card or expansion board such as PCI bus 14, PCI bridge 17, memory 18, control bus 19, CPU 20, memory 21, decoder 22 to decoder 24, and selector 25 are provided with a personal computer. You may make it function as the reproducing | regenerating apparatus 1 by attaching an expansion card. Further, these may be further divided into a plurality of devices to constitute the playback device 1.

  Next, the operation of the playback device 1 will be described.

  The HDD 16 stores compressed video data compressed by the MPEG Long GOP method.

  The CPU 11 controls the south bridge 15 via the north bridge 12 to read out the compressed and encoded stream data from the HDD 16 based on a user operation input supplied from an operation input unit (not shown). Via the north bridge 12, the PCI bus 14, and the PCI bridge 17, it is supplied to the memory 18 for storage, and information indicating the playback speed (including information indicating the playback direction), a decode start command, or a display start A command or the like is written into the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14.

  The CPU 20 determines a schedule for decoding and displaying the compressed and encoded stream data based on the command from the CPU 11 written in the command buffer 31 of the PCI bridge 17. Specifically, the CPU 20 selects the decoders 22 to 24 used for decoding, the input timing of the compression-encoded stream data to the decoders 22 to 24, the decoding timing for each frame, the reference image The setting of the bank position, the allocation of the bank memory at the time of decoding, and the output of the decoded picture, that is, the display timing are determined.

  Then, the CPU 20 controls the PCI bridge 17 so that the compressed and encoded stream data stored in the memory 18 corresponds to one of the decoders 22 to 24 based on the determined schedule. To supply.

  The CPU 20 controls the decoders 22 to 24 to decode the supplied compressed and encoded data. The decoders 22 to 24 decode the supplied compressed and encoded stream data, generate non-compressed SDI data, and output to the selector 25.

  Then, the CPU 20 controls the selector 25 to switch the output of uncompressed SDI data output from the decoders 22 to 24.

  FIG. 2 is a block diagram showing a more detailed configuration of the decoders 22 to 24. As shown in FIG.

  The input processing unit 71 supplies the compression-encoded stream data supplied from the PCI bridge 17 to the memory controller 74 and stores it in the input buffer 75. From the supplied stream data, the start address, The data size, picture header information, Q matrix, etc. are acquired and supplied to the address management table 72.

  The address management table 72 stores information such as the head address in units of pictures, data size, picture header information, and Q matrix supplied from the input processing unit 71 as table information that can be distinguished by table ID, for each picture. To do.

  The elementary stream address determination unit 73 can supply the stream data stored in the input buffer 75 to the decode processing unit 77 on a picture basis based on a control signal supplied from the CPU 20 via the control bus 19. As described above, the head address and picture size information of the corresponding picture are read out from the table information indicated by the predetermined table ID held in the address management table 72 and supplied to the memory controller 74.

  The memory controller 74 controls writing and reading of stream data to the input buffer 75. In other words, the memory controller 74 writes the stream data supplied from the input processing unit 71 to the input buffer 75, and based on the start address and picture size information of the corresponding picture supplied from the elementary stream address determination unit 73. The predetermined picture is read out and supplied to the decoding processing unit 77.

  The input buffer 75 corresponds to a part of the recording area of the memory 41 to the memory 43 shown in FIG. 1 constituted by a storage memory such as SDRAM, and stores stream data under the control of the memory controller 74. .

  The control bus 76 outputs control signals supplied from the CPU 20 via the data bus 19 to an elementary stream address determining unit 73, a decoding processing unit 77, a write image address determining unit 78, a reference image address determining unit 79, and an output. In addition to being supplied to the address determination unit 80, information related to processing executed in the decoders 22 to 24 is supplied to the CPU 20 via the data bus 19.

  The decode processing unit 77 decodes the MPEG video stream read from the input buffer 75 by the memory controller 74 with reference to the reference image supplied from the reference image address determination unit 79 as necessary, and the decoded base. The band (uncompressed) video signal is supplied to the writing image address determination unit 78.

  The writing image address determination unit 78 acquires a control signal supplied from the CPU 20 via the data bus 19 via the control bus 76, and is decoded and supplied by the decoding processing unit 77 based on this control signal. The recording position of the baseband video signal in the video bank memory 82, that is, the bank position to be stored is determined, and the baseband video signal is stored in a predetermined bank position of the video bank memory 82 via the memory controller 81. Let

  The reference picture address determination unit 79 acquires a control signal supplied from the CPU 20 via the data bus 19 via the control bus 76, and based on this control signal, the reference picture address determination unit 79 precedes the P picture in the video bank memory 82. Frame image data held in the bank designated as the reference image bank in the direction (forward), and frame images held in the bank designated as the reference image bank in the forward direction and backward direction (backward) of the B picture Data is read by controlling the memory controller 81 and supplied to the decoding processing unit 77.

  The output address determination unit 80 acquires a control signal supplied from the CPU 20 via the data bus 19 via the control bus 76, and the frame image data held in the video bank memory 82 based on this control signal. The output image, that is, the bank of the frame to be displayed is designated, the memory controller 81 is controlled to read and output.

  The memory controller 81 controls writing and reading of frame images to and from the video bank memory 82. The video bank memory 82 is an 8-bank (8-side) frame image bank memory corresponding to a part of the recording area of the memory 41 to the memory 43 shown in FIG. Based on the control of the memory controller 81, the frame image data of one frame is held in the set bank.

  Next, control processing executed by the CPU 11 will be described with reference to the flowchart of FIG.

  In step S <b> 1, the CPU 11 controls the north bridge 12 and the south bridge 15 to read out from the HDD 16 a plurality of GOPs of the compression-coded stream data designated as stream data to be decoded and output by the user.

  In step S <b> 2, the CPU 11 supplies the read stream data of the plurality of GOPs to the PCI bridge 17 via the PCI bus 14 and transfers it to the memory 18.

  In step S <b> 3, the CPU 11 supplies the command buffer 31 of the PCI bridge 17 with the data transfer completion and the picture information of the picture included in the GOP transferred to the memory 18 via the north bridge 12 and the PCI bus 14. Thus, the CPU 20 is notified of data transfer completion and picture information. The picture information includes, for example, information such as a picture type, header information for each picture, and picture size.

  In step S <b> 4, the CPU 11 receives a notification of completion of preparation from the CPU 20 and the memory 18. Specifically, the CPU 11 reads, via the north bridge 12 and the PCI bus 14, the results for the data transfer completion and picture information notification supplied by the CPU 20 to the result buffer 32 of the PCI bridge 17 via the control bus 19. At the same time, the memory 18 is notified of the end of storage of stream data of a plurality of GOPs via the PCI bridge 17, the PCI bus 14 and the north bridge 12.

  In step S <b> 5, the CPU 11 receives a command to start reproduction output processing by a user from an operation input unit (not shown), and sends a decode start command to the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14. Then, the decoder 22 through the decoder 24 start the decoding process. The decode start command includes display speed information.

  In step S6, the CPU 11 transmits a display start command to the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14, and in step S7, the SDI signal obtained by decoding by the decoder, that is, Then, display of 1 GOP of the baseband image signal is started.

  In step S8, the CPU 11 determines the result of the display start command supplied by the CPU 20 to the result buffer 32 of the PCI bridge 17 via the control bus 19, that is, in step S194 of FIG. The display completion notification for each frame written in 32 is read via the north bridge 12 and the PCI bus 14, and it is always checked which picture display has been completed, thereby detecting the completion of 1GOP display. To do.

  In step S9, the CPU 11 determines whether or not the displayed GOP is the last stream data to be displayed. In step S9, when it is determined that the displayed GOP is the last of the displayed stream data, the process is terminated.

  When it is determined in step S9 that the displayed GOP is not the last of the displayed stream data, in step S10, the CPU 11 determines, for example, stream data based on a signal supplied from an operation input unit (not shown). It is determined whether or not a command accompanying a change in the input stream state, such as an end of playback, a change in stream data being played back, or a command to change the playback speed or direction, is input.

  If it is determined in step S10 that a command accompanying a change in the input stream state has been input from the user, in step S11, the CPU 11 stores the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14. A command corresponding to the user's operation input is transmitted.

  In step S10, when it is determined that the command accompanying the change of the input stream state is not input from the user, or after the process of step S11 is completed, in step S12, the CPU 11 stores the stream data to be displayed on the HDD 16. Determine if it remains. If it is determined in step S12 that there is no stream data to be displayed remaining in the HDD 16, the process returns to step S7 and is transferred to the memory 18, and the process after step S7 is performed on the stream data not yet displayed. Repeated.

  If it is determined in step S12 that stream data to be displayed remains in the HDD 16, in step S13, the CPU 11 controls the north bridge 12 and the south bridge 15 to decode and output the stream data. One GOP following the GOP that has been transferred to the memory 18 is read from the HDD 16.

  In step S <b> 14, the CPU 11 supplies the read 1 GOP stream data to the PCI bridge 17 via the PCI bus 14 and transfers it to the memory 18. In other words, the memory 18 basically holds a predetermined number of GOPs except when the vicinity of the end portion of the stream data to be reproduced is held.

  In step S 15, the CPU 11 supplies the command buffer 31 of the PCI bridge 17 with the data transfer completion and the picture information of the picture included in the GOP transferred to the memory 18 via the north bridge 12 and the PCI bus 14. Thus, the CPU 20 is notified of data transfer completion and picture information. The picture information includes, for example, information such as picture type and picture unit size.

  In step S <b> 16, the CPU 11 receives a notification of completion of preparation from the CPU 20 and the memory 18. Specifically, the CPU 11 reads the result for the data transfer completion and picture information notification supplied from the CPU 20 to the PCI bridge result buffer 32 via the control bus 19 via the north bridge 12 and the PCI bus 14. The memory 18 is notified of the end of storage of stream data of a plurality of GOPs via the PCI bridge 17, the PCI bus 14, and the north bridge 12.

  After the process of step S16 ends, the process proceeds to step S7, and the subsequent processes are repeated.

  By such processing, the CPU 11 can supply a command to the CPU 20, receive a result for the supplied command, and control decoding of stream data and display of the decoded data.

  Here, the case where the decoded data is displayed one GOP at a time has been described. However, when the decoded SDI signal is output to the outside, the CPU 11 causes the CPU 20 to execute the same process. It is needless to say that decoding of stream data and output of the decoded data to the outside can be controlled by receiving a result for the supplied command.

  Then, the CPU 20 controls the decoding process by a plurality of decoders (decoder 22 to decoder 24 in FIG. 1) based on the command supplied from the CPU 11. Specifically, the CPU 20 selects the decoder 22 to decoder 24 used for decoding, in other words, which of the decoder 22 to decoder 24 is the destination of the compressed and encoded stream data. Execute the process to select. Further, the CPU 20 sets the input timing of the compressed encoded stream data to the corresponding one of the decoders 22 to 24, the decoding timing for each picture, the setting of the bank position of the reference image, and the bank memory at the time of decoding. The output of the allocated and decoded pictures, that is, the display timing is determined, and the PCI bridge 17, the decoders 22 to 24, and the selector 25 are controlled based on these timings. Hereinafter, decoding and display output control by the CPU 20 will be described with reference to FIGS.

  The CPU 20 has a plurality of registers and information queues that can hold various types of information in the memory 21 in order to control the decoding processing by the decoders 22 to 24 and the selection processing of the SDI signal output from the selector 25. Has been made. The information queue has a first-in first-out (FIFO) queue structure, a command supplied by the CPU 11, and a picture ID associated with the picture type information and information accompanying the picture ID (for example, time information). Can be stored at a predetermined depth for each use of scheduling of decoding timing and control of decoding and display.

  The CPU 20 controls the decoding and display timing using the information stored in the corresponding information queue. That is, the picture is not queued in the memory 21, but the picture ID is set in each information queue based on the control of the CPU 20, so that the CPU 20 performs arithmetic processing for controlling the timing of decoding and display. Can be executed.

  As an information queue for storing various information, for example, a command queue for storing a command acquired from the command buffer 31 of the PCI bridge 17 via the control bus 19, and a picture ID of an input picture corresponding to a processing queue are used. From the input picture queue stored in the coding order, the display ID information stored in the display order after reordering the picture IDs stored in the input picture queue and rearranging them in the display order, and the picture ID stored in the display order information queue In addition to the I / P picture decoding queue for extracting and storing the P pictures and rearranging them in the decoding order, and the picture IDs set in the I / P picture decoding queue, time information corresponding to these picture IDs is further stored. I / P pic with time information Decoding queue, display order setting queue in which picture IDs are set in display order, and display order setting queue with time information in which time information corresponding to these picture IDs is further accumulated in addition to the picture IDs set in the display order setting queue A display queue that holds a picture ID of a picture to be displayed next is used for various controls by the CPU 20. Details of information stored in each queue, depth of each queue, and processing executed using the information will be described later.

  Next, the process 1 performed for every frame is demonstrated with reference to the flowchart of FIG. This processing routine is repeatedly executed for each frame until the stream data for which display is instructed is completed or until display is instructed.

  In step S31, an input stream state change process which will be described later with reference to FIG. 5 is executed. The input stream state change process is a process for confirming whether or not a new command has been issued from the CPU 11.

  In step S32, decode schedule processing 1 described later with reference to FIG. 6 is executed. In decode schedule processing 1, decode timing is scheduled.

  In step S33, the CPU 20 refers to a time counter that is a counter representing the processing time in units of one frame, so that the processing target is the first frame of the stream data to be reproduced in the decoding order. It is determined whether the frame is one of the sixth frames from the first frame.

  If it is determined in step S33 that the processing target is not one of the sixth frames to the sixth frame of the stream data to be reproduced in the decoding order, in step S34 A one-frame delay display setting process, which will be described later with reference to FIG. 38, is executed. By the one-frame delay display setting process, the display of the baseband frame image decoded and generated in the frame control process 1 of step S35 in the immediately preceding process routine is set.

  If it is determined in step S33 that the processing target is any one of the first to sixth frames of the stream data to be reproduced in the decoding order, or After the process of S34 is completed, a frame control process 1 described later with reference to FIG. 18 is executed in step S35. In the frame control process 1, a frame to be processed is decoded.

  In step S36, the CPU 20 determines whether or not the processing of all frames has been completed. If it is determined in step S36 that all the frames have not been processed, the CPU 20 increments a time counter in units of one frame in step S37.

  After the process of step S37 is completed, the process returns to step S31, and the subsequent processes are repeated. If it is determined in step S36 that all frames have been processed, the process ends.

  In this way, the CPU 20 counts up the time counter for each processing of one frame, schedules decoding according to the playback speed instructed by the user, performs decoding for each frame, and displays the display. Can be set.

  Next, the input stream state change process executed in step S31 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S <b> 51, the CPU 20 checks a command queue that accumulates commands acquired from the command buffer 31 of the PCI bridge 17.

  In step S52, the CPU 20 determines whether or not a new command for changing the input stream state is stored in the command queue, such as a change in playback speed (including the playback direction) or a playback end command. To do.

  If it is determined in step S52 that a new command is stored in the command queue, in step S53, the CPU 20 sets the playback speed and playback direction based on the command stored at the earliest time in the command queue. Change the stream input state based on. If it is determined in step S52 that no new command is stored in the command queue, or after the process of step S53 is completed, the process returns to step S31 in FIG. 4 and proceeds to step S32.

  By such processing, the command stored at the earliest time in the command queue for accumulating commands acquired from the command buffer 31 of the PCI bridge 17 is referred to, and the stream input state is changed based on the commands.

  Next, the decoding schedule process 1 executed in step S32 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S71, the CPU 20 refers to the input picture queue and determines whether or not the input picture queue is empty. The input picture queue is an information queue set in an input process (step S72) described later, and an input picture for which a decoding schedule is determined next and a picture ID of a picture necessary for the scheduling are set.

  As shown in FIG. 7, when the stream data handled by the playback apparatus 1 is MPEG LONG GOP stream data in which 1 GOP is composed of 15 pictures, a decoder 22 that performs decoding processing for each 15 pictures equivalent to 1 GOP. Each of the decoders 24 has 13 pictures excluding the two B pictures that are headed in the display order in each GOP, and, in the case of playback in the forward direction, is headed in the display order in the preceding GOP. In the case of the IBB 3 pictures in the reverse direction, 16 pictures including the IBB 3 pictures that are the head in the display order are supplied in the GOP behind them.

  With reference to FIG. 8, a description will be given of the decoding unit that each of the decoders 22 to 24 takes charge of. In FIG. 8, the arrangement of pictures supplied to the decoders 22 to 24 is shown in display order. In the playback apparatus 1, the decoding process is performed in one of the decoders 22 to 24 for each 1 GOP (15 pictures). As described above, each of the decoders 22 to 24 has a decoding process. Sixteen pictures including 13 pictures excluding the two B pictures that are first in the display order in 1 GOP and three pictures from the top in the display order in the preceding or subsequent GOP are supplied. Therefore, when the playback direction is the forward direction, as shown in FIG. 8A, the first decoder among the decoders 22 to 24 receives the 13 pictures excluding the first two B pictures of the first GOP and the second picture. The first three pictures of the first GOP are supplied, and the second decoder is supplied with the 13 pictures excluding the first two B pictures of the second GOP and the first three pictures of the third GOP. 13 pictures excluding the top two B pictures of the third GOP and the top three pictures of the fourth GOP are supplied to the decoder. Also, when the playback direction is the reverse direction, as shown in FIG. 8B, the first decoder among the decoders 22 to 24, the 13 pictures excluding the first two B pictures of the second GOP, and the third picture The first three pictures of the first GOP are supplied, and 13 pictures excluding the first two B pictures of the first GOP and the first three pictures of the second GOP are supplied to the second decoder.

  In the input picture queue, a picture ID of an input picture that is waiting for a decoding timing schedule among pictures input to the decoder 22 to decoder 24 and a picture necessary for the scheduling is set. That is, in the input picture queue, 18 picture IDs of 15 pictures of 1 GOP and 3 pictures of IBB at the head of the GOP before or after the GOP stream data are held in the LONG GOP stream data.

  In FIG. 9A, the picture IDs of 15 pictures of the first GOP and 3 pictures of the first IBB of the second GOP after the stream data of the MPEG LONG GOP are input for reproduction in the forward direction. FIG. 9B shows a state in which the picture queue is set, and in order to reproduce in the reverse direction, among the LONG GOP stream data of MPEG, the 15 pictures of the second GOP are preceded in the reverse display order. The picture ID of the three pictures of the first IBB of the third GOP to be displayed is set in the input picture queue.

  If it is determined in step S71 that the input picture queue is not empty, the process returns to step S32 in FIG. 4 and proceeds to step S33. In other words, the decoding schedule processing is executed collectively for each processing unit of 16 pictures of 13 pictures set from a position shifted by 2 pictures from the 15 LONG GOP pictures and the next three pictures.

  If it is determined in step S71 that the input picture queue is empty, in step S72, an input process to be described later is executed using the flowchart of FIG.

  In step S73, based on the value of the register indicating the decoder that supplies the next data, the CPU 20 determines whether the display order setting queue with time information set corresponding to the decoder that receives the next data is empty. Judge whether or not. The display order setting queue with time information is a queue that is set in the schedule determination processing with time information in step S80 described later. Each of the plurality of decoders (in the case described with reference to FIG. Each of 24 three decoders). Details of the display order setting queue with time information will be described later with reference to the flowchart of FIG.

  In step S73, when it is determined that the display order setting queue with time information corresponding to the decoder to which data is next supplied is not empty, that is, for each scheduled picture corresponding to 1 GOP, decoding processing is performed for each frame. Alternatively, when the display process is being executed, the process returns to step S32 in FIG. 4 and proceeds to step S33.

  In step S73, when it is determined that the display order setting queue with time information corresponding to the decoder to which data is next supplied is empty, in step S74, the CPU 20 executes reorder processing. The reorder process is a process of replacing the picture IDs corresponding to 18 pictures arranged in the coding order set in the input picture queue with the display order and setting them in the display order information queue.

  Therefore, when the playback direction is the forward direction, as shown in FIG. 10A, the picture ID set in the input picture queue described with reference to FIG. 9A is rearranged in the display order in the display order information queue. When the playback direction is the reverse direction, the picture ID set in the input picture queue described with reference to FIG. 9B is displayed in the display order information queue as shown in FIG. 10B. Sorted to be set.

  In step S74, when the reorder process is executed and the picture ID is set in the display order information queue, all the picture IDs queued in the input picture queue are output, and the input picture queue becomes empty. In other words, the case where the input picture queue is determined to be empty in the above-described step S71 is a case where the reorder processing for the picture ID queued in the input picture queue is performed, and the input picture queue is not empty. In the case where it is determined that the display order setting queue with time information corresponding to the decoder that receives the next data supply is executed after the input process is executed in step S72 of the decode schedule process 1 executed before this process. This is a case where the reorder process is not executed in step S74 because it is not empty.

  In step S75, the CPU 20 refers to the display order information queue set in step S74, and sets the picture IDs of the I and P pictures in the GOP to be decoded in the I / P picture decoding queue in the decoding order. The I / P picture decoding queue is a queue for setting the picture IDs of the I picture and the P picture that are decoded prior to the B picture in decoding order.

  FIG. 11 shows an I / P picture decoding queue in forward reproduction and backward reproduction. As shown in FIG. 11A, the I / P picture decoding queue in the case of forward reproduction includes the I picture and the P picture among the picture IDs set in the display order information queue described with reference to FIG. 10A. The picture IDs of the corresponding six pictures are set, and the I / P picture decoding queue in the case of reverse playback is set to the display order information queue described with reference to FIG. 10B as shown in FIG. 11B. Among the picture IDs, picture IDs of six pictures corresponding to the I picture and the P picture are set.

  In step S76, the CPU 20 designates a bank position for storing the I picture and the P picture and a reference picture bank in the decoding of the P picture. The I picture and the P picture use six fixed banks among the eight banks in the video bank memory 82 of FIG.

  By decoding the I picture and P picture (also called anchor frame) first and fixing the bank position held after decoding, playback from any picture, such as forward direction, backward direction, heading, etc. It can be done immediately. Also, by decoding the I picture and P picture first, the shorter the processing time of the six I pictures and P pictures that are decoded first, the more the user can start playback or change the playback speed or playback direction. The time from the instruction to the display start reflecting the instruction can be shortened regardless of the position in the GOP of the display start frame, or the display time when displaying an arbitrary picture by scrub playback can be shortened. As a result, the performance during high-speed playback is improved.

  In step S77, the CPU 20 designates the position of the reference image bank in the decoding of the B picture, based on the bank position where the I picture and the P picture are stored, respectively, designated by the process in step S76. Note that the bank position where the B picture is stored is specified in the frame control process 1 described later.

  In step S78, the CPU 20 sets a display order setting queue.

  FIG. 12 shows a display order setting queue in forward reproduction and reverse reproduction. As shown in FIG. 12A, the display order setting queue in the case of forward playback is the first two B of the 18 picture IDs queued in the display order information queue described with reference to FIG. 10A. Of the pictures and 15 picture IDs excluding the last I picture, that is, among the pictures supplied to one of the decoders 22 to 24 in the case of forward reproduction described with reference to FIG. 8A The picture IDs of 15 pictures excluding the I picture are set in the display order.

  As shown in FIG. 12B, the display order setting queue in the case of reverse playback is the first two of the 18 picture IDs queued in the display order information queue described with reference to FIG. 10B. 15 picture IDs excluding one B picture and the last I picture, that is, among pictures supplied to one of the decoders 22 to 24 in the case of backward reproduction described with reference to FIG. 8B The picture IDs of 15 pictures excluding the last I picture are set in the actual display order.

  When the display order setting queue is set in step S78, all the picture IDs queued in the display order information queue are output, and the display order information queue becomes empty.

  In step S79, a display phase determination process to be described later is executed using the flowchart of FIG. The display phase determination process is a process for determining a difference in timing between the start of decoding and the start of display in a processing unit of 15 frames + 1 frame equivalent to 1 GOP.

  In step S80, a schedule determination process with time information, which will be described later using the flowchart of FIG. 17, is executed. The schedule determination process with time information is a process of executing decoding scheduling and setting time information in association with a picture ID in a predetermined information queue in order to control the decoding timing for each frame.

  Decoding and display timings are scheduled by the processing in steps S79 and S80. Specifically, for example, when the display head is an I picture or a P picture, for example, when the playback direction is the normal direction and playback is at normal speed, as shown in FIG. Is decoded, the B picture is decoded, and the display start timing is shifted by 6 pictures from the decoding start, so that the decoding timing and display timing of the B picture are shifted by one frame. The timing schedule is performed. Also, when the playback direction is the reverse direction, in other words, when the display head is a B picture, such as when the speed setting is a negative value, as shown in FIG. After the picture is decoded, the B picture is decoded, and the display start timing is shifted by 7 pictures from the decoding start, so that the B picture decoding timing and the display timing are shifted by one frame. The display timing is scheduled.

  In step S81, the CPU 20 executes a process of switching the setting of a decoder that supplies data to be decoded next. Specifically, the CPU 20 has one less register value indicating the decoder that supplies the next data than the number of decoders (in the reproducing apparatus 1 described with reference to FIG. 1, three decoders 22 to 24). When the value is equal to 2 (2 in the reproducing apparatus 1 described with reference to FIG. 1), the register value is set to 0. When the register value is 2 or less than the number of decoders, the register value is incremented by 1. After the process of step S81 is completed, the process returns to step S32 in FIG. 4 and proceeds to step S33.

  By such processing, the decoding and display timing is scheduled.

  Next, the input process executed in step S72 of FIG. 6 will be described with reference to the flowchart of FIG.

  In step S101, the CPU 20 displays the display speed information included in the decode start command transmitted from the CPU 11 to the command buffer 31 in step S5 of the control process described with reference to FIG. 3, or the control described with reference to FIG. The speed setting value is acquired from the command corresponding to the user's operation input transmitted from the CPU 11 to the command buffer 31 in step S11 of the process, and stored in the memory 21. When the speed setting value is a positive value, the playback process may be forward playback, and when the speed setting value is a negative value, the playback process may be backward playback.

  For example, when the speed set value is 1, normal playback is assumed. When the speed set value is 1 or more, high speed playback is assumed. When the speed set value is a positive value less than 1. When the speed setting value is −1, it is assumed that the playback speed is normal, and when the speed setting value is −1 or less, the playback speed is high speed. When the speed setting value is a negative value less than the absolute value 1, it can be assumed that low-speed backward reproduction is performed.

  In step S102, the CPU 20 determines whether the process to be executed is a positive direction reproduction process based on whether the speed setting value acquired in step S101 is a positive value or a negative value. .

  If it is determined in step S102 that the playback process is in the forward direction, in step S103, the CPU 20 determines the 1 GOP including 13 frames from the top of the 15 frames to be decoded next and the I and B of the next GOP. , B picture IDs are set in the input picture queue described with reference to FIG. 9A.

  If it is determined in step S102 that the playback process is not forward, that is, reverse playback, in step S104, the CPU 20 includes 1 GOP including 13 frames from the back of the 15 frames to be decoded next. Then, the picture IDs of the previous GOP I, B, and B pictures are set in the input picture queue described with reference to FIG. 9B.

  After the processing of step S103 or step S104 is completed, in step S105, the CPU 20 controls the PCI bridge 17 to set the input picture queue and the value of the register indicating the decoder that supplies the next data (reproduced). The first GOP of the stream is a value determined by the initial setting, and the second and subsequent GOPs are values determined by the process of step S81 in FIG. 6). Of the stream data, the transfer of the 16-frame compressed image data described with reference to FIG. 8 to a predetermined decoder among the decoders 22 to 24 is controlled.

  The input processing unit 71 of the decoders 22 to 24 supplies the supplied 16-frame data to the memory controller 74 and stores it in the input buffer 75, and also stores it in the address management table 72 as the start address and data size in units of pictures. , Information such as picture header information and Q matrix is supplied, and each picture is held as table information distinguishable by table ID.

  In step S <b> 106, the CPU 20 supplies a result indicating the end of the transfer processing of the stream equivalent to 1 GOP to the predetermined decoder among the decoders 22 to 24 to the result buffer 32 of the PCI bridge 17 via the control bus 19. Thus, the CPU 11 is notified of the end of the stream transfer process, and the process returns to step S72 in FIG. 6 and proceeds to step S73.

  By such processing, 16 frames of data serving as the decoding processing unit described with reference to FIG. 8 is supplied to the decoders 22 to 24.

  Next, the display phase determination process for setting the phase for delaying the display start timing with respect to the decode start timing, executed in step S79 of FIG. 6, will be described with reference to the flowchart of FIG.

  In step S131, the CPU 20 stores information on the number of pictures to be displayed, which is set in the display order setting queue described with reference to FIG. 12, in the display picture number register. In FIG. 12, since the picture IDs for 15 pictures are set in the display order setting queue, the value 15 is stored in the display picture number register.

  In step S132, the CPU 20 holds the total number of decoded I and P pictures held in the I / P picture decoding queue described with reference to FIG. 11 in the I / P picture number register. In FIG. 11, since picture IDs for six pictures are set in the I / P picture decoding queue, the value 6 is stored in the I / P picture number register.

  In step S133, the CPU 20 determines whether or not the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is a B picture. This is synonymous with determining whether the reproduction direction is the forward direction or the reverse direction when calculating the phase shift amount in the normal speed reproduction or the normal speed reproduction in the reverse direction. After the thinning process 1 described later is executed, even if the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is a B picture, depending on the playback speed setting value, The playback direction may be the forward direction or the reverse direction.

  If it is determined in step S133 that the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is a B picture, in step S134, the CPU 20 decodes the I picture and P picture to be decoded. The number obtained by adding 1 to the total number corresponds to the picture ID held in the display order setting queue with respect to the decoding start timing of the I picture and P picture corresponding to the picture ID held in the I / P picture decoding queue. A temporal phase shift amount disp_phase of the picture display start timing is set.

  For example, as shown in FIG. 14 described above, when the playback speed is −1, the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is B picture. After the I picture and P picture are decoded, the display start timing is shifted by 7 pictures from the start of decoding, and the B picture decode is performed so that the B picture decode timing and the display timing are shifted by one frame. Is done.

  When it is determined in step S133 that the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is not a B picture, in step S135, the CPU 20 determines the decoded I picture and P picture. Of the display start timing of the picture corresponding to the picture ID held in the display order setting queue with respect to the decode timing of the I picture and P picture corresponding to the picture ID held in the I / P picture decode queue It is assumed that the amount of phase shift is disp_phase.

  For example, as shown in FIG. 13 described above, when the playback speed is 1 time, the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is I picture, and in B picture Therefore, after the I picture and P picture are first decoded, the display start timing is shifted by 6 pictures from the start of decoding, so that the B picture decode timing and the display timing are shifted by one frame. B picture is decoded.

  After the processing of step S134 or step S135 is completed, in step S136, the CPU 20 stores the display phase shift amount disp_phase determined in step S134 or step S135 in an internal register.

  In step S137, the CPU 20 determines whether or not the GOP being processed is a display start GOP (including a playback start portion at a corresponding speed when the playback speed is changed).

  If it is determined in step S137 that the GOP being processed is not the display start GOP, in step S138, the CPU 20 determines the previous processing from the display phase shift amount disp_phase determined in step S134 or step S135, that is, The display phase shift amount prev_disp_phase in the GOP displayed immediately before is subtracted, and the result is stored in the internal register as the shift amount correction value disp_zero, and the display phase shift amount determined in step S134 or step S135. By substituting disp_phase for the display phase shift amount prev_disp_phase in the GOP displayed immediately before, the process returns to step S79 in FIG. 6 and proceeds to step S80.

  If it is determined in step S137 that the GOP being processed is the display start GOP, in step S139, the CPU 20 sets an initial value 0 as the shift amount correction value disp_zero and stores it in the internal register. Then, the process returns to step S79 in FIG. 6 and proceeds to step S80.

  By such processing, the phase for delaying the display start timing with respect to the decode start timing is determined.

  Next, the schedule determination process with time information executed in step S80 of FIG. 6 will be described with reference to the flowchart of FIG.

  In step S161, the CPU 20 determines whether the processing target is a decoding processing unit corresponding to the first 1 GOP after the input stream state is changed. Since the picture type is changed before and after the thinning out in at least the second and subsequent decoding processing units, in step S161, it is determined that the processing target is the decoding processing unit corresponding to the first 1 GOP. The processing proceeds to step S166 described later.

  If it is determined in step S161 that the processing target is not a decoding processing unit corresponding to the first 1 GOP, in step S162, the CPU 20 changes the leading picture from an I picture or a P picture to a B picture before and after thinning. Determine whether or not.

  If it is determined in step S162 that the leading picture has been changed from the I picture or the P picture to the B picture before and after the thinning, in step S163, the CPU 20 sets the phase adjustment value to 1, and the process will be described later. The process proceeds to S167.

  If it is determined in step S162 that the leading picture has not been changed from the I picture or the P picture to the B picture before and after the thinning, in step S164, the CPU 20 determines that the leading picture is the I or P from the B picture before and after the thinning. It is determined whether or not the picture has been changed.

  If it is determined in step S164 that the leading picture has been changed from the B picture to the I or P picture before and after the thinning, in step S165, the CPU 20 sets the phase adjustment value to −1, and the process will be described later. The process proceeds to S167.

  If it is determined in step S161 that the processing target is the first decoding processing unit, or in step S164, it is determined that the leading picture has not been changed from a B picture to an I or P picture before and after thinning. In this case, in step S166, the CPU 20 sets the phase adjustment value to 0.

  After the process of step S163, step S165, or step S166 is completed, in step S167, the CPU 20 starts with the 16 pictures in the decoding process unit to be decoded by any one of the decoders 22 to 24. The value of the decoding start time information time_base indicating the timing at which the frame is decoded is prev_time_base, which is the decoding start time information of the previous decoding processing unit, disp_zero indicating the display phase shift amount correction value, and thinning processing 1 described later Is calculated using the time information adjustment value added_count calculated in step S1 and the phase adjustment value obtained by the processing in steps S161 to S166 (formula (1)).

Decoding start time information time_base = previous GOP decoding start time information prev_time_base−display phase shift amount correction value disp_zero + time information adjustment value added_count + phase adjustment value
... (1)

  Note that, when the calculation process of Expression (1) is executed for the display start GOP, prev_time_base indicating the decoding start time information of the previous GOP and the time information adjustment value added_count calculated in the previous GOP thinning process 1 Is calculated as 0.

  In step S168, the CPU 20 sets an I / P picture decoding queue with time information corresponding to the decoder to which data is next supplied.

  The I / P picture decoding queue with time information is associated with the picture ID set in the I / P picture decoding queue described with reference to FIG. 11, and information on the decoding start time time_base of the picture decoded at the head, In addition, the count value of the time counter in units of one frame is set, and is provided corresponding to each decoder (here, each of the decoder 22 to decoder 24) provided in the playback device 1. Yes.

  Specifically, the CPU 20 refers to the value of the register indicating the decoder that supplies the next data, and sets the I / P picture decode queue with time information corresponding to the decoder to which the next data is supplied. The CPU 20 uses the information of the decoding start time information time_base described above as information indicating the timing at which the frame corresponding to the head picture ID among the picture IDs queued in the I / P picture decoding queue is decoded. As information indicating the timing at which each frame corresponding to each picture ID is decoded, the count value of the time counter in units of one frame is used.

  In step S168, when the I / P picture decoding queue with time information is set, all the picture IDs queued in the I / P picture decoding queue are output, and the I / P picture decoding queue becomes empty.

  In step S169, the CPU 20 sets a display order setting queue with time information corresponding to the decoder to which data is next supplied.

  The display order setting queue with time information is associated with the picture ID set in the display order setting queue described with reference to FIG. 12, and the shift amount of the display timing phase with respect to the decoding start time of the picture displayed at the head A value obtained by subtracting 1 from the above and a count value of a time counter in units of one frame are set for each decoder provided in the reproducing apparatus 1 (here, each of the decoders 22 to 24). It is provided corresponding to.

  Specifically, the CPU 20 refers to the value of the register indicating the decoder that supplies the next data, and sets the display order setting queue with time information corresponding to the decoder to which the next data is supplied. The CPU 20 displays the display timing of the frame corresponding to the first frame in the actual display order among the picture IDs queued in the display order setting queue, and the phase shift amount determined in the display phase determination process described above A value obtained by subtracting 1 from disp_phase is used as reference time information in accordance with the decoding timing of the B picture, and information indicating the timing at which each frame corresponding to each picture ID is decoded is in units of one frame. The count value of the time counter is used.

  When the display order setting queue with time information is set in step S169, all the picture IDs queued in the display order setting queue are output, and the display order setting queue becomes empty.

  In step S170, the CPU 20 adds the value obtained by adding the value held in the display picture number register in step S131 of FIG. 16 described above to the decoding start time information time_base as the decoding start time information prev_time_base of the previous GOP. The process is saved, and the process returns to step S80 in FIG. 6 and proceeds to step S81.

  By such processing, the decoding processing timing for 16 frames as a decoding processing unit is set.

  16 and 17, the decoding phase and the display phase are based on the number of I pictures and P pictures, the number of pictures to be displayed, and whether or not the picture to be displayed at the top is a B picture. And is set as time information. As a result, the speed is dynamically increased by following the change in the number of pictures that are decoded and output in each decoder, which are generated when high-speed playback in the forward and reverse directions is performed using a plurality of decoders. It is possible to change and display continuously decoded images. In addition, even when a change in playback speed is commanded and the thinning interval is changed from a picture at an arbitrary position, the playback speed can be adjusted within the supported speed range by reflecting the increase or decrease in the number to be displayed. It is possible to change the speed continuously by changing the frame unit.

  The decode schedule process 1 is executed in step S32 of FIG. 4 by the process described with reference to FIGS.

  Then, in step S33 of FIG. 4, it is determined whether the frame is any frame from the first frame to the sixth frame, and is determined to be any frame from the first frame to the sixth frame. In this case, the one-frame delay display setting process in step S34 is skipped, and the frame control process 1 is executed in step S35.

  Next, the frame control process 1 executed in step S35 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S191, the CPU 20 refers to the time management counter, which is a counter for managing the timing of each process executed in the playback device 1, and the I / P picture decode queue with time information, and the display time has passed. It is determined whether there is stream data. If it is determined in step S191 that there is stream data whose display time has passed, the process proceeds to step S197 described later.

  If it is determined in step S191 that there is no stream data whose display time has passed, an I picture and P picture decoding process, which will be described later with reference to FIG. 19, is executed in step S192.

  In step S193, a B picture decoding process to be described later with reference to FIG. 20 is executed.

  In step S194, the CPU 20 notifies the display picture information to the CPU 11. Specifically, the CPU 20 writes display picture information as a result for the display start command transmitted from the CPU 11 in step S6 of FIG. 3 to the result buffer 32 of the PCI bridge 17 via the control bus 19. The display picture information is notified to the CPU 11. The CPU 11 can know which picture of which GOP the picture to be displayed by referring to the display picture information written in the result buffer 32 of the PCI bridge 17.

  In step S195, the CPU 20 increments the time management counter.

  In step S196, a thinning process 1 described later with reference to FIG. 23 is executed, and the process returns to step S35 in FIG. 4 and proceeds to step S36.

  If it is determined in step S191 that there is stream data whose display time has passed, underflow processing described later with reference to FIG. 35 is executed in step S197, and the processing returns to step S35 in FIG. The process proceeds to step S36.

  If display is not delayed by such processing, decoding for one frame is executed based on the set decoding schedule, display picture information is notified to the CPU 11, and thinning-out processing 1 is executed. When the display is delayed, underflow processing described later is executed.

  Next, the I picture and P picture decoding processing executed in step S192 in FIG. 18 will be described with reference to the flowchart in FIG.

  In step S221, the CPU 20 determines whether the value of the time management counter matches the time information associated with the picture ID of the next decoded picture set in the I / P picture decoding queue with time information. Judge whether or not. If it is determined in step S221 that the value of the time management counter does not match the time information set in the I / P picture decoding queue with time information, the process returns to step S192 in FIG. Proceed to

  If it is determined in step S221 that the value of the time management counter matches the time information set in the I / P picture decoding queue with time information, in step S222, the CPU 20 is set as a decoder that performs decoding. Any one of the decoders 22 to 24 is controlled via the control bus 19 to decode the I picture or P picture, and the decode command is executed from the I / P picture decode queue with time information. The picture ID corresponding to the selected picture is deleted.

  Specifically, the CPU 20 refers to the value held in the register indicating the decoder that supplies the next data, and the elementary stream address of the decoder 22 to the decoder 24 that is set as the decoder that performs decoding. The determining unit 73 is controlled to cause the memory controller 74 to read out the picture data corresponding to the picture ID set in the I / P picture decoding queue with time information from the input buffer 75 and to the decoding processing unit 77. Supply.

  When the picture to be decoded is an I picture, the CPU 20 controls the decoding processing unit 77 to decode the I picture supplied from the memory controller 74 and also controls the writing image address determining unit 78 to perform decoding. The frame data is supplied to the memory controller 81 and stored in the bank designated for storing the I picture in step S76 of FIG. 6 in the video bank memory 82. Further, when the picture to be decoded is a P picture, the CPU 20 controls the reference picture address determination unit 79, and based on the reference bank position of the P picture set in step S76 in FIG. The reference picture stored in the video bank memory 82 is read out and supplied to the decoding processing unit 77, and the decoding processing unit 77 is controlled to decode and write the P picture supplied from the memory controller 74. The image address determination unit 78 is controlled to supply the decoded frame data to the memory controller 81 and stored in the bank designated for storing the P picture in the step S76 of FIG. 6 in the video bank memory 82. .

  After the process of step S222 is completed, the process returns to step S192 of FIG. 18 and proceeds to step S193.

  Through such processing, an I picture or a P picture is decoded based on the set schedule.

  Next, the B picture decoding process executed in step S193 in FIG. 18 will be described with reference to the flowchart in FIG.

  In step S241, the CPU 20 determines whether or not the setting of the time management counter matches the time information corresponding to the current first picture ID set in the display order setting queue with time information. In the display phase determination process described above, the time information set in the display order setting queue with time information indicates the display timing of the frame corresponding to the first frame in the actual display order among the 15 frames at the time of scheduling. A value obtained by subtracting 1 from the determined phase shift amount disp_phase (reference time information in accordance with the decoding timing of the B picture) or each picture ID other than the first frame in the actual display order among 15 frames. The count value of the corresponding time counter in units of one frame. If it is determined in step S241 that the setting of the time management counter does not match the time information set in the display order setting queue with time information, the process returns to step S193 in FIG. 18 and proceeds to step S194.

  In step S241, when it is determined that the setting of the time management counter matches the time information set in the display order setting queue with time information, in step S242, the CPU 20 determines that it matches the time information. It is determined whether or not the picture ID corresponds to the B picture.

  In step S242, when it is determined that the picture ID corresponding to the B picture is determined to match the time information, in step S243, the CPU 20 sets the decoders 22 to 22 that are set as decoders that perform decoding. Any one of the decoders 24 is controlled via the control bus 19 to decode the B picture indicated by the picture ID.

  Specifically, the CPU 20 refers to the value held in the register indicating the decoder that supplies the next data, and the elementary stream address of the decoder 22 to the decoder 24 that is set as the decoder that performs decoding. The determination unit 73 is controlled so that the picture data corresponding to the picture ID set in the display order setting queue with time information is read from the input buffer 75 by the memory controller 74 and supplied to the decoding processing unit 77. . Then, the CPU 20 controls the reference picture address determination unit 79, and the reference stored in the video bank memory 82 by the memory controller 81 based on the reference bank position of the B picture set in step S77 in FIG. The image is read out and supplied to the decoding processing unit 77, and the decoding processing unit 77 is controlled to decode the B picture supplied from the memory controller 74.

  In step S244, the CPU 20 sets a bank position for storing the B picture. That is, the CPU 20 controls the write image address determination unit 78 so that B pictures are alternately stored in two banks of the video bank memory 82 that are not designated for storing I pictures or P pictures. To do. The CPU 20 controls the writing image address determining unit 78 to supply the frame data decoded by the decoding processing unit 77 to the memory controller 81, and the decoded frame data at the set bank position in the video bank memory 82. Remember.

  In step S242, when it is determined that the picture ID corresponding to the time information is not the picture ID corresponding to the B picture, or after the process of step S244 is completed, the CPU 20 adds the time information. The current top picture ID set in the display order setting queue is set in the display queue. The display queue is a queue of depth 1 that holds only one picture ID.

  Specifically, when the CPU 20 determines in step S242 that it is not the picture ID corresponding to the B picture that is determined to match the time information, in step S222 of FIG. 19 described above, the time information is added. Since decoding of the I picture or P picture corresponding to the current first picture ID set in the display order setting queue is controlled, the CPU 20 sets the picture ID corresponding to the I picture or P picture in the display queue. To do. In step S242, if it is determined that the picture ID corresponding to the B picture corresponds to the time information, and decoding of the B picture is controlled in step S243, the CPU 20 adds the time information. The current head picture ID set in the display order setting queue, that is, the picture ID corresponding to the decoded B picture is set in the display queue.

  The current top picture ID set in the display order setting queue with time information is output from the display order setting queue with time information and displayed next to the picture corresponding to the picture ID set in the display queue. The picture ID corresponding to the picture is the head of the display order setting queue with time information, or the display setting queue with time information is empty. After the process of step S245 ends, the process returns to step S193 in FIG. 18 and proceeds to step S194.

  In this way, decoding is executed based on the time information set in the I / P picture decoding queue with time information and the display order setting queue with time information. In the case of forward reproduction, as shown in FIG. 21, the I picture and P picture are decoded based on the time information set in the I / P picture decoding queue with time information, and the display order with time information is set. The B picture is decoded based on the time information set in the queue. In the case of reverse playback, as shown in FIG. 22, the I picture and P picture are decoded based on the time information set in the I / P picture decoding queue with time information, and the display with time information is displayed. Based on the time information set in the order setting queue, the B picture is decoded.

  In addition, as shown in FIGS. 21 and 22, the decoding timing of the B picture is determined by the 1-frame delay display setting process described later, regardless of whether the playback is in the forward direction or the backward direction. The decoding timing is shifted by one frame from the display timing.

  21 and 22 show the decode timing and the display timing in the case of 1 × speed and −1 × speed, respectively, but when high-speed playback is executed, time information is obtained by thinning-out processing 1 described later. The setting of the added display order setting queue is changed, and in the next processing routine, decoding is executed based on the setting of the display order setting queue with time information after the thinning-out process 1. When high-speed playback is executed, all B pictures are not decoded but are decoded by being thinned out. However, decoding of I pictures and P pictures also applies to all pictures when high-speed playback is executed. Executed in

  Next, with reference to the flowchart of FIG. 23, the thinning process 1 executed in step S195 of FIG. 18 will be described.

  In step S271, the CPU 20 uses the stream input state set in the input stream state change process described with reference to FIG. 5, and the playback speed based on the user setting is a fast playback in the forward direction or the reverse direction. It is determined whether or not. If it is determined in step S271 that the playback is not at high speed, the process returns to step S196 in FIG. 18 and proceeds to step S36 in FIG.

  If it is determined in step S271 that high-speed playback is being performed, in step S272, the CPU 20 determines whether or not the frame being processed is the first frame of the first GOP after the speed setting has been changed. .

  If it is determined in step S272 that the frame being processed is the first frame of the first GOP after the input stream state has been changed, in step S273, the CPU 20 determines the thinning cycle based on the speed setting value. Is stored in a register.

  Specifically, for example, when reproduction is performed at 2 × speed or −2 × speed, the CPU 20 stores the thinning cycle in the register as ½, and when reproduction is performed at 3 × speed or −3 × speed, Is saved in the register as 1/3.

  In step S274, the CPU 20 resets a frame counter that counts the number of frames in the thinning process 1 regardless of the decoding process unit.

  In step S272, if it is determined that the frame being processed is not the first frame of the first GOP after the input stream state is changed, or after the processing of step S274 is completed, the CPU 20 determines in step S275. Whether or not all the display order setting queues with time information have been confirmed based on whether or not the confirmed flag is set in association with the picture ID held in the display order setting queue with time information. Determine whether. The confirmed flag is a flag that is set in the display order setting queue with time information by the processing in step S280 described later. If it is determined in step S275 that all display order setting queues with time information have been confirmed, the process returns to step S196 in FIG. 18 and proceeds to step S36 in FIG.

  If it is determined in step S275 that all the display order setting queues with time information have not been confirmed, in other words, it is determined that there is still a picture ID for which the confirmed flag is not set in the display order setting queue with time information. In step S276, the CPU 20 increments the frame counter by one.

  In step S277, as a result of determining the thinning cycle, the CPU 20 refers to the thinning cycle held in the register and the value of the frame counter, and determines whether or not the frame indicated by the frame counter is displayed. Specifically, when the thinning cycle is ½, the CPU 20 performs display if the value of the frame counter that counts the number of frames is 2n (n is a positive integer), otherwise, When the display is not performed or the thinning cycle is 1/3, if the value of the frame counter that counts the number of frames is 3n (n is a positive integer), the display is performed. Otherwise, the display is performed. Do not display. If it is determined in step S277 that display is to be performed, that is, if it is determined that the frame is not thinned, the process proceeds to step S280 described later.

  If it is determined in step S277 that it is not displayed, that is, if it is determined that the frame is to be thinned out, in step S278, the CPU 20 sets the picture ID corresponding to the processing target frame to the display order with time information. Either delete from the queue, or associate a flag indicating non-display with the corresponding picture ID in the display order setting queue with time information.

  In step S279, the time information resetting process described with reference to FIG. 24 is executed.

  When it is determined in step S277 that the frame indicated by the frame counter is displayed, or after the processing of step S279 is completed, in step S280, the CPU 20 indicates in the frame counter of the display order setting queue with time information. The confirmed flag is set in association with the picture ID corresponding to the frame to be processed, the process returns to step S275, and the subsequent processes are repeated.

  By such processing, the picture ID of the frame that is not displayed is deleted from the display order setting queue with time information, or is not displayed with respect to the corresponding picture ID in the display order setting queue with time information. Are associated with each other. The B picture decoding process and the one-frame delay display setting process (described later) are executed with reference to the display order setting queue with time information. Since the setting of the display order setting queue with time information is updated based on the setting of high-speed playback, the B picture decoded after this processing routine is only displayed (the B picture to be thinned is decoded) The I picture or P picture to be thinned out is not decoded but is not displayed.

  Further, the frame counter is continuously incremented without being reset regardless of the GOP until the speed setting is changed, that is, until the input stream state is changed. For example, 1 GOP is composed of 15 frames. If the denominator of the decimation period becomes a value that cannot divide the number of frames constituting 1 GOP, such as 2 × speed, 4 × speed, −2 × speed, −4 × speed, etc. Even when the position of a picture that is not changed is changed, it is possible to easily determine whether or not display is performed based on the thinning cycle by using the value of the frame counter indicating the order of frames in the input stream. it can.

  In this way, the B picture is thinned out by the stream input to the decoder, and the I picture and the P picture are thinned out at equal intervals by stopping the display after decoding, so that the dynamic change of the speed can be followed. It is possible to perform high-speed playback. Since the I picture and the P picture may be used as reference images from other pictures at the time of decoding, this method performs high-speed playback by thinning out at equal intervals while reducing the number of faces of the bank memory as much as possible. Therefore, it is an effective method.

  Thus, when two decoders are used while thinning out at equal intervals, the speed can be set in a range of -3 to 3 times, and when three decoders are used, -6 to 6 times. In addition, the speed can be set within the range of the above, and the high-speed reproduction can be realized by applying the same control of the thinning process 1 to two or more decoders.

  Next, the time information resetting process executed in step S279 of FIG. 23 will be described with reference to the flowchart of FIG.

  In step S <b> 301, the CPU 20 detects the number of picture changes (the number of deletions or the number of additions) due to the thinning-out process 1 generated by the change of the speed setting value.

  In step S302, the CPU 20 sets the number of picture changes (the number of deletions or the number of additions) as the time information adjustment value added_count.

  In step S303, the CPU 20 resets the time information in the display order setting queue with time information so as to be continuous, and the process returns to step S279 in FIG. 23 and proceeds to step S280.

  By such processing, the setting of the display order setting queue with time information after thinning is changed corresponding to the set value of the playback speed, and the display order setting queue with changed time information is changed in subsequent processing routines. Based on this, the decoding timing of the B picture and the display setting of all frames are controlled.

  The setting of the display order setting queue with time information in the thinning process 1 will be described with reference to FIGS. In FIG. 25 to FIG. 30, the state of scheduling before thinning is shown in the upper part by describing the thinned frames with dotted lines, and the state of scheduling after the thinning process 1 is shown in the lower part. ing. In FIG. 25 to FIG. 30, the numbers 0, 1, and 2 in parentheses are information accumulated in information queues respectively set corresponding to any of the decoders 22 to 24, or This indicates that the process is executed in any one of the decoders 22 to 24.

  For example, in the case of high-speed playback at + 2 × speed, as shown in FIG. 25, the change in the number of displayed pictures in the decoding unit before and after thinning is −7, and the time information adjustment value added_count is −7. Since the picture type of the first picture of the next decoding unit is changed from I picture to B picture, the phase adjustment value is −1. Therefore, the adjustment amount of time_base is the display phase shift amount correction value disp_zero. When is 0, it is -8. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  Further, for example, in the case of high-speed playback at −2 × speed, as shown in FIG. 26, the change in the number of displayed pictures in the decoding unit before and after thinning is −7, and the time information adjustment value added_count is −7. . Since the picture type of the first picture of the next decoding unit remains the B picture, the phase adjustment value is 0, and therefore the time_base adjustment amount is 0 for the display phase shift amount correction value disp_zero. When it becomes -7. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  For example, in the case of high-speed playback at + 4 × speed, as shown in FIG. 27, the change in the number of displayed pictures in the decoding unit before and after thinning is −11, and the time information adjustment value added_count is −11. Since the picture type of the first picture of the next decoding unit is changed from I picture to B picture, the phase adjustment value is −1, and the adjustment amount of time_base is the display phase shift amount correction value disp_zero. When is 0, it is −12. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  For example, in the case of high-speed playback at -4 times speed, as shown in FIG. 28, the change in the number of displayed pictures in the decoding unit before and after thinning is -11, and the time information adjustment value added_count is -11. Since the picture type of the first picture of the next decoding unit remains the B picture, the phase adjustment value is 0, and therefore the time_base adjustment amount is 0 for the display phase shift amount correction value disp_zero. Then -11. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  For example, in the case of high-speed playback at + 5 × speed, as shown in FIG. 29, the change in the number of displayed pictures in the decoding unit before and after thinning is −12, and the time information adjustment value added_count is −12. Since the picture type of the first picture of the next decoding unit remains unchanged from I picture, the phase adjustment value is 0, and therefore the display phase shift amount correction value disp_zero is 0 as the time_base adjustment amount. When it becomes -12. The display start timing of the second GOP is delayed by 6 frames from the decoding start timing of the I picture because the head is the I picture.

  For example, in the case of -5 × high-speed playback, as shown in FIG. 30, the change in the number of displayed pictures in the decoding unit before and after thinning is −12, and the time information adjustment value added_count is −12. Since the picture type of the first picture of the next decoding unit remains the B picture, the phase adjustment value is 0, and therefore the time_base adjustment amount is 0 for the display phase shift amount correction value disp_zero. When it becomes -12. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  Then, as shown in FIG. 25 to FIG. 30, in step S167 of the schedule determination process with time information described with reference to FIG. Calculated based on 1). Then, as shown in FIG. 25 to FIG. 30, based on the calculated decoding start time information time_base, decoding of the I picture and P picture corresponding to the picture ID set in the I / P picture decoding queue with time information The start timing is determined, and the decoding and display schedule of the B picture after the thinning-out process 1 is determined based on the calculated decoding start time information time_base and the display order setting queue with time information from which frames that are not displayed are deleted. The

  For example, when a playback apparatus 1 decodes a LONG GOP MPEG stream with N = 15 and M = 3, the bank No. of the eight banks of the video bank memory 82 in FIG. The remaining banks are such that the anchor frames of I, P, P, P, P, and I are fixedly stored in the six banks 0 to 5, and the B picture is decoded one frame before the display. No. By storing alternately in 6 and 7, even if the bank provided in the video bank memory 82 has only 8 faces, the number of decoders in the forward direction and the reverse direction (reproduction of this embodiment) In the apparatus 1, it is possible to execute display within a speed range determined corresponding to three).

  The setting of the video bank memory 82 in FIG. 2 will be described with reference to FIGS.

  FIG. 31 is a diagram illustrating a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. At the same time as the display timing of the first I2 picture, the bank No. 6 stores the B3 picture, and at the same time when the B3 picture is displayed, the bank No. 7 is stored, and at the timing when the B3 picture is displayed, the bank No. in which the B3 picture that has been displayed is stored is stored. 6 and the bank No. in which the I2 picture that has been used as a reference image has been stored. 0 is released. After that, bank no. 6 and 7 store B pictures alternately so that the display timing of the B pictures is delayed by one frame with respect to the decode timing, and are released after display. In addition, bank No. 1 to 5 are released when the stored P picture is used as a reference image. That is, bank no. 0 to 5 are not released when the picture is displayed, but are released when the use of the stored I picture or P picture as the reference image and the display of the picture are completed.

  FIG. 32 is a diagram showing a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. At the same time as the display timing of the first I2 picture, the bank No. 6 stores the B4 picture, and at the same time the B4 picture is displayed, the bank No. 7 is stored, and at the timing when the B6 picture is displayed, the bank No. in which the B4 picture that has been displayed is stored is stored. 6 and the bank No. in which the I2 picture that has been used as a reference image has been stored. 0 is released. After that, bank no. In 6 and 7, B pictures that are not thinned out are alternately stored so that the display timing of the B pictures is delayed by one frame with respect to the decoding timing, and are released after display. In addition, bank No. 0 to 5 are not released when the picture is displayed, but are released when the use of the stored I picture or P picture as the reference image and the display of the picture are completed. . 1 to 5 are released when the use of the stored P picture as a reference image and the display of the picture are completed.

  FIG. 33 is a diagram illustrating a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. And bank no. 5 at the next timing when the I2 picture is stored in the bank No. 6 stores the B1 picture, and at the same time when the B1 picture is displayed, the bank No. 7 stores the B0 picture, and at the timing when the B1 picture is displayed, the bank No. in which the B1 picture that has been displayed is stored is stored. 6 is opened. After that, bank no. In 6 and 7, the B picture is alternately stored so that the display timing of the B picture is delayed by one frame with respect to the decode timing, and is released after display. Bank No. 0 to 5 are released at the later timing of the display of the picture or the point in time when the use of the stored I picture or P picture as the reference image ends. That is, in the case of FIG. Since the I2 picture stored in 0 is displayed last, it is not released until the display of this GOP is completed.

  FIG. 34 is a diagram illustrating a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. And bank no. 5 at the next timing when the I2 picture is stored in the bank No. 6 stores the B1 picture, and at the timing next to the timing when the B1 picture is displayed, the bank No. 7 stores the B12 picture and the bank No. in which the B1 picture that has been displayed is stored. 6 is opened. After that, bank no. In 6 and 7, B pictures that are not thinned out are alternately stored so that the display timing of the B pictures is delayed by one frame with respect to the decoding timing, and are released after display. Bank No. 0 to 5 are released at the later timing of the display of the picture or the point in time when the use of the stored I picture or P picture as the reference image ends. That is, in the case of FIG. Since the I2 picture stored in 0 is displayed last, it is not released until the display of this GOP is completed.

  In this way, when video data compressed using general bidirectional inter-frame prediction in an image compression method typified by MPEG or the like is played back in reverse or at high speed, the I picture and P picture are first used. By decoding and scheduling the decoding of the B picture at the timing one frame before the display, the I picture and the P picture are stored in a fixed position of the bank holding the frame, and complex bank surface control is performed. Without performing the above, it is possible to efficiently realize reverse reproduction and reverse high-speed reproduction by reducing the number of bank faces as much as possible.

  Specifically, if the number of banks holding frames is the total number of I pictures and P pictures included in the decoding processing unit and two planes for storing B pictures, the anchor frame is used. A certain I picture and P picture can be stored in a fixed position of the bank, and high-speed playback and reverse playback can be realized without performing complicated bank surface control.

  For example, as in this embodiment, in an MPEG LONG GOP stream with N = 15 and M = 3, 5 planes of I, P, P, P, and P pictures + 1 plane of the next I picture + 2 planes of B picture In total, by preparing an 8-side video bank memory, I pictures and P pictures are stored at fixed positions in the bank, and high-speed playback, reverse playback, and reverse are performed without complicated bank plane control. Direction high-speed playback can be realized.

  In addition, in order to improve the speed change response by the operation from the user, when the process of decoding the B picture and stopping the display is performed for the purpose of changing the speed in frame units, the decoding of the B picture and the display Even though the timing control is managed separately, it is possible to simplify the bank management by preventing complicated processing for managing the bank. For example, it is illegal in the transient state of the input stream. Even if a reference process or the like is performed, it can be easily restored (underflow process described later), and a speed change can be performed on a frame basis.

  Next, the underflow process executed in step S197 in FIG. 18 will be described with reference to the flowchart in FIG.

  In step S361, the CPU 20 refers to the time management counter and the time counter, and determines whether the stream data is not supplied in time for the display process, that is, whether underflow has occurred. If it is determined in step S361 that no underflow has occurred, the process returns to step S197 in FIG. 18 and proceeds to step S36 in FIG.

  If it is determined in step S361 that underflow has occurred, in step S362, the CPU 20 sets the value of the time counter, which is a counter indicating the time, to the start time of the I / P picture decoding queue with time information. At the same time, the process returns to step S197 in FIG. 18 and proceeds to step S36 in FIG.

  36 and 37, correction of the value of the time counter when an underflow occurs will be described. In FIGS. 36 and 37, the numbers 0, 1, and 2 in parentheses are information accumulated in information queues respectively set corresponding to any of the decoders 22 to 24, or This indicates that the process is executed in any one of the decoders 22 to 24.

  FIG. 36 shows the information stored in the information queue and the decoding and display for the time counter when no underflow has occurred in -5 × playback as in the case described with reference to FIG. The timing of is shown. FIG. 36 shows an example in which the value of the time counter of the decoding start timing of an I picture of a certain GOP is 7.

  For example, when an underflow has occurred for two frames, as shown in FIG. 37, the time counter is delayed by two frames and the processing is restarted with reference to the time counter. Decoding and display control can be executed without delay.

  By such processing, for example, even when the supply of the stream is delayed due to insufficient throughput of the HDD 16 during high-speed playback, an underflow state due to the delayed supply of the stream is detected, and the time information is counted. It is possible to resume the reproduction process without failure by returning the time underflowed.

  If it is determined in step S36 of FIG. 4 that the processing of all frames has not been completed, the time counter is incremented in step S37, and the process returns to step S31, and for the next frame, The subsequent processing is repeated.

  From the seventh frame onward, in step S33, since it is determined that it is not any frame from the first frame to the sixth frame, one-frame delay display setting processing is executed in step S34.

  Next, with reference to the flowchart of FIG. 38, the one-frame delay display process executed in step S34 of FIG. 4 after the seventh frame will be described.

  In step S361, the CPU 20 displays a display command so that display is performed with a delay of one frame from the decoding processing by the set decoder among the decoders 22 to 24 based on the information held in the display queue. To the set decoder among the decoders 22 and 24 via the control bus 19 and delete the corresponding picture ID in the display queue. At this time, the output address determination unit 80 of the set decoder among the decoders 22 to 24 receives the control signal from the CPU 20 via the control bus 76 and controls the memory controller 80 to control the video bank. The corresponding picture is read from the memory 82 and supplied to the selector 25.

  In step S362, the CPU 20 controls the selector 25 based on the value held in the register indicating the decoder that supplies the next data set in step S81 in FIG. 6, and outputs the decoded frame. The process returns to step S34 in FIG. 4 and proceeds to step S35.

  For example, when the playback speed is 1 time, as described with reference to FIG. 21, with respect to the decoding timing of the B picture executed based on the time information set in the display order setting queue with time information, The display is set in the order of the pictures set in the display order setting queue with time information so that the display of the B picture for one frame is delayed.

  Also, when the playback speed is -1 times, as described with reference to FIG. 22, the decoding timing of the B picture executed based on the time information set in the display order setting queue with time information is also described. Thus, the display is set in the order of the pictures set in the display order setting queue with time information so that the display of the B picture for one frame is delayed.

  25 for high-speed playback at + 2 × speed, FIG. 26 for high-speed playback at −2 × speed, FIG. 27 for high-speed playback at + 4 × speed, and FIG. 28 at + 4 × high-speed playback, + 5 × speed. As shown in FIG. 29 in the case of high-speed playback and in FIG. 30 in the case of high-speed playback at -5 times speed, the processing is executed based on the time information set in the display order setting queue with time information. The display is set in the order of the pictures set in the display order setting queue with time information so that the display of the B picture for one frame is delayed with respect to the decoding timing of the B picture.

  As a result of such processing, if the number of banks holding frames is the total number of I pictures and P pictures included in the decoding processing unit and two planes for storing B pictures, anchor frames The I picture and the P picture can be stored at fixed positions in the bank, and high-speed reproduction, reverse reproduction, and reverse high-speed reproduction can be realized without performing complicated bank surface control.

  The phase shift between the decoding start timing and the display start timing has been described based on the number of I pictures and P pictures included in the decoding processing unit. For example, among the frames included in the decoding processing unit, Based on the number of frames to be displayed, it may be possible to obtain a phase shift between the decode and display start timings.

  When high-speed playback in the forward direction or the reverse direction is executed, for example, in the scheduling of decoding in the second and subsequent decoding processing units, determination of a frame to be displayed and a frame not to be displayed, that is, thinning is performed. Prior to this, for example, an encoding parameter such as a picture type of a picture displayed at the head of a decoding processing unit may be detected in advance.

  For example, before the determination of the frame to be displayed and the frame not to be displayed is made, based on the frame counter counted in the decoding schedule of the previous decoding processing unit and the calculated thinning cycle, the decoding processing unit The picture type of the picture displayed at the head may be detected in advance, or the picture type of the picture displayed at the head of the decoding process unit may be detected in advance by another method. .

  By doing so, it is possible to execute the decoding schedule processing more accurately and at high speed.

  An example of specific processing for detecting in advance the picture type of the picture displayed at the beginning of the decoding processing unit will be described below.

  With reference to the flowchart of FIG. 39, description will be given of a process 2 performed for each frame, in which a process of detecting a picture type of a picture displayed at the head of a decoding process unit in advance can be performed prior to scheduling. This processing routine is repeatedly executed for each frame until the stream data for which display is instructed is completed or until display is instructed.

  In step S431, the input stream state change process described with reference to FIG. 5 is executed.

  In step S432, decode schedule processing 2 described later with reference to FIG. 40 is executed. In the decode schedule process 2, the decode timing is scheduled. Prior to the decoding timing schedule processing, processing for detecting in advance the picture type of the picture displayed at the head of the decoding processing unit is executed.

  In step S433, the CPU 20 refers to the time counter that is a counter representing the processing time in units of one frame, so that the processing target is the first frame of the stream data to be reproduced in the decoding order. It is determined whether the frame is one of the sixth frames from the first frame.

  If it is determined in step S433 that the processing target is not one of the sixth frames to the sixth frame of the stream data to be reproduced in the decoding order, in step S434 The one-frame delay display setting process described with reference to FIG. 38 is executed.

  If it is determined in step S433 that the processing target is any one of the sixth frame to the sixth frame of the stream data to be reproduced in the decoding order, or step After the processing of S434 is completed, in step S435, frame control processing 2 described later with reference to FIG. 42 is executed. In the frame control process 2, the frame to be processed is decoded.

  In step S436, the CPU 20 determines whether or not processing of all frames has been completed. If it is determined in step S436 that processing of all frames has not been completed, in step S437, the CPU 20 increments a time counter in units of one frame.

  After the process of step S437 is completed, the process returns to step S431, and the subsequent processes are repeated. If it is determined in step S436 that all the frames have been processed, the process ends.

  In this way, the CPU 20 counts up the time counter for each processing of one frame, schedules decoding according to the playback speed instructed by the user, performs decoding for each frame, and displays the display. In this process, a process for detecting in advance the picture type of the picture displayed at the head of the decoding process unit is executed prior to the decoding timing schedule process.

  Next, the decoding schedule process 1 executed in step S432 in FIG. 39 will be described with reference to the flowchart in FIG.

  In steps S471 through S478, basically the same processing as in steps S71 through S78 of FIG. 6 is executed.

  That is, referring to the input picture queue, it is determined whether or not the input picture queue is empty. If it is determined that the input picture queue is not empty, the process returns to step S432 in FIG. Proceed to When it is determined that the input picture queue is empty, the input process described with reference to the flowchart of FIG. 15 is executed.

  Then, it is determined whether or not the display order setting queue with time information set corresponding to the decoder that receives the next data supply is empty, and it is determined that the display order setting queue with time information is not empty. In other words, that is, when the decoding process or the display process is being executed for each frame for the scheduled picture corresponding to 1 GOP, the process returns to step S432 in FIG. 39 and proceeds to step S433.

  When it is determined that the display order setting queue with time information is empty, reorder processing is executed, and the picture IDs of the I picture and P picture of the GOP to be decoded are set in the decoding order in the I / P picture decoding queue. Is done. Then, a bank position for storing the I picture and the P picture, and a reference image bank in the decoding of the P picture are designated, and a reference picture in the decoding of the B picture is based on the bank position in which the I picture and the P picture are respectively stored. The bank position is designated, and the display order setting queue described with reference to FIG. 12 is set.

  In step S479, the thinning process 2 described later with reference to FIG. 41 is executed. This thinning-out process 2 is a process for detecting in advance the picture type of the picture displayed at the head of the decoding process unit prior to the decoding timing schedule process.

  Then, in steps S480 to S482, basically the same processing as the processing executed in steps S79 to S81 in FIG. 6 is executed. That is, the display phase determination process described using the flowchart of FIG. 16 is executed, the schedule determination process with time information described using the flowchart of FIG. 17 is executed, and the timing of decoding and display is scheduled.

  Specifically, the thinning process 2 executed in step S479 can detect in advance the picture type of the picture displayed at the beginning of the decoding processing unit prior to the decoding timing scheduling process. When the head of the picture is an I picture or a P picture, as described with reference to FIG. 13, after the I picture and the P picture are first decoded, the B picture is decoded, and the display start timing is from the start of decoding. The decoding and display timing is scheduled so that the B picture decoding timing and the display timing are shifted by one frame by shifting by six pictures. If the top of the display is a B picture, as described with reference to FIG. 14, after the I picture and the P picture are first decoded, the B picture is decoded, and the display start timing is from the start of decoding. The decoding and display timing is scheduled so that the B picture decoding timing and the display timing are shifted by one frame by shifting by seven pictures.

  Then, a process of switching the setting of a decoder that supplies data to be decoded next is executed, and the process returns to step S432 in FIG. 39 and proceeds to step S433.

  By such processing, the decoding and display timing is scheduled.

  Next, the thinning process 2 executed in step S479 of FIG. 40 will be described with reference to the flowchart of FIG.

  In step S501, based on the stream input state set in the input stream state change process described with reference to FIG. 5, the CPU 20 sets the playback speed based on the user setting to high-speed playback in the forward direction or the reverse direction. It is determined whether or not. If it is determined in step S501 that high-speed playback is not performed, the process proceeds to step S510 described later.

  If it is determined in step S501 that high-speed playback is performed, in step S502, the CPU 20 determines whether or not the frame being processed is the first frame of the first GOP after the speed setting is changed. .

  If it is determined in step S502 that the frame being processed is the first frame of the first GOP after the input stream state has been changed, in step S503, the CPU 20 decimates based on the speed setting value GOP_Speed. Determine the period and save it in the register.

  Specifically, for example, when reproduction is performed at 2 × speed or −2 × speed, the CPU 20 stores the thinning cycle in the register as ½, and when reproduction is performed at 3 × speed or −3 × speed, Is saved in the register as 1/3.

  In step S504, the CPU 20 resets a frame counter that counts the number of frames in the thinning-out process 2 regardless of the decoding process unit.

  In step S502, if it is determined that the frame being processed is not the first frame of the first GOP after the input stream state is changed, or after the processing in step S504 is completed, the CPU 20 determines in step S505. Based on whether or not the confirmed flag is set in association with the picture ID held in the display order setting queue, it is determined whether or not all the display order setting queues have been confirmed. The confirmed flag is a flag that is set in the display order setting queue by processing in step S509 described later. If it is determined in step S505 that all display order setting queues have been confirmed, the process proceeds to step S510 described later.

  If it is determined in step S505 that all display order setting queues have not been confirmed, in other words, if there is a picture ID for which no confirmed flag is set in the display order setting queue, the CPU 20 in step S506 The frame counter is incremented by one.

  In step S507, the CPU 20 refers to the thinning cycle held in the register and the value of the frame counter as a result of determining the thinning cycle, and determines whether or not the frame indicated by the frame counter is displayed. Specifically, when the thinning cycle is ½, the CPU 20 performs display if the value of the frame counter that counts the number of frames is 2n (n is a positive integer), otherwise, When the display is not performed or the thinning cycle is 1/3, if the value of the frame counter that counts the number of frames is 3n (n is a positive integer), the display is performed. Otherwise, the display is performed. Do not display. If it is determined in step S507 that display is to be performed, that is, if it is determined that the frame is not thinned out, the process proceeds to step S509 described later.

  If it is determined in step S507 that the frame is not displayed, that is, if it is determined that the frame is to be thinned out, in step S508, the CPU 20 determines that the frame to be processed in the display order setting queue is not displayed. Set the delete flag to indicate.

  If it is determined in step S507 that the frame indicated by the frame counter is to be displayed, or after the processing of step S508 is completed, in step S509, the CPU 20 sets the frame indicated by the frame counter in the display order setting queue. A confirmed flag is set in association with the corresponding picture ID, the process returns to step S505, and the subsequent processes are repeated.

  If it is determined in step S501 that high-speed playback is not performed, or if it is determined in step S505 that all display order setting queues have been confirmed, in step S510, the CPU 20 thins out the display order setting queue. GOP_Speed, which is a speed setting value at the time of executing process 2, is set, the process returns to step S479 in FIG. 40, and the process proceeds to step S480.

  By such processing, in the display order setting queue, a deletion flag indicating non-display is associated with a non-displayed frame prior to decoding scheduling, so when displaying a decoding schedule, the display is displayed at the head of the decoding processing unit. The picture type of the picture to be played can be detected. The B picture decoded after this processing routine is only displayed (the B picture to be thinned is not supplied to the decoding processing unit 77), and the I picture or P picture to be thinned is decoded. But not displayed.

  Next, the frame control process 2 executed in step S435 in FIG. 39 will be described with reference to the flowchart in FIG.

  In step S541, the CPU 20 refers to the time management counter, which is a counter for managing the timing of each process executed in the playback device 1, and the I / P picture decode queue with time information, and the display time has passed. It is determined whether there is stream data. If it is determined in step S541 that there is stream data whose display time has passed, the process proceeds to step S547 described later, and the underflow process described with reference to FIG. 35 is executed. Returning to step S435 of step 39, the process proceeds to step S436.

  If it is determined in step S541 that there is no stream data whose display time has passed, basically the same processing as that in steps S192 to S195 of FIG. 18 is executed in steps S542 to S545.

  That is, the I picture and P picture decoding process described with reference to FIG. 19 is executed, and the B picture decoding process described with reference to FIG. 20 is executed. Then, the display picture information is notified from the CPU 20 to the CPU 11, and the CPU 20 increments the time management counter. These processes are executed for frames for which the deletion flag is not set (not thinned out) in step S508 of FIG.

  In step S546, the thinning process 3 described later with reference to FIG. 43 is executed, and the process returns to step S435 in FIG. 39 and proceeds to step S436.

  If display is not delayed by such processing, decoding for one frame is executed based on the set decoding schedule, display picture information is notified to the CPU 11, and thinning-out processing 3 is executed. When the display is delayed, the underflow process described using FIG. 35 is executed.

  Next, the thinning process 3 executed in step S546 in FIG. 42 will be described with reference to the flowchart in FIG.

  In step S <b> 571, the CPU 20 sets the playback speed setting compared to the execution of the thinning process that was executed immediately before (when the thinning process 2 is executed in the decoding schedule process 2). It is determined whether or not the speed is increased in the same direction. Specifically, the CPU 20 determines whether or not speed / GOP_speed> 1 is satisfied based on the current speed setting value speed and the GOP_speed set in the display order setting queue. It is determined whether or not the playback speed setting has become faster in the same direction as compared to the execution of the thinning process executed previously. In step S571, whether or not the playback speed setting is faster in the same direction as compared with the execution of the thinning process executed immediately before, that is, whether the speed of the previous thinning process is changed. If it is determined that the time has been delayed or the direction has been reversed, the process returns to step S546 in FIG. 42, and the process proceeds to step S436 in FIG.

  If it is determined in step S571 that the playback speed setting has become faster in the same direction as compared with the execution of the thinning process executed immediately before, the CPU 20 performs the thinning process 2 in step S572. Based on the speed setting values at the time of execution and the current values, a thinning cycle is determined and stored in a register.

  Specifically, the CPU 20 sets the thinning cycle based on the reciprocal of the absolute value of speed / GOP_speed. For example, when the thinning process 2 is executed, the speed setting is double speed, but the current speed setting value is 4 In the case of double speed, the thinning cycle is halved and stored in a register that holds the thinning cycle.

  In step S <b> 573, the CPU 20 resets the frame counter that counts the number of frames in the thinning-out process 3 regardless of the decoding process unit.

  In step S574, the CPU 20 associates all of the display order with time information display queues with reference to whether or not the confirmed flag is set in association with the picture ID held in the display order setting queue with time information. It is determined whether or not it has been confirmed. The confirmed flag is a flag that is set in the display order setting queue with time information by the process of step S579 described later. If it is determined in step S574 that all display order setting queues with time information have been confirmed, the process returns to step S546 in FIG. 42, and the process proceeds to step S436 in FIG.

  If it is determined in step S574 that all display order setting queues with time information have not been confirmed, in other words, it is determined that there is still a picture ID for which the confirmed flag is not set in the display order setting queue with time information. In step S575, the CPU 20 increments the frame counter by 1.

  In step S576, the CPU 20 refers to the thinning cycle held in the register and the value of the frame counter as a result of the determination of the thinning cycle, and determines whether the frame indicated by the frame counter is displayed. Specifically, when the thinning cycle is ½, the CPU 20 performs display if the value of the frame counter that counts the number of frames is 2n (n is a positive integer), otherwise, When the display is not performed or the thinning cycle is 1/3, if the value of the frame counter that counts the number of frames is 3n (n is a positive integer), the display is performed. Otherwise, the display is performed. Do not display. If it is determined in step S576 that display is to be performed, that is, if it is determined that the frame is not thinned out, the process proceeds to step S579 described later.

  If it is determined in step S576 that the frame is not displayed, that is, if it is determined that the frame is to be thinned out, in step S577, the CPU 20 sets the picture ID corresponding to the processing target frame to the display order with time information. Either delete from the queue, or associate a flag indicating non-display with the corresponding picture ID in the display order setting queue with time information.

  In step S578, the time information resetting process described with reference to FIG. 24 is executed. At this time, the time information adjustment value added_count calculated in step S302 is the number of pictures changed by decimation by the processing of step S576 and step S577 when the speed setting is changed compared to the previous decimation processing. It is.

  When it is determined in step S576 that the frame indicated by the frame counter is to be displayed, or after the processing of step S578 is completed, in step S579, the CPU 20 indicates the frame counter in the display order setting queue with time information. The confirmed flag is set in association with the picture ID corresponding to the frame to be processed, the process returns to step S574, and the subsequent processes are repeated.

  With such processing, when the speed setting is changed from the thinning-out processing 2 and the speed is increased in the same direction, the picture ID of the frame that is not displayed is deleted from the display order setting queue with time information. Alternatively, a flag indicating non-display is associated with the corresponding picture ID in the display order setting queue with time information. The B picture decoding process and the one-frame delay display setting process are executed with reference to the reset display order setting queue with time information. When the speed setting is changed from the thinning process 2 and the speed is increased in the same direction, the setting of the display order setting queue with time information is updated based on the speed setting. Subsequent B pictures to be decoded are only displayed (thinned B pictures are not supplied to the decoding processing unit 77), and thinned I or P pictures are decoded but not displayed. It is made like.

  Therefore, even after the scheduling of decoding is completed, whether or not there is a change in the speed setting is detected for each frame, and the speed setting is changed from the thinning-out process 2 to increase the speed in the same direction. In such a case, since the display order setting queue with time information is reset, it is possible to quickly follow the speed change and schedule the decoding so that the stream is reproduced.

  In the above, the case where 1 GOP is configured with 15 pictures has been described. For example, the number of anchor frames (I picture and P picture) included in 1 GOP is 5 or more or 4 or less. Will be described with reference to FIGS. 44 to 64. FIG.

  44 and 45, since the number of anchor frames of a picture constituting 1 GOP is large, decoding is performed in the same manner as in the case where 1 GOP is composed of the 15 pictures described above by the playback apparatus 1 described with reference to FIG. A problem that occurs when processing is performed will be described.

  First, GOP (0) in which 1 GOP is composed of 15 pictures from B0 to P14, GOP (1) in which 1 GOP is composed of 21 pictures from B0 to P20, and 1 GOP in 15 pictures from B0 to P14 A stream including the configured GOP (2) is decoded by one decoder (any one of the decoders 22 to 24) in the same manner as when the 1 GOP is configured with the 15 pictures described above. A case of reproducing in the forward direction at 1 × speed will be described with reference to FIG.

  The leading B picture of each GOP is decoded along with the previous GOP. Since the anchor frame of GOP (1) is 7 frames, in the decoder for decoding GOP (1), of the 8 banks of the video bank memory 82, 6 banks used for decoding the anchor frame are I2 to P17 becomes full, and the following anchor frame (P20 and I2 of the next GOP (2)) cannot be arranged. Therefore, the decoder that decodes GOP (1) cannot refer to the anchor frame P20 and I2 of the next GOP (2) at the time of decoding. As a result, the picture after P17 of GOP (1) and B0B1 of GOP (2) cannot be decoded.

  Next, GOP (0) in which 1 GOP is composed of 15 pictures from B0 to P14, GOP (1) in which 1 GOP is composed of 21 pictures from B0 to P20, and 1 GOP in 15 pictures from B0 to P14 1 GOP is decoded by one decoder (any one of decoders 22 to 24) in the same manner as the case where 1 GOP is composed of 15 pictures as described above. A case of reproducing in the reverse direction at 1 × speed will be described with reference to FIG.

  The top B picture of each GOP is decoded together with the GOP to be decoded next. Even in this case, since the anchor frame of GOP (1) is 7 frames, the decoder of GOP (1) decodes the eight banks of the video bank memory 82 as in the case described with reference to FIG. Of these, the six banks used for decoding the anchor frame are filled with I2 to P17, and the subsequent anchor frame (P20 and I2 of the previous GOP (2)) cannot be arranged. Therefore, the decoder that decodes GOP (1) cannot refer to the anchor frame P20 and I2 of the previous GOP (2) at the time of decoding. As a result, the picture after P17 of GOP (1) and B0B1 of GOP (2) cannot be decoded.

  As described above, when the number of anchor frames of a picture constituting one GOP is large, decoding processing is performed for each GOP in the same manner as in the case where one GOP is constituted by the 15 pictures described above by the playback device 1 described with reference to FIG. If applied, a frame that cannot be reproduced is generated.

  On the other hand, a problem that occurs when a GOP in which the number of anchor frames included in one GOP is five or less and a GOP in which the number of anchor frames included in one GOP is five or more are continuous and played back at high speed This will be described with reference to FIGS. 46 and 47. FIG.

  First, GOP (0), GOP (1), and GOP (2) in which 1 GOP is composed of 3 pictures of B0B1I2 are continuous, and GOP (3) in which 1 GOP is composed of 15 pictures from B0 to P14. A stream including GOP (4) is decoded by one decoder (any one of the decoders 22 to 24) and double-speed-corrected in the same manner as in the case where one GOP is composed of 15 pictures described above. The case of reproducing in the direction will be described with reference to FIG.

  The leading B picture of each GOP is decoded along with the previous GOP. Each GOP (0) to GOP (2) has only one anchor frame, and the following GOP (3) has five anchor frames. Of the B0B1 of GOP (0), B0, which is the displayed picture, is decoded by the decoder 2 together with the previous frame, and then the I2 picture of GOP (0) and the displayed GOP (1) B1 is decoded by the decoder 0, and then the I2 picture of GOP (1) and the B0 of the displayed GOP (2) are decoded by the decoder 1. In each decoder, after all the pictures to be displayed are output, the next decoding process is started.

  That is, in decoder 0, since B1 of GOP (1) is output for display, decoding of the anchor frame of GOP (3) is started, so that a decoding delay occurs, and GOP (3) The B1 of GOP (3) decoded by the decoder 2 is output until B3 which is the first displayed picture is decoded after the decoding of the anchor frame is completed.

  Next, GOP (4), GOP (3), and GOP (2) in which 1 GOP is composed of 3 pictures of B0B1I2 are consecutive, and GOP (1) in which 1 GOP is composed of 15 pictures from B0 to P14 1 GOP is decoded by one decoder (any one of decoders 22 to 24) in the same manner as in the case where 1 GOP is composed of 15 pictures as described above, and the stream including GOP (0) is doubled. The case of reproducing in the reverse direction will be described with reference to FIG.

  The top B picture of each GOP is decoded together with the GOP to be decoded next. Also in this case, there are only one anchor frame for GOP (4) to GOP (2), and there are five anchor frames for GOP (1). Of B0B1 of GOP before GOP (4), B0 to be displayed is decoded by decoder 1 together with I2 of GOP (4), and B1 which is a picture to be displayed among B0B1 of GOP (4) is Is decoded in the decoder 0 together with I2 of the GOP (3). Next, B1 which is a picture to be displayed in B0B1 of GOP (3) is decoded by decoder 2 together with I2 of next GOP (2), and then displayed in B0B1 of GOP (2). The picture B0 is decoded by the decoder 1 together with the next GOP (1). In each decoder, after all the pictures to be displayed are output, the next decoding process is started.

  That is, the decoder 1 starts decoding the anchor frame of the GOP (1) after the I2 of the GOP (4) is output for display, so that a decoding delay occurs and the GOP (1) After the decoding of the anchor frame is completed, I2 of GOP (3) decoded by decoder 2 is output until B0 of GOP (2), which is the first displayed picture, is decoded. End up.

  In this way, when the number of anchor frames of a picture constituting one GOP is small and large, a case where 1 GOP is constituted by the above-described 15 pictures by the playback apparatus 1 described with reference to FIG. Similarly, when decoding processing is performed for each GOP, a decoding delay occurs due to the time required for decoding the anchor frame.

  As described with reference to FIGS. 44 to 47, in order to solve the problem in the case where 1 GOP is not configured with 15 pictures, the playback apparatus 1 described with reference to FIG. A decoding unit as a decoding processing unit that detects and has an anchor frame corresponding to the number of video bank memories 82 of the decoders 22 to 24 may be configured by dividing and combining GOPs.

  GOP division when 30 frames are included in one GOP and decoding of each of the divided GOPs will be described with reference to FIGS. 48 to 50. FIG.

  As shown in FIG. 48, GOP (0) is composed of 30 frames from B0 to P29, followed by GOP (1). In each decoding processing unit, the first two B pictures are decoded together with the preceding GOP.

  In the video bank memory 82, six of the eight banks of the video bank memory 82 are allocated to the anchor frames. However, since there are ten anchor frames in GOP (0), as described above, 15 In the same way as when 1 GOP is composed of pictures, the method of performing decoding processing for each GOP cannot decode all frames. Therefore, as shown in the lower part of FIG. 48, GOP (0) is divided into two so that the anchor frame is 6 frames or less to form a decoding processing unit, and the P picture and It is assumed that decoding is performed including an anchor frame necessary for decoding all B pictures.

  As shown in FIG. 49, GOP (0) is divided into two decoding units GOP (0-0) and GOP (0-1) of I2 to P17 and B18 to P29 and B0B1, and each is divided into different decoders. To decode. In order to decode the first two B pictures B18B19 of the latter half GOP (0-1), the last anchor frame P17 of GOP (0-0) is required. That is, P17 is also an anchor frame of GOP (0-1). Further, in order to decode the anchor frame of the latter half GOP (0-1), the anchor frame of the first half GOP (0-0) is necessary. Therefore, before decoding the anchor frame of GOP (0-1), the anchor frame of GOP (0-0) is decoded using the six banks for decoding the anchor frame, and then GOP (0-1). ) And the first I picture of the next GOP are decoded using the six banks for decoding the anchor frame (overwriting each bank).

  Therefore, in a decoder that decodes any decoding processing unit of GOP (0-0) and GOP (0-1), an anchor frame is decoded in a fixed bank, Whether the playback is normal playback or high-speed playback, the decoding order is unchanged. On the other hand, in any decoding processing unit of GOP (0-0) and GOP (0-1), the decoding order of B pictures differs depending on the playback direction and playback speed. FIG. 49 shows the decoding order in forward reproduction and reverse reproduction with a reproduction speed of 1 ×.

  That is, as shown in FIG. 50, in forward playback at a playback speed of 1 time, after GOP (0-0) anchor frames I2 to P17 are decoded by any decoder, GOP (0-0) ) B pictures B3 to B16 are decoded and anchor frames I2 to P14 are decoded in different decoders, and are then used as reference images to anchor frames P17 to P29 and GOP (1) of GOP (0-1). ) At the head I2 is decoded, and then B pictures B18 to B28 of GOP (0-1) and B0B1 of GOP (1) are decoded.

  In reverse playback at a playback speed of 1 ×, after any of the anchor frames I2 to P14 is decoded by any decoder, the anchor frames P17 to P29 of GOP (0-1) and GOP are used as reference images. The first I2 of (1) is decoded, and then B1B0 of GOP (1) and B pictures B28 to B18 of GOP (0-1) are decoded, and the GOP (0-0) anchor frame is decoded in different decoders. After I2 to P17 are decoded, B pictures B16 to B3 of GOP (0-0) are decoded.

  Next, setting of decoding processing units and decoding processing when GOPs having 4 or less anchor frames included in one GOP continue will be described with reference to FIGS.

  As shown in FIG. 51, GOP (0) of 1 GOP is composed of 6 frames B0 to P5, GOP (1) is composed of 9 frames B (0) to P8, and GOP (2) is composed of in the process of. In each decoding processing unit, the first two B pictures are decoded together with the preceding GOP.

  In the video bank memory 82, six of the eight banks of the video bank memory 82 are allocated to the anchor frame. However, there are two anchor frames in GOP (0), and GOP (1) has two frames. There are three anchor frames. Therefore, as shown in the lower part of FIG. 51, GOP (0) and GOP (1) are combined to set a decoding processing unit in which anchor frames are 6 frames or less, and decoding is performed.

  Here, the top B0 and B1 of GOP (0) are decoded together with the previous GOP, and GOP (0) 's I2 to P5, GOP (1), and the top B0 and B1 of GOP (2) are Decoding is performed as one decoding processing unit GOP (0-0). As shown in FIG. 52, the anchor frame is decoded in a fixed bank, and the decoding order is invariable regardless of whether it is normal direction, reverse direction, normal reproduction, or high-speed reproduction. is there. On the other hand, the decoding order of B pictures differs depending on the playback direction and playback speed. In FIG. 52, the decoding order in forward reproduction and reverse reproduction at a reproduction speed of 1 is shown.

  That is, as shown in FIG. 53, in forward playback at a playback speed of 1 ×, the anchor frame of GOP (0-0) and the head I2 of GOP (2) are decoded in either decoder, Thus, the B picture of GOP (0-0) is decoded. In reverse playback at a playback speed of 1 ×, the anchor frame of GOP (0-0) and the leading I2 of GOP (2) are decoded in any decoder, and then GOP (0-0) The B pictures are decoded so as to be reproduced in the reverse direction.

  Next, if a long GOP with 6 GOP or more anchor frames included in one GOP and a short GOP with 4 or less anchor frames included in 1 GOP are consecutive, these GOPs are combined and then divided and decoded. A case where the unit is set and the load on the decoder is equalized will be described with reference to FIGS.

  As shown in FIG. 54, GOP (0) of 1 GOP is composed of 21 frames from B0 to P20, GOP (1) of 1 GOP is composed of 9 frames from B0 to P8, and then GOP (2) follows. ing. In each decoding processing unit, the first two B pictures are decoded together with the preceding GOP.

  In the video bank memory 82, six of the eight banks of the video bank memory 82 are allocated to the anchor frame. However, since there are seven anchor frames in GOP (0), as described above, 15 In the same manner as when 1 GOP is configured with a picture, the method of performing decoding processing for each 1 GOP cannot be decoded without any trouble. Therefore, GOP (0) may be divided into two decoding processing units in which the anchor frame is 6 frames or less, but here, since the number of frames constituting the subsequent GOP is small, it is shown in the lower part of FIG. As shown in the figure, GOP (0) and GOP (1) are combined and then divided, and GOP (0) and GOP (1) are divided into two decoding processing units GOP (0-0) and GOP (0-1). ) Is set, and decoding is performed based on this decoding processing unit.

  As shown in FIG. 55, after combining GOP (0) and GOP (1), I2 to P17 of GOP (0) are set as the first decoding processing unit GOP (0-0), and GOP (0) B18 to P20, the entire GOP (1), and B1B2 of GOP (2) are decoded as different decoding processing units GOP (0-1) by different decoders. In order to decode the first two B pictures B18B19 of GOP (0-1), the last anchor frame P17 of GOP (0-0) is required. That is, P17 is also an anchor frame of GOP (0-1). Further, in order to decode the anchor frame of the latter half GOP (0-1), the anchor frame of the first half GOP (0-0) is necessary. Therefore, before decoding the anchor frame of GOP (0-1), the anchor frame of GOP (0-0) is decoded using the six banks for decoding the anchor frame, and then GOP (0-1). ) And the first I picture of the next GOP are decoded using the six banks for decoding the anchor frame (overwriting each bank).

  Therefore, in a decoder that decodes any decoding processing unit of GOP (0-0) and GOP (0-1), an anchor frame is decoded in a fixed bank, Whether the playback is normal playback or high-speed playback, the decoding order is unchanged. On the other hand, in any decoding processing unit of GOP (0-0) and GOP (0-1), the decoding order of B pictures differs depending on the playback direction and playback speed. FIG. 55 shows the decoding order in forward reproduction and backward reproduction at a reproduction speed of 1 ×.

  That is, as shown in FIG. 56, in forward playback at a playback speed of 1 ×, IOP to G17 of GOP (0), which is an anchor frame of GOP (0-0), is decoded in any decoder. Then, the B picture of GOP (0-0), that is, B3 to B16 of GOP (0) are decoded. Then, after the anchor frames I2 to P14 of GOP (0-0) are decoded in different decoders, using them as reference images, P17 and P20 of GOP (0) which are anchor frames of GOP (0-1) , GOP (1) I2, P5, P8 and GOP (2) leading I2 are decoded, followed by GOP (0-1) B picture, GOP (0) B18, B19, GOP B0 to B7 in (1) and B0B1 in GOP (2) are decoded.

  In reverse playback at a playback speed of 1 time, after any of the anchor frames I2 to P14 of GOP (0-0) is decoded in any decoder, it is used as a reference image for GOP (0-1). The anchor frames P17 and P20 of GOP (0), I2, P5 and P8 of GOP (1), and the top I2 of GOP (2) are decoded, and then B1B0 of GOP (2) and GOP B7 to B0 of GOP (1) and B19 and B18 of GOP (0), which are B pictures of (0-1), are decoded. Then, after different I2 to P17 of GOP (0), which are anchor frames of GOP (0-0), are decoded by different decoders, B picture of GOP (0-0), that is, B16 of GOP (0) Through B3 are decoded.

  Next, if a short GOP with 4 or less anchor frames included in 1 GOP and a long GOP with 6 or more anchor frames included in 1 GOP are consecutive, these GOPs are combined and then divided and decoded. The case where the processing unit is set and the load on the decoder is equalized will be described with reference to FIGS.

  As shown in FIG. 57, GOP (0) of 1 GOP is composed of 9 frames B0 to P8, GOP (1) of 1 GOP is composed of 21 frames of B0 to P20, and then GOP (2) follows. ing. In each decoding processing unit, the first two B pictures are decoded together with the preceding GOP.

  In the video bank memory 82, six of the eight banks of the video bank memory 82 are allocated to anchor frames. GOP (0) has only three anchor frames, but GOP (1) has seven anchor frames. Therefore, as shown in the lower part of FIG. 57, GOP (0) and GOP ( 1) are combined and divided, and two decoding processing units GOP (0-0) and GOP (0-1) are set from GOP (0) and GOP (1). It is assumed that decoding is performed based on this.

  As shown in FIG. 58, after combining GOP (0) and GOP (1), I2 of GOP (0) to P8 of GOP (1) are set as the first decoding processing unit GOP (0-0). B9 to P20 of GOP (1) and B1B2 of GOP (2) are decoded by different decoders as second decoding processing units GOP (0-1). In order to decode the first two B pictures B9B10 of GOP (0-1), the last anchor frame P8 of GOP (0-0) is required. That is, P8 is also an anchor frame of GOP (0-1). Further, in order to decode the anchor frame of the latter half GOP (0-1), I2 and P5 of GOP (1) are required among the anchor frames of the first half GOP (0-0). Therefore, before decoding the anchor frame of GOP (0-1), I2 and P5 of GOP (1) included in the anchor frame of GOP (0-0) are selected from the six banks for decoding the anchor frame. After that, the GOP (0-1) anchor frame and the first I picture of the next GOP are decoded using the six banks for anchor frame decoding (overwriting each bank). ) Decode.

  Therefore, in a decoder that decodes any decoding processing unit of GOP (0-0) and GOP (0-1), an anchor frame is decoded in a fixed bank, Whether the playback is normal playback or high-speed playback, the decoding order is unchanged. On the other hand, in any decoding processing unit of GOP (0-0) and GOP (0-1), the decoding order of B pictures differs depending on the playback direction and playback speed. FIG. 58 shows the decoding order in forward playback and backward playback at a playback speed of 1 ×.

  That is, as shown in FIG. 59, in forward playback at a playback speed of 1 ×, in any decoder, GOP (0-0) I2 to P8, which are anchor frames of GOP (0-0), and GOP After I2 through P8 of (1) are decoded, B pictures of GOP (0-0), that is, B3 through B7 of GOP (0) and B0 through B7 of GOP (1) are decoded. Then, in different decoders, I2 and P5 which are anchor frames of GOP (1) among the anchor frames of GOP (0-0) are decoded, and then are used as reference images to anchor frames of GOP (0-1). P8 to P20 of GOP (1) and the head I2 of GOP (2) are decoded, and then B9 to B19 of GOP (1) which is a B picture of GOP (0-1), and B0B1 of GOP (2) is decoded.

  Then, in reverse playback at a playback speed of 1 ×, any decoder decodes I2 and P5 which are anchor frames of GOP (1) out of the anchor frames of GOP (0-0), and then decodes them. As reference images, P8 to P20 of GOP (1), which is an anchor frame of GOP (0-1), and the top I2 of GOP (2) are decoded, and then B1B0 of GOP (2) and GOP B19 to B9 of GOP (1) which are B pictures of (0-1) are decoded. Then, in different decoders, the GOP (0-0) anchor frames I2 to P8 of GOP (0) and I2 to P8 of GOP (1) are decoded, and then the B picture of GOP (0-0) That is, B7 to B0 of GOP (1) and B7 to B3 of GOP (0) are decoded.

  As described with reference to FIGS. 48 to 59, a decoding unit as a decoding processing unit is configured, so that scheduling is executed for each decoding unit so that playback is performed at a specified playback direction and playback speed. In addition, a thinning process is performed as necessary, decoding is performed, and a stream is reproduced and output.

  Specifically, the CPU 20 reads the configuration of the GOP to be decoded next among the plurality of GOPs transferred and stored in the memory 18 and the next (second) GOP, and determines the number of anchor frames. Based on the above, a decoding unit as a decoding processing unit is configured by dividing and combining GOPs, a control command is sent to the PCI bridge 17, and stream data is read from the memory 18 for each decoding unit, and the decoder 22 Or the decoder 24 is controlled so as to be supplied. The PCI bridge 17 reads the stream data for each decoding unit from the memory 18 based on the control of the CPU 20 and supplies the stream data to any one of the decoders 22 to 24.

  Then, the CPU 20 performs scheduling for the decode unit in the same manner as described above. At this time, for example, the GOP (0-1) described with reference to FIG. 48, the GOP (0-1) described with reference to FIG. 54, or the GOP (0-1) FIG. 54 described with reference to FIG. When it is necessary to decode at least a part of the anchor frame of another decoding unit in order to decode the anchor frame of the decoding unit, such as GOP (0-1) described above, the input picture queue includes Anchor frames of other decoding units necessary for decoding the anchor frame are also set, and these are set in order from the head of the I / P picture decoding queue. However, the anchor frames of other decoding units necessary for decoding the anchor frame are not displayed by this processing, and thus are not set in the display order setting queue.

  Then, the CPU 20 refers to a value held in a register indicating a decoder that supplies the next data, and controls one of the decoders 22 to 24 that is set as a decoder that performs decoding. The elementary stream address determination unit 73 of any one of the decoders 22 to 24 that executes the decoding process corresponds to the picture ID set in the I / P picture decoding queue with time information based on the control of the CPU 20. The picture data is read from the input buffer 75 by the memory controller 74 and supplied to the decoding processing unit 77.

  When the picture to be decoded is an I picture, the CPU 20 controls the decoding processing unit 77 to decode the I picture supplied from the memory controller 74 and also controls the writing image address determining unit 78 to perform decoding. The frame data is supplied to the memory controller 81 and stored in the bank designated for storing the I picture in the video bank memory 82. When the picture to be decoded is a P picture, the CPU 20 controls the reference picture address determination unit 79 and stores it in the video bank memory 82 by the memory controller 81 based on the reference bank position of the P picture. The reference image is read out and supplied to the decoding processing unit 77, the decoding processing unit 77 is controlled to decode the P picture supplied from the memory controller 74, and the writing image address determining unit 78 is controlled, The decoded frame data is supplied to the memory controller 81 and stored in the bank designated for storing the P picture in the video bank memory 82. If the picture to be decoded is a B picture, the CPU 20 controls the reference picture address determination unit 79 and stores it in the video bank memory 82 by the memory controller 81 based on the reference bank position of the B picture. The reference picture is read out, supplied to the decode processing unit 77, and the decode processing unit 77 is controlled to decode the B picture supplied from the memory controller 74.

  Next, GOP division / combination processing when the number of pictures constituting one GOP is other than 15 will be described with reference to the flowchart of FIG.

  In step S601, the CPU 20 determines whether there is any unscheduled decoding unit after the division.

  When it is determined in step S601 that there is an unscheduled decoding unit, in step S602, the CPU 20 performs unscheduled decoding after the process 1 performed for each frame or the process 2 performed for each frame. Schedule and decode unit decoding.

  If it is determined in step S601 that there is no unscheduled decoding unit, in step S603, the CPU 20 detects the configuration of the next GOP and the second GOP that are not scheduled for decoding.

  In step S604, the CPU 20 determines whether or not the next GOP is larger than the maximum size that can be decoded by one decoder. Specifically, the CPU 20 confirms the number of anchor frames of the next GOP and compares it with the number of banks prepared for decoding the anchor frame in one decoder, so that the next GOP has one decoder. It is determined whether or not the size is larger than the maximum size that can be decoded by.

  If it is determined in step S604 that the next GOP is larger than the maximum size that can be decoded by one decoder, in step S605, the CPU 20 combines the next GOP and the second GOP, It is determined whether or not the size is decodable by the decoder. Specifically, when the video bank memory 82 has eight banks, the CPU 20 determines that the anchor frame is 10 frames or less when the next GOP and the second GOP are combined, that is, the video bank memory 82. It is determined whether or not it is less than or equal to twice the value obtained by subtracting 3 from the number of banks.

  If it is determined in step S605 that the next GOP and the second GOP are combined to be a size that can be decoded by two decoders (for example, as described with reference to FIGS. 54 to 56, 1 GOP For example, when a long GOP including 6 GOPs or more and a short GOP including 4 or less anchor frames included in one GOP are consecutive), the process proceeds to step S610 described later.

  If it is determined in step S605 that the next GOP and the second GOP are combined and cannot be decoded by two decoders, in step S606, the CPU 20 uses, for example, FIG. 48 to FIG. As in the case where 1 GOP is composed of 30 pictures described above, the next GOP is divided into a plurality of decoding units of a size that can be decoded by one decoder, and the process proceeds to step S612 described later.

  If it is determined in step S604 that the next GOP is not larger (that is, smaller) than the maximum size that can be decoded by one decoder, in step S607, the CPU 20 determines the next GOP and the second GOP. In combination, it is determined whether or not the size is one that can be decoded by one decoder.

  If it is determined in step S607 that the next GOP and the second GOP are combined to be a size that can be decoded by one decoder, in step S608, the CPU 20 uses, for example, FIG. 51 to FIG. As in the case where GOPs in which the number of anchor frames included in one GOP is 4 or less are consecutive, the next GOP and the second GOP are combined into one decoding unit, and the process is a step described later. The process proceeds to S612.

  If it is determined in step S607 that the next GOP and the second GOP are combined and cannot be decoded by one decoder, the CPU 20 determines in step S609 that the next GOP and the second GOP Are combined to determine whether the size can be decoded by the two decoders. Specifically, the CPU 20 includes, for example, a short GOP in which the number of anchor frames included in one GOP described with reference to FIGS. 57 to 59 is four or less and a long GOP in which the number of anchor frames included in one GOP is 6 GOP or more. When the video bank memory 82 has 8 banks, such as when it is continuous, the anchor frame is 10 frames or less when the next GOP and the second GOP are combined, that is, the video bank It is determined whether or not the value is equal to or less than twice the value obtained by subtracting 3 from the number of banks in the memory 82.

  If it is determined in step S605 that the next GOP and the second GOP are combined to be a size that can be decoded by two decoders, or in step S609, the next GOP and the second GOP are combined. When it is determined that the size can be decoded by the two decoders, in step S610, for example, the CPU 20 has been described with reference to FIGS. 54 to 56, or with reference to FIGS. As in the case, the next GOP and the second GOP are combined and then divided into two decoding units, and the process proceeds to step S612 described later.

  If it is determined in step S609 that the next GOP and the second GOP are combined and the size cannot be decoded by the two decoders, in step S611, the CPU 20 directly changes the next GOP to one A decoding unit.

  After step S606, step S608, step S610, or step S611 is completed, in step S612, the CPU 20 performs decoding of the decoding unit to be decoded next among the decoding units set by the above-described processing. Scheduling and decoding are performed by processing 1 performed for each frame or processing 2 performed for each frame.

  In step S613, if there is a divided decoding unit that is not scheduled, the CPU 20 holds the decoding unit as data waiting for the schedule, and the process is terminated.

  By such processing, even when the number of pictures constituting one GOP is other than 15 pictures and is different for each GOP, division and combination of GOPs are performed so that decoding processing can be performed at high speed.

  It should be noted that here, the video bank memory 82 of each of the decoders 22 to 24 is 8 banks, of which GOP division is such that scheduling is performed without waste when 6 banks are fixed for anchor frame decoding. Although the method of combining has been described, the number of frames (the number of banks) that can be held in the video bank memory 82 of each of the decoders 22 to 24 is not eight, or is fixed for decoding an anchor frame. Depending on the number of banks that are different from those described above, the number of frames (number of banks) that can be held in the video bank memory 82 and the number of banks that are fixed for anchor frame decoding are used. , GOP may be split or combined. It goes without saying. Specifically, when the number of banks fixed for decoding an anchor frame is less than 6, the decode unit is set so that the number of anchor frames included in one decode unit is less than 6. If the number of banks fixed for decoding an anchor frame is more than six, the number of anchor frames included in one decoding unit is fixed for decoding an anchor frame larger than six. The decoding unit is set so as to be smaller than the number of.

  As described with reference to FIG. 44, the processing described above performs decoding processing without any trouble as shown in FIG. 61 even in the normal direction 1 × speed playback when 1 GOP is composed of 21 frames. .

  That is, GOP (1) in which 1 GOP is composed of 21 frames is divided into two decoding units and decoded by decoder 1 and decoder 2. At that time, in order to decode the anchor frame of the second half decoding unit, the anchor frame of the first half decoding unit which is not output from the decoder 2 is first decoded, and then the anchor frame of the second half decoding unit is fixed for the anchor frame. Is decoded (overwritten on the anchor frame of the first decoding unit if necessary).

  Similarly, as described with reference to FIG. 45, the decoding process is executed without any trouble as shown in FIG. 62 even in the reverse 1 × speed playback when 1 GOP is composed of 21 frames. .

  That is, GOP (1) in which 1 GOP is composed of 21 frames is divided into two decode units and decoded by decoder 2 and decoder 1. At that time, in order to decode the anchor frame of the second half decoding unit, the anchor frame of the first half decoding unit which is not output from the decoder 2 is first decoded, and then the anchor frame of the second half decoding unit is fixed for the anchor frame. Is decoded (overwritten on the anchor frame of the first decoding unit if necessary).

  Similarly, as described with reference to FIG. 46, in the double-speed playback in the forward direction when a GOP with a small number of anchor frames and a GOP with a large number of anchor frames are continuous, as shown in FIG. The decoding process is executed.

  That is, GOP (0) and GOP (1) configured by B0B1I2 are combined to form one decoding unit, and configured by GOP (2) configured by B0B1I2 and 15 frames B0 to P14. GOP (3), which has been combined, is divided into two decoding units.

  Necessary for decoding the displayed B (0) of B0B1 (B0B1 of GOP (0)) of the decoding unit composed of GOP (0) and GOP (1) and this B picture The reference picture I2 is decoded by the decoder 2 together with the previous GOP or decoding unit. In order to decode this B picture, the displayed B (0) of B0B1 (B0B1 of GOP (2)) at the head of the decoding unit composed of GOP (2) and the first half of GOP (3) The reference picture I2 necessary for the decoding is decoded by the decoder 0 together with the decoding unit composed of the preceding decoding units GOP (0) and GOP (1). B (7), which is the head of the B picture to be displayed of the decoding unit configured in the second half of GOP (3), is composed of GOP (2), which is the preceding decoding unit, and the first half of GOP (3). It is decoded by the decoder 1 together with the decoded unit. Of the first B0B1 of GOP (4), B0 to be displayed and I2 which is a reference picture necessary for decoding this B picture are composed of the latter half of GOP (3) which is the preceding decoding unit. It is decoded by the decoder 2 together with the decoding unit. Then, after I2 of GOP (4), it is decoded by the decoder 0.

  Further, similarly, as described with reference to FIG. 47, also in reverse double speed playback when a GOP with a small number of anchor frames and a GOP with a large number of anchor frames are continuous, as shown in FIG. The decoding process is executed without any problems.

  That is, GOP (4) composed of B0B1I2 and GOP (3) are combined to form one decoding unit, and composed of GOP (2) composed of B0B1I2 and 15 frames B0 to P14. GOP (1), which has been combined, is divided into two decoding units.

  Display of a picture excluding the first B0B1 (B0B1 of GOP (3)) of the decoding unit composed of GOP (4) and GOP (3) and two B pictures of the preceding decoding unit A picture (B0 in this figure) and a reference picture I2 necessary for decoding the B picture are decoded by the decoder 1. In order to decode this B picture, the displayed B (0) of B0B1 (B0B1 of GOP (3)) at the head of the decoding unit composed of GOP (4) and GOP (3) is displayed. The reference picture I2 necessary for the decoding is decoded by the decoder 0 together with the decoding unit composed of the second half of GOP (2) and GOP (1) which are the decoding units to be decoded next. In order to decode B (9) displayed in B9B10 (B9B10 of GOP (1)) at the head of the decoding unit composed of GOP (2) and the latter half of GOP (1), and this B picture P8P11, which is a reference picture necessary for the above, is decoded by the decoder 2 together with the first half of GOP (1), which is a decoding unit to be decoded next. B (1), which is the head of the B picture displayed by the decoding unit configured in the first half of GOP (1), is decoded by decoder 1 together with GOP (0).

  In this way, the CPU 20 appropriately divides or combines the GOPs based on the number of anchor frames, and decodes the number of anchor frames corresponding to the number of video bank memories 82 provided in the decoders 22 to 24. The unit is configured, and the PCI bridge 17 is controlled so that the stream is supplied to the decoder 22 to the decoder 24 for each decoding unit, the decoding process and the display order are scheduled for each decoding unit, and the decoder 22 to the decoder 24 are controlled. To be decoded. As a result, even when stream data whose number of anchor frames differs depending on the GOP is supplied, the playback device 1 performs a high-speed decoding process without generating a frame that is not decoded or causing a decoding delay. It becomes possible to.

  In the decoding unit after the GOP division, that is, the decoding unit that needs to decode the anchor frame of the preceding decoding unit for anchor frame decoding, the number of anchor frames included in the decoding unit Is 6 frames when the start is an I picture or P picture, and 7 pictures when the head is a B picture. It is. In addition, when the number of anchor frames included in the decode unit is n frames or less, the difference between the decode start timing and the display start timing of the anchor frame included in the decode unit is It is changed based on the number of included anchor frames. When the head is an I picture or P picture, the frame is shifted by n frames, and when it is a B picture, the frame is shifted by n + 1 frames.

  In the above description, the decoding unit is arranged so that the number of anchor frames included in one decoding unit is the same or less than the number of banks fixed for decoding the anchor frame. Although described as being set, the decoding unit is m (m is a positive integer that can be set experimentally and empirically equal to or greater than 1, for example, 2 to It is more preferable to set the decoding unit so that the number of frames is not more than 4).

  For example, when a GOP with 1 anchor frame and a GOP with 10 anchor frames are continuous, the total number of anchor frames of 2 GOP is 11, and two decoding units can be configured by adding 2 GOPs. Can not. For this reason, decoding is performed with a configuration of “anchor frame number 1 + 1”, “anchor frame number 5 + 1”, and “anchor frame number 5 + 1”, and a decoding delay occurs.

  Therefore, for example, when the decoding unit is set so as not to include two or more anchor frames compared to the number of anchor frames of the previous decoding unit, when the total number of anchor frames of 2 GOP is 11, Since the decoding unit is configured with the configuration of “anchor frame number 1 + 1”, “anchor frame number 3 + 1”, “anchor frame number 3 + 1”, and “anchor frame number 4 + 1”, and decoding is executed, no decoding delay occurs.

  In the processing described above (both in the case where the thinning-out processing is in two steps and in the case of only one step), the compression encoded data recorded in the HDD 16 is effective as data read from the HDD 16. A flag group for reading indicating whether or not there is a flag group for decoding indicating whether or not it is effective in scheduling for decoding, and a display for indicating whether or not it is effective in scheduling for displaying decoded data It is also possible to manage scheduling by appropriately providing a flag group or the like as metadata and automatically updating a series of flag groups according to the playback speed and direction.

  At this time, it is also possible to manage a series of scheduling and flag group update information used in the past variable-speed playback processing as separate scheduling metadata (history information). It may be described as syntax inside or separately recorded on the HDD 16 or the like as a recording medium.

  Also, the number of decoders, the number of banks, the decoder ID, and the like can be managed as metadata (configuration history information). Furthermore, it is possible to manage the playback speed, playback direction, and the like as metadata (playback history information). At this time, these metadata may be described as syntax in the compressed and encoded data as needed, or may be separately recorded on the HDD 16 or the like as a recording medium.

  By referring to such metadata (history information), scheduling processing performed in the past can be reused, and scheduling processing can be executed more accurately and at high speed.

  Note that such metadata may be managed by an external device as a database, for example.

  In the above-described embodiment, the present invention can be applied even when the decoder 22 to the decoder 24 do not completely decode (decode halfway) the compression-coded data recorded in the HDD 16. is there.

  Specifically, for example, the decoder 22 to the decoder 24 only perform decoding and inverse quantization on the variable length code and do not perform inverse DCT transform, or perform inverse quantization but do not perform decoding on the variable length code. The present invention can also be applied to cases. In such a case, for example, the decoder 22 to the decoder 24 generate, as necessary, history information indicating how many stages (for example, the inverse quantization stage) have been performed in the encoding process and the decoding process. However, it may be possible to output in association with incompletely decoded data.

  Further, in the above-described embodiment, incompletely encoded data (for example, data that has been subjected to DCT transform and quantization but not subjected to variable length encoding processing) is stored in the HDD 16. Where necessary, history information of the encoding process and the decoding process is stored, and the decoders 22 to 24 decode the supplied incompletely encoded data based on the control of the CPU 20, The present invention can be applied even in a case where conversion into a baseband signal is possible.

  Specifically, the decoder 22 to the decoder 24 perform, for example, inverse DCT on incompletely encoded data that has been subjected to DCT transform and quantization but not subjected to variable length encoding processing. The present invention can also be applied to cases where only transformation and inverse quantization are performed and decoding for variable length codes is not performed.

  In such a case, for example, the CPU 20 acquires the history information of the encoding process and the decoding process stored in the HDD 16 in association with the incompletely encoded data, and based on these information Decoding scheduling by the decoders 22 to 24 may be performed.

  Further, in the above-described embodiment, the HDD 16 stores incompletely encoded data and, if necessary, history information of the encoding process and the decoding process. The present invention can also be applied to a case where the supplied incompletely encoded data is not completely decoded (decodes halfway) based on the control of the CPU 20.

  Also in such a case, for example, the CPU 20 acquires the history information of the encoding process and the decoding process stored in the HDD 16 in association with the incompletely encoded data, and based on these information Thus, decoding scheduling by the decoders 22 to 24 may be performed. Further, in this case, the decoder 22 to the decoder 24 can generate the history information of the encoding process and the decoding process as necessary, and output the history information in association with the incompletely decoded data. Also good.

  In other words, the present invention can be applied even when the decoder 22 to the decoder 24 perform partial decoding based on the control of the CPU 20 (execute a part of the decoding process). The CPU 20 acquires the history information of the encoding process and the decoding process stored in the HDD 16 in association with the incompletely encoded data, and schedules decoding by the decoder 22 to the decoder 24 based on the information. The decoder 22 to the decoder 24 can generate the history information of the encoding process and the decoding process as necessary, and output the history information in association with the incompletely decoded data. good.

  Further, the history information of the encoding process and the decoding process may be further recorded in the HDD 16 in association with the compression encoded stream data, and the CPU 20 decodes the compression encoded stream data. The scheduling may be performed based on the history information of the encoding process and the decoding process. Further, even when the decoder 22 to the decoder 24 can decode the stream data that has been compression-encoded under the control of the CPU 20 and convert the stream data into a baseband signal, the encoding process and the decoding process are performed. The history information may be generated as necessary and output in association with the baseband signal.

  In the above-described embodiment, the playback apparatus 1 has been described as having a plurality of decoders. However, the present invention can be applied to cases where the decoders are configured as independent apparatuses. Is applicable.

  At this time, the decoder configured as an independent device receives the compressed encoded data, decodes it, displays or outputs it, and supplies the compressed encoded data in the same manner as described above. Received, partially decoded up to the middle stage, output to the outside along with encoding and decoding history information, or supplied with partially encoded data, decoded, and converted to a baseband signal Then, the data may be output to the outside, supplied with partially encoded data, partially decoded up to an intermediate stage, and output to the outside together with encoding and decoding history information.

  Furthermore, in the above-described embodiment, the CPU 11 and the CPU 20 are configured in different forms. However, the configuration of the CPU is not limited to this, and for example, the CPU 11 and the CPU 20 control the entire playback device 1 1. A configuration in which two CPUs are configured is also conceivable. Further, even when the CPU 11 and the CPU 20 are configured independently, the CPU 11 and the CPU 20 may be configured as one chip.

  Further, when the CPU 11 and the CPU 20 are configured independently of each other, at least a part of the processing executed by the CPU 11 in the above-described embodiment can be executed by the CPU 20 in, for example, time division, For example, the CPU 11 may execute at least a part of the processing executed by the CPU 20 by time division. That is, a processor capable of distributed processing may be used for the CPU 11 and the CPU 20.

  Further, for example, the playback apparatus 1 is configured to be connectable to a network, and in the above-described embodiment, at least a part of the processing executed by the CPU 11 or the CPU 20 is performed in the CPU of another apparatus connected via the network. It may be made possible to execute.

  Similarly, in the above-described embodiment, the memory 13 and the memory 21 are configured in different forms. However, the present invention is not limited to this, and the memory 13 and the memory 21 are configured as one memory in the playback device 1. Forms are also conceivable.

  Furthermore, in the above-described embodiment, the case where the HDD 16, the decoder 22 to the decoder 24, and the selector 25 are connected via a bridge and a bus and integrated as a playback device has been described. The invention is not limited to this. For example, some of these components are connected to each other by wire or wirelessly, or these components are connected to each other in various connection forms. This can also be applied.

  Furthermore, in the above-described embodiment, the case where the compressed stream data is stored in the HDD has been described. However, the present invention is not limited to this, and for example, an optical disk, a magneto-optical disk, a semiconductor memory, a magnetic disk, etc. The present invention can also be applied to a case where reproduction processing is performed on stream data recorded on various recording media.

  Furthermore, in the above-described embodiment, the CPU 20, the memory 21, the memory 18, the decoders 22 to 24, and the selector 25 are mounted on the same expansion card (for example, a PCI card or a PCI-Express card). For example, when the transfer rate between cards is high by a technique such as PCI-Express, these components may be mounted on different expansion cards.

  Needless to say, the present invention is also applicable to other encoding methods such as H264 / AVC.

  The series of processes described above can also be executed by software. The software is a computer in which the program constituting the software is incorporated in dedicated hardware, or various functions can be executed by installing various programs, for example, a general-purpose personal computer For example, it is installed from a recording medium. In this case, for example, the playback apparatus 1 described with reference to FIG. 1 is configured by a personal computer 201 as shown in FIG.

  65, a CPU (Central Processing Unit) 211 performs various processes according to a program stored in a ROM (Read Only Memory) 212 or a program loaded from a storage unit 218 to a RAM (Random Access Memory) 213. Execute. The RAM 213 also appropriately stores data necessary for the CPU 211 to execute various processes.

  The CPU 211, ROM 212, and RAM 213 are connected to each other via a bus 214. An input / output interface 215 is also connected to the bus 214.

  The input / output interface 215 includes an input unit 216 including a keyboard and a mouse, an output unit 217 including a display and a speaker, a storage unit 218 including a hard disk, and a communication unit 219 including a modem and a terminal adapter. It is connected. The communication unit 219 performs communication processing via a network including the Internet.

  A drive 220 is connected to the input / output interface 215 as necessary, and a magnetic disk 231, an optical disk 232, a magneto-optical disk 233, a semiconductor memory 234, or the like is appropriately mounted, and a computer program read from them is loaded. The storage unit 218 is installed as necessary.

  When a series of processing is executed by software, a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a network or a recording medium into a general-purpose personal computer or the like.

  As shown in FIG. 65, the recording medium is distributed to supply a program to the user separately from the apparatus main body, and a magnetic disk 231 (including a floppy disk) storing the program, an optical disk 232 ( Package media including CD-ROM (compact disk-read only memory), DVD (including digital versatile disk), magneto-optical disk 233 (including MD (mini-disk) (trademark)), or semiconductor memory 234 In addition to being configured, it is configured by a ROM 212 storing a program and a hard disk included in the storage unit 218 supplied to the user in a state of being pre-installed in the apparatus main body.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a block diagram which shows the structure of the reproducing | regenerating apparatus to which this invention is applied. FIG. 2 is a block diagram illustrating a detailed configuration of a decoder in FIG. 1. It is a flowchart for demonstrating a control process. It is a flowchart for demonstrating the process 1 performed for every flame | frame. It is a flowchart for demonstrating an input stream state change process. 10 is a flowchart for explaining decode schedule processing 1; It is a figure for demonstrating MPEG LONG GOP. It is a figure for demonstrating the processing unit in which decoding is performed by one decoder. It is a figure for demonstrating the information accumulate | stored in an input picture queue. It is a figure for demonstrating the information accumulate | stored in a display order information queue. It is a figure for demonstrating the information accumulate | stored in an I / P picture decoding queue. It is a figure for demonstrating the information accumulate | stored in a display order setting queue. It is a figure for demonstrating the timing of a decoding and a display. It is a figure for demonstrating the timing of a decoding and a display. It is a flowchart for demonstrating an input process. It is a flowchart for demonstrating a display phase determination process. It is a flowchart for demonstrating the schedule determination process with time information. 5 is a flowchart for explaining frame control processing 1; It is a flowchart for demonstrating an I picture and P picture decoding process. It is a flowchart for demonstrating a B picture decoding process. It is a figure for demonstrating the schedule of a decoding and a display. It is a figure for demonstrating the schedule of a decoding and a display. 5 is a flowchart for explaining a thinning process 1; It is a flowchart for demonstrating a time information reset process. It is a figure for demonstrating the schedule of the decoding after thinning | decimation in the case of 2 times speed, and a display. FIG. 10 is a diagram for explaining a decoding and display schedule after thinning in the case of −2 times speed. It is a figure for demonstrating the schedule of the decoding after thinning | decimation in the case of 4 times speed, and a display. FIG. 6 is a diagram for explaining a decoding and display schedule after thinning in the case of -4 × speed. It is a figure for demonstrating the schedule of the decoding and display after thinning | decimating in the case of 5 times speed. It is a figure for demonstrating the schedule of the decoding after thinning | decimation in the case of -5 times speed, and a display. It is a figure for demonstrating the bank management at the time of normal reproduction | regeneration. It is a figure for demonstrating the bank management at the time of double speed reproduction | regeneration. It is a figure for demonstrating the bank management at the time of -1 time-speed reproduction | regeneration. It is a figure for demonstrating the bank management at the time of -2 speed reproduction | regeneration. It is a flowchart for demonstrating an underflow process. It is a figure for demonstrating the time counter when the underflow has not generate | occur | produced. It is a figure for demonstrating correction of the time counter when an underflow generate | occur | produces. It is a flowchart for demonstrating 1 frame delay processing. It is a flowchart for demonstrating the process 2 performed for every flame | frame. 10 is a flowchart for explaining decode schedule processing 2; 10 is a flowchart for explaining a thinning process 2; 10 is a flowchart for explaining frame control processing 2; 10 is a flowchart for explaining a thinning process 3; It is a figure for demonstrating the case where GOP with many anchor frames is decoded. It is a figure for demonstrating the case where GOP with many anchor frames is decoded. It is a figure for demonstrating the case where GOP with few anchor frames is decoded. It is a figure for demonstrating the case where GOP with few anchor frames is decoded. It is a figure for demonstrating the decoding unit comprised by the division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding and division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding and division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding and division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding and division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding and division | segmentation of GOP. It is a figure for demonstrating the decoding unit comprised by the coupling | bonding and division | segmentation of GOP. It is a flowchart for demonstrating a GOP division | segmentation / coupling | bonding process. It is a figure for demonstrating the decoding process of the decoding unit comprised by the division | segmentation of GOP. It is a figure for demonstrating the decoding process of the decoding unit comprised by the division | segmentation of GOP. It is a figure for demonstrating the decoding process of the decoding unit comprised by the coupling | bonding after GOP coupling | bonding and GOP coupling | bonding. It is a figure for demonstrating the decoding process of the decoding unit comprised by the coupling | bonding after GOP coupling | bonding and GOP coupling | bonding. It is a block diagram which shows the structure of a personal computer.

Explanation of symbols

  1 playback device, 11 CPU, 16 HDD, 20 CPU, 22 to 24 decoder, 25 selector, 71 input processing unit, 72 address management table, 73 elementary stream address determination unit, 74 memory controller, 75 input buffer, 76 control bus , 77 decode processing unit, 78 writing image address determining unit, 79 reference image address determining unit, 80 output address determining unit, 81 memory controller, 82 video bank memory

Claims (47)

In an information processing apparatus for decoding compression-encoded video data,
Decoding means for decoding the compression-encoded video data;
Supply control means for controlling the supply of the compressed encoded video data to the decoding means;
Control means for controlling the processing executed by the supply control means and the decoding means,
The decoding means includes a number of bank memories corresponding to the number of pictures included in a processing unit in which decoding processing is performed, and holds decoded picture data.
The control means holds the I picture and the P picture at a fixed position determined by the picture type in the bank memory, and the decoded picture data held in the bank memory An information processing apparatus for controlling a decoding process by the decoding means so as to be used as a reference image. The information processing apparatus according to claim 1, wherein the decoding unit includes the bank memory capable of holding a number of pictures obtained by adding two to the number of pictures of the I picture and the P picture included in the processing unit. Three decoding means are provided,
The information processing apparatus according to claim 1, wherein the decoding unit includes each of the bank memories that can hold eight pictures. The control means determines an order of decoding processing for each picture so that the I picture and the P picture are decoded before a B picture among a plurality of pictures included in the processing unit. The information processing apparatus according to 1. Reproduction speed command means for commanding the control means for reproduction speed,
The control means includes
Based on the playback speed instructed by the playback speed command means, a picture output from the decoding means is selected from the pictures included in the processing unit,
The decoding means includes
Decoding processing execution means for executing decoding processing;
Picture supply control means for controlling the supply of pictures to the decoding processing execution means,
The picture supply control means, based on the control of the control means, out of the pictures included in the processing unit, the I picture and the P picture, and the B selected as a picture output from the decoding means Supplying a picture to the decoding means;
The decoding processing means decodes each picture supplied by the picture supply control means based on the control of the control means, and outputs a picture selected as a picture output from the decoding means. The information processing apparatus according to 1. A plurality of the decoding means are provided,
Further comprising output switching means for receiving the supply of uncompressed data output from the plurality of decoding means, and switching and selectively outputting the supplied uncompressed data;
The information processing apparatus according to claim 1, wherein the control unit further controls processing by the output switching unit. The control means, when the picture outputted at the head of the processing unit among the decoded pictures outputted from the decoding means is the I picture or the P picture, the decoding start timing by the decoding means The information processing apparatus according to claim 1, wherein the decoding unit is controlled such that a timing at which the decoding unit starts outputting decoded pictures is shifted by a first predetermined number of pictures. The information processing apparatus according to claim 7, wherein the first predetermined number is a number obtained by adding 1 to a total number of the I picture and the P picture. When the picture output at the head of the processing unit among the decoded pictures output from the decoding means is a B picture, the control means includes a decoding start timing by the decoding means, and the decoding means The information processing apparatus according to claim 1, wherein the decoding unit is controlled so that a timing at which an output of a decoded picture is started is shifted by a second predetermined number of pictures. The information processing apparatus according to claim 9, wherein the second predetermined number is a number obtained by adding 2 to a total number of the I picture and the P picture. When the playback speed and playback direction instructed by the playback speed command means for instructing the playback speed and playback direction to the control means are the normal playback speed and the playback direction is the positive direction, the control means 2. The information processing according to claim 1, wherein the decoding means is controlled such that a start timing of decoding by the means and a timing at which output of a decoded picture from the decoding means is started are shifted by a first predetermined number of pictures. apparatus. The information processing apparatus according to claim 11, wherein the first predetermined number is a number obtained by adding 1 to a total number of the I picture and the P picture. When the playback speed and the playback direction instructed by the playback speed command means are a normal playback speed and the playback direction is the reverse direction, the control means has a decoding start timing by the decoding means, and the decoding means The information processing apparatus according to claim 1, wherein the decoding unit is controlled so that a timing at which an output of a decoded picture is started is shifted by a second predetermined number of pictures. The information processing apparatus according to claim 13, wherein the second predetermined number is a number obtained by adding 2 to a total number of the I picture and the P picture. The control means sets the timing of the decoding process for each picture by the decoding means so that the timing at which the B picture is decoded by the decoding means is one picture before the timing at which the B picture is decoded and output. The information processing apparatus according to claim 1. The decoding means includes, as the number of bank memories corresponding to the number of pictures included in a processing unit in which decoding processing is executed, a number of bank memories smaller than the number of pictures included in the processing unit in which decoding processing is executed. Item 4. The information processing apparatus according to Item 1. The compressed encoded video data is composed of GOP,
When the control means receives a GOP including the number of the I picture or the P picture that is larger than a value obtained by subtracting 3 from the number of the bank memories, the control means divides the supplied GOP to obtain the number of the bank memories. A decoding processing unit including the number of the I picture or the P picture smaller than a value obtained by subtracting 2 from the control unit, and controlling the supply control unit to send the compressed encoded video data of the decoding processing unit to the decoding unit The information processing apparatus according to claim 1. The control means includes a total of the number of the I picture or the P picture included in the decoded processing unit generated by division included in a GOP or a decoding processing unit one time earlier than the decoding processing unit. The information processing apparatus according to claim 17, wherein the decoding unit is configured so as not to exceed a predetermined number more than a total number of the I pictures or the P pictures. The compressed encoded video data is composed of GOP,
When receiving the supply of the first GOP including the number of the I picture or the P picture less than the value obtained by subtracting 3 from the number of the bank memories, the control means is continuous with the first GOP in terms of time. The total number of the I picture or the P picture included in the first GOP and the second GOP is calculated by subtracting 3 from the number of the bank memories. When the number is small, the first GOP and the second GOP are combined to form a decoding processing unit, and the supply control means is controlled to cause the decoding means to send the compressed code of the decoding processing unit. The information processing apparatus according to claim 1, wherein the video data is supplied. The control means is configured such that the total number of the I pictures or the P pictures included in the decoding processing unit is the number of the I pictures or the P pictures included in the GOP that is temporally previous to the decoding processing unit. The information processing apparatus according to claim 19, wherein the decoding unit is configured so as not to exceed a predetermined number more than a total of the information. The compressed encoded video data is composed of GOP,
The control means detects a configuration of a first GOP and a second GOP that is temporally continuous with the first GOP, and the I G included in the first GOP and the second GOP. If the total number of pictures or P pictures is less than twice the number of bank memories minus 3, the first GOP and the second GOP are combined and then divided. Forming a first decoding processing unit and a second decoding processing unit including the number of the I picture or the P picture smaller than a value obtained by subtracting 2 from the number of the bank memories, and controlling the supply control means The information processing apparatus according to claim 1, wherein the decoding unit separately supplies the compressed encoded video data of the first decoding processing unit and the second decoding processing unit. The control means is configured such that the total number of the I picture or the P picture included in the decoding processing unit is a decoding processing unit that is temporally previous to the decoding processing unit or the I picture included in a GOP. The information processing apparatus according to claim 21, wherein the decoding unit is configured so as not to exceed a predetermined number more than a total number of the P pictures. In an information processing method of an information processing apparatus for decoding compression-encoded video data,
A supply control step for controlling supply of the compressed encoded video data to a plurality of decoders;
Decoding step of decoding the compressed encoded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed Including and
In the bank memory, an I picture and a P picture are held at fixed positions determined by a picture type,
In the decoding step, the decoded picture data held in the bank memory is used as a reference image as necessary, and decoding is executed. A program for causing a computer to execute processing for decoding compression-encoded video data,
A supply control step for controlling supply of the compressed encoded video data to a plurality of decoders;
Decoding step of decoding the compressed encoded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed Including and
In the bank memory, an I picture and a P picture are held at fixed positions determined by a picture type,
In the decoding step, the decoded picture data held in the bank memory is used as a reference image as necessary, and a program for causing the computer to execute the decoding process is recorded. Recording medium. A program for causing a computer to execute processing for decoding compression-encoded video data,
A supply control step for controlling supply of the compressed encoded video data to a plurality of decoders;
A decoding step of decoding the compressed encoded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed. Including and
In the bank memory, an I picture and a P picture are held at fixed positions determined by a picture type,
A program for causing a computer to execute processing in which decoding is performed by using decoded picture data held in the bank memory as a reference image as necessary in the processing of the decoding step. In an information processing apparatus for decoding compression-encoded video data,
Storage means for storing the compressed encoded video data;
Reading means for reading out and outputting the compressed encoded video data stored in the storage means;
Decoding means for decoding the compression-encoded video data;
Supply control means for controlling the supply of the compressed encoded video data to the decoding means;
Control means for controlling processing executed by the supply control means and the decoding means;
A playback speed command means for commanding the playback speed to the control means,
The decoding means includes a number of bank memories corresponding to the number of pictures included in a processing unit in which decoding processing is performed, and holds decoded picture data.
The control means holds the I picture and the P picture at a fixed position determined by the picture type in the bank memory, and the decoded picture data held in the bank memory An information processing apparatus for controlling a decoding process by the decoding means so as to be used as a reference image. In an information processing method of an information processing apparatus for decoding compression-encoded video data,
A reading step of reading out the compressed and encoded video data stored in the storage unit;
A playback speed command supply step for supplying a playback speed command;
A playback speed command acquisition step for acquiring the playback speed command supplied by the processing of the playback speed command supply step;
A supply control step for controlling supply of the compressed encoded video data to a plurality of decoders;
Decoding step of decoding the compressed encoded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed Including and
In the bank memory, an I picture and a P picture are held at fixed positions determined by a picture type,
In the decoding step, the decoded picture data held in the bank memory is used as a reference image as necessary, and decoding is executed. A program for causing a computer to execute processing for decoding compression-encoded video data,
A reading step of reading out the compressed and encoded video data stored in the storage unit;
A playback speed command supply step for supplying a playback speed command;
A playback speed command acquisition step for acquiring the playback speed command supplied by the processing of the playback speed command supply step;
A supply control step for controlling supply of the compressed encoded video data to a plurality of decoders;
Decoding step of decoding the compressed encoded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed Including and
In the bank memory, an I picture and a P picture are held at fixed positions determined by a picture type,
In the decoding step, the decoded picture data held in the bank memory is used as a reference image as necessary, and a program for causing the computer to execute the decoding process is recorded. Recording medium. A program for causing a computer to execute processing for decoding compression-encoded video data,
A reading step of reading out the compressed and encoded video data stored in the storage unit;
A playback speed command supply step for supplying a playback speed command;
A playback speed command acquisition step for acquiring the playback speed command supplied by the processing of the playback speed command supply step;
A supply control step for controlling supply of the compressed encoded video data to a plurality of decoders;
Decoding step of decoding the compressed encoded video data whose supply to the decoder is controlled by the processing of the supply control step using the number of bank memories corresponding to the number of pictures included in the processing unit in which the decoding process is executed Including and
In the bank memory, an I picture and a P picture are held at fixed positions determined by a picture type,
A program for causing a computer to execute a process in which the decoded picture data held in the bank memory is used as a reference image as needed in the decoding step. In an information processing apparatus for decoding compression-encoded video data,
Decoding means for decoding the compression-encoded video data;
Supply control means for controlling the supply of the compressed encoded video data to the decoding means;
Control means for controlling the processing executed by the supply control means and the decoding means,
The decoding means comprises a predetermined number of bank memories, holds decoded picture data,
The compressed encoded video data is composed of GOP,
The control means divides or combines the GOPs by comparing the number of I-pictures or P-pictures included in the compression-coded video data of 1 GOP and the number of the bank memories, thereby forming a decoding processing unit. An information processing apparatus that controls the supply control means to cause the decoding means to supply the compressed encoded video data of the decoding processing unit. When the control means receives a GOP including the number of the I picture or the P picture that is larger than a value obtained by subtracting 3 from the number of the bank memories, the control means divides the supplied GOP to obtain the number of the bank memories. The decoding processing unit including the I picture or the P picture having a number smaller than the value obtained by subtracting 2 from the control unit is configured, and the supply control unit is controlled so that the decoding unit receives the compressed encoded video of the decoding processing unit. The information processing apparatus according to claim 30, wherein data is supplied. The control means includes a total of the number of the I picture or the P picture included in the decoded processing unit generated by division included in a GOP or a decoding processing unit one time earlier than the decoding processing unit. 32. The information processing apparatus according to claim 31, wherein the decoding unit is configured so as not to exceed a predetermined number more than a total number of the I pictures or the P pictures. When receiving the supply of the first GOP including the number of the I picture or the P picture less than the value obtained by subtracting 3 from the number of the bank memories, the control means is continuous with the first GOP in terms of time. The total number of the I picture or the P picture included in the first GOP and the second GOP is calculated by subtracting 3 from the number of the bank memories. When the number is small, the first GOP and the second GOP are combined to form the decoding processing unit, and the supply control means is controlled to cause the decoding means to compress the decoding processing unit. The information processing apparatus according to claim 30, wherein encoded video data is supplied. The control means is configured such that the total number of the I pictures or the P pictures included in the decoding processing unit is the number of the I pictures or the P pictures included in the GOP that is temporally previous to the decoding processing unit. 34. The information processing apparatus according to claim 33, wherein the decoding unit is configured so as not to exceed a predetermined number more than a total of the information. The control means detects a configuration of a first GOP and a second GOP that is temporally continuous with the first GOP, and the I G included in the first GOP and the second GOP. If the total number of pictures or P pictures is less than twice the number of bank memories minus 3, the first GOP and the second GOP are combined and then divided. Forming a first decoding processing unit and a second decoding processing unit including the number of the I picture or the P picture smaller than a value obtained by subtracting 2 from the number of the bank memories, and controlling the supply control means The information processing apparatus according to claim 30, wherein the decoding unit individually supplies the compressed encoded video data of the first decoding processing unit and the second decoding processing unit. The control means is configured such that the total number of the I picture or the P picture included in the decoding processing unit is a decoding processing unit that is temporally previous to the decoding processing unit or the I picture included in a GOP. The information processing apparatus according to claim 35, wherein the decoding unit is configured so as not to exceed a predetermined number more than a total number of the P pictures. The control means, when the picture outputted at the head of the processing unit among the decoded pictures outputted from the decoding means is the I picture or the P picture, the decoding start timing by the decoding means 31. The information processing apparatus according to claim 30, wherein the decoding unit is controlled such that a timing at which output of a decoded picture from the decoding unit is started is shifted by a first predetermined number of pictures. The information processing apparatus according to claim 37, wherein the first predetermined number is a number obtained by adding 1 to a total number of the I picture and the P picture. When the picture output at the head of the processing unit among the decoded pictures output from the decoding means is a B picture, the control means includes a decoding start timing by the decoding means, and the decoding means 31. The information processing apparatus according to claim 30, wherein the decoding unit is controlled so that a timing at which output of a decoded picture is started from a second predetermined number of pictures is shifted. 40. The information processing apparatus according to claim 39, wherein the second predetermined number is a number obtained by adding 2 to a total number of the I picture and the P picture. When the playback speed and playback direction instructed by the playback speed command means for instructing the playback speed and playback direction to the control means are the normal playback speed and the playback direction is the positive direction, the control means 31. The information processing according to claim 30, wherein the decoding means is controlled such that a start timing of decoding by the means and a timing at which output of a decoded picture from the decoding means starts are shifted by a first predetermined number of pictures. apparatus. The information processing apparatus according to claim 41, wherein the first predetermined number is a number obtained by adding 1 to a total number of the I picture and the P picture. When the playback speed and the playback direction instructed by the playback speed command means are a normal playback speed and the playback direction is the reverse direction, the control means has a decoding start timing by the decoding means, and the decoding means 31. The information processing apparatus according to claim 30, wherein the decoding unit is controlled so that a timing at which output of a decoded picture is started from a second predetermined number of pictures is shifted. 44. The information processing apparatus according to claim 43, wherein the second predetermined number is a number obtained by adding 2 to a total number of the I picture and the P picture. In an information processing method of an information processing apparatus for decoding compression-coded video data composed of a plurality of GOPs,
A detection step of detecting a configuration of a GOP included in the compressed encoded video data;
A comparison step of comparing the number of I-pictures or P-pictures included in the compression-coded video data of 1 GOP with the number of bank memories for holding decoded picture data;
A decoding processing unit configuration step that forms a decoding processing unit by dividing or combining GOPs based on a comparison result by the processing of the comparison step;
A decoding processing step for performing decoding processing for each decoding processing unit configured by processing of the decoding processing unit configuration step. A program for causing a computer to execute processing for decoding compression-encoded video data composed of a plurality of GOPs,
A detection step of detecting a configuration of a GOP included in the compressed encoded video data;
A comparison step of comparing the number of I-pictures or P-pictures included in the compression-coded video data of 1 GOP with the number of bank memories for holding decoded picture data;
A decoding processing unit configuration step that forms a decoding processing unit by dividing or combining GOPs based on a comparison result by the processing of the comparison step;
A recording medium on which a program for causing a computer to execute a process including a decoding process step for performing a decoding process for each decoding process unit configured by the process of the decoding process unit configuration step is recorded. A program for causing a computer to execute processing for decoding compression-encoded video data composed of a plurality of GOPs,
A detection step of detecting a configuration of a GOP included in the compressed encoded video data;
A comparison step of comparing the number of I-pictures or P-pictures included in the compression-coded video data of 1 GOP with the number of bank memories for holding decoded picture data;
A decoding processing unit configuration step that forms a decoding processing unit by dividing or combining GOPs based on a comparison result by the processing of the comparison step;
A program for causing a computer to execute a process including a decoding process step of performing a decoding process for each decoding process unit configured by the process of the decoding process unit configuration step.

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