JP2003244643A - Information reproducing apparatus and information reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information reproducing technology capable of smoothly reproducing a video image at a speed optional times multiplied. <P>SOLUTION: This invention provides the information reproducing technology whereby the information reproducing apparatus reproduces a picture of an original video comprising n (n is a natural number greater than 1) images without dropping their frames and reproduces a video image comprising about n/m images in the case of m (m is a natural number greater than 1 and smaller than n) times multiplied speed, and which is characterized in that a plurality of image decoding units decode the image in the case of reproduction at m times multiplied speed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing technique for reproducing information-compressed video information, and more particularly to MPEG (M
oving Picture Experts Group) technology for double-speed playback of video coded.

[0002]

2. Description of the Related Art "ITU-T White Book, Audiovisual / Multimedia Related (H Series) Recommendations" as a method for compressing video such as moving images and audio (Japan ITU Association, February 1995) Issued on the 18th) P375-P
595 (hereinafter referred to as Document 1), there is a moving image and audio compression standard H.262 (referred to as MPEG2 system). In the moving image compression by the MPEG2 system, one screen (called one image frame) is divided into a rectangular block group of 16 pixels × 16 pixels called a macroblock, and the macroblock to be compressed is selected from the temporally preceding and following image frames. A region (referred to as a reference region) similar to, and a motion vector indicating the spatial distance and orientation between the reference region and the region to be compressed, and difference information indicating the difference between the reference region and the region to be compressed. Is calculated, and this information is converted to DCT (Discre
te Cosine Transform), variable length coding is used to compress the stream. In this way, the method of compressing only the motion vector and the difference information can realize much more efficient compression than the method of compressing the original image itself. That is, if the same degree of compression distortion is allowed, it is possible to compress to a smaller amount of information. By the way, an image frame compressed by a motion vector and difference information cannot be decoded without an image frame to be referred to (referred to as a reference image frame). Therefore, in order to decode from the middle of a stream, an image that does not refer to another image frame It is necessary to provide frames periodically. This image frame is I
It is called a picture (Intra coded Picture). Decoding the next image frame using the I picture as the reference image frame,
Further, subsequent image frames are decoded using the already decoded image frame as a reference image frame. Among the image frames to be decoded using the reference image frame, a P picture (Predictive-coded Picutre) in which only the image frame preceding in time is used as the reference image frame, and the image frames preceding and succeeding in time are referred to as the reference image frame. B picture
(Bidirectionally predictive-coded picture). Similar to the I picture, the P picture can be a reference image frame of another image frame. Therefore, when decoding a compressed moving image, it is necessary to decode the preceding and following I picture or P picture before decoding the B picture, and the image frames in a different order from the order of the image frames as the reproduced video. Need to decrypt. Therefore, when the double speed reproduction is performed, the decoding process cannot be completed in time.

As a method for solving this problem, Japanese Unexamined Patent Publication No. H6-6
-133304 and Japanese Patent Laid-Open No. 7-154743. The former encodes an I picture and a P picture with a constant cycle in order to smooth a double speed reproduced video, and thus, when performing a double speed reproduction, decodes the I picture and the P picture with a constant cycle. I can do things. In the latter case, when the double speed reproduction is performed, the difference information is not calculated in the decoding process of the P picture and B picture streams, so that the processing is lightened and a smooth reproduced video is realized. Also,
There is a DVD (Digital Versatile Disk) as one of the media in which reproduced video information is compressed and recorded by applying the MPEG2. Normally, there is only one stream recorded on a DVD, but it is possible to record video from multiple camera angles (multi-angle function) or multiple different stories (multi-story function) depending on the scene. is there.
As a conventional information reproducing apparatus which realizes such a decoding process of a plurality of streams, there is one disclosed in Japanese Patent Laid-Open No. 2001-223991. FIG. 17 shows this information reproducing apparatus. In FIG. 17, the stream input from the input terminal 103 includes information of all angles, but the stream ID of all the information is E0. Stream ID is a flag determined by the MPEG standard and is E
It is possible to set a total of 16 values from 0 to EF. The stream ID changing circuit 101 changes the stream ID according to the angle number inputted from the input terminal 104 to the multi-angle stream inputted from the input terminal 103. Each MPEG decoder 102a
˜102p decodes streams of different stream IDs, and outputs the decoded image frame to each output terminal 105a˜1.
Output to 05p. In the invention described in Japanese Patent Laid-Open No. 2001-223991, the input stream is thus divided into a plurality of MPEG decoders for each angle and decoded by using the angle number, and the video of a plurality of angles can be reproduced simultaneously. . However, in this invention, there is no description about performing double speed reproduction.

[0004]

In the conventional information reproducing technique, it is desired that the reproduced image of double speed reproduction is smooth. In the information reproducing apparatus disclosed in Japanese Patent Laid-Open No. 6-133304, encoding is performed so that I pictures or P pictures are arranged in a certain cycle in accordance with a preset speed of double speed reproduction. Therefore, in the double speed reproduction at the set speed, it is possible to output an image frame at a constant cycle and realize a smooth reproduced video, but it is not possible to support the double speed reproduction at an arbitrary speed. Further, in the information reproducing apparatus disclosed in Japanese Patent Laid-Open No. 7-154743, the difference calculation with the reference image frame is not performed in order to lighten the decoding process of the P-picture and B-picture streams for double-speed reproduction. Therefore, although it is possible to realize double-speed reproduction at an arbitrary double speed, the image is not smooth because the difference information is not taken into consideration. Therefore, an object of the present invention is to provide an information reproducing technique capable of reproducing a smooth video at an arbitrary speed.

[0005]

According to the present invention, n (n is 1)
An image of the original image composed of a larger number of natural images) is reproduced without skipping, and when m (m is a natural number greater than 1 and smaller than n) double speed reproduction is composed of approximately n / m images. In the information reproducing technique for reproducing the video, the information reproducing technique is characterized in that the image is decoded by a plurality of image decoding units at the time of m-times speed reproduction.

[0006]

DETAILED DESCRIPTION OF THE INVENTION The first embodiment will be described below. FIG. 1 shows an overall configuration diagram of the information reproducing apparatus of the first embodiment.

In FIG. 1, a reproduction speed input terminal 21 is an input terminal for information indicating a reproduction speed. The reproduction mode setting circuit 2 outputs the reproduction mode information 22 to the stream control circuit 1 and the decoding result selection circuit 5 based on the information indicating the reproduction speed input from the reproduction speed input terminal 21, and the image decoding circuit 3
Image decoding circuit switching information 231 to 23n indicating operation or non-operation is output to 1 to 3n. Although the reproduction mode setting circuit 2 is configured to be processed by the circuit, it may be processed by software. Based on the image decoding circuit switching information 231 to 23n, the image decoding circuit 31 to
3n becomes an operating state or a non-operating state. The stream input terminal 11 is an input terminal for an MPEG compressed stream. The stream control circuit 1 determines the configuration of the image frame of the original video by analyzing the picture type of the stream input from the input terminal 11 and the period of each picture type. Further, the stream control circuit 1 distributes and outputs the image frames to the image decoding circuits 31 to 3n, as described later, during the double speed reproduction. Although the stream control circuit 1 is configured to be processed by a circuit, it may be processed by software. In addition, the control unit (not shown in FIG. 1) controls the stream control circuit 1, the reproduction mode setting circuit 2, the image decoding circuits 31 to 3n, or the decoding result selection circuit 5 to perform the processing described in the present embodiment. To do. The image decoding circuits 31 to 3n decode the stream input from the stream control circuit 1 into image frames. Although the image decoding unit for decoding the image is processed by the circuit in this embodiment, it may be processed by software. The image decoding circuits 31 to 3n output the decoded image frame to the decoding result selection circuit 5 at the output timing, and store the reproduced image information 51 in the image frame memory 4 at the output timing. Playback video information 51
The output timing of will be described later. When the decoded image frame is an I picture or a P picture, the image decoding circuits 31 to 3n store the decoded image frame in the image frame memory 4 as a reference image frame. It should be noted that the image frame memory 4 stores the reproduced video information 5
The output image frame memory for storing the image frame for adjusting the output timing of 1 and the reference image frame memory for storing the reference image frame are shared. The reason for adopting such a configuration is that the initial delay at the time of reproduction can be shortened, as will be described later. However, the image frame memory 4 does not necessarily need to share the reference image frame memory with the above-mentioned output image frame memory, and the reference image frame memory may be arranged in each of the image decoding circuits 31 to 3n. next,
When decoding the P picture or the B picture, the image decoding circuits 31 to 3n calculate the motion vector or the difference information based on the reference image frame recorded in the image frame memory 4, and decode the image frame. . The decoding result selection circuit 5 outputs the image frames input by the image decoding circuits 31 to 3n as reproduction video information 51 at the output timing described later based on the reproduction mode information 22 input by the reproduction mode setting circuit 2.

Next, a reproduction process for reproducing an image of an original video without skipping (hereinafter referred to as normal reproduction) will be described with reference to FIGS. 1 and 2. The reproduction mode setting circuit 2 outputs information indicating "normal reproduction" as the reproduction mode information 22 to the stream control circuit 1 and the decoding result selection circuit 5 if the information indicating the reproduction speed input from the reproduction speed input terminal 21 is normal reproduction. Then, the image decoding circuit switching information 231 indicating the operation is output to the image decoding circuit 31, and the image decoding circuit 32 is output.
The image decoding circuit switching information 23 indicating non-operation is included in 3n.
2 to 23n are output. The stream control circuit 1 determines the structure of the image frame of the original video (FIG. 2A) by analyzing the picture type of the input stream and analyzing the period of each picture type. As shown in FIG. 2B, the stream control circuit 1 outputs the stream input from the input terminal 11 to the image decoding circuit 31 as it is. At this time, since the image decoding circuits 32 to 3n are in the non-operating state, the stream control circuit 1 may output the stream to all the image decoding circuits. Image decoding circuit 3
This is because the 2 to 3n are in the non-operating state, and there is no problem as the reproduction processing. 2 and subsequent figures, fr represents one image frame, and the numbers represent the order of the image frames of the original video. Further, in MPEG, each frame has information indicating the frame number of its own original video and information indicating the picture type, and based on these information, the image decoding circuits 31 to 3n perform the decoding processing described below. Do. The image decoding circuit 31 to which the image decoding circuit switching information 231 indicating the operation is input by the reproduction mode setting circuit 2 first decodes the I picture and uses the decoded I picture as a reference image frame in the image frame memory 4
To memorize. Next, the P picture or B picture is decoded based on the reference image frame stored in the image frame memory 4. Then, as shown in FIGS. 2B and 2C, the decoded image frames are output to the decoding result selection circuit 5 in the order of the image frames of the original video. In addition, the image decoding circuits 32 to 3n to which the image decoding circuit switching information 232 to 23n indicating the non-operation is input by the reproduction mode setting circuit 2 are input.
Can stop the clock and power supply. This reduces the power consumption of the image decoding circuits 32 to 3n. The image frame memory 4 may output the reference image frame to all the image decoding circuits, or may output the reference image frame only to the image decoding circuit 31. Next, the decoding result selection circuit 5 reproduces the image frame decoded by the image decoding circuit 31 as it is as shown in FIG.
Output as.

Further, here, only the image decoding circuit 31 is set to the operating state at the time of normal reproduction, but the image decoding circuits 31 and 32 are set to the operating state and a plurality of image frames are decoded in parallel in time. You may. As a result, fr1 can be output as a reproduced image immediately after the reproduction is started.
This is because before decoding fr1, it is necessary to decode fr3 and fr0 which is a P picture (not shown) before that, but the image decoding circuit 31 cannot decode fr3 which is a P picture (not shown) at the same time as fr3. .
Therefore, the image decoding circuit 31 and the image decoding circuit 31 decode the fr3 and fr0 in parallel in time, so that the image decoding circuit 31 causes the fr3 and fr0 immediately after the decoding of the fr3.
Fr1 can be decoded by using as a reference image frame. Next, the ideal playback video information 51 for double-speed playback 51
The ideal image frame configuration of is described with reference to FIGS. 3 and 4. FIG. 3 shows an example of the image frame structure of the original video. On the other hand, in FIG. 4A, the image frames of the original image shown in FIG.
It is represented in. This is the smoothest reproduced video when the reproduced video is output at double speed and at equal intervals. This is because, in the MPEG2 system, the number of image frames output as reproduced video every second is set to 30 image frames. Therefore, during double-speed reproduction, half of the image frames shown in FIG. 3 cannot be reproduced. Therefore, as shown in FIG. 4A, by outputting the image frames of the original video image at equal time intervals, the smoothest reproduced video image can be obtained. The image frame of the reproduced video shown in FIG. 4C is the smoothest reproduced video when the reproduced video is composed of the image frames of only the I picture and P picture in the double speed reproduction. In this case,
B picture is not decoded. Therefore, Figure 4 (b)
It is necessary to output an I picture or a B picture instead of the B picture as shown in FIG. Note that fr1 and fr2 in FIG. 3 need to be decoded based on an image frame before fr1 (not shown in FIG. 3). Therefore, for convenience of explanation, fr1 and fr2 are omitted.

Next, a method for realizing the reproduced image shown in FIG. 4A at the time of double speed reproduction will be described with reference to FIGS. 1, 3 and 5.
Will be explained. However, fr1 in FIG.
It is necessary to decode fr2 based on an image frame before fr1 (not shown in FIG. 4A). Therefore, for convenience of description, description of the decoding process of fr1 and fr2 is omitted. This also applies to other embodiments below.

If the information indicating the reproduction speed input from the reproduction speed input terminal 21 is the double speed reproduction, the reproduction mode setting circuit 2 outputs "double speed reproduction" as the reproduction mode information 22 to the stream control circuit 1 and the decoding result selection circuit 5. Is output, the image decoding circuit switching information 231 and 232 indicating the operation is output to the image decoding circuits 31 and 32, and the image decoding circuit 3 is output.
Image decoding circuit switching information 2 indicating non-operation in 3 to 3n
33 to 23n are output. The stream control circuit 1 determines the configuration of the image frame of the original video (see FIG. 5A) by analyzing the picture type of the stream input from the input terminal 11 and the cycle of each picture type. Then, as shown in (b), (c), and (e) of FIG. 5, the stream control circuit 1 selects an image frame required for decoding at double speed reproduction from the stream input from the input terminal 11. And outputs to the image decoding circuits 31 and 32. In addition, f which is a B picture in the image frame
r4, fr8, fr10, fr14, fr16, fr2
0, fr22, fr26 ... Are not output to the image decoding circuits 31 and 32. This is because the B picture does not become a reference image frame, and in double speed reproduction, as shown in FIG. 4, fr4, fr8, fr10, fr14, fr1.
This is because 6, fr20, fr22, fr26 ... Are not reproduced images. Hereinafter, this also applies to other embodiments. Note that in the present embodiment, as shown in FIGS. 5B, 5C, and 5E, image frames are imaged in image frame units (15 image frames) that can be decoded based on one I picture. It is distributed to the decoding circuits 31 and 32. However, the present invention is not limited to this, and the image frame may be distributed for each decoding of the I picture such as distributing the image frame for each GOP. In addition, the image decoding circuit 33
Since 3 to 3n are in the non-operating state, the image frame may or may not be output to the image decoding circuits 33 to 3n. This is because there is no problem in the reproduction process. The image decoding circuit 3 to which the image decoding circuit switching information 231 and 232 indicating the operation is input by the reproduction mode setting circuit 2
As shown in FIGS. 5C and 5E, the image decoding circuits 31 and 32 decode the image frames input from the stream control circuit 1 in order from fr3 to image decoding circuit 32 from fr18. Here, the time required for each image decoding circuit to decode each image frame is much longer than the time required for the stream control circuit 1 to distribute and output the stream. Therefore, it is assumed that each image decoding circuit can input and output image frames substantially simultaneously.
This also applies to other embodiments below. Next, the decoded image frame is temporarily stored in the image frame memory and is output to the decoding result selection circuit 5 at the output timing of the reproduced video information 51 shown in FIG.
Also in this case, the time required for each image decoding circuit to decode the image frame is much longer than the time required for each image decoding unit to output the image frame to the image frame memory 4, the decoding result selection circuit 5 and the like. Therefore, the image decoding circuit 31,
It is assumed that 32 can input and output image frames substantially at the same time. This also applies to other embodiments below. Note that the decoded image frame is directly output to the decoding result selection circuit 5 at the timing of outputting the decoded image frame as in fr13. Also, I picture, P
Of the pictures, fr6, fr12, fr1 not output
.., fr24, fr30 ... Are not used after being used as reference image frames, and therefore need not be stored in the image frame memory 4.

In the present embodiment, as shown in FIGS. 5 (c) and 5 (g), the output of the reproduced video information 51 is started at the time point A, but about 0 from the time point 0 when the decoding of the image frame is started. There is an initial delay for playback by the time it takes to decode 6 image frames.

In the first embodiment, the time B shown in FIG.
At this point, the image decoding circuit 31 needs fr15 and fr18 as reference image frames in order to decode fr17.
However, when the decoding process is performed only by the image decoding circuit 31, fr18 cannot be decoded by the time point B. Therefore, as shown in FIG. 5 (e), the image decoding circuit 32 decodes fr18 by time point B and stores fr18 in the image frame memory 4 as a reference image frame memory. This allows the image decoding circuit 31 to decode fr17 at time point B. At time C, the image decoding circuit 32 starts decoding fr19 as shown in FIG. 5 (e), but at the same time, the image decoding circuit 31 decodes fr33 as shown in FIG. 5 (c). To start. As a result, the image decoding circuit 32 causes fr3
Before outputting 1, the image decoding circuit 31 decodes fr33 and stores fr33 in the image frame memory 4 as an output image frame. The image result selection unit 5 is shown in FIG.
The image frames decoded by the image decoding circuits 31 and 32 as shown in (1) are output as the reproduced video information 51 at the output timing. This is the smoothest reproduced video in the case of the double speed reproduction shown in FIG.

As described above, in the first embodiment, the image frames are decoded by the two image decoding circuits, so that at the time of double speed reproduction, the image frames which cannot be decoded by only one image decoding circuit are decoded. It is possible to realize a smooth reproduced image. The image frame memory 4 needs to have a memory capacity of 10 image frames or more. Because, as mentioned above, it is necessary to store the reference image frames for four image frames,
Further, as described above, at least 6 image frames are required to store the decoded image frame up to the output timing of the reproduced video information 51.

Next, a second embodiment will be described.
In the present embodiment, a method for realizing the reproduced video information 51 in the double speed reproduction shown in FIG. 6G will be described. Figure 6
The reproduced video information 51 at the time of the double speed reproduction shown in (g) is not as smooth as in FIG. 4A, but the reproduced video information 51 is smoother than that in FIG. 4C.

The image decoding circuits 31 and 32 are shown in FIG.
As shown in (e), the stream input from the stream control circuit 1 is decoded. Decoding result selection circuit 5
Is the image decoding circuits 31, 32 as shown in FIG.
The decoded image frame is output as reproduced video information 51 at the output timing.

As described above, in the second embodiment,
Although the image at the time of double speed reproduction is not as smooth as that of the first embodiment, as is clear from comparison between FIGS. 5C and 5G with FIGS. In the second embodiment, from the time 0 point (the start of decoding the image frame) to the time A point (the start of outputting the reproduced video information 51), an initial delay occurs for the decoding time of about 6 frames of the image in the second embodiment. Time 0
There is an effect that it is possible to reduce the initial delay by the decoding time of about 2 image frames from the point (start of decoding the image frame) to the time point A (start of outputting the reproduced video information 51). Also,
As a result, the memory capacity of the image frame memory 4 can be reduced.

Next, a third embodiment will be described. In the third embodiment, an example of realizing the reproduced video shown in FIG. 4C will be described with reference to FIGS. 1, 3 and 7.

When the information indicating the reproduction speed input from the reproduction speed input terminal 21 is the double speed reproduction, the reproduction mode setting circuit 2 gives "double speed reproduction" as the reproduction mode information 22 to the stream control circuit 1 and the decoding result selection circuit 5. Is output, the image decoding circuit switching information 231 and 232 indicating the operation is output to the image decoding circuits 31 and 32, and the image decoding circuit 3 is output.
Image decoding circuit switching information 2 indicating non-operation in 3 to 3n
33 to 23n are output. As shown in FIG. 7 (a),
The stream control circuit 1 determines the configuration of the image frame of the original video by analyzing the picture type of the stream input from the input terminal 11 and the cycle of each picture type. Then, as shown in FIG. 7B, the stream control circuit 1 outputs the stream input from the input terminal 11 to the image decoding circuits 31 and 32 without distributing the stream. At this time, the stream control circuit 1 may output the stream input from the input terminal 11 to all the image decoding circuits. This is because the image decoding circuits 33 to 3n are in a non-operating state, so that there is no problem in reproduction processing. Next, the image decoding circuits 31 and 32 to which the image decoding circuit switching information 231 and 232 indicating the operation by the reproduction mode setting circuit 2 are input, skip the B picture from the stream input from the stream control circuit 1. ,
Of the I picture or P picture, FIG.
As shown in (d), (e), and (f), reproduced video information 51
The image frames matched with the output timing (see FIG. 7G) are alternately decoded using the common image frame memory 4. Here, the process of skipping image frames by the image decoding circuits 31 and 32 is delayed by one image frame regardless of the number of image frames to be skipped. Therefore, when the image frame is decoded only by the image decoding circuit 31, fr6 cannot be decoded by the time point B. Therefore, the image decoding circuit 32 sets f before the point A.
r6 is decoded and fr6 is stored in the image frame memory 4 as an output image frame. As a result, it is possible to decode an image frame that cannot be decoded only by the image decoding circuit 31. However, in order to solve the problem that the image decoding circuits 31 to 3n skip the image frames by a delay of one image frame, the image decoding circuits 31 and 32.
The stream control circuit 1 may distribute and output only the streams decoded by the respective image decoding circuits, instead of performing the skip processing. As a result, the processing delay for one image frame can be shortened. Next, the decoding result selection circuit 5 selects the image frames in the order shown in FIG. 7G so that the reproduced video becomes the smoothest in the image frames of only the I picture and P picture, and outputs the reproduced video information 51. . This is the reproduced image shown in FIG.

As described above, in the third embodiment, the reproduced video of FIG. 4C can be realized by using a plurality of image decoding circuits. Further, as compared with the first embodiment, the reference image frame and the image frame for adjusting the output timing can be reduced, so that the capacity of the image frame memory can be reduced. Further, since the stream control circuit 1 outputs the image frame memories without distribution, the configuration of the stream control circuit 1 can be simplified as compared with the first embodiment.

Next, a fourth embodiment will be described.
In the present embodiment, a method of realizing the reproduced video information 51 in the double speed reproduction shown in FIG. 8G will be described. The reproduced video information 51 in the double speed reproduction shown in FIG. 8G is not as smooth as in FIG. 4A, but the reproduced video information 51 is smoother than that in FIG. 4C.

Also in this embodiment, the stream control circuit 1 outputs the image frames to the image decoding circuits 31 and 32 without distributing them (see FIG. 8B), and each image decoding circuit does not need to decode. The image frame is skipped (see FIGS. 8D and 8F). And FIG. 8 (g)
As shown in, the decoding result selection circuit 5 outputs the image frame decoded by the image decoding circuits 31 and 32 as the reproduced video information 51 at the output timing.

As described above, in the fourth embodiment, the stream control circuit 1 outputs the image frames to the image decoding circuit without allocating them, so that the processing of the stream control circuit 1 is simpler than in the first embodiment. Can be Also, a smoother reproduced video can be output as compared with the third embodiment.

Next, a fifth embodiment will be described.
In the present embodiment, a method for realizing the reproduced video information 51 in the double speed reproduction shown in FIG. 9G will be described. The reproduced video information 51 at the time of double speed reproduction shown in FIG. 9 (g) is not as smooth as in FIG. 4 (a), but it shows smoother reproduced video information 51 than in FIG. 4 (c).

Also in the present embodiment, the stream control circuit 1 outputs the image frames to the image decoding circuits 31 and 32 without distributing them (see FIG. 9B), and each image decoding circuit does not need to perform decoding. The image frame is skipped (see FIGS. 9D and 9F). And FIG. 9 (g)
As shown in, the decoding result selection circuit 5 outputs the image frame decoded by the image decoding circuits 31 and 32 as the reproduced video information 51 at the output timing.

As described above, in the fifth embodiment, the stream control circuit 1 outputs the image frames to the image decoding circuit without allocating them, so that the processing of the stream control circuit 1 is simpler than in the first embodiment. Can be Also, a smoother reproduced video can be output as compared with the third embodiment.

Next, a sixth embodiment will be described. In the sixth embodiment, the image decoding circuits 31 to 31 in FIG.
A method for realizing the reproduced video shown in FIG. 4A with 33 as the operating state will be described.

Image decoding circuits 31 to 33 are shown in FIGS.
The decoding process of is shown. In this embodiment, FIGS. 10 (a), 10 (b), 11 (a), 11 (b) and 12 are used.
As shown in (a) and (b), the stream control circuit outputs the input stream to the image decoding circuits 31 to 33 without distributing the stream. 10 (c), (d), and FIG.
1 (c) and (d), and as shown in FIGS. 12 (c) and 12 (d), the image decoding circuits 31 to 33 decode the image frames, and as a result, FIGS. 10 (e) and 11 (e). And FIG.
The reproduced video information 51 shown in (e) is output. this is,
This is the smoothest reproduced image in the double speed reproduction shown in FIG.

As described above, in the sixth embodiment, 3
The image frame is decoded by one decoding circuit. As a result, as is clear from comparison between FIGS. 5C and 5G and FIGS. 10C and 10E, in the first embodiment, from time 0 point (decoding start of the image frame) In the sixth embodiment, the initial delay occurs by the decoding time of about 6 frames of the image until the time point A (start of output of the reproduced video information 51).
There is an effect that it is possible to reduce the initial delay by the decoding time of about 2 image frames from the point (start of decoding the image frame) to the time point A (start of outputting the reproduced video information 51). Also,
As a result, the memory capacity of the image frame memory 4 can be reduced.

Next, a seventh embodiment will be described.
In the seventh embodiment, quad speed reproduction processing will be described.

First, regarding the ideal image frame structure of the ideal reproduction video information 51 at the time of 4 × speed reproduction, FIG.
This will be described with reference to FIG. FIG. 13 shows an example of reproduced video information 51 output from the decoding result selection circuit 5 during normal reproduction. On the other hand, the case where the output image frames shown in FIG. 14A are output at quadruple speed and at equal intervals (that is, the reproduced video is formed every three image frames in the reproduced video information 51 of FIG. 13), The smoothest playback image is obtained in the case of quad speed playback. The output image frame shown in FIG. 14B is an image frame of only I pictures and P pictures, and the reproduced video is the smoothest.

Next, a method of outputting the information of the reproduced video shown in FIG. 14A will be described with reference to FIGS. 1, 13, 15, and 16.
Will be explained.

If the information indicating the reproduction speed input from the reproduction speed input terminal 21 is the quadruple speed reproduction, the reproduction mode setting circuit 2 gives "4x speed reproduction" as the reproduction mode information 22 to the stream control circuit 1 and the decoding result selection circuit 5. Is output, the image decoding circuit switching information 231 and 232 indicating the operation is output to the image decoding circuits 31 and 32, and the image decoding circuit 3 is output.
Image decoding circuit switching information 2 indicating non-operation in 3 to 3n
33 to 23n are output. The stream control circuit 1 compares the picture type of the stream input from the input terminal 11 and the cycle of each picture type, as shown in FIGS. 15 (a) and 16 (a). Determine the configuration of. Then, the stream control circuit 1 outputs the stream input from the input terminal 11 to the stream shown in FIG.
(C), as shown in FIG. 16 (c), the image decoding circuit 31,
It outputs to 32. All image frames may be output to the image decoding circuits 33 to 3n. This is because the image decoding circuits 33 to 3n are in a non-operating state and there is no problem in the decoding processing. The image decoding circuits 31 and 32 to which the image decoding circuit switching information 231 and 232 indicating the operation are input by the reproduction mode setting circuit 2 are input to the stream control circuit 1.
From the input stream, the image frames are synchronized with the output timing of the reproduced video information 51 (see FIGS. 15 (e) and 16 (e)) as shown in FIGS. 15 (c) and 16 (c). Decrypt. Then, the image decoding circuits 31, 3
2 outputs the image frame decoded as shown in FIGS. 15D and 16D to the decoding result selection circuit 5. As shown in FIGS. 15 (e) and 16 (e), the image result selection unit 5 delays the output start time of the reproduced video by four image frames, so that the result shown in FIGS. 15 (e) and 16 (e) is displayed. Such reproduced video information 51 can be output. this is,
This is the smoothest reproduced video in the case of the 4 × speed reproduction shown in FIG. In the present embodiment, when the image frame is decoded only by the image decoding circuit 31 during the 4 × speed reproduction, for example, when fr19 is decoded at the time point A in FIGS. 15 (c) and 16 (c). The decoding process will not be in time. Because to decode fr19, f
r18. This is because the fr21 is required, and the fr18 and fr21 cannot be decoded before the time point A only by the image decoding circuit 31. The image frame memory 4
Needs to have a memory capacity for 6 image frames. This is because it is necessary to store reference image frames for four image frames, and at least two image frames for storing decoded image frames up to the output timing of the reproduced video information 51.

As described above, in the seventh embodiment, by decoding the image frames by the image decoding circuits 31 and 32, it is possible to output the smoothest reproduced video in the 4 × speed reproduction. .

As described above, according to the present invention, by providing the information reproducing apparatus having a plurality of image decoding circuits, the output image frames can be arranged at equal intervals during the double speed reproduction, and the smooth double speed reproduction is realized. be able to.

Further, in the present embodiment, the original video has been described as being composed of the image frames shown in FIG. 3 or FIG. 13, but the structure of the image frame of the original video is not limited to these. Absent. Further, in the present embodiment, the process of setting the image decoding circuits 31 to 33 in the operating state has been described. However, by setting more image decoding circuits in the operating state, the initial delay and the like are further prevented, and the image frame memory It is possible to reduce the capacity. In the present invention, only the 2 × speed reproduction and the 4 × speed reproduction have been described.
In the case of the double speed reproduction, the reproduced video is composed every (n-1) image frames so that the reproduced video can be made smooth in the arbitrary speed reproduction. Also, the reproduction processing can be lightened by slightly lowering the image quality of the reproduced video of the double speed reproduction. Further, in the present embodiment, the stream control circuit 1, the reproduction mode setting circuit 2, the image decoding circuits 31 to 3n, and the decoding result selection circuit 5 are configured to be processed by circuits, but these processes may be performed by software. This is as described above. Also,
By assigning the image decoding circuit to the decoding processing of each angle even for a multi-angle stream, it is possible to reproduce any angle.

[0037]

As described above, according to the present invention, it is possible to provide an information reproducing technique capable of reproducing a smooth image at an arbitrary speed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the overall configuration of an information reproducing device.

FIG. 2 is an explanatory diagram of the order of image frames in normal reproduction.

FIG. 3 is an explanatory diagram of an image frame structure of an original image.

FIG. 4 is an explanatory diagram of a configuration of an image frame which becomes ideal reproduced video information 51 at the time of double speed reproduction.

FIG. 5 is an explanatory diagram of a process for realizing the reproduced video information 51 of FIG.

FIG. 6 is an explanatory diagram of processing at double speed reproduction (processing of reproduced video including B picture).

FIG. 7 is an explanatory diagram of a process for realizing the reproduced video information 51 of FIG. 4C.

FIG. 8 is an explanatory diagram of processing at double speed reproduction (processing of reproduced video including B picture).

FIG. 9 is an explanatory diagram of processing at double speed reproduction (processing of reproduced video including B picture).

FIG. 10 is an explanatory diagram of a process at the time of double-speed reproduction (using three image decoding circuits), an image decoding circuit 31 part.

FIG. 11 is an explanatory diagram of a process at the time of double-speed reproduction (using three image decoding circuits), an image decoding circuit 32 part.

FIG. 12 is an explanatory diagram of a process at the time of double-speed reproduction (using three image decoding circuits), an image decoding circuit 33 part

FIG. 13 is an explanatory diagram of an image frame structure of an original image.

FIG. 14 is an ideal reproduction video information 51 at the time of 4 × speed reproduction.
Of the image frame structure

15 is an explanatory diagram of a process (image decoding circuit 31 portion) for realizing the reproduced video information 51 of FIG. 14A.

16 is an explanatory diagram of a process (image decoding circuit 32 portion) for realizing the reproduced video information 51 of FIG.

FIG. 17 is an explanatory diagram of a configuration of a conventional information reproducing device.

[Explanation of symbols]

1 ... Stream control circuit, 21 ... Reproduction speed input terminal, 1
1 ... Stream input terminal, 2 ... Play mode setting circuit, 2
2 ... Playback mode information, 231-23n ... Image decoding circuit switching information, 31-3n ... Image decoding circuit, 4 ... Image frame memory, 5 ... Decoding result selection circuit 51 ... Playback video information, 101 ... Stream ID replacement circuit, 102a ~ 1
02p ... MPEG decoder, 103 ... Input stream input terminal, 104 ... Control information input terminal, 105a to 105p
... Video output terminal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yukitoshi Tsuboi             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F-term (reference) 5C053 GA11 GB37 HA24 KA30                 5D044 AB07 BC08 CC09 DE12 DE32                       DE39 FG18 FG24 GK08 GK12

Claims (12)

[Claims] 1. An original image composed of n (n is a natural number larger than 1) images is reproduced without skipping, and m is reproduced.
(M is a natural number greater than 1 and less than n) In an information reproducing apparatus for reproducing a video composed of approximately n / m images at the time of double speed reproduction, a plurality of image decoding units at the time of m times speed reproduction. An information reproducing apparatus characterized in that an image is decoded by. 2. The information reproducing apparatus according to claim 1, wherein the m-times speed reproduction video is a video composed of every m-1 images of the original video. An information reproducing apparatus characterized in that an image is decoded by a unit. 3. The information reproducing apparatus according to claim 1, wherein only the first image decoding unit of the plurality of image decoding units has m.
An information reproducing apparatus, wherein an image which cannot be decoded in time when an image of double speed reproduction is decoded is decoded by an image decoding unit other than the first image decoding unit. 4. An information reproducing apparatus for reproducing video from a stream, comprising a plurality of image decoding units for decoding images from the stream, and a decoding result selection for selectively outputting the images decoded by the plurality of image decoding units. Unit and a control unit that controls the plurality of image decoding units and the decoding result selection unit according to the reproduction speed. When reproducing an image of an original video without skipping, the control unit is The first image decoding unit of the image decoding units is controlled to decode the stream, and the decoding result selection unit is controlled to output the image decoded by the first image decoding unit as it is, n ( (n is a natural number larger than 1) During double speed reproduction, the control unit causes the plurality of image decoding units to perform decoding of the stream, and the decoding result selection unit performs decoding by the plurality of image decoding units. An information reproducing apparatus characterized in that it controls so as to selectively output the encoded image. 5. The information reproducing apparatus according to claim 4, wherein the decoding result selection unit causes the control unit to display the n-times speed reproduction image as an image composed of images at substantially equal time intervals. An information reproducing apparatus characterized by controlling so as to select and output an image. 6. The information reproducing apparatus according to claim 4 or 5, wherein the control unit is configured to perform decoding when an image of n-times speed reproduction is decoded only by the first image decoding unit. An information reproducing apparatus characterized by controlling an image decoding unit other than the first image decoding unit to decode an image which is not in time. 7. An original image composed of n (n is a natural number larger than 1) images is reproduced without skipping, and m is reproduced.
(M is a natural number greater than 1 and less than n) In an information reproducing method for reproducing a video composed of approximately n / m images at the time of double speed reproduction, a plurality of image decoding units at the time of m times speed reproduction. An information reproducing method characterized in that an image is decoded by. 8. The information reproducing method according to claim 7, wherein the m-times-speed reproduction video is a video composed of every m-1 images of the original video. An information reproducing method characterized in that an image is decoded by a unit. 9. The information reproducing method according to claim 7, wherein only the first image decoding unit of the plurality of image decoding units has m.
An information reproducing method characterized in that an image which cannot be decoded in time when an image of double speed reproduction is decoded is decoded by an image decoding unit other than the first image decoding unit. 10. An information reproducing method for reproducing a video from a stream, wherein, when reproducing an image of an original video without skipping it, a first image decoding unit decodes the stream,
A video is composed of the images decoded by the image decoding unit of, and at the time of n (n is a natural number larger than 1) double speed reproduction, a plurality of image decoding units including the first image decoding unit And an image is composed of the images decoded by the plurality of image decoding units. 11. The information reproducing method according to claim 10, wherein the images are reproduced by the plurality of image decoding units so that the n-times speed reproduction images are images composed of images at substantially equal time intervals. An information reproducing method characterized by decoding. 12. The information reproducing method according to claim 10 or 11, wherein the image which cannot be decoded in time when an image of n-times speed reproduction is decoded only by the first image decoding unit is used. An information reproducing method characterized by performing decoding by an image decoding unit other than the first image decoding unit.