JP2007336069A - Information processor and processing method, program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect a possessed anchor frame which can be deleted. <P>SOLUTION: Possessed anchor banks for 10 frames are provided and when a GOP(N-3) is supplied under such a state as the baseband image data of a possessed anchor frame corresponding to the GOP(N-1), GOP(N) and GOP(N+1), respectively, are stored in bank 1 to bank 9, bank 10 of empty bank is assured at the time of decoding an I2 picture and corresponding baseband image data is stored. The P5 picture and B10 picture of the GOP(N+1) are waiting a display command and since the P8 picture of the GOP(N-1) is not included in the decode schedule already, the baseband image data corresponding to the possessed anchor frame of the GOP(N+1) and GOP(N-1) is not deleted but the baseband image data corresponding to the possessed anchor frame of the GOP(N) is deleted. The invention is applicable to a reproducer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing device, an information processing method, a recording medium, and a program, and in particular, an information processing device capable of reproducing compressed and encoded data without controlling a complicated frame memory. The present invention relates to an information processing method, a recording medium, and a program.

  MPEG (Moving Picture Coding Experts Group / Moving Picture Experts Group) is widely used as a video compression technique.

  When decoding and reproducing stream data compressed and encoded by MPEG, there is a technique for executing high-speed reproduction or reproducing in the reverse direction in addition to normal reproduction.

  For example, in MPEG LongGOP which constitutes 1 GOP with 15 pictures, the B picture is thinned out at the input to the decoder, so that it is -3 to 3 times (minus the speed indicates reverse playback, and so on). High-speed reproduction can be performed (see, for example, Patent Document 1). Further, by having a table of picture information to be displayed for each reproduction speed, it is possible to perform reproduction at the speed of the prepared table.

JP-A-8-98142

  Also, for example, a compression-coded signal is acquired intermittently for 10 frames at intervals of 5 frames, and all the acquired compressed-coded signals are demodulated and then alternately supplied to the two decoding units for 5 frames. There is a technique in which, after each decoding process is executed, the decoded data is written in a memory and read out every other frame so that a double-speed reproduction signal can be obtained (for example, Patent Document 2). reference).

JP-A-8-56334

  Also, MPEG streams are convenient for playback in the forward direction. For example, the sequence of pictures in the coding order of 1 GOP in MPEG Long GOP that constitutes 1 GOP with 15 pictures is I (2) B (0) B (1), P (5), B (3), B (4), P (8), B (6), B (7), P (11), B (9), B (10), P (14), B (12), B (13) (however, in parentheses The number indicates the order when the coding order is rearranged into the display order), and the picture referred to by the P picture is the previous I picture or P picture, and the picture referenced by the B picture is The previous I picture or P picture in the coding order and the second previous I picture or P picture. As a result, by reserving two reference picture memories (two banks), both the P picture and the B picture can be decoded, and the memory can be used efficiently.

  In this way, in order to reversely play back an MPEG stream that is convenient for playback in the forward direction, a decoding process is executed using a plurality of decoders, and a GOP immediately preceding the GOP to be decoded is added. There is a technique in which a reference image of a picture to be reproduced can be used correctly even in backward reproduction by supplying the data to a decoder (for example, Patent Document 3).

JP-A-10-150635

  For example, in MPEG LongGOP which constitutes 1 GOP with 15 pictures, the B picture is thinned out at the input to the decoder, so that it is -3 to 3 times (minus the speed indicates reverse playback, and so on). High-speed playback is possible, but the display interval of pictures becomes irregular, resulting in an unnatural display.

  In addition, when decoding is performed using a plurality of decoder chips, by combining with a process of thinning out B pictures that are not to be displayed at the input stage, even higher-speed playback (for example, 2 times with 2 chips, 4 times with 3 chips, 5 times with 4 chips, 7 times with 5 chips), but in the output processing, it is necessary to thin out I pictures or P pictures, Control of the baseband memory and processing for selecting data to be displayed from decoded data become complicated. For this reason, it has been difficult to reproduce and display by dynamically changing the speed using the conventional technique.

  Further, as described above, by having a table of picture information to be displayed for each reproduction speed, it is possible to reproduce at a speed corresponding to the prepared table. However, in such processing, the change of speed becomes a table unit, and moreover, complicated control is required to perform display at the time of switching without delay.

  As described above, the MPEG stream can be conveniently reproduced in the forward direction. However, when playback in the reverse direction is performed in the input order of the streams, if playback is performed in the reverse direction after decoding for 1 GOP is completed, a frame that can record data of at least 1 GOP (for example, 15 frames) can be recorded. Since a memory is provided and a large number of banks for reference image data must be reserved, a large memory capacity is required.

  The present invention has been made in view of such a situation, and makes it possible to perform high-speed reproduction, reverse reproduction, and high-speed reverse reproduction of compression-encoded data.

  An information processing apparatus according to a first aspect of the present invention is an information processing apparatus that decodes an encoded stream, and includes a holding unit that holds data generated by decoding for a plurality of frames, and uses the holding unit. A decoding unit that decodes the encoded stream, a supply unit that supplies the encoded stream to the decoding unit, and a control unit that controls processing performed by the supply unit and the decoding unit. The means supplies a reference frame to be referred to for decoding the predetermined frame of the encoded stream before the timing at which the predetermined frame is decoded by the decoding means to the decoding means, When the decoding unit decodes any reference frame, the decoding unit stores new data in the holding unit. Necessary for decoding the first frame or the first frame that has no storage area and is decoded by the decoding means but not output into the data corresponding to the reference frame held by the holding means Different from either the second frame to be decoded, the third frame determined to be decoded by the decoding means, or the fourth frame necessary for decoding the third frame. If there is data corresponding to the fifth frame, the data corresponding to the fifth frame is deleted.

  The encoded stream has a GOP structure, and the holding means can hold data corresponding to a predetermined frame that is not continuous among the reference frames in one GOP.

  The holding means is used when a storage area for X frames for holding data generated by decoding the reference frame and a P picture or B picture other than the predetermined frame are decoded and output. The storage area for two frames can be included.

  The storage area for the X frames is a first frame for one frame for holding data generated by decoding the P picture other than the predetermined frame, which is used for decoding the predetermined frame. A storage area; a second storage area for one frame for holding data generated by decoding the P picture other than the predetermined frame, used to decode the B picture; And a third storage area for X-2 frames for holding data generated by decoding the first frame.

  When the decoding means decodes any of the reference frames, there is no new data storage area in the third storage area of the holding means, and the data held in the third storage area In addition, when the fifth frame exists, the fifth frame can be deleted from the third storage area.

  The storage area for the X frames is used for decoding the I picture included in the predetermined frame, and is for holding data generated by decoding the P picture other than the predetermined frame A first storage area for a frame and data generated by decoding the P picture other than the predetermined frame, which is used to decode the P picture or the B picture other than the predetermined frame A second storage area for two frames, the predetermined frame, and the P picture other than the predetermined frame used for decoding the P picture included in the predetermined frame are decoded. And a third storage area for X-3 frames for holding the generated data It can be as.

  When the decoding means decodes any of the reference frames, there is no new data storage area in the third storage area of the holding means, and the data held in the third storage area In addition, when the fifth frame exists, the fifth frame can be deleted from the third storage area.

  The information processing method or program according to the first aspect of the present invention provides a reference frame that is referred to in order to decode the predetermined frame of the encoded stream prior to a timing at which the predetermined frame is decoded. To the decoder, schedule the decoding process of the reference frame, determine whether there is a storage area for new data in the holding unit that holds a plurality of frames of decoded and generated data, The first frame that is decoded by the decoder but not output is decoded into the data corresponding to the reference frame held by the holding unit, which has no new data storage area, or the first frame is decoded. The second frame that is needed for the first or second to be decoded by the decoder If there is data corresponding to a fifth frame different from any of the third frame or the fourth frame necessary for decoding the third frame, the data corresponding to the fifth frame is A reference frame for decoding and decoding the predetermined frame based on a schedule when there is a storage area for new data in the holding unit or when the fifth data is deleted from the holding unit When the output of the data corresponding to the predetermined frame is requested, the predetermined frame is decoded using the data corresponding to the reference frame generated by decoding.

  In the first aspect of the present invention, a reference frame referred to for decoding a predetermined frame in the encoded stream is supplied to the decoder prior to a timing at which the predetermined frame is decoded. It is determined whether or not there is a new data storage area in the holding unit that holds a plurality of frames of data that is scheduled to be decoded and is decoded, and there is no new data storage area in the holding unit. A first frame that is decoded by the decoder but not output, or a second frame that is necessary for decoding the first frame, or data corresponding to the reference frame held by the holding unit; or Decode the third frame or the third frame that is determined to be decoded by the decoder If there is data corresponding to a fifth frame that is different from any of the fourth frames required for the purpose, the data corresponding to the fifth frame is deleted, and the reference frame is decoded. Used to decode a predetermined frame.

  An information processing apparatus according to a second aspect of the present invention is an information processing apparatus that decodes an encoded stream, and includes a holding unit that holds data generated by decoding for a plurality of frames, and uses the holding unit. A decoding unit that decodes the encoded stream, a supply unit that supplies the encoded stream to the decoding unit, and a control unit that controls processing performed by the supply unit and the decoding unit. The means supplies a reference frame to be referred to for decoding the predetermined frame of the encoded stream before the timing at which the predetermined frame is decoded by the decoding means to the decoding means, When the decoding unit decodes any reference frame, the decoding unit adds a new reference to the holding unit. Necessary in order to decode the first frame or the first frame which has no data storage area corresponding to the frame, is decoded by the decoding means but is not output to the data held by the holding means If there is data corresponding to a third frame different from any of the second frames, the data corresponding to the third frame is deleted.

  In the second aspect of the present invention, a reference frame referred to for decoding a predetermined frame in the encoded stream is supplied to the decoder prior to a timing at which the predetermined frame is decoded. It is determined whether or not there is a new data storage area in the holding unit that holds a plurality of frames of data that is scheduled to be decoded and is decoded, and there is no new data storage area in the holding unit. Of data corresponding to the reference frame held by the holding unit, the first frame decoded by the decoder but not output, or the second frame necessary for decoding the first frame If there is data corresponding to a third frame that is different from any of the data, the data corresponding to the third frame is Is divided, the reference frame is decoded, by using the predetermined frame is decoded.

  An information processing apparatus according to a third aspect of the present invention is an information processing apparatus that decodes an encoded stream, and includes a holding unit that holds data generated by decoding for a plurality of frames, and uses the holding unit. A decoding unit that decodes the encoded stream, a supply unit that supplies the encoded stream to the decoding unit, and a control unit that controls processing performed by the supply unit and the decoding unit. The means supplies a reference frame to be referred to for decoding the predetermined frame of the encoded stream before the timing at which the predetermined frame is decoded by the decoding means to the decoding means, When the decoding unit decodes any reference frame, the decoding unit adds a new reference to the holding unit. Necessary for decoding the first frame or the first frame determined to be decoded by the decoding means into the data held by the holding means without the data storage area corresponding to the frame If there is data corresponding to a third frame different from any of the second frames, the data corresponding to the third frame is deleted.

  In the third aspect of the present invention, a reference frame referred to for decoding a predetermined frame in the encoded stream is supplied to the decoder prior to a timing at which the predetermined frame is decoded. It is determined whether or not there is a new data storage area in the holding unit that holds a plurality of frames of data that is scheduled to be decoded and is decoded, and there is no new data storage area in the holding unit. Of the first frame determined to be decoded by the decoder or the second frame necessary for decoding the first frame, into the data corresponding to the reference frame held by the holding unit If there is data corresponding to a third frame different from any of the above, the data corresponding to the third frame is Is divided, the reference frame is decoded, by using the predetermined frame is decoded.

  The network is a mechanism in which at least two devices are connected and information can be transmitted from one device to another device. The devices that communicate via the network may be independent devices, or may be internal blocks that constitute one device.

  The communication is not only wireless communication and wired communication, but also communication in which wireless communication and wired communication are mixed, that is, wireless communication is performed in a certain section and wired communication is performed in another section. May be. Further, communication from one device to another device may be performed by wired communication, and communication from another device to one device may be performed by wireless communication.

  The playback device may be an independent device or a block that performs playback processing of the recording / playback device.

  As described above, according to the present invention, an encoded stream can be decoded. In particular, a reference frame can be decoded prior to the timing at which a predetermined frame is decoded, and can be further deleted in the frame memory. Since a new reference frame is decoded only when there is correct data, display or output errors can be suppressed while reducing the capacity of the frame memory.

  Embodiments of the present invention will be described below. Correspondences between constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  The information processing apparatus according to the first aspect of the present invention is an information processing apparatus (for example, the playback apparatus 101 in FIG. 44) that decodes an encoded stream, and holds data generated by decoding for a plurality of frames. Means (for example, the frame memory 131-3 in FIG. 45) and using the holding means, decode means (for example, the decoder 122 in FIG. 44) for decoding the encoded stream, and the code to the decoding means Supply means (for example, PCI bridge 17 in FIG. 44) and control means (for example, CPU 121 in FIG. 44) for controlling processing executed by the supply means and the decoding means. Is preceded by the timing at which a predetermined frame is decoded by the decoding means. A reference frame (for example, an anchor frame) referred to for decoding the predetermined frame is supplied to the decoding means, and the decoding means adds a new frame to the holding means when decoding any reference frame. In order to decode the first frame or the first frame which is not output but has not been output to the data corresponding to the reference frame held by the holding unit without the data storage area Either the second frame required for decoding, the third frame determined to be decoded by the decoding means, or the fourth frame required for decoding the third frame. If data corresponding to a different fifth frame exists, the fifth frame To delete the data.

  The encoded stream has a GOP structure, and the holding unit corresponds to a predetermined nonconsecutive frame (for example, retained anchor frame) among the reference frames (for example, I picture or P picture) in one GOP. Data can be retained.

  The holding unit stores a storage area (for example, a reference bank in FIG. 51 or FIG. 76) for X frames for holding data generated by decoding the reference frame (for example, an anchor frame), the predetermined frame Storage area (for example, B / non-owned anchor display bank of FIG. 51 or FIG. 76) used for decoding and outputting a P picture other than a frame (for example, non-owned anchor frame) or a B picture Can be included.

  The storage area for X frames is used to decode the predetermined frame, and holds data generated by decoding the P picture (for example, non-owned anchor frame) other than the predetermined frame. 1 frame of first storage area (for example, non-owned anchor bank in FIG. 51) and the P picture (for example, non-owned anchor frame) other than the predetermined frame used for decoding the B picture ) Is decoded to generate a second storage area for one frame (for example, a non-owned anchor bank for B picture display in FIG. 51) and the predetermined frame (for example, a retained anchor frame). ) Is stored in the third storage area (for example, X-2 frames) for holding the data generated by decoding It can be assumed to be constituted by 51 stored anchor bank) and the.

  When the decoding means decodes any of the reference frames, the third storage area (for example, the retained anchor bank in FIG. 51) of the holding means has no new data storage area, and the third storage area When the fifth frame exists in the data held in the storage area, the fifth frame can be deleted from the third storage area.

  The storage area for X frames is generated by decoding the P picture (for example, non-owned anchor frame) other than the predetermined frame, which is used to decode the I picture included in the predetermined frame. Used to decode the first storage area (for example, non-owner anchor bank in FIG. 76) for holding the data and the P picture or the B picture other than the predetermined frame, A second storage area for two frames (for example, the non-held anchor for display in FIG. 76) for holding data generated by decoding the P picture other than the predetermined frame (for example, the non-owned anchor frame) Bank), the predetermined frame (for example, owned anchor frame), and the predetermined frame. Third storage for X-3 frames for holding data generated by decoding the P picture (for example, non-owner anchor frame) other than the predetermined frame used to decode the P picture It can be constituted by a region (for example, a holding / non-owning anchor combined bank in FIG. 76).

  When the decoding means decodes any of the reference frames, the third storage area (for example, the retained anchor bank in FIG. 51) of the holding means has no new data storage area, and the third storage area When the fifth frame exists in the data held in the storage area, the fifth frame can be deleted from the third storage area.

  An information processing method or program according to an aspect of the present invention provides a reference frame (for example, a reference frame referred to for decoding the predetermined frame of the encoded stream prior to a timing at which the predetermined frame is decoded). , Anchor frame) is supplied to a decoder (for example, the decoder 122 in FIG. 44) (for example, the process in step S901 in FIG. 89), and the decoding process for the reference frame is scheduled (for example, in the process in step S932 in FIG. 90). Then, it is determined whether there is a storage area for new data in the holding unit (for example, the frame memory 131-3 in FIG. 45) that holds the data generated by decoding for a plurality of frames (for example, step S951 in FIG. ), There is no storage area for new data in the holding unit, and the holding unit holds the data The data corresponding to the reference frame is decoded by the first frame that is decoded by the decoder but not output, or the second frame that is necessary for decoding the first frame, or by the decoder If there is data corresponding to a fifth frame that is different from any of the third frame determined by or the fourth frame required to decode the third frame, the fifth frame When data corresponding to a frame is deleted (for example, the process of step S959 in FIG. 91), and there is a storage area for new data in the holding unit, or the fifth data is deleted from the holding unit Then, based on the schedule, a reference frame for decoding the predetermined frame is decoded (for example, the frame of FIG. When the output of data corresponding to the predetermined frame is requested, the predetermined frame is decoded using the data corresponding to the reference frame generated by decoding (for example, processing in step S961). Step S908 of FIG. 89).

  The information processing apparatus according to the second aspect of the present invention is an information processing apparatus (for example, the playback apparatus 101 in FIG. 44) that decodes an encoded stream, and holds data generated by decoding for a plurality of frames. Means (for example, the frame memory 131-3 in FIG. 45) and using the holding means, decode means (for example, the decoder 122 in FIG. 44) for decoding the encoded stream, and the code to the decoding means Supply means (for example, PCI bridge 17 in FIG. 44) and control means (for example, CPU 121 in FIG. 44) for controlling processing executed by the supply means and the decoding means. Is preceded by a timing at which a predetermined frame is decoded by the decoding means, A reference frame (for example, an anchor frame) referred to for decoding the predetermined frame is supplied to the decoding means, and the decoding means adds a new frame to the holding means when decoding any reference frame. In order to decode the first frame or the first frame which has no data storage area corresponding to the reference frame and is decoded by the decoding unit but not output into the data held by the holding unit If there is data corresponding to a third frame that is different from any of the second frames required for the first frame, the data corresponding to the third frame is deleted.

  The information processing apparatus according to the third aspect of the present invention is an information processing apparatus (for example, the playback apparatus 101 in FIG. 44) that decodes an encoded stream, and holds data generated by decoding for a plurality of frames. Means (for example, the frame memory 131-3 in FIG. 45) and using the holding means, decode means (for example, the decoder 122 in FIG. 44) for decoding the encoded stream, and the code to the decoding means Supply means (for example, PCI bridge 17 in FIG. 44) and control means (for example, CPU 121 in FIG. 44) for controlling processing executed by the supply means and the decoding means. Is preceded by a timing at which a predetermined frame is decoded by the decoding means, A reference frame (for example, an anchor frame) referred to for decoding the predetermined frame is supplied to the decoding means, and the decoding means adds a new frame to the holding means when decoding any reference frame. In order to decode the first frame or the first frame which has no data storage area corresponding to the reference frame and is determined to be decoded by the decoding means into the data held by the holding means If there is data corresponding to a third frame that is different from any of the second frames required for the first frame, the data corresponding to the third frame is deleted.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The first embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a hardware configuration of the playback apparatus 1.

  A CPU (Central Processing Unit) 11 is connected to the north bridge 12 and controls processing such as reading of data stored in an HDD (Hard disk Drive) 16, scheduling of decoding executed by the CPU 20, decoding In addition, a command for instructing start, change, or end of processing such as display output control is generated and output. The north bridge 12 is connected to a PCI bus (Peripheral Component Interconnect / Interface) 14. For example, under the control of the CPU 11, the north bridge 12 receives supply of data stored in the HDD 16 via the south bridge 15 and receives the PCI bus. 14, and supplied to the memory 18 via the PCI bridge 17. The north bridge 12 is also connected to the memory 13, and exchanges data necessary for the processing of the CPU 11.

  The memory 13 is a storage memory that can store data necessary for processing executed by the CPU 11 and that can be accessed at high speed, such as DDR (Double Data Rate). The south bridge 15 controls writing and reading of data in the HDD 16. The HDD 16 stores compressed and encoded stream data.

  The PCI bridge 17 includes a command buffer 31 and a result buffer 32 therein, and is connected to a memory 18 that buffers stream data read from the HDD 16 under the control of the CPU 11. The PCI bridge 17 can supply stream data read from the HDD 16 based on the control of the CPU 11 to the memory 18 and store the stream data, and stream data stored in the memory 18 based on the control of the CPU 20. Is supplied to the decoders 22 to 24. The PCI bridge 17 controls transmission / reception of a control signal corresponding to a command or a result via the PCI bus 14 or the control bus 19.

  The command buffer 31 receives commands written from the CPU 11 via the north bridge 12 and the PCI bus 14, and reads written commands from the CPU 20 via the control bus 19. The result buffer 32 receives a result written to the command by the CPU 20 via the control bus 19 and reads the written result from the CPU 11 via the north bridge 12 and the PCI bus 14. ing.

  The memory 18 stores compression-encoded stream data read by the HDD 16 based on the control of the PCI bridge 17 and is configured by, for example, SDRAM (Synchronous Dynamic Random Access Memory). .

  The CPU 20 reads a command written in the command buffer 31 of the PCI bridge 17 by the CPU 11 via the control bus 19, and processes executed by the PCI bridge 17, the decoders 22 to 24, and the selector 25 according to this command. To control. The memory 21 stores data necessary for the processing of the CPU 20.

  The decoders 22 to 24 decode the supplied compressed and encoded stream data based on the control of the CPU 20 and output an uncompressed video signal. The decoder 22 has a memory 41 therein, the decoder 23 has a memory 42 therein, and the decoder 24 has a memory 43 therein, and the compressed and encoded stream data supplied as necessary. Alternatively, the decoded uncompressed video signal can be held. The decoders 22 to 24 may be provided as independent devices that are not included in the playback device 1.

  The selector 25 can switch the output of uncompressed SDI (Serial Digital Interface) data output by the decoder 22 to the decoder 24 with frame accuracy based on the setting by the CPU 20.

  Note that the playback device 1 in FIG. 1 may be configured as a single device or may be configured by a plurality of devices. For example, in the playback device of FIG. 1, the CPU 11, the north bridge 12, the memory 13, the south bridge 15, and the HDD 16 are assumed to be a part of the configuration of the personal computer. An expansion card or expansion board such as PCI bus 14, PCI bridge 17, memory 18, control bus 19, CPU 20, memory 21, decoder 22 to decoder 24, and selector 25 are provided with a personal computer. You may make it function as the reproducing | regenerating apparatus 1 by attaching an expansion card. Further, these may be further divided into a plurality of devices to constitute the playback device 1.

  Next, the operation of the playback device 1 will be described.

  The HDD 16 stores compressed video data compressed by the MPEG Long GOP method.

  The CPU 11 controls the south bridge 15 via the north bridge 12 to read out the compressed and encoded stream data from the HDD 16 based on a user operation input supplied from an operation input unit (not shown). Via the north bridge 12, the PCI bus 14, and the PCI bridge 17, it is supplied to the memory 18 for storage, and information indicating the playback speed (including information indicating the playback direction), a decode start command, or a display start A command or the like is written into the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14.

  The CPU 20 determines a schedule for decoding and displaying the compressed and encoded stream data based on the command from the CPU 11 written in the command buffer 31 of the PCI bridge 17. Specifically, the CPU 20 selects the decoders 22 to 24 used for decoding, the input timing of the compression-encoded stream data to the decoders 22 to 24, the decoding timing for each frame, the reference image The setting of the bank position, the allocation of the bank memory at the time of decoding, and the output of the decoded picture, that is, the display timing are determined.

  Then, the CPU 20 controls the PCI bridge 17 so that the compressed and encoded stream data stored in the memory 18 corresponds to one of the decoders 22 to 24 based on the determined schedule. To supply.

  The CPU 20 controls the decoders 22 to 24 to decode the supplied compressed and encoded data. The decoders 22 to 24 decode the supplied compressed and encoded stream data, generate non-compressed SDI data, and output to the selector 25.

  Then, the CPU 20 controls the selector 25 to switch the output of uncompressed SDI data output from the decoders 22 to 24.

  FIG. 2 is a block diagram showing a more detailed configuration of the decoders 22 to 24. As shown in FIG.

  The input processing unit 71 supplies the compression-encoded stream data supplied from the PCI bridge 17 to the memory controller 74 and stores it in the input buffer 75. From the supplied stream data, the start address, The data size, picture header information, Q matrix, etc. are acquired and supplied to the address management table 72.

  The address management table 72 stores information such as the head address in units of pictures, data size, picture header information, and Q matrix supplied from the input processing unit 71 as table information that can be distinguished by table ID, for each picture. To do.

  The elementary stream address determination unit 73 can supply the stream data stored in the input buffer 75 to the decode processing unit 77 on a picture basis based on a control signal supplied from the CPU 20 via the control bus 19. As described above, the head address and picture size information of the corresponding picture are read out from the table information indicated by the predetermined table ID held in the address management table 72 and supplied to the memory controller 74.

  The memory controller 74 controls writing and reading of stream data to the input buffer 75. In other words, the memory controller 74 writes the stream data supplied from the input processing unit 71 to the input buffer 75, and based on the start address and picture size information of the corresponding picture supplied from the elementary stream address determination unit 73. The predetermined picture is read out and supplied to the decoding processing unit 77.

  The input buffer 75 corresponds to a part of the recording area of the memory 41 to the memory 43 shown in FIG. 1 constituted by a storage memory such as SDRAM, and stores stream data under the control of the memory controller 74. .

  The control bus 76 outputs control signals supplied from the CPU 20 via the data bus 19 to an elementary stream address determining unit 73, a decoding processing unit 77, a write image address determining unit 78, a reference image address determining unit 79, and an output. In addition to being supplied to the address determination unit 80, information related to processing executed in the decoders 22 to 24 is supplied to the CPU 20 via the data bus 19.

  The decode processing unit 77 decodes the MPEG video stream read from the input buffer 75 by the memory controller 74 with reference to the reference image supplied from the reference image address determination unit 79 as necessary, and the decoded base. The band (uncompressed) video signal is supplied to the writing image address determination unit 78.

  The writing image address determination unit 78 acquires a control signal supplied from the CPU 20 via the data bus 19 via the control bus 76, and is decoded and supplied by the decoding processing unit 77 based on this control signal. The recording position of the baseband video signal in the video bank memory 82, that is, the bank position to be stored is determined, and the baseband video signal is stored in a predetermined bank position of the video bank memory 82 via the memory controller 81. Let

  The reference picture address determination unit 79 acquires a control signal supplied from the CPU 20 via the data bus 19 via the control bus 76, and based on this control signal, the reference picture address determination unit 79 precedes the P picture in the video bank memory 82. Frame image data held in the bank designated as the reference image bank in the direction (forward), and frame images held in the bank designated as the reference image bank in the forward direction and backward direction (backward) of the B picture Data is read by controlling the memory controller 81 and supplied to the decoding processing unit 77.

  The output address determination unit 80 acquires a control signal supplied from the CPU 20 via the data bus 19 via the control bus 76, and the frame image data held in the video bank memory 82 based on this control signal. The output image, that is, the bank of the frame to be displayed is designated, the memory controller 81 is controlled to read and output.

  The memory controller 81 controls writing and reading of frame images to and from the video bank memory 82. The video bank memory 82 is an 8-bank (8-side) frame image bank memory corresponding to a part of the recording area of the memory 41 to the memory 43 shown in FIG. Based on the control of the memory controller 81, the frame image data of one frame is held in the set bank.

  Next, control processing executed by the CPU 11 will be described with reference to the flowchart of FIG.

  In step S <b> 1, the CPU 11 controls the north bridge 12 and the south bridge 15 to read out from the HDD 16 a plurality of GOPs of the compression-coded stream data designated as stream data to be decoded and output by the user.

  In step S <b> 2, the CPU 11 supplies the read stream data of the plurality of GOPs to the PCI bridge 17 via the PCI bus 14 and transfers it to the memory 18.

  In step S <b> 3, the CPU 11 supplies the command buffer 31 of the PCI bridge 17 with the data transfer completion and the picture information of the picture included in the GOP transferred to the memory 18 via the north bridge 12 and the PCI bus 14. Thus, the CPU 20 is notified of data transfer completion and picture information. The picture information includes, for example, information such as a picture type, header information for each picture, and picture size.

  In step S <b> 4, the CPU 11 receives a notification of completion of preparation from the CPU 20 and the memory 18. Specifically, the CPU 11 reads, via the north bridge 12 and the PCI bus 14, the results for the data transfer completion and picture information notification supplied by the CPU 20 to the result buffer 32 of the PCI bridge 17 via the control bus 19. At the same time, the memory 18 is notified of the end of storage of stream data of a plurality of GOPs via the PCI bridge 17, the PCI bus 14, and the north bridge 12.

  In step S <b> 5, the CPU 11 receives a command to start reproduction output processing by a user from an operation input unit (not shown), and sends a decode start command to the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14. Then, the decoder 22 through the decoder 24 start the decoding process. The decode start command includes display speed information.

  In step S6, the CPU 11 transmits a display start command to the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14, and in step S7, the SDI signal obtained by decoding by the decoder, that is, Then, display of 1 GOP of the baseband image signal is started.

  In step S8, the CPU 11 determines the result of the display start command supplied by the CPU 20 to the result buffer 32 of the PCI bridge 17 via the control bus 19, that is, in step S194 of FIG. The display completion notification for each frame written in 32 is read via the north bridge 12 and the PCI bus 14, and it is always checked which picture display has been completed, thereby detecting the completion of 1GOP display. To do.

  In step S9, the CPU 11 determines whether or not the displayed GOP is the last stream data to be displayed. In step S9, when it is determined that the displayed GOP is the last of the displayed stream data, the process is terminated.

  When it is determined in step S9 that the displayed GOP is not the last of the displayed stream data, in step S10, the CPU 11 determines, for example, stream data based on a signal supplied from an operation input unit (not shown). It is determined whether or not a command accompanying a change in the input stream state, such as an end of playback, a change in stream data being played back, or a command to change the playback speed or direction, is input.

  If it is determined in step S10 that a command accompanying a change in the input stream state has been input from the user, in step S11, the CPU 11 stores the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14. A command corresponding to the user's operation input is transmitted.

  In step S10, when it is determined that the command accompanying the change of the input stream state is not input from the user, or after the process of step S11 is completed, in step S12, the CPU 11 stores the stream data to be displayed on the HDD 16. Determine if it remains. If it is determined in step S12 that there is no stream data to be displayed remaining in the HDD 16, the process returns to step S7 and is transferred to the memory 18, and the process after step S7 is performed on the stream data not yet displayed. Repeated.

  If it is determined in step S12 that stream data to be displayed remains in the HDD 16, in step S13, the CPU 11 controls the north bridge 12 and the south bridge 15 to decode and output the stream data. One GOP following the GOP that has been transferred to the memory 18 is read from the HDD 16.

  In step S <b> 14, the CPU 11 supplies the read 1 GOP stream data to the PCI bridge 17 via the PCI bus 14 and transfers it to the memory 18. In other words, the memory 18 basically holds a predetermined number of GOPs except when the vicinity of the end portion of the stream data to be reproduced is held.

  In step S 15, the CPU 11 supplies the command buffer 31 of the PCI bridge 17 with the data transfer completion and the picture information of the picture included in the GOP transferred to the memory 18 via the north bridge 12 and the PCI bus 14. Thus, the CPU 20 is notified of data transfer completion and picture information. The picture information includes, for example, information such as picture type and picture unit size.

  In step S <b> 16, the CPU 11 receives a notification of completion of preparation from the CPU 20 and the memory 18. Specifically, the CPU 11 reads the result for the data transfer completion and picture information notification supplied from the CPU 20 to the PCI bridge result buffer 32 via the control bus 19 via the north bridge 12 and the PCI bus 14. The memory 18 is notified of the end of storage of stream data of a plurality of GOPs via the PCI bridge 17, the PCI bus 14, and the north bridge 12.

  After the process of step S16 ends, the process proceeds to step S7, and the subsequent processes are repeated.

  By such processing, the CPU 11 can supply a command to the CPU 20, receive a result for the supplied command, and control decoding of stream data and display of the decoded data.

  Here, the case where the decoded data is displayed one GOP at a time has been described. However, when the decoded SDI signal is output to the outside, the CPU 11 causes the CPU 20 to execute the same process. It is needless to say that decoding of stream data and output of the decoded data to the outside can be controlled by receiving a result for the supplied command.

  Then, the CPU 20 controls the decoding process by a plurality of decoders (decoder 22 to decoder 24 in FIG. 1) based on the command supplied from the CPU 11. Specifically, the CPU 20 selects the decoder 22 to decoder 24 used for decoding, in other words, which of the decoder 22 to decoder 24 is the destination of the compressed and encoded stream data. Execute the process to select. Further, the CPU 20 sets the input timing of the compressed encoded stream data to the corresponding one of the decoders 22 to 24, the decoding timing for each picture, the setting of the bank position of the reference image, and the bank memory at the time of decoding. The output of the allocated and decoded pictures, that is, the display timing is determined, and the PCI bridge 17, the decoders 22 to 24, and the selector 25 are controlled based on these timings. Hereinafter, decoding and display output control by the CPU 20 will be described with reference to FIGS.

  The CPU 20 has a plurality of registers and information queues that can hold various types of information in the memory 21 in order to control the decoding processing by the decoders 22 to 24 and the selection processing of the SDI signal output from the selector 25. Has been made. The information queue has a first-in first-out (FIFO) queue structure, a command supplied by the CPU 11, and a picture ID associated with the picture type information and information accompanying the picture ID (for example, time information). Can be stored at a predetermined depth for each use of scheduling of decoding timing and control of decoding and display.

  The CPU 20 controls the decoding and display timing using the information stored in the corresponding information queue. That is, the picture is not queued in the memory 21, but the picture ID is set in each information queue based on the control of the CPU 20, so that the CPU 20 performs arithmetic processing for controlling the timing of decoding and display. Can be executed.

  As an information queue for storing various information, for example, a command queue for storing a command acquired from the command buffer 31 of the PCI bridge 17 via the control bus 19, and a picture ID of an input picture corresponding to a processing queue are used. From the input picture queue stored in the coding order, the display ID information stored in the display order after reordering the picture IDs stored in the input picture queue and rearranging them in the display order, and the picture ID stored in the display order information queue In addition to the I / P picture decoding queue for extracting and storing the P pictures and rearranging them in the decoding order, and the picture IDs set in the I / P picture decoding queue, time information corresponding to these picture IDs is further stored. I / P pic with time information Decoding queue, display order setting queue in which picture IDs are set in display order, and display order setting queue with time information in which time information corresponding to these picture IDs is further accumulated in addition to the picture IDs set in the display order setting queue A display queue that holds a picture ID of a picture to be displayed next is used for various controls by the CPU 20. Details of information stored in each queue, depth of each queue, and processing executed using the information will be described later.

  Next, the process 1 performed for every frame is demonstrated with reference to the flowchart of FIG. This processing routine is repeatedly executed for each frame until the stream data for which display is instructed is completed or until display is instructed.

  In step S31, an input stream state change process which will be described later with reference to FIG. 5 is executed. The input stream state change process is a process for confirming whether or not a new command has been issued from the CPU 11.

  In step S32, decode schedule processing 1 described later with reference to FIG. 6 is executed. In decode schedule processing 1, decode timing is scheduled.

  In step S33, the CPU 20 refers to a time counter that is a counter representing the processing time in units of one frame, so that the processing target is the first frame of the stream data to be reproduced in the decoding order. It is determined whether the frame is one of the sixth frames from the first frame.

  If it is determined in step S33 that the processing target is not one of the sixth frames to the sixth frame of the stream data to be reproduced in the decoding order, in step S34 A one-frame delay display setting process, which will be described later with reference to FIG. 38, is executed. By the one-frame delay display setting process, the display of the baseband frame image decoded and generated in the frame control process 1 of step S35 in the immediately preceding process routine is set.

  If it is determined in step S33 that the processing target is any one of the first to sixth frames of the stream data to be reproduced in the decoding order, or After the process of S34 is completed, a frame control process 1 described later with reference to FIG. 18 is executed in step S35. In the frame control process 1, a frame to be processed is decoded.

  In step S36, the CPU 20 determines whether or not the processing of all frames has been completed. If it is determined in step S36 that all the frames have not been processed, the CPU 20 increments a time counter in units of one frame in step S37.

  After the process of step S37 is completed, the process returns to step S31, and the subsequent processes are repeated. If it is determined in step S36 that all frames have been processed, the process ends.

  In this way, the CPU 20 counts up the time counter for each processing of one frame, schedules decoding according to the playback speed instructed by the user, performs decoding for each frame, and displays the display. Can be set.

  Next, the input stream state change process executed in step S31 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S <b> 51, the CPU 20 checks a command queue that accumulates commands acquired from the command buffer 31 of the PCI bridge 17.

  In step S52, the CPU 20 determines whether or not a new command for changing the input stream state is stored in the command queue, such as a change in playback speed (including the playback direction) or a playback end command. To do.

  If it is determined in step S52 that a new command is stored in the command queue, in step S53, the CPU 20 sets the playback speed and playback direction based on the command stored at the earliest time in the command queue. Change the stream input state based on. If it is determined in step S52 that no new command is stored in the command queue, or after the process of step S53 is completed, the process returns to step S31 in FIG. 4 and proceeds to step S32.

  By such processing, the command stored at the earliest time in the command queue for accumulating commands acquired from the command buffer 31 of the PCI bridge 17 is referred to, and the stream input state is changed based on the commands.

  Next, the decode schedule process 1 executed in step S32 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S71, the CPU 20 refers to the input picture queue and determines whether or not the input picture queue is empty. The input picture queue is an information queue set in an input process (step S72) described later, and an input picture for which a decoding schedule is determined next and a picture ID of a picture necessary for the scheduling are set.

  As shown in FIG. 7, when the stream data handled by the playback apparatus 1 is MPEG LONG GOP stream data in which 1 GOP is composed of 15 pictures, a decoder 22 that performs decoding processing for each 15 pictures equivalent to 1 GOP. Each of the decoders 24 has 13 pictures excluding the two B pictures that are headed in the display order in each GOP, and, in the case of playback in the forward direction, is headed in the display order in the preceding GOP. In the case of the IBB 3 pictures in the reverse direction, 16 pictures including the IBB 3 pictures that are the head in the display order are supplied in the GOP behind them.

  With reference to FIG. 8, a description will be given of the decoding unit that each of the decoders 22 to 24 takes charge of. In FIG. 8, the arrangement of pictures supplied to the decoders 22 to 24 is shown in display order. In the playback apparatus 1, the decoding process is performed in one of the decoders 22 to 24 for each 1 GOP (15 pictures). As described above, each of the decoders 22 to 24 has a decoding process. Sixteen pictures including 13 pictures excluding the two B pictures that are first in the display order in 1 GOP and three pictures from the top in the display order in the preceding or subsequent GOP are supplied. Therefore, when the playback direction is the forward direction, as shown in FIG. 8A, the first decoder among the decoders 22 to 24 receives the 13 pictures excluding the first two B pictures of the first GOP and the second picture. The first three pictures of the first GOP are supplied, and the second decoder is supplied with the 13 pictures excluding the first two B pictures of the second GOP and the first three pictures of the third GOP. 13 pictures excluding the top two B pictures of the third GOP and the top three pictures of the fourth GOP are supplied to the decoder. Also, when the playback direction is the reverse direction, as shown in FIG. 8B, the first decoder among the decoders 22 to 24, the 13 pictures excluding the first two B pictures of the second GOP, and the third picture The first three pictures of the first GOP are supplied, and 13 pictures excluding the first two B pictures of the first GOP and the first three pictures of the second GOP are supplied to the second decoder.

  In the input picture queue, a picture ID of an input picture that is waiting for a decoding timing schedule among pictures input to the decoder 22 to decoder 24 and a picture necessary for the scheduling is set. That is, in the input picture queue, 18 picture IDs of 15 pictures of 1 GOP and 3 pictures of IBB at the head of the GOP before or after the GOP stream data are held in the LONG GOP stream data.

  In FIG. 9A, the picture IDs of 15 pictures of the first GOP and 3 pictures of the first IBB of the second GOP after the stream data of the MPEG LONG GOP are input for reproduction in the forward direction. FIG. 9B shows a state in which the picture queue is set, and in order to reproduce in the reverse direction, among the LONG GOP stream data of MPEG, the 15 pictures of the second GOP are preceded in the reverse display order. The picture ID of the three pictures of the first IBB of the third GOP to be displayed is set in the input picture queue.

  If it is determined in step S71 that the input picture queue is not empty, the process returns to step S32 in FIG. 4 and proceeds to step S33. In other words, the decoding schedule processing is executed collectively for each processing unit of 16 pictures of 13 pictures set from a position shifted by 2 pictures from the 15 LONG GOP pictures and the next three pictures.

  If it is determined in step S71 that the input picture queue is empty, in step S72, an input process to be described later is executed using the flowchart of FIG.

  In step S73, based on the value of the register indicating the decoder that supplies the next data, the CPU 20 determines whether the display order setting queue with time information set corresponding to the decoder that receives the next data is empty. Judge whether or not. The display order setting queue with time information is a queue that is set in the schedule determination processing with time information in step S80 described later. Each of the plurality of decoders (in the case described with reference to FIG. Each of 24 three decoders). Details of the display order setting queue with time information will be described later with reference to the flowchart of FIG.

  In step S73, when it is determined that the display order setting queue with time information corresponding to the decoder to which data is next supplied is not empty, that is, for each scheduled picture corresponding to 1 GOP, decoding processing is performed for each frame. Alternatively, when the display process is being executed, the process returns to step S32 in FIG. 4 and proceeds to step S33.

  In step S73, when it is determined that the display order setting queue with time information corresponding to the decoder to which data is next supplied is empty, in step S74, the CPU 20 executes reorder processing. The reorder process is a process of replacing the picture IDs corresponding to 18 pictures arranged in the coding order set in the input picture queue with the display order and setting them in the display order information queue.

  Therefore, when the playback direction is the forward direction, as shown in FIG. 10A, the picture ID set in the input picture queue described with reference to FIG. 9A is rearranged in the display order in the display order information queue. When the playback direction is the reverse direction, the picture ID set in the input picture queue described with reference to FIG. 9B is displayed in the display order information queue as shown in FIG. 10B. Sorted to be set.

  In step S74, when the reorder process is executed and the picture ID is set in the display order information queue, all the picture IDs queued in the input picture queue are output, and the input picture queue becomes empty. In other words, the case where the input picture queue is determined to be empty in the above-described step S71 is a case where the reorder processing for the picture ID queued in the input picture queue is performed, and the input picture queue is not empty. In the case where it is determined that the display order setting queue with time information corresponding to the decoder that receives the next data supply is executed after the input process is executed in step S72 of the decode schedule process 1 executed before this process. This is a case where the reorder process is not executed in step S74 because it is not empty.

  In step S75, the CPU 20 refers to the display order information queue set in step S74, and sets the picture IDs of the I and P pictures in the GOP to be decoded in the I / P picture decoding queue in the decoding order. The I / P picture decoding queue is a queue for setting the picture IDs of the I picture and the P picture that are decoded prior to the B picture in decoding order.

  FIG. 11 shows an I / P picture decoding queue in forward reproduction and backward reproduction. As shown in FIG. 11A, the I / P picture decoding queue in the case of forward reproduction includes the I picture and the P picture among the picture IDs set in the display order information queue described with reference to FIG. 10A. The picture IDs of the corresponding six pictures are set, and the I / P picture decoding queue in the case of reverse playback is set to the display order information queue described with reference to FIG. 10B as shown in FIG. 11B. Among the picture IDs, picture IDs of six pictures corresponding to the I picture and the P picture are set.

  In step S76, the CPU 20 designates a bank position for storing the I picture and the P picture and a reference picture bank in the decoding of the P picture. The I picture and the P picture use six fixed banks among the eight banks in the video bank memory 82 of FIG.

  By decoding the I picture and P picture (also called anchor frame) first and fixing the bank position held after decoding, playback from any picture, such as forward direction, backward direction, heading, etc. It can be done immediately. Also, by decoding the I picture and P picture first, the shorter the processing time of the six I pictures and P pictures that are decoded first, the more the user can start playback or change the playback speed or playback direction. The time from the instruction to the display start reflecting the instruction can be shortened regardless of the position in the GOP of the display start frame, or the display time when displaying an arbitrary picture by scrub playback can be shortened. As a result, the performance during high-speed playback is improved.

  In step S77, the CPU 20 designates the position of the reference image bank in the decoding of the B picture, based on the bank position where the I picture and the P picture are stored, respectively, designated by the process in step S76. Note that the bank position where the B picture is stored is specified in the frame control process 1 described later.

  In step S78, the CPU 20 sets a display order setting queue.

  FIG. 12 shows a display order setting queue in forward reproduction and reverse reproduction. As shown in FIG. 12A, the display order setting queue in the case of forward playback is the first two B of the 18 picture IDs queued in the display order information queue described with reference to FIG. 10A. Of the pictures and 15 picture IDs excluding the last I picture, that is, among the pictures supplied to one of the decoders 22 to 24 in the case of forward reproduction described with reference to FIG. 8A The picture IDs of 15 pictures excluding the I picture are set in the display order.

  As shown in FIG. 12B, the display order setting queue in the case of reverse playback is the first two of the 18 picture IDs queued in the display order information queue described with reference to FIG. 10B. 15 picture IDs excluding one B picture and the last I picture, that is, among pictures supplied to one of the decoders 22 to 24 in the case of backward reproduction described with reference to FIG. 8B The picture IDs of 15 pictures excluding the last I picture are set in the actual display order.

  When the display order setting queue is set in step S78, all the picture IDs queued in the display order information queue are output, and the display order information queue becomes empty.

  In step S79, a display phase determination process to be described later is executed using the flowchart of FIG. The display phase determination process is a process for determining a difference in timing between the start of decoding and the start of display in a processing unit of 15 frames + 1 frame equivalent to 1 GOP.

  In step S80, a schedule determination process with time information, which will be described later using the flowchart of FIG. 17, is executed. The schedule determination process with time information is a process of executing decoding scheduling and setting time information in association with a picture ID in a predetermined information queue in order to control the decoding timing for each frame.

  Decoding and display timings are scheduled by the processing in steps S79 and S80. Specifically, for example, when the display head is an I picture or a P picture, for example, when the playback direction is the normal direction and playback is at normal speed, as shown in FIG. Is decoded, the B picture is decoded, and the display start timing is shifted by 6 pictures from the decoding start, so that the decoding timing and display timing of the B picture are shifted by one frame. The timing schedule is performed. Also, when the playback direction is the reverse direction, in other words, when the display head is a B picture, such as when the speed setting is a negative value, as shown in FIG. After the picture is decoded, the B picture is decoded, and the display start timing is shifted by 7 pictures from the decoding start, so that the B picture decoding timing and the display timing are shifted by one frame. The display timing is scheduled.

  In step S81, the CPU 20 executes a process of switching the setting of a decoder that supplies data to be decoded next. Specifically, the CPU 20 has one less register value indicating the decoder that supplies the next data than the number of decoders (in the reproducing apparatus 1 described with reference to FIG. 1, three decoders 22 to 24). When the value is equal to 2 (2 in the reproducing apparatus 1 described with reference to FIG. 1), the register value is set to 0. When the register value is 2 or less than the number of decoders, the register value is incremented by 1. After the process of step S81 is completed, the process returns to step S32 in FIG. 4 and proceeds to step S33.

  By such processing, the decoding and display timing is scheduled.

  Next, the input process executed in step S72 of FIG. 6 will be described with reference to the flowchart of FIG.

  In step S101, the CPU 20 displays the display speed information included in the decode start command transmitted from the CPU 11 to the command buffer 31 in step S5 of the control process described with reference to FIG. 3, or the control described with reference to FIG. The speed setting value is acquired from the command corresponding to the user's operation input transmitted from the CPU 11 to the command buffer 31 in step S11 of the process, and stored in the memory 21. When the speed setting value is a positive value, the playback process may be forward playback, and when the speed setting value is a negative value, the playback process may be backward playback.

  For example, when the speed set value is 1, normal playback is assumed. When the speed set value is 1 or more, high speed playback is assumed. When the speed set value is a positive value less than 1. When the speed setting value is −1, it is assumed that the playback speed is normal, and when the speed setting value is −1 or less, the playback speed is high speed. When the speed setting value is a negative value less than the absolute value 1, it can be assumed that low-speed backward reproduction is performed.

  In step S102, the CPU 20 determines whether the process to be executed is a positive direction reproduction process based on whether the speed setting value acquired in step S101 is a positive value or a negative value. .

  If it is determined in step S102 that the playback process is in the forward direction, in step S103, the CPU 20 determines the 1 GOP including 13 frames from the top of the 15 frames to be decoded next, and the I and B of the next GOP. , B picture IDs are set in the input picture queue described with reference to FIG. 9A.

  If it is determined in step S102 that the playback process is not forward, that is, reverse playback, in step S104, the CPU 20 includes 1 GOP including 13 frames from the back of the 15 frames to be decoded next. Then, the picture IDs of the previous GOP I, B, and B pictures are set in the input picture queue described with reference to FIG. 9B.

  After the processing of step S103 or step S104 is completed, in step S105, the CPU 20 controls the PCI bridge 17 to set the input picture queue and the value of the register indicating the decoder that supplies the next data (reproduced). The first GOP of the stream is a value determined by the initial setting, and the second and subsequent GOPs are values determined by the process of step S81 in FIG. 6). Of the stream data, the transfer of the 16-frame compressed image data described with reference to FIG. 8 to a predetermined decoder among the decoders 22 to 24 is controlled.

  The input processing unit 71 of the decoders 22 to 24 supplies the supplied 16-frame data to the memory controller 74 and stores it in the input buffer 75, and also stores it in the address management table 72 as the start address and data size in units of pictures. , Information such as picture header information and Q matrix is supplied, and each picture is held as table information distinguishable by table ID.

  In step S <b> 106, the CPU 20 supplies a result indicating the end of the transfer processing of the stream equivalent to 1 GOP to the predetermined decoder among the decoders 22 to 24 to the result buffer 32 of the PCI bridge 17 via the control bus 19. Thus, the CPU 11 is notified of the end of the stream transfer process, and the process returns to step S72 in FIG. 6 and proceeds to step S73.

  By such processing, 16 frames of data serving as the decoding processing unit described with reference to FIG. 8 is supplied to the decoders 22 to 24.

  Next, the display phase determination process for setting the phase for delaying the display start timing with respect to the decode start timing, executed in step S79 of FIG. 6, will be described with reference to the flowchart of FIG.

  In step S131, the CPU 20 stores information on the number of pictures to be displayed, which is set in the display order setting queue described with reference to FIG. 12, in the display picture number register. In FIG. 12, since the picture IDs for 15 pictures are set in the display order setting queue, the value 15 is stored in the display picture number register.

  In step S132, the CPU 20 holds the total number of decoded I and P pictures held in the I / P picture decoding queue described with reference to FIG. 11 in the I / P picture number register. In FIG. 11, since picture IDs for six pictures are set in the I / P picture decoding queue, the value 6 is stored in the I / P picture number register.

  In step S133, the CPU 20 determines whether or not the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is a B picture. This is synonymous with determining whether the reproduction direction is the forward direction or the reverse direction when calculating the phase shift amount in the normal speed reproduction or the normal speed reproduction in the reverse direction. After the thinning process 1 described later is executed, even if the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is a B picture, depending on the playback speed setting value, The playback direction may be the forward direction or the reverse direction.

  If it is determined in step S133 that the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is a B picture, in step S134, the CPU 20 decodes the I picture and P picture to be decoded. The number obtained by adding 1 to the total number corresponds to the picture ID held in the display order setting queue with respect to the decoding start timing of the I picture and P picture corresponding to the picture ID held in the I / P picture decoding queue. A temporal phase shift amount disp_phase of the picture display start timing is set.

  For example, as shown in FIG. 14 described above, when the playback speed is −1, the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is B picture. After the I picture and P picture are decoded, the B picture is decoded so that the display start timing is shifted by 7 pictures from the decoding start, and the B picture decoding timing and the display timing are shifted by one frame. Is done.

  When it is determined in step S133 that the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is not a B picture, in step S135, the CPU 20 determines the decoded I picture and P picture. Of the display start timing of the picture corresponding to the picture ID held in the display order setting queue with respect to the decode timing of the I picture and P picture corresponding to the picture ID held in the I / P picture decode queue It is assumed that the amount of phase shift is disp_phase.

  For example, as shown in FIG. 13 described above, when the playback speed is 1 time, the picture type of the picture corresponding to the picture ID set at the head of the display order setting queue is I picture, and in B picture Therefore, after the I picture and P picture are first decoded, the display start timing is shifted by 6 pictures from the start of decoding, so that the B picture decode timing and the display timing are shifted by one frame. B picture is decoded.

  After the processing of step S134 or step S135 is completed, in step S136, the CPU 20 stores the display phase shift amount disp_phase determined in step S134 or step S135 in an internal register.

  In step S137, the CPU 20 determines whether or not the GOP being processed is a display start GOP (including a playback start portion at a corresponding speed when the playback speed is changed).

  If it is determined in step S137 that the GOP being processed is not the display start GOP, in step S138, the CPU 20 determines the previous processing from the display phase shift amount disp_phase determined in step S134 or step S135, that is, The display phase shift amount prev_disp_phase in the GOP displayed immediately before is subtracted, and the result is stored in the internal register as the shift amount correction value disp_zero, and the display phase shift amount determined in step S134 or step S135. By substituting disp_phase for the display phase shift amount prev_disp_phase in the GOP displayed immediately before, the process returns to step S79 in FIG. 6 and proceeds to step S80.

  If it is determined in step S137 that the GOP being processed is the display start GOP, in step S139, the CPU 20 sets an initial value 0 as the shift amount correction value disp_zero and stores it in the internal register. Then, the process returns to step S79 in FIG. 6 and proceeds to step S80.

  By such processing, the phase for delaying the display start timing with respect to the decode start timing is determined.

  Next, the schedule determination process with time information executed in step S80 of FIG. 6 will be described with reference to the flowchart of FIG.

  In step S161, the CPU 20 determines whether the processing target is a decoding processing unit corresponding to the first 1 GOP after the input stream state is changed. Since the picture type is changed before and after the thinning out in at least the second and subsequent decoding processing units, in step S161, it is determined that the processing target is the decoding processing unit corresponding to the first 1 GOP. The processing proceeds to step S166 described later.

  If it is determined in step S161 that the processing target is not a decoding processing unit corresponding to the first 1 GOP, in step S162, the CPU 20 changes the leading picture from an I picture or a P picture to a B picture before and after thinning. Determine whether or not.

  If it is determined in step S162 that the leading picture has been changed from the I picture or the P picture to the B picture before and after the thinning, in step S163, the CPU 20 sets the phase adjustment value to 1, and the process will be described later. The process proceeds to S167.

  If it is determined in step S162 that the leading picture has not been changed from the I picture or the P picture to the B picture before and after the thinning, in step S164, the CPU 20 determines that the leading picture is the I or P from the B picture before and after the thinning. It is determined whether or not the picture has been changed.

  If it is determined in step S164 that the leading picture has been changed from the B picture to the I or P picture before and after the thinning, in step S165, the CPU 20 sets the phase adjustment value to −1, and the process will be described later. The process proceeds to S167.

  If it is determined in step S161 that the processing target is the first decoding processing unit, or in step S164, it is determined that the leading picture has not been changed from a B picture to an I or P picture before and after thinning. In this case, in step S166, the CPU 20 sets the phase adjustment value to 0.

  After the process of step S163, step S165, or step S166 is completed, in step S167, the CPU 20 starts with the 16 pictures in the decoding process unit to be decoded by any one of the decoders 22 to 24. The value of the decoding start time information time_base indicating the timing at which the frame is decoded is prev_time_base, which is the decoding start time information of the previous decoding processing unit, disp_zero indicating the display phase shift amount correction value, and thinning processing 1 described later Is calculated using the time information adjustment value added_count calculated in step S1 and the phase adjustment value obtained by the processing in steps S161 to S166 (formula (1)).

  Decoding start time information time_base = previous GOP decoding start time information prev_time_base−display phase shift amount correction value disp_zero + time information adjustment value added_count + phase adjustment value (1)

  Note that, when the calculation process of Expression (1) is executed for the display start GOP, prev_time_base indicating the decoding start time information of the previous GOP and the time information adjustment value added_count calculated in the previous GOP thinning process 1 Is calculated as 0.

  In step S168, the CPU 20 sets an I / P picture decoding queue with time information corresponding to the decoder to which data is next supplied.

  The I / P picture decoding queue with time information is associated with the picture ID set in the I / P picture decoding queue described with reference to FIG. 11, and information on the decoding start time time_base of the picture decoded at the head, In addition, the count value of the time counter in units of one frame is set, and is provided corresponding to each decoder (here, each of the decoder 22 to decoder 24) provided in the playback device 1. Yes.

  Specifically, the CPU 20 refers to the value of the register indicating the decoder that supplies the next data, and sets the I / P picture decode queue with time information corresponding to the decoder to which the next data is supplied. The CPU 20 uses the information of the decoding start time information time_base described above as information indicating the timing at which the frame corresponding to the head picture ID among the picture IDs queued in the I / P picture decoding queue is decoded. As information indicating the timing at which each frame corresponding to each picture ID is decoded, the count value of the time counter in units of one frame is used.

  In step S168, when the I / P picture decoding queue with time information is set, all the picture IDs queued in the I / P picture decoding queue are output, and the I / P picture decoding queue becomes empty.

  In step S169, the CPU 20 sets a display order setting queue with time information corresponding to the decoder to which data is next supplied.

  The display order setting queue with time information is associated with the picture ID set in the display order setting queue described with reference to FIG. 12, and the shift amount of the display timing phase with respect to the decoding start time of the picture displayed at the head A value obtained by subtracting 1 from the above and a count value of a time counter in units of one frame are set for each decoder provided in the reproducing apparatus 1 (here, each of the decoders 22 to 24). It is provided corresponding to.

  Specifically, the CPU 20 refers to the value of the register indicating the decoder that supplies the next data, and sets the display order setting queue with time information corresponding to the decoder to which the next data is supplied. The CPU 20 displays the display timing of the frame corresponding to the first frame in the actual display order among the picture IDs queued in the display order setting queue, and the phase shift amount determined in the display phase determination process described above A value obtained by subtracting 1 from disp_phase is used as reference time information in accordance with the decoding timing of the B picture, and information indicating the timing at which each frame corresponding to each picture ID is decoded is in units of one frame. The count value of the time counter is used.

  When the display order setting queue with time information is set in step S169, all the picture IDs queued in the display order setting queue are output, and the display order setting queue becomes empty.

  In step S170, the CPU 20 adds the value obtained by adding the value held in the display picture number register in step S131 of FIG. 16 described above to the decoding start time information time_base as the decoding start time information prev_time_base of the previous GOP. The process is saved, and the process returns to step S80 in FIG. 6 and proceeds to step S81.

  By such processing, the decoding processing timing for 16 frames as a decoding processing unit is set.

  16 and 17, the decoding phase and the display phase are based on the number of I pictures and P pictures, the number of pictures to be displayed, and whether or not the picture to be displayed at the top is a B picture. And is set as time information. As a result, the speed is dynamically increased by following the change in the number of pictures that are decoded and output in each decoder, which are generated when high-speed playback in the forward and reverse directions is performed using a plurality of decoders. It is possible to change and display continuously decoded images. In addition, even when a change in playback speed is commanded and the thinning interval is changed from a picture at an arbitrary position, the playback speed can be adjusted within the supported speed range by reflecting the increase or decrease in the number to be displayed. It is possible to change the speed continuously by changing the frame unit.

  The decode schedule process 1 is executed in step S32 of FIG. 4 by the process described with reference to FIGS.

  Then, in step S33 of FIG. 4, it is determined whether the frame is any frame from the first frame to the sixth frame, and is determined to be any frame from the first frame to the sixth frame. In this case, the one-frame delay display setting process in step S34 is skipped, and the frame control process 1 is executed in step S35.

  Next, the frame control process 1 executed in step S35 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S191, the CPU 20 refers to the time management counter, which is a counter for managing the timing of each process executed in the playback device 1, and the I / P picture decode queue with time information, and the display time has passed. It is determined whether there is stream data. If it is determined in step S191 that there is stream data whose display time has passed, the process proceeds to step S197 described later.

  If it is determined in step S191 that there is no stream data whose display time has passed, an I picture and P picture decoding process, which will be described later with reference to FIG. 19, is executed in step S192.

  In step S193, a B picture decoding process to be described later with reference to FIG. 20 is executed.

  In step S194, the CPU 20 notifies the display picture information to the CPU 11. Specifically, the CPU 20 writes display picture information as a result for the display start command transmitted from the CPU 11 in step S6 of FIG. 3 to the result buffer 32 of the PCI bridge 17 via the control bus 19. The display picture information is notified to the CPU 11. The CPU 11 can know which picture of which GOP the picture to be displayed by referring to the display picture information written in the result buffer 32 of the PCI bridge 17.

  In step S195, the CPU 20 increments the time management counter.

  In step S196, a thinning process 1 described later with reference to FIG. 23 is executed, and the process returns to step S35 in FIG. 4 and proceeds to step S36.

  If it is determined in step S191 that there is stream data whose display time has passed, underflow processing described later with reference to FIG. 35 is executed in step S197, and the processing returns to step S35 in FIG. The process proceeds to step S36.

  If display is not delayed by such processing, decoding for one frame is executed based on the set decoding schedule, display picture information is notified to the CPU 11, and thinning-out processing 1 is executed. When the display is delayed, underflow processing described later is executed.

  Next, the I picture and P picture decoding processing executed in step S192 in FIG. 18 will be described with reference to the flowchart in FIG.

  In step S221, the CPU 20 determines whether the value of the time management counter matches the time information associated with the picture ID of the next decoded picture set in the I / P picture decoding queue with time information. Judge whether or not. If it is determined in step S221 that the value of the time management counter does not match the time information set in the I / P picture decoding queue with time information, the process returns to step S192 in FIG. Proceed to

  If it is determined in step S221 that the value of the time management counter matches the time information set in the I / P picture decoding queue with time information, in step S222, the CPU 20 is set as a decoder that performs decoding. Any one of the decoders 22 to 24 is controlled via the control bus 19 to decode the I picture or P picture, and the decode command is executed from the I / P picture decode queue with time information. The picture ID corresponding to the selected picture is deleted.

  Specifically, the CPU 20 refers to the value held in the register indicating the decoder that supplies the next data, and the elementary stream address of the decoder 22 to the decoder 24 that is set as the decoder that performs decoding. The determining unit 73 is controlled to cause the memory controller 74 to read out the picture data corresponding to the picture ID set in the I / P picture decoding queue with time information from the input buffer 75 and to the decoding processing unit 77. Supply.

  When the picture to be decoded is an I picture, the CPU 20 controls the decoding processing unit 77 to decode the I picture supplied from the memory controller 74 and also controls the writing image address determining unit 78 to perform decoding. The frame data is supplied to the memory controller 81 and stored in the bank designated for storing the I picture in step S76 of FIG. 6 in the video bank memory 82. Further, when the picture to be decoded is a P picture, the CPU 20 controls the reference picture address determination unit 79, and based on the reference bank position of the P picture set in step S76 in FIG. The reference picture stored in the video bank memory 82 is read out and supplied to the decoding processing unit 77, and the decoding processing unit 77 is controlled to decode and write the P picture supplied from the memory controller 74. The image address determination unit 78 is controlled to supply the decoded frame data to the memory controller 81 and stored in the bank designated for storing the P picture in the step S76 of FIG. 6 in the video bank memory 82. .

  After the process of step S222 ends, the process returns to step S192 of FIG. 18 and proceeds to step S193.

  Through such processing, an I picture or a P picture is decoded based on the set schedule.

  Next, the B picture decoding process executed in step S193 in FIG. 18 will be described with reference to the flowchart in FIG.

  In step S241, the CPU 20 determines whether or not the setting of the time management counter matches the time information corresponding to the current first picture ID set in the display order setting queue with time information. In the display phase determination process described above, the time information set in the display order setting queue with time information indicates the display timing of the frame corresponding to the first frame in the actual display order among the 15 frames at the time of scheduling. A value obtained by subtracting 1 from the determined phase shift amount disp_phase (reference time information in accordance with the decoding timing of the B picture) or each picture ID other than the first frame in the actual display order among 15 frames. The count value of the corresponding time counter in units of one frame. If it is determined in step S241 that the setting of the time management counter does not match the time information set in the display order setting queue with time information, the process returns to step S193 in FIG. 18 and proceeds to step S194.

  In step S241, when it is determined that the setting of the time management counter matches the time information set in the display order setting queue with time information, in step S242, the CPU 20 determines that it matches the time information. It is determined whether or not the picture ID corresponds to the B picture.

  In step S242, when it is determined that the picture ID corresponding to the B picture is determined to match the time information, in step S243, the CPU 20 sets the decoders 22 to 22 that are set as decoders that perform decoding. Any one of the decoders 24 is controlled via the control bus 19 to decode the B picture indicated by the picture ID.

  Specifically, the CPU 20 refers to the value held in the register indicating the decoder that supplies the next data, and the elementary stream address of the decoder 22 to the decoder 24 that is set as the decoder that performs decoding. The determination unit 73 is controlled so that the picture data corresponding to the picture ID set in the display order setting queue with time information is read from the input buffer 75 by the memory controller 74 and supplied to the decoding processing unit 77. . Then, the CPU 20 controls the reference picture address determination unit 79, and the reference stored in the video bank memory 82 by the memory controller 81 based on the reference bank position of the B picture set in step S77 in FIG. The image is read out and supplied to the decoding processing unit 77, and the decoding processing unit 77 is controlled to decode the B picture supplied from the memory controller 74.

  In step S244, the CPU 20 sets a bank position for storing the B picture. That is, the CPU 20 controls the write image address determination unit 78 so that B pictures are alternately stored in two banks of the video bank memory 82 that are not designated for storing I pictures or P pictures. To do. The CPU 20 controls the writing image address determining unit 78 to supply the frame data decoded by the decoding processing unit 77 to the memory controller 81, and the decoded frame data at the set bank position in the video bank memory 82. Remember me.

  In step S242, when it is determined that the picture ID corresponding to the time information is not the picture ID corresponding to the B picture, or after the process of step S244 is completed, the CPU 20 adds the time information. The current top picture ID set in the display order setting queue is set in the display queue. The display queue is a queue of depth 1 that holds only one picture ID.

  Specifically, when the CPU 20 determines in step S242 that it is not the picture ID corresponding to the B picture that is determined to match the time information, in step S222 of FIG. 19 described above, the time information is added. Since decoding of the I picture or P picture corresponding to the current first picture ID set in the display order setting queue is controlled, the CPU 20 sets the picture ID corresponding to the I picture or P picture in the display queue. To do. In step S242, if it is determined that the picture ID corresponding to the B picture corresponds to the time information, and decoding of the B picture is controlled in step S243, the CPU 20 adds the time information. The current head picture ID set in the display order setting queue, that is, the picture ID corresponding to the decoded B picture is set in the display queue.

  The current top picture ID set in the display order setting queue with time information is output from the display order setting queue with time information and displayed next to the picture corresponding to the picture ID set in the display queue. The picture ID corresponding to the picture is the head of the display order setting queue with time information, or the display setting queue with time information is empty. After the process of step S245 ends, the process returns to step S193 in FIG. 18 and proceeds to step S194.

  In this way, decoding is executed based on the time information set in the I / P picture decoding queue with time information and the display order setting queue with time information. In the case of forward reproduction, as shown in FIG. 21, the I picture and P picture are decoded based on the time information set in the I / P picture decoding queue with time information, and the display order with time information is set. The B picture is decoded based on the time information set in the queue. In the case of reverse playback, as shown in FIG. 22, the I picture and P picture are decoded based on the time information set in the I / P picture decoding queue with time information, and the display with time information is displayed. Based on the time information set in the order setting queue, the B picture is decoded.

  In addition, as shown in FIGS. 21 and 22, the decoding timing of the B picture is determined by the 1-frame delay display setting process described later, regardless of whether the playback is in the forward direction or the backward direction. The decoding timing is shifted by one frame from the display timing.

  21 and 22 show the decode timing and the display timing in the case of 1 × speed and −1 × speed, respectively, but when high-speed playback is executed, time information is obtained by thinning-out processing 1 described later. The setting of the added display order setting queue is changed, and in the next processing routine, decoding is executed based on the setting of the display order setting queue with time information after the thinning-out process 1. When high-speed playback is executed, all B pictures are not decoded but are decoded by being thinned out. However, decoding of I pictures and P pictures also applies to all pictures when high-speed playback is executed. Executed in

  Next, with reference to the flowchart of FIG. 23, the thinning process 1 executed in step S195 of FIG. 18 will be described.

  In step S271, the CPU 20 uses the stream input state set in the input stream state change process described with reference to FIG. 5, and the playback speed based on the user setting is a fast playback in the forward direction or the reverse direction. It is determined whether or not. If it is determined in step S271 that the playback is not at high speed, the process returns to step S196 in FIG. 18 and proceeds to step S36 in FIG.

  If it is determined in step S271 that high-speed playback is being performed, in step S272, the CPU 20 determines whether or not the frame being processed is the first frame of the first GOP after the speed setting has been changed. .

  If it is determined in step S272 that the frame being processed is the first frame of the first GOP after the input stream state has been changed, in step S273, the CPU 20 determines the thinning cycle based on the speed setting value. Is stored in a register.

  Specifically, for example, when reproduction is performed at 2 × speed or −2 × speed, the CPU 20 stores the thinning cycle in the register as ½, and when reproduction is performed at 3 × speed or −3 × speed, Is saved in the register as 1/3.

  In step S274, the CPU 20 resets a frame counter that counts the number of frames in the thinning process 1 regardless of the decoding process unit.

  In step S272, if it is determined that the frame being processed is not the first frame of the first GOP after the input stream state is changed, or after the processing of step S274 is completed, the CPU 20 determines in step S275. Whether or not all the display order setting queues with time information have been confirmed based on whether or not the confirmed flag is set in association with the picture ID held in the display order setting queue with time information. Determine whether. The confirmed flag is a flag that is set in the display order setting queue with time information by the processing in step S280 described later. If it is determined in step S275 that all display order setting queues with time information have been confirmed, the process returns to step S196 in FIG. 18 and proceeds to step S36 in FIG.

  If it is determined in step S275 that all the display order setting queues with time information have not been confirmed, in other words, it is determined that there is still a picture ID for which the confirmed flag is not set in the display order setting queue with time information. In step S276, the CPU 20 increments the frame counter by one.

  In step S277, as a result of determining the thinning cycle, the CPU 20 refers to the thinning cycle held in the register and the value of the frame counter, and determines whether or not the frame indicated by the frame counter is displayed. Specifically, when the thinning cycle is ½, the CPU 20 performs display if the value of the frame counter that counts the number of frames is 2n (n is a positive integer), otherwise, When the display is not performed or the thinning cycle is 1/3, if the value of the frame counter that counts the number of frames is 3n (n is a positive integer), the display is performed. Otherwise, the display is performed. Do not display. If it is determined in step S277 that display is to be performed, that is, if it is determined that the frame is not thinned, the process proceeds to step S280 described later.

  If it is determined in step S277 that it is not displayed, that is, if it is determined that the frame is to be thinned out, in step S278, the CPU 20 sets the picture ID corresponding to the processing target frame to the display order with time information. Either delete from the queue, or associate a flag indicating non-display with the corresponding picture ID in the display order setting queue with time information.

  In step S279, the time information resetting process described with reference to FIG. 24 is executed.

  When it is determined in step S277 that the frame indicated by the frame counter is displayed, or after the processing of step S279 is completed, in step S280, the CPU 20 indicates in the frame counter of the display order setting queue with time information. The confirmed flag is set in association with the picture ID corresponding to the frame to be processed, the process returns to step S275, and the subsequent processes are repeated.

  By such processing, the picture ID of a frame that is not displayed is deleted from the display order setting queue with time information, or is not displayed with respect to the corresponding picture ID in the display order setting queue with time information. Are associated with each other. The B picture decoding process and the one-frame delay display setting process (described later) are executed with reference to the display order setting queue with time information. Since the setting of the display order setting queue with time information is updated based on the setting of high-speed playback, the B picture decoded after this processing routine is only displayed (the B picture to be thinned is decoded) The I picture or P picture to be thinned out is not decoded but is not displayed.

  Further, the frame counter is continuously incremented without being reset regardless of the GOP until the speed setting is changed, that is, until the input stream state is changed. For example, 1 GOP is composed of 15 frames. If the denominator of the decimation period becomes a value that cannot divide the number of frames constituting 1 GOP, such as 2 × speed, 4 × speed, −2 × speed, −4 × speed, etc. Even when the position of a picture that is not changed is changed, it is possible to easily determine whether or not display is performed based on the thinning cycle by using the value of the frame counter indicating the order of frames in the input stream. it can.

  In this way, the B picture is thinned out by the stream input to the decoder, and the I picture and the P picture are thinned out at equal intervals by stopping the display after decoding, so that the dynamic change of the speed can be followed. It is possible to perform high-speed playback. Since the I picture and the P picture may be used as reference images from other pictures at the time of decoding, this method performs high-speed playback by thinning out at equal intervals while reducing the number of faces of the bank memory as much as possible. Therefore, it is an effective method.

  Thus, when two decoders are used while thinning out at equal intervals, the speed can be set in a range of -3 to 3 times, and when three decoders are used, -6 to 6 times. In addition, the speed can be set within the range of the above, and the high-speed reproduction can be realized by applying the same control of the thinning process 1 to two or more decoders.

  Next, the time information resetting process executed in step S279 of FIG. 23 will be described with reference to the flowchart of FIG.

  In step S <b> 301, the CPU 20 detects the number of picture changes (deletion number or addition number) by the thinning-out process 1 generated by changing the speed setting value.

  In step S302, the CPU 20 sets the number of picture changes (the number of deletions or the number of additions) as the time information adjustment value added_count.

  In step S303, the CPU 20 resets the time information in the display order setting queue with time information so as to be continuous, and the process returns to step S279 in FIG. 23 and proceeds to step S280.

  By such processing, the setting of the display order setting queue with time information after thinning is changed corresponding to the set value of the playback speed, and the display order setting queue with changed time information is changed in subsequent processing routines. Based on this, the decoding timing of the B picture and the display setting of all frames are controlled.

  The setting of the display order setting queue with time information in the thinning process 1 will be described with reference to FIGS. In FIG. 25 to FIG. 30, the state of scheduling before thinning is shown in the upper part by describing the thinned frames with dotted lines, and the state of scheduling after the thinning process 1 is shown in the lower part. ing. In FIG. 25 to FIG. 30, the numbers 0, 1, and 2 in parentheses are information accumulated in information queues respectively set corresponding to any of the decoders 22 to 24, or This indicates that the process is executed in any one of the decoders 22 to 24.

  For example, in the case of high-speed playback at + 2 × speed, as shown in FIG. 25, the change in the number of displayed pictures in the decoding unit before and after thinning is −7, and the time information adjustment value added_count is −7. Since the picture type of the first picture of the next decoding unit is changed from I picture to B picture, the phase adjustment value is −1. Therefore, the adjustment amount of time_base is the display phase shift amount correction value disp_zero. When is 0, it is -8. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  Further, for example, in the case of high-speed playback at −2 × speed, as shown in FIG. 26, the change in the number of displayed pictures in the decoding unit before and after thinning is −7, and the time information adjustment value added_count is −7. . Since the picture type of the first picture of the next decoding unit remains the B picture, the phase adjustment value is 0, and therefore the time_base adjustment amount is 0 for the display phase shift amount correction value disp_zero. When it becomes -7. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  For example, in the case of high-speed playback at + 4 × speed, as shown in FIG. 27, the change in the number of displayed pictures in the decoding unit before and after thinning is −11, and the time information adjustment value added_count is −11. Since the picture type of the first picture of the next decoding unit is changed from I picture to B picture, the phase adjustment value is −1, and the adjustment amount of time_base is the display phase shift amount correction value disp_zero. When is 0, it is −12. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  For example, in the case of high-speed playback at -4 times speed, as shown in FIG. 28, the change in the number of displayed pictures in the decoding unit before and after thinning is -11, and the time information adjustment value added_count is -11. Since the picture type of the first picture of the next decoding unit remains the B picture, the phase adjustment value is 0, and therefore the time_base adjustment amount is 0 for the display phase shift amount correction value disp_zero. Then -11. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  For example, in the case of high-speed playback at + 5 × speed, as shown in FIG. 29, the change in the number of displayed pictures in the decoding unit before and after thinning is −12, and the time information adjustment value added_count is −12. Since the picture type of the first picture in the next decoding unit remains unchanged from I picture, the phase adjustment value is 0. Therefore, the display phase shift amount correction value disp_zero is 0 as the time_base adjustment amount. When it becomes -12. The display start timing of the second GOP is delayed by 6 frames from the decoding start timing of the I picture because the head is the I picture.

  For example, in the case of -5 × high-speed playback, as shown in FIG. 30, the change in the number of displayed pictures in the decoding unit before and after thinning is −12, and the time information adjustment value added_count is −12. Since the picture type of the first picture of the next decoding unit remains the B picture, the phase adjustment value is 0, and therefore the time_base adjustment amount is 0 for the display phase shift amount correction value disp_zero. When it becomes -12. The display start timing of the second GOP is delayed by 7 frames from the decoding start timing of the I picture because the head is a B picture.

  Then, as shown in FIG. 25 to FIG. 30, in step S167 of the schedule determination process with time information described with reference to FIG. Calculated based on 1). Then, as shown in FIG. 25 to FIG. 30, based on the calculated decoding start time information time_base, decoding of the I picture and P picture corresponding to the picture ID set in the I / P picture decoding queue with time information The start timing is determined, and the decoding and display schedule of the B picture after the thinning-out process 1 is determined based on the calculated decoding start time information time_base and the display order setting queue with time information from which frames that are not displayed are deleted. The

  For example, when a playback apparatus 1 decodes a LONG GOP MPEG stream with N = 15 and M = 3, the bank No. of the eight banks of the video bank memory 82 in FIG. The remaining banks are such that the anchor frames of I, P, P, P, P, and I are fixedly stored in the six banks 0 to 5, and the B picture is decoded one frame before the display. No. By storing alternately in 6 and 7, even if the bank provided in the video bank memory 82 has only 8 faces, the number of decoders in the forward direction and the reverse direction (reproduction of this embodiment) In the apparatus 1, it is possible to execute display within a speed range determined corresponding to three).

  The setting of the video bank memory 82 in FIG. 2 will be described with reference to FIGS.

  FIG. 31 is a diagram illustrating a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. At the same time as the display timing of the first I2 picture, the bank No. 6 stores the B3 picture, and at the same time when the B3 picture is displayed, the bank No. 7 is stored, and at the timing when the B3 picture is displayed, the bank No. in which the B3 picture that has been displayed is stored is stored. 6 and the bank No. in which the I2 picture that has been used as a reference image has been stored. 0 is released. After that, bank no. 6 and 7 store B pictures alternately so that the display timing of the B pictures is delayed by one frame with respect to the decode timing, and are released after display. In addition, bank No. 1 to 5 are released when the stored P picture is used as a reference image. That is, bank no. 0 to 5 are not released when the picture is displayed, but are released when the use of the stored I picture or P picture as the reference image and the display of the picture are completed.

  FIG. 32 is a diagram showing a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. At the same time as the display timing of the first I2 picture, the bank No. 6 stores the B4 picture, and at the same time the B4 picture is displayed, the bank No. 7 is stored, and at the timing when the B6 picture is displayed, the bank No. in which the B4 picture that has been displayed is stored is stored. 6 and the bank No. in which the I2 picture that has been used as a reference image has been stored. 0 is released. After that, bank no. In 6 and 7, B pictures that are not thinned out are alternately stored so that the display timing of the B pictures is delayed by one frame with respect to the decoding timing, and are released after display. In addition, bank No. 0 to 5 are not released when the picture is displayed, but are released when the use of the stored I picture or P picture as the reference image and the display of the picture are completed. . 1 to 5 are released when the use of the stored P picture as a reference image and the display of the picture are completed.

  FIG. 33 is a diagram illustrating a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. And bank no. 5 at the next timing when the I2 picture is stored in the bank No. 6 stores the B1 picture, and at the same time when the B1 picture is displayed, the bank No. 7 stores the B0 picture, and at the timing when the B1 picture is displayed, the bank No. in which the B1 picture that has been displayed is stored is stored. 6 is opened. After that, bank no. In 6 and 7, the B picture is alternately stored so that the display timing of the B picture is delayed by one frame with respect to the decode timing, and is released after display. Bank No. 0 to 5 are released at the later timing of the display of the picture or the point in time when the use of the stored I picture or P picture as the reference image ends. That is, in the case of FIG. Since the I2 picture stored in 0 is displayed last, it is not released until the display of this GOP is completed.

  FIG. 34 is a diagram illustrating a state in which each picture is stored in eight banks of the video bank memory 82 of FIG.

  Bank No. 0 to 5 are occupied by I pictures and P pictures, and decoded I pictures and P pictures are stored in the decoding order. And bank no. 5 at the next timing when the I2 picture is stored in the bank No. 6 stores the B1 picture, and at the timing next to the timing when the B1 picture is displayed, the bank No. 7 stores the B12 picture and the bank No. in which the B1 picture that has been displayed is stored. 6 is opened. After that, bank no. In 6 and 7, B pictures that are not thinned out are alternately stored so that the display timing of the B pictures is delayed by one frame with respect to the decoding timing, and are released after display. Bank No. 0 to 5 are released at the later timing of the display of the picture or the point in time when the use of the stored I picture or P picture as the reference image ends. That is, in the case of FIG. Since the I2 picture stored in 0 is displayed last, it is not released until the display of this GOP is completed.

  In this way, when video data compressed using general bidirectional inter-frame prediction in an image compression method typified by MPEG or the like is played back in reverse or at high speed, the I picture and P picture are first used. By decoding and scheduling the decoding of the B picture at the timing one frame before the display, the I picture and the P picture are stored in a fixed position of the bank holding the frame, and complex bank surface control is performed. Without performing the above, it is possible to efficiently realize reverse reproduction and reverse high-speed reproduction by reducing the number of bank faces as much as possible.

  Specifically, if the number of banks holding frames is the total number of I pictures and P pictures included in the decoding processing unit and two planes for storing B pictures, the anchor frame is used. A certain I picture and P picture can be stored in a fixed position of the bank, and high-speed playback and reverse playback can be realized without performing complicated bank surface control.

  For example, as in this embodiment, in an MPEG LONG GOP stream with N = 15 and M = 3, 5 planes of I, P, P, P, and P pictures + 1 plane of the next I picture + 2 planes of B picture In total, by preparing an 8-side video bank memory, I pictures and P pictures are stored at fixed positions in the bank, and high-speed playback, reverse playback, and reverse are performed without complicated bank plane control. Direction high-speed playback can be realized.

  In addition, in order to improve the speed change response by the operation from the user, when trying to perform the process of decoding and stopping the display of the B picture for the purpose of changing the speed in units of frames, the decoding and display of the B picture Although the timing control is managed separately, the bank management can be simplified by avoiding complicated processing for managing the bank. For example, it is illegal in the transient state of the input stream. Even if a reference process or the like is performed, it can be easily restored (underflow process described later), and a speed change can be performed on a frame basis.

  Next, the underflow process executed in step S197 in FIG. 18 will be described with reference to the flowchart in FIG.

  In step S361, the CPU 20 refers to the time management counter and the time counter, and determines whether the stream data is not supplied in time for the display process, that is, whether underflow has occurred. If it is determined in step S361 that no underflow has occurred, the process returns to step S197 in FIG. 18 and proceeds to step S36 in FIG.

  If it is determined in step S361 that underflow has occurred, in step S362, the CPU 20 sets the value of the time counter, which is a counter indicating the time, to the start time of the I / P picture decoding queue with time information. At the same time, the process returns to step S197 in FIG. 18 and proceeds to step S36 in FIG.

  36 and 37, correction of the value of the time counter when an underflow occurs will be described. In FIGS. 36 and 37, the numbers 0, 1, and 2 in parentheses are information accumulated in information queues respectively set corresponding to any of the decoders 22 to 24, or This indicates that the process is executed in any one of the decoders 22 to 24.

  FIG. 36 shows the information stored in the information queue and the decoding and display for the time counter when no underflow has occurred in -5 × playback as in the case described with reference to FIG. The timing of is shown. FIG. 36 shows an example in which the value of the time counter of the decoding start timing of an I picture of a certain GOP is 7.

  For example, when an underflow has occurred for two frames, as shown in FIG. 37, the time counter is delayed by two frames and the processing is restarted with reference to the time counter. Decoding and display control can be executed without delay.

  By such processing, for example, even when the supply of the stream is delayed due to insufficient throughput of the HDD 16 during high-speed playback, an underflow state due to the delayed supply of the stream is detected, and the time information is counted. By returning the underflowed time, the reproduction process can be resumed without failure.

  If it is determined in step S36 of FIG. 4 that the processing of all frames has not been completed, the time counter is incremented in step S37, and the process returns to step S31, and for the next frame, The subsequent processing is repeated.

  From the seventh frame onward, in step S33, since it is determined that it is not any frame from the first frame to the sixth frame, one-frame delay display setting processing is executed in step S34.

  Next, with reference to the flowchart of FIG. 38, the one-frame delay display process executed in step S34 of FIG. 4 after the seventh frame will be described.

  In step S361, the CPU 20 displays a display command so that display is performed with a delay of one frame from the decoding processing by the set decoder among the decoders 22 to 24 based on the information held in the display queue. To the set decoder among the decoders 22 and 24 via the control bus 19 and delete the corresponding picture ID in the display queue. At this time, the output address determination unit 80 of the set decoder among the decoders 22 to 24 receives the control signal from the CPU 20 via the control bus 76 and controls the memory controller 80 to control the video bank. The corresponding picture is read from the memory 82 and supplied to the selector 25.

  In step S362, the CPU 20 controls the selector 25 based on the value held in the register indicating the decoder that supplies the next data set in step S81 in FIG. 6, and outputs the decoded frame. The process returns to step S34 in FIG. 4 and proceeds to step S35.

  For example, when the playback speed is 1 time, as described with reference to FIG. 21, with respect to the decoding timing of the B picture executed based on the time information set in the display order setting queue with time information, The display is set in the order of the pictures set in the display order setting queue with time information so that the display of the B picture for one frame is delayed.

  Also, when the playback speed is -1 times, as described with reference to FIG. 22, the decoding timing of the B picture executed based on the time information set in the display order setting queue with time information is also described. Thus, the display is set in the order of the pictures set in the display order setting queue with time information so that the display of the B picture for one frame is delayed.

  25 for high-speed playback at + 2 × speed, FIG. 26 for high-speed playback at −2 × speed, FIG. 27 for high-speed playback at + 4 × speed, and FIG. 28 at + 4 × high-speed playback, + 5 × speed. As shown in FIG. 29 in the case of high-speed playback and in FIG. 30 in the case of high-speed playback at -5 times speed, the processing is executed based on the time information set in the display order setting queue with time information. The display is set in the order of the pictures set in the display order setting queue with time information so that the display of the B picture for one frame is delayed with respect to the decoding timing of the B picture.

  As a result of such processing, if the number of banks holding frames is the total number of I pictures and P pictures included in the decoding processing unit and two planes for storing B pictures, anchor frames The I picture and the P picture can be stored at fixed positions in the bank, and high-speed reproduction, reverse reproduction, and reverse high-speed reproduction can be realized without performing complicated bank surface control.

  The phase shift between the decoding start timing and the display start timing has been described based on the number of I pictures and P pictures included in the decoding processing unit. For example, among the frames included in the decoding processing unit, Based on the number of frames to be displayed, it may be possible to obtain a phase shift between the decode and display start timings.

  When high-speed playback in the forward direction or the reverse direction is executed, for example, in the scheduling of decoding in the second and subsequent decoding processing units, determination of a frame to be displayed and a frame not to be displayed, that is, thinning is performed. Prior to this, for example, an encoding parameter such as a picture type of a picture displayed at the head of a decoding processing unit may be detected in advance.

  For example, before the determination of the frame to be displayed and the frame not to be displayed is made, based on the frame counter counted in the decoding schedule of the previous decoding processing unit and the calculated thinning cycle, the decoding processing unit The picture type of the picture displayed at the head may be detected in advance, or the picture type of the picture displayed at the head of the decoding process unit may be detected in advance by another method. .

  By doing so, it is possible to execute the decoding schedule processing more accurately and at high speed.

  An example of specific processing for detecting in advance the picture type of the picture displayed at the beginning of the decoding processing unit will be described below.

  With reference to the flowchart of FIG. 39, description will be given of a process 2 performed for each frame, in which a process of detecting a picture type of a picture displayed at the head of a decoding process unit in advance can be performed prior to scheduling. This processing routine is repeatedly executed for each frame until the stream data for which display is instructed is completed or until display is instructed.

  In step S431, the input stream state change process described with reference to FIG. 5 is executed.

  In step S432, decode schedule processing 2 described later with reference to FIG. 40 is executed. In the decode schedule process 2, the decode timing is scheduled. Prior to the decoding timing schedule processing, processing for detecting in advance the picture type of the picture displayed at the head of the decoding processing unit is executed.

  In step S433, the CPU 20 refers to the time counter that is a counter representing the processing time in units of one frame, so that the processing target is the first frame of the stream data to be reproduced in the decoding order. It is determined whether the frame is one of the sixth frames from the first frame.

  If it is determined in step S433 that the processing target is not one of the sixth frames to the sixth frame of the stream data to be reproduced in the decoding order, in step S434 The one-frame delay display setting process described with reference to FIG. 38 is executed.

  If it is determined in step S433 that the processing target is any one of the sixth frame to the sixth frame of the stream data to be reproduced in the decoding order, or step After the processing of S434 is completed, in step S435, frame control processing 2 described later with reference to FIG. 42 is executed. In the frame control process 2, the frame to be processed is decoded.

  In step S436, the CPU 20 determines whether or not processing of all frames has been completed. If it is determined in step S436 that processing of all frames has not been completed, in step S437, the CPU 20 increments a time counter in units of one frame.

  After the process of step S437 is completed, the process returns to step S431, and the subsequent processes are repeated. If it is determined in step S436 that all the frames have been processed, the process ends.

  In this way, the CPU 20 counts up the time counter for each processing of one frame, schedules decoding according to the playback speed instructed by the user, performs decoding for each frame, and displays the display. In this process, a process for detecting in advance the picture type of the picture displayed at the head of the decoding process unit is executed prior to the decoding timing schedule process.

  Next, the decoding schedule process 1 executed in step S432 in FIG. 39 will be described with reference to the flowchart in FIG.

  In steps S471 through S478, basically the same processing as in steps S71 through S78 of FIG. 6 is executed.

  That is, referring to the input picture queue, it is determined whether or not the input picture queue is empty. If it is determined that the input picture queue is not empty, the process returns to step S432 in FIG. Proceed to When it is determined that the input picture queue is empty, the input process described with reference to the flowchart of FIG. 15 is executed.

  Then, it is determined whether or not the display order setting queue with time information set corresponding to the decoder that receives the next data supply is empty, and it is determined that the display order setting queue with time information is not empty. In other words, that is, when the decoding process or the display process is being executed for each frame for the scheduled picture corresponding to 1 GOP, the process returns to step S432 in FIG. 39 and proceeds to step S433.

  When it is determined that the display order setting queue with time information is empty, reorder processing is executed, and the picture IDs of the I picture and P picture of the GOP to be decoded are set in the decoding order in the I / P picture decoding queue. Is done. Then, a bank position for storing the I picture and the P picture, and a reference image bank in the decoding of the P picture are designated, and a reference picture in the decoding of the B picture is based on the bank position in which the I picture and the P picture are respectively stored. The bank position is designated, and the display order setting queue described with reference to FIG. 12 is set.

  In step S479, the thinning process 2 described later with reference to FIG. 41 is executed. This thinning-out process 2 is a process for detecting in advance the picture type of the picture displayed at the head of the decoding process unit prior to the decoding timing schedule process.

  Then, in steps S480 to S482, basically the same processing as the processing executed in steps S79 to S81 in FIG. 6 is executed. That is, the display phase determination process described using the flowchart of FIG. 16 is executed, the schedule determination process with time information described using the flowchart of FIG. 17 is executed, and the timing of decoding and display is scheduled.

  Specifically, the thinning process 2 executed in step S479 can detect in advance the picture type of the picture displayed at the beginning of the decoding processing unit prior to the decoding timing scheduling process. When the head of the picture is an I picture or a P picture, as described with reference to FIG. 13, after the I picture and the P picture are first decoded, the B picture is decoded, and the display start timing is from the start of decoding. The decoding and display timing is scheduled so that the B picture decoding timing and the display timing are shifted by one frame by shifting by six pictures. If the top of the display is a B picture, as described with reference to FIG. 14, after the I picture and the P picture are first decoded, the B picture is decoded, and the display start timing is from the start of decoding. The decoding and display timing is scheduled so that the B picture decoding timing and the display timing are shifted by one frame by shifting by seven pictures.

  Then, a process of switching the setting of a decoder that supplies data to be decoded next is executed, and the process returns to step S432 in FIG. 39 and proceeds to step S433.

  By such processing, the decoding and display timing is scheduled.

  Next, the thinning process 2 executed in step S479 of FIG. 40 will be described with reference to the flowchart of FIG.

  In step S501, based on the stream input state set in the input stream state change process described with reference to FIG. 5, the CPU 20 sets the playback speed based on the user setting to high-speed playback in the forward direction or the reverse direction. It is determined whether or not. If it is determined in step S501 that high-speed playback is not performed, the process proceeds to step S510 described later.

  If it is determined in step S501 that high-speed playback is performed, in step S502, the CPU 20 determines whether or not the frame being processed is the first frame of the first GOP after the speed setting is changed. .

  If it is determined in step S502 that the frame being processed is the first frame of the first GOP after the input stream state has been changed, in step S503, the CPU 20 decimates based on the speed setting value GOP_Speed. Determine the period and save it in the register.

  Specifically, for example, when reproduction is performed at 2 × speed or −2 × speed, the CPU 20 stores the thinning cycle in the register as ½, and when reproduction is performed at 3 × speed or −3 × speed, Is saved in the register as 1/3.

  In step S504, the CPU 20 resets a frame counter that counts the number of frames in the thinning-out process 2 regardless of the decoding process unit.

  In step S502, if it is determined that the frame being processed is not the first frame of the first GOP after the input stream state is changed, or after the processing in step S504 is completed, the CPU 20 determines in step S505. Based on whether or not the confirmed flag is set in association with the picture ID held in the display order setting queue, it is determined whether or not all the display order setting queues have been confirmed. The confirmed flag is a flag that is set in the display order setting queue by processing in step S509 described later. If it is determined in step S505 that all display order setting queues have been confirmed, the process proceeds to step S510 described later.

  If it is determined in step S505 that all display order setting queues have not been confirmed, in other words, if there is a picture ID for which no confirmed flag is set in the display order setting queue, the CPU 20 in step S506 The frame counter is incremented by one.

  In step S507, the CPU 20 refers to the thinning cycle held in the register and the value of the frame counter as a result of determining the thinning cycle, and determines whether or not the frame indicated by the frame counter is displayed. Specifically, when the thinning cycle is ½, the CPU 20 performs display if the value of the frame counter that counts the number of frames is 2n (n is a positive integer), otherwise, When the display is not performed or the thinning cycle is 1/3, if the value of the frame counter that counts the number of frames is 3n (n is a positive integer), the display is performed. Otherwise, the display is performed. Do not display. If it is determined in step S507 that display is to be performed, that is, if it is determined that the frame is not thinned out, the process proceeds to step S509 described later.

  If it is determined in step S507 that the frame is not displayed, that is, if it is determined that the frame is to be thinned out, in step S508, the CPU 20 determines that the frame to be processed in the display order setting queue is not displayed. Set the delete flag to indicate.

  If it is determined in step S507 that the frame indicated by the frame counter is to be displayed, or after the processing of step S508 is completed, in step S509, the CPU 20 sets the frame indicated by the frame counter in the display order setting queue. A confirmed flag is set in association with the corresponding picture ID, the process returns to step S505, and the subsequent processes are repeated.

  If it is determined in step S501 that high-speed playback is not performed, or if it is determined in step S505 that all display order setting queues have been confirmed, in step S510, the CPU 20 thins out the display order setting queue. GOP_Speed, which is a speed setting value at the time of executing process 2, is set, the process returns to step S479 in FIG. 40, and the process proceeds to step S480.

  By such processing, in the display order setting queue, a deletion flag indicating non-display is associated with a non-displayed frame prior to decoding scheduling, so when displaying a decoding schedule, the display is displayed at the head of the decoding processing unit. The picture type of the picture to be played can be detected. The B picture decoded after this processing routine is only displayed (the B picture to be thinned is not supplied to the decoding processing unit 77), and the I picture or P picture to be thinned is decoded. But not displayed.

  Next, the frame control process 2 executed in step S435 in FIG. 39 will be described with reference to the flowchart in FIG.

  In step S541, the CPU 20 refers to the time management counter, which is a counter for managing the timing of each process executed in the playback device 1, and the I / P picture decode queue with time information, and the display time has passed. It is determined whether there is stream data. If it is determined in step S541 that there is stream data whose display time has passed, the process proceeds to step S547 described later, and the underflow process described with reference to FIG. 35 is executed. Returning to step S435 of step 39, the process proceeds to step S436.

  If it is determined in step S541 that there is no stream data whose display time has passed, basically the same processing as that in steps S192 to S195 of FIG. 18 is executed in steps S542 to S545.

  That is, the I picture and P picture decoding process described with reference to FIG. 19 is executed, and the B picture decoding process described with reference to FIG. 20 is executed. Then, the display picture information is notified from the CPU 20 to the CPU 11, and the CPU 20 increments the time management counter. These processes are executed for frames for which the deletion flag is not set (not thinned out) in step S508 of FIG.

  In step S546, the thinning process 3 described later with reference to FIG. 43 is executed, and the process returns to step S435 in FIG. 39 and proceeds to step S436.

  If display is not delayed by such processing, decoding for one frame is executed based on the set decoding schedule, display picture information is notified to the CPU 11, and thinning-out processing 3 is executed. When the display is delayed, the underflow process described using FIG. 35 is executed.

  Next, the thinning process 3 executed in step S546 in FIG. 42 will be described with reference to the flowchart in FIG.

  In step S <b> 571, the CPU 20 sets the playback speed setting compared to the execution of the thinning process that was executed immediately before (when the thinning process 2 is executed in the decoding schedule process 2). It is determined whether or not the speed is increased in the same direction. Specifically, the CPU 20 determines whether or not speed / GOP_speed> 1 is satisfied based on the current speed setting value speed and the GOP_speed set in the display order setting queue. It is determined whether or not the playback speed setting has become faster in the same direction as compared to the execution of the thinning process executed previously. In step S571, whether or not the playback speed setting is faster in the same direction as compared with the execution of the thinning process executed immediately before, that is, whether the speed of the previous thinning process is changed. If it is determined that the time has been delayed or the direction has been reversed, the process returns to step S546 in FIG. 42, and the process proceeds to step S436 in FIG.

  If it is determined in step S571 that the playback speed setting has become faster in the same direction as compared with the execution of the thinning process executed immediately before, the CPU 20 performs the thinning process 2 in step S572. Based on the speed setting values at the time of execution and the current values, a thinning cycle is determined and stored in a register.

  Specifically, the CPU 20 sets the thinning cycle based on the reciprocal of the absolute value of speed / GOP_speed. For example, when the thinning process 2 is executed, the speed setting is double speed, but the current speed setting value is 4 In the case of double speed, the thinning cycle is halved and stored in a register that holds the thinning cycle.

  In step S <b> 573, the CPU 20 resets the frame counter that counts the number of frames in the thinning-out process 3 regardless of the decoding process unit.

  In step S574, the CPU 20 associates all of the display order with time information display queues with reference to whether or not the confirmed flag is set in association with the picture ID held in the display order setting queue with time information. It is determined whether or not it has been confirmed. The confirmed flag is a flag that is set in the display order setting queue with time information by the process of step S579 described later. If it is determined in step S574 that all display order setting queues with time information have been confirmed, the process returns to step S546 in FIG. 42, and the process proceeds to step S436 in FIG.

  If it is determined in step S574 that all display order setting queues with time information have not been confirmed, in other words, it is determined that there is still a picture ID for which the confirmed flag is not set in the display order setting queue with time information. In step S575, the CPU 20 increments the frame counter by 1.

  In step S576, the CPU 20 refers to the thinning cycle held in the register and the value of the frame counter as a result of the determination of the thinning cycle, and determines whether the frame indicated by the frame counter is displayed. Specifically, when the thinning cycle is ½, the CPU 20 performs display if the value of the frame counter that counts the number of frames is 2n (n is a positive integer), otherwise, When the display is not performed or the thinning cycle is 1/3, if the value of the frame counter that counts the number of frames is 3n (n is a positive integer), the display is performed. Otherwise, the display is performed. Do not display. If it is determined in step S576 that display is to be performed, that is, if it is determined that the frame is not thinned out, the process proceeds to step S579 described later.

  If it is determined in step S576 that the frame is not displayed, that is, if it is determined that the frame is to be thinned out, in step S577, the CPU 20 sets the picture ID corresponding to the processing target frame to the display order with time information. Either delete from the queue, or associate a flag indicating non-display with the corresponding picture ID in the display order setting queue with time information.

  In step S578, the time information resetting process described with reference to FIG. 24 is executed. At this time, the time information adjustment value added_count calculated in step S302 is the number of pictures changed by decimation by the processing of step S576 and step S577 when the speed setting is changed compared to the previous decimation processing. It is.

  When it is determined in step S576 that the frame indicated by the frame counter is to be displayed, or after the processing of step S578 is completed, in step S579, the CPU 20 indicates the frame counter in the display order setting queue with time information. The confirmed flag is set in association with the picture ID corresponding to the frame to be processed, the process returns to step S574, and the subsequent processes are repeated.

  With such processing, when the speed setting is changed from the thinning-out processing 2 and the speed is increased in the same direction, the picture ID of the frame that is not displayed is deleted from the display order setting queue with time information. Alternatively, a flag indicating non-display is associated with the corresponding picture ID in the display order setting queue with time information. The B picture decoding process and the one-frame delay display setting process are executed with reference to the reset display order setting queue with time information. When the speed setting is changed from the thinning process 2 and the speed is increased in the same direction, the setting of the display order setting queue with time information is updated based on the speed setting. Subsequent B pictures to be decoded are only displayed (thinned B pictures are not supplied to the decoding processing unit 77), and thinned I or P pictures are decoded but not displayed. It is made like.

  Therefore, even after the scheduling of decoding is completed, whether or not there is a change in the speed setting is detected for each frame, and the speed setting is changed from the thinning-out process 2 to increase the speed in the same direction. In such a case, since the display order setting queue with time information is reset, it is possible to quickly follow the speed change and schedule the decoding so that the stream is reproduced.

  By the way, in the above-described processing, each of the decoders 22 to 24 is provided with a video bank memory 83 capable of holding 8 frames of baseband image data, and each of the decoders 22 to 24 stores MPEG Long GOP compressed video by 1 GOP. By acquiring and decoding an anchor frame before decoding a B picture, high-speed playback in the forward and reverse directions has been realized.

  On the other hand, for example, if the performance of the decoder is higher than that of the decoders 22 to 24 and the time required for decoding one frame is sufficiently short relative to the display time of one frame, three decoders are not prepared. However, by performing the same scheduling process and decoding process with one decoder, for example, random reproduction and scrub reproduction can be performed in addition to normal and reverse high-speed reproduction. However, when the above-described scheduling process or decoding process is applied to one decoder with a sufficiently short time required to decode one frame, anchor frames for several GOPs are temporarily stored and further displayed B In order to temporarily hold a picture, it is necessary to provide a large-capacity frame memory.

  For example, in scrub playback, the start of display from an arbitrary picture can be commanded. In particular, when a B picture of a GOP whose anchor frame has not been decoded is designated as a playback start position, the B picture is decoded. Therefore, the B picture at the display start position cannot be decoded unless all the reference images for decoding are decoded, and thus the image cannot be output quickly. That is, if the capacity of the frame memory for holding the previously decoded anchor frame is small, the range in which the picture at the reproduction start position can be reproduced and output at high speed in scrub reproduction is reduced.

  Specifically, for example, if an anchor frame for 3 GOP can be decoded and held in advance, if any position for 3 GOP is designated as a playback position for scrub playback, it is quickly designated. Frames can be played back and output. However, if a position other than that is designated as the playback start position for scrub playback and the designated frame is a P picture or B picture, the anchor frame that becomes the reference image must be decoded, so the designated position is designated. Frame playback output is slow. On the other hand, for example, if anchor frames for 5 GOP can be decoded and held in advance, the range in which a designated frame can be reproduced and output is 5 GOPs. In other words, it is advantageous to predecode as many GOP anchor frames as possible and store them in the frame memory in order to expand the range in which the designated frame can be reproduced and output quickly in scrub reproduction. is there.

  That is, in particular, a decoder that uses a sufficiently short time to decode one frame with respect to the display time of one frame is used. For example, in addition to forward and reverse high-speed playback, random playback, scrub playback, or a short interval In the case of performing transient playback in which the playback in the forward direction and the reverse direction is continuously performed, the frame memory can be used effectively and the picture at the playback start position can be played back at high speed in scrub playback or random playback. It is preferable that the range is as wide as possible.

  However, in order to decode as many GOP anchor frames as possible in advance, a large memory capacity is required.

  Next, as a second embodiment, by decoding in advance a wide range of GOP I and P pictures and storing them in the frame memory, forward / reverse inversion playback, random playback, or scrub playback can be performed by one decoder. In order to be able to reproduce the reproduction start frame in a wide range as fast as possible, a frame when every several baseband images of anchor frames (I or P picture) are stored in the frame memory The management of the memory (video bank memory) will be described.

  FIG. 44 is a block diagram illustrating a hardware configuration of the playback apparatus 101.

  In addition, the same code | symbol is attached | subjected to the part corresponding to the case in FIG. 1, The description is abbreviate | omitted suitably.

  44 is provided with a CPU 121 in place of the CPU 20, a decoder 122 having a memory 131 is provided in place of the decoder 22, and the decoder 23, the decoder 24, and the selector 25 are omitted. Except for this, it has basically the same configuration as the playback device 1 of FIG.

  In other words, the PCI bridge 17 can supply the stream data read from the HDD 16 based on the control of the CPU 11 to be stored in the memory 18 and can be stored in the memory 18 based on the control of the CPU 121. The stream data is read and supplied to the decoder 122. Each GOP of stream data read from the HDD 16 is preferably provided with GOP header information including information on the GOP ID, the number of frames, and the number of anchor frames. The PCI bridge 17 controls transmission / reception of a control signal corresponding to a command or a result via the PCI bus 14 or the control bus 19.

  The CPU 121 reads a command written in the command buffer 31 of the PCI bridge 17 by the CPU 11 via the control bus 19 and controls processing executed by the PCI bridge 17 and the decoder 122 according to the command. The memory 21 stores data necessary for the processing of the CPU 121.

  In addition, when each GOP of the stream data read from the HDD 16 does not have GOP header information that is information including the GOP ID, the number of frames, and the number of anchor frames, the CPU 121 reads the data from the HDD 16. GOP ID for distinguishing each GOP of stream data and recognizing the arrangement order thereof, and GOP header information which is information including the number of frames and the number of anchor frames included in the GOP are generated. It is added to each GOP that constitutes it.

  The decoder 122 decodes the supplied compressed and encoded stream data based on the control of the CPU 121 and outputs an uncompressed video signal. The decoder 122 includes a decoding processing unit capable of decoding one frame with a sufficiently short time (for example, about 1/3 to 1/4 of the display time of one frame) with respect to the display time of one frame. Have. In addition, the decoder 122 has a memory 131 therein, and if necessary, the compressed and encoded stream data supplied from the PCI bridge 17 or the uncompressed video signal decoded by the decoder 122 itself. It is made possible to hold. In addition, the decoder 122 may be provided as an independent device that is not included in the playback device 101.

  Note that the playback device 101 in FIG. 44 may be configured as a single device or may be configured by a plurality of devices. For example, in the playback device of FIG. 44, the CPU 11, the north bridge 12, the memory 13, the south bridge 15, and the HDD 16 are part of the configuration of the personal computer. An expansion card such as a PCI bus 14, a PCI bridge 17, a memory 18, a control bus 19, a CPU 121, a memory 21, and a decoder 122 are provided on the expansion card. You may make it function as the reproducing | regenerating apparatus 101. FIG. Further, these may be further divided into a plurality of devices to constitute the playback device 101.

  Next, the operation of the playback apparatus 101 will be described.

  The HDD 16 stores compressed video data compressed by the MPEG Long GOP method.

  The CPU 11 controls the south bridge 15 via the north bridge 12 to read out the compressed and encoded stream data from the HDD 16 based on a user operation input supplied from an operation input unit (not shown). Via the north bridge 12, the PCI bus 14, and the PCI bridge 17, it is supplied to the memory 18 for storage, and information indicating the playback speed (including information indicating the playback direction), a decode start command, or a display start A command or the like is written into the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14.

  The CPU 121 determines a schedule for decoding and displaying the compressed and encoded stream data based on the command from the CPU 11 written in the command buffer 31 of the PCI bridge 17. Specifically, the CPU 121 inputs the compression-encoded stream data to the decoder 122, sets the decoding timing for each frame, sets the bank position of the reference image, assigns bank memory at the time of decoding, and decodes The output of the processed picture, that is, the display timing is determined.

  Then, the CPU 121 controls the PCI bridge 17 to supply the decoder 122 with the compressed and encoded stream data stored in the memory 18 based on the determined schedule.

  At this time, the CPU 121, when each GOP of the stream data read from the HDD 16 and stored in the memory 18 does not have GOP header information that is information including the GOP ID, the number of frames, and the number of anchor frames GOP header information that is information including a GOP ID that can distinguish each GOP of the stream data read from the HDD 16 and recognize the arrangement order thereof, and the number of frames and the number of anchor frames included in the GOP Is added to each GOP constituting the stream data.

  The CPU 121 controls the decoder 122 to decode the supplied compressed and encoded data. The decoder 122 decodes the supplied compressed and encoded stream data and outputs the decoded data to, for example, a display device (not shown) or a recording device for recording the decoded data on a predetermined recording medium.

  That is, also in the playback apparatus 101 shown in FIG. 44, the control processing executed by the CPU 11 is basically the same as the processing described with reference to the flowchart of FIG.

  Specifically, the CPU 11 controls the north bridge 12 and the south bridge 15 to read from the HDD 16 a plurality of GOPs of the compression-coded stream data designated as stream data to be decoded and output by the user. Then, the read stream data of the plurality of GOPs is supplied to the PCI bridge 17 via the PCI bus 14 and transferred to the memory 18.

  Then, the CPU 11 supplies the command buffer 31 of the PCI bridge 17 with the data transfer completion and the picture information of the picture included in the GOP transferred to the memory 18 via the north bridge 12 and the PCI bus 14. After notifying the CPU 121 of completion of data transfer and picture information, the CPU 121 and the memory 18 are notified of the completion of preparation. The picture information includes, for example, information such as picture type, header information for each picture, and picture size.

  Then, the CPU 11 receives a command to start reproduction output processing by a user from an operation input unit (not shown), and transmits a decode start command to the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14. The decoder 122 starts decoding processing, and then transmits a display start command to start display or output of the SDI signal obtained by decoding by the decoder, that is, the baseband image signal.

  Then, the CPU 11 sends a result for the display start command supplied to the result buffer 32 of the PCI bridge 17 by the CPU 121 via the control bus 19, that is, a notification of display completion for each frame via the north bridge 12 and the PCI bus 14. By reading and always checking which picture display has been completed, the display completion of 1 GOP is detected, and it is determined whether the displayed GOP is the end of the displayed stream data. .

  If it is determined that the displayed GOP is not the last of the displayed stream data, the CPU 11 is reproducing and reproducing the stream data, for example, based on a signal supplied from an operation input unit (not shown). It is determined whether or not a command accompanying a change in the input stream state, such as a change in stream data or a command for changing the playback speed or direction, is input from the user.

  When it is determined that a command accompanied by a change in the input stream state is input from the user, the CPU 11 sends a command corresponding to the user's operation input to the command buffer 31 of the PCI bridge 17 via the north bridge 12 and the PCI bus 14. Send.

  When it is determined that a command accompanying a change in the input stream state has not been input from the user, or after transmission of a command corresponding to the user's operation input, the CPU 11 determines whether or not stream data to be displayed remains in the HDD 16. Determine whether. When it is determined that there is no stream data to be displayed, the reproduction process of stream data that has been transferred to the memory 18 but not yet displayed is repeated.

  When it is determined that there is still stream data to be displayed in the HDD 16, the CPU 11 controls the north bridge 12 and the south bridge 15 to store the GOP that has been transferred to the memory 18 among the stream data to be decoded and output. The subsequent 1 GOP is read from the HDD 16, the read 1 GOP stream data is supplied to the PCI bridge 17 via the PCI bus 14, transferred to the memory 18, the data transfer is completed to the command buffer 31 of the PCI bridge 17, and the memory 18 By supplying the picture information of the picture included in the GOP transferred to, the CPU 121 is notified of the completion of data transfer and the picture information.

  Then, the CPU 11 receives a notification of preparation completion from the CPU 121 and the memory 18. Specifically, the CPU 11 reads the result for the data transfer completion and picture information notification supplied from the CPU 121 to the PCI bridge result buffer 32 via the control bus 19 via the north bridge 12 and the PCI bus 14. The memory 18 is notified of the end of storage of stream data of a plurality of GOPs via the PCI bridge 17, the PCI bus 14, and the north bridge 12.

  Then, the display or output of the SDI signal obtained by decoding by the decoder 122, that is, the baseband image signal is started, the display completion of 1 GOP is detected, and the displayed or output GOP is displayed or output. If it is determined that the stream data is the last, the process is terminated.

  By such processing, the CPU 11 can supply a command to the CPU 121, receive a result for the supplied command, and control decoding of the stream data and display of the decoded data.

  Further, the CPU 11 uses the period during which the decoding process for display output is not performed by the decoder 122, so that the GOP data supplied to the memory 18 is stored so that the I picture and the P picture are decoded and accumulated in advance. The GOP post-transfer command command is generated and supplied to the CPU 121 so as to be supplied in advance to the memory 131 of the decoder 122. The timing of the forward transfer differs depending on the reproduction direction and reproduction speed, the number of GOPs that can be stored in the memory 131, and the like. A specific example of the timing of the forward transfer will be described later with reference to FIGS.

  The memory 131 includes a stream buffer for accumulating the compressed encoded stream supplied from the memory 18, a frame memory for accumulating baseband image data generated by decoding by the decoder 131, and various pieces of information necessary for decoding processing. Various storage areas with a memory for holding

  Then, the CPU 121 controls the decoding process by the decoder 122 based on the command supplied from the CPU 11. Specifically, the CPU 121 determines the input timing of the compression-encoded stream data to the memory 131 of the decoder 122, the decoding timing for each picture, and the output of the decoded picture, that is, the display timing. Based on these timings, the PCI bridge 17 and the decoder 122 are controlled.

  The CPU 121 recognizes how many GOPs of data can be stored in a stream buffer in the memory 131 in which the compression-coded stream before decoding processing is buffered, and which GOP is held. Are managed based on GOP_ID. This is to avoid wasteful transfer of a stream to the stream buffer, such as transferring a GOP with the same GOP_ID when a GOP with a certain GOP_ID is stored in the stream buffer.

  Based on the GOP forward transfer command command supplied from the CPU 11, the CPU 121 transfers the GOP forward to the memory 131 (stream buffer) in time for picture output. The timing of the forward transfer will be described later with reference to FIGS. Then, the CPU 121 supplies an anchor frame decoding start command for the GOP transferred to the memory 131 (stream buffer thereof) to the decoder 122 so that the anchor frame is decoded in advance.

  The GOP transfer control process of the CPU 121 will be described with reference to the flowchart of FIG.

  In step S591, the CPU 121 receives supply of the GOP forward transfer command command of GOP ID x to the command buffer 31 of the PCI bridge 17 by the processing of the CPU 11.

  In step S592, the CPU 121 determines whether data of GOP ID x exists in the stream buffer of the memory 131 of the decoder 122 (stream buffer 131-1 described later with reference to FIG. 46).

  If it is determined in step S592 that GOP ID x data does not exist in the stream buffer, in step S593, the CPU 121 controls the forward transfer processing to the GOP ID x memory 131 stored in the memory 18. The process is terminated.

  If it is determined in step S592 that GOP ID x data exists in the stream buffer, in step S594, the CPU 121 transmits an anchor frame decoding start command for GOP ID x to the decoder 122, and the process ends. .

  As a result of such processing, the CPU 121 determines that there is no GOP data corresponding to the GOP forward transfer command command in the stream buffer of the memory 131 of the decoder 122 (stream buffer 131-1 described later with reference to FIG. 46). Based on the command, the forward transfer process of the designated GOP is controlled. When the data of the corresponding GOP already exists, the anchor frame decoding process is started without repeating the transfer of the same GOP.

  FIG. 46 is a block diagram showing a more detailed configuration of the decoder 122.

  The input processing unit 151 stores the compression-encoded stream data supplied from the PCI bridge 17 in the stream buffer 131-1, and from the supplied stream data, the start address, the data size, and the picture header in units of pictures. Information, Q matrix, etc. are acquired and supplied to the stream information buffer 131-2.

  The stream buffer 131-1 is a predetermined storage area in the memory 131 of FIG. 44 configured by a storage memory such as SDRAM, buffers the stream data supplied from the input processing unit 151, and selects the selector 152. To supply. The stream buffer 131-1 can hold at least stream data of the same number of GOPs as the number of GOPs of anchor frames that can be held in a frame memory 131-3 described later. Also, if the stream buffer 131-1 can hold the number of GOPs equal to or greater than the number of anchor frames GOP that can be held in the frame memory 131-3, which will be described later, for example, the playback direction is reversed. If the playback start position is changed, there is a high possibility that it can be handled without supplying a new GOP to the stream buffer 131-1, which is preferable.

  The stream information buffer 131-2 is a predetermined storage area in the memory 131 in FIG. 44, and is supplied from the input processing unit 151 and includes information such as the top address in units of pictures, data size, picture header information, and Q matrix. For each picture.

  Based on the control signal supplied from the CPU 121, the decode controller 153 reads the address and stream information of each picture held in the stream buffer 131-1 from the stream information buffer 131-2, and processes each unit of the decoder 122. To control. Specifically, the decode controller 153 controls the decode timing of each picture supplied to the decode processing unit 154 by controlling the selector 152. The decode controller 153 controls the selector 155 to control the storage position in the frame memory 131-3 of the baseband image signal obtained by decoding by the decode processing unit 154. The decode controller 153 controls the selector 156 to control the baseband image signal supplied from the frame memory 131-3 as the reference image to the decode processing unit 154, that is, the P picture or the picture executed in the decode processing unit 154. Controls supply of a reference picture in decoding of a B picture. The decode controller 153 controls the baseband image signal that the selector 157 reads and outputs from the frame memory 131-3, thereby outputting the decoded baseband image signal output for display or the like, that is, Control the display timing of the playback image.

  The selector 152 supplies the stream data stored in the stream buffer 131-1 to the decoding processing unit 154 in units of pictures based on the control of the decoding controller 153.

  The decode processing unit 154 decodes the MPEG video stream supplied from the selector 152 with reference to the reference image supplied from the selector 156 as necessary, and decodes the decoded baseband (uncompressed) image signal. This is supplied to the selector 155.

  The selector 155 stores the recording position of the baseband image signal decoded and supplied by the decoding processing unit 154 in the frame memory 131-3 based on the control of the decode controller 153, that is, the baseband image signal. The bank position is determined, and the baseband image signal supplied from the decoding processing unit 154 is stored in a predetermined bank position of the frame memory 131-3. In other words, the decode controller 153 determines the bank position in the frame memory 131-3 of the baseband image signal obtained by decoding by the decode processing unit 154, and the baseband image signal is recorded at that position. Then, the selector 155 is controlled.

  The frame memory 131-3 is a predetermined storage area in the memory 131 of FIG. 44, and displays an I picture used as a reference image of other pictures, a reference bank storing a P picture, a B picture, and the like. The reference bank includes a reference bank for an anchor frame that is pre-decoded and held, and a reference for an anchor frame that is decoded according to the timing to be reproduced and output. There are separate banks. An example of the bank configuration in the frame memory 131-3 will be described later with reference to FIG.

  Under the control of the decode controller 153, the selector 156 selects the frame image data held in the bank designated as the forward reference picture bank of the P picture in the frame memory 131-3, or the B picture The frame image data held in the bank designated as the reference image bank in the forward direction and the backward direction (backward) are read out and supplied to the decoding processing unit 154.

  Under the control of the decode controller 153, the selector 157 reads out and outputs an output image of the frame image data held in the frame memory 131-3, that is, a bank of frames to be displayed.

  Next, the operation of the decoder 122 will be described. Here, as an example, a case where N15 and M3 MPEG LongGOP are decoded will be described.

  As shown in FIG. 47, each GOP supplied to the input processing unit 151 includes GOP header information in addition to the data of each picture composed of I, P, and B pictures. The GOP header information is given in advance to each GOP constituting the stream data held in the HDD 16, or GOP header information is generated by the processing of the CPU 121, read from the HDD 16, and read out by the decoder 122. Is provided to each GOP constituting the stream data supplied to.

  The GOP header information includes, for example, the GOP ID, the number of frames included in the GOP, the number of anchor frames included in the frame, and the like.

  The input processing unit 151 supplies the picture data to the stream buffer 131-1, and also transmits information such as GOP header information, the head address in units of pictures, data size, picture header information, and Q matrix to the stream information buffer 131-. 2 is supplied.

  The stream information buffer 131-2 holds the GOP header information and information such as the top address of each picture, data size, picture header information, and Q matrix.

  The decode controller 153 stores the GOP header information stored in the stream information buffer 131-2 and information such as the top address of each picture, the data size, the picture header information, and the Q matrix. 48. The decoding related information of each GOP picture is generated, and the stream buffer GOP queue shown in FIG. 48 configured by the GOP header information and the decoding related information in the display order reordered in the display order is managed.

  The decoding related information is information necessary for decoding processing at the time of a picture output request. For example, the corresponding picture is a retained anchor frame, a non-retained anchor frame, or the first B picture of the GOP. Type information indicating whether the picture is a B picture other than the head of the GOP, a decoded image storage destination bank which is information indicating a storage destination of a decoded baseband image, and a reference image necessary for decoding the corresponding picture Of the forward reference picture index number indicating the forward reference picture, and the backward reference picture index number indicating the backward reference picture of the reference pictures necessary for decoding the corresponding picture, Consists of what is needed.

  In the stream buffer GOP queue, 1 GOP worth of decoding related information is managed as one data unit. For example, it is configured by FIFO (First in First Out), or new data is PUSH. In such a case, the information of the GOP that is farthest from the currently playing GOP is POPped.

  In the playback apparatus 1 according to the first embodiment described above, all anchor frames are decoded in advance before the B picture. On the other hand, in the decoder 122, all anchor frames are decoded. Only anchor frames selected every several frames, not frames, are decoded in advance before the B picture.

  Specifically, for example, in the decoder 122, as shown in FIG. 49, every other anchor frame in the GOP may be decoded in advance from the I picture. Hereinafter, an anchor frame that is decoded in advance and held in the bank is referred to as a retained anchor frame, and an anchor frame that is not decoded in advance, that is, not previously retained in the bank is referred to as a non-owned anchor frame.

  Specifically, for example, when a GOP with N: 15, M: 3, and GOP ID 1 is input and the leading bank used by the GOP ID 1 GOP anchor frame is “1” (FIG. 52). As described in FIG. 50, information is accumulated in the stream buffer GOP queue.

  That is, GOP ID 1, number of frames 15 and number of anchor frames 5 are described in the GOP header information of the corresponding GOP. In the decoding related information, the picture type, decoded picture storage destination bank, forward reference picture index number, and backward reference picture index number of each picture reordered in the picture display order are described. Here, the picture type is not a classification of I, B, P, but is a retained anchor frame, a non-retained anchor frame, or one of the two B pictures at the head of the GOP ( The first B picture) or the B picture other than the first GOP of the GOP (non-first B picture). Then, the I picture of index 2, the P picture of index 8, and the P picture of index 14 are held anchor frames, and the P picture of index 5 and the P picture of index 11 are non-owned anchor frames.

  Only the retained anchor frame is determined in advance and the bank number is written in the decoded image storage destination bank. However, in the non-retained anchor frame and the B picture, it is not yet determined at the time when the decoding related information is generated. Since it is not, it becomes an indefinite value. The forward reference picture index number of the first B picture with index numbers 0 and 1 (the B picture with the previous GOP I picture or P picture as the reference picture) has the previous GOP in the stream buffer at the initial setting. Since it may not exist, it is not set at this time, and is set when the last I picture or P picture of the previous GOP is searched for at the time of decoding. Then, the forward reference picture index number and backward reference picture index number of the other B picture, and the forward reference picture index number of the P picture are set.

  Details of the picture management process using the stream buffer GOP queue by the decode controller 153 will be described later with reference to the flowchart of FIG.

  Then, the decode controller 153 controls the decoding timing of each frame in the supplied stream data based on the decoding related information managed by the stream buffer GOP queue.

  That is, the decode controller 153 does not select all the anchor frames, but, for example, every other frame from the I picture, or every other selected anchor frame as described with reference to FIG. Only the frame is set as the possessed anchor frame, and the selector 152 is controlled so that the decoding processing unit 154 decodes in advance during the idle time of the decoding process before the B picture is decoded.

  As described above, the decoding processing unit 154 decodes one frame with a sufficiently short time (for example, about 1/3 to 1/4 of the display time of one frame) with respect to the display time of one frame. Is possible. Therefore, the decode controller 153 is configured so that the number of retained anchor frames that can be held in the frame memory 131-3 is decoded in advance in units of 1 GOP, supplied to a predetermined bank of the frame memory 131-3, and held. The selector 152, the selector 155, and the selector 156 are controlled.

  Every other anchor frame in the GOP is a possessed anchor frame, and the frame memory 131-3 temporarily holds an X frame baseband image data area and display image data for two frames. FIG. 51 shows a bank configuration diagram when an area can be secured, that is, when a bank memory of X + 2 banks is secured.

  Of the banks corresponding to X + 2 frames in the frame memory 131-3, two banks are used as display-only banks for B pictures or non-owned anchor frames. Other banks, that is, banks for X frames are used for reference images. Of the reference image banks for X frames, one is used as a non-owned anchor bank for storing a baseband image of a non-owned anchor frame used as a reference image when the retained anchor frame is decoded in advance. The other one is used as a B picture display non-owned anchor bank for storing a baseband image of a non-owned anchor frame used as a reference image when a displayed B picture is decoded. Then, the other X-2 frame banks are used as retained anchor banks for storing the decoded retained anchor frames.

  Specifically, when an I picture that is a retained anchor frame is decoded, the I picture is decoded alone and stored in the retained anchor bank. In addition, when a P picture that is a retained anchor frame is decoded, a non-retained anchor frame that is a previous anchor frame is a retained anchor frame that is stored in a retained anchor bank that is a previous anchor frame. The baseband image is decoded and stored in the non-retained anchor bank. With reference to this, the P picture that is the retained anchor frame is decoded and stored in the retained anchor bank.

  Then, when the display of any frame in the GOP in which the anchor frame is held in advance in the holding anchor bank is instructed, if the holding anchor frame is displayed, the holding anchor stored in the holding anchor bank The baseband image of the frame is read and displayed. If the non-owned anchor frame is displayed, the baseband image of the retained anchor frame stored in the retained anchor bank is used as a reference image, and the displayed non-owned anchor frame is decoded. It is stored and displayed in the B-non-owner anchor display bank, which is a display-only bank. If the B picture is displayed, the non-owned anchor frame is decoded with reference to the baseband image of the retained anchor frame stored in the retained anchor bank, which is the previous anchor frame. Stored in the non-owned anchor bank for B picture display, referenced with the baseband image of the retained anchor frame stored in the retained anchor bank, and the displayed B picture is decoded and stored in the display-only bank Displayed.

  That is, the retained anchor frame included in the GOP and the non-retained anchor frame required as a reference image for decoding the retained anchor frame are decoded in advance and stored in the frame memory 131-3. Non-retained anchor frames that are not required as a reference image for decoding retained anchor frames (for example, when the last anchor frame in GOP is a non-retained anchor frame) are displayed. Until then, the decoding process need not be executed.

  With reference to FIG. 52, management of the frame memory 131-3 by the decode controller 153 will be described.

  As shown in FIG. 52, the decode controller 153 uses the retained anchor information and the GOP retained anchor information for a plurality of frames retained in the GOP retained anchor queue to control the timing of the retained anchor frame decoding process. . The retained anchor information is information necessary for creating a GOP retained anchor queue, and includes information on the first and last banks used, and the number of banks used. The GOP holding anchor queue is a bidirectional queue that can be pushed to both the head and tail, and is information about the holding anchor frame held between the head bank used and the tail bank described in the holding anchor information. A certain GOP possession anchor information is retained for each GOP. The GOP possession anchor information is information required when determining the bank storage location of the baseband image of the possession anchor frame of each GOP. The GOP possession anchor information includes the GOP ID of the corresponding GOP and the possession of the GOP. The first bank used by the anchor frame and the number of banks used by the anchor frame held by the GOP are included.

  The decode controller 153 uses the timing at which the displayed non-owned anchor frame or B picture is not decoded to schedule the decoding order so that the held anchor frame is preferentially decoded, and controls the selector 156. Then, the decoding processing unit 154 is caused to supply the retained anchor frame to execute the decoding process, and the decoding is performed while referring to the retained anchor information and the GOP retained anchor information for a plurality of frames retained in the GOP retained anchor queue. It is determined in which reference bank of the frame memory 131-3 the baseband image data of the already held anchor frame is stored, and the selector 155 is controlled to determine a predetermined bank of the reference bank of the frame memory 131-3. A possessed app that has been decoded to a position Stores the baseband image data of the anchor frame.

  When the retained anchor frame to be decoded in advance is an I picture, the selector 152 is controlled, the I picture is supplied to the decoding processing unit 154, and after decoding, the selector 155 is controlled to control the frame memory 131-3. Stored in one of the owned anchor banks.

  If the retained anchor frame to be decoded in advance is a P picture, the immediately preceding non-owned anchor frame is supplied to the decoding processing unit 154 and decoded, and then the selector 155 is controlled to control the frame memory. It is stored in the non-owned anchor bank of the reference bank 131-3. Then, the selector 152 is controlled to supply the P picture that is the retained anchor frame to the decoding processing unit 154, and the selector 156 is controlled to refer to the baseband image data stored in the non-owned anchor bank. , P picture decoding processing is executed, and the selector 155 is controlled and stored in one of the owned anchor banks of the reference banks of the frame memory 131-3.

  The decode controller 153 includes, among anchor frames included in the supplied GOP, a retained anchor frame that is previously subjected to decoding processing, and a non-retained anchor frame that is necessary as a reference image for decoding the retained anchor frame. The decoding schedule and the bank position of the reference bank after decoding are managed using an anchor frame decoding queue. That is, the decoding controller 153 determines whether each picture is a retained anchor frame or a non-retained anchor frame required as a reference image for decoding the retained anchor frame from the beginning of the GOP. In a picture to be decoded in advance, a bank position where the baseband image data after each decoding is held is set, and is pushed to the anchor frame decoding queue.

  With reference to FIGS. 53 and 54, an example of a specific process for managing the owned anchor bank will be described. Here, a case where 10 banks can be used as possession anchor banks, that is, a case where 14 frames of baseband image data can be held in the frame memory 131-3 will be described.

  First, in the state of FIG. 53A, the baseband images of the possessed anchor frames with GOP IDs 1, 2, and 3 decoded in advance are stored in banks 0 to 3 of the ten retained anchor banks of the frame memory 131-3, respectively. , Stored in banks 4 to 6 and banks 7 to 9. At this time, the retained anchor information and the GOP retained anchor queue managed by the decode controller 153 are in the state of FIG. 53B. That is, it is managed that the used first bank is 1, the last used bank is 9, and the number of used banks is 9, according to the retained anchor information, and the GOP ID anchor queue holds GOP ID1. The anchor bank uses three banks from bank 1, the anchor bank owned by GOP ID2 uses three banks from bank 4, and the anchor bank owned by GOP ID3 has three banks from bank 7 The use of is managed.

  Next, when the GOP ID 4 stream data with the anchor frame number 5 is supplied, the number of anchor frames held by the GOP with the GOP ID 4 is 3, and the only vacant bank is the bank 10, and the GOP ID Since all of the GOP possession anchor frames of 4 GOPs cannot be stored, it is necessary to delete any of the currently stored GOP possession anchor frames from the possession anchor bank.

  Therefore, the decode controller 153 POPs the GOP possession anchor information of GOP ID 1 which is the information related to the GOP farthest from GOP ID 4 out of the information currently retained in the GOP possession anchor queue from the GOP possession anchor queue. Push the ID 4 GOP holding anchor information to the tail of the GOP holding anchor queue.

  FIG. 54A shows the state of the ten anchor banks in the frame memory 131-3 at that time, and FIG. 54B shows the state of the anchor information and the GOP anchor anchor queue. That is, among the ten owned anchor banks of the frame memory 131-3, banks 4 to 6 have GOP ID2 owned anchor frames, banks 7 to 9 have GOP ID3 owned anchor frames, and FIG. The stored anchor frames of GOP ID 4 that are newly supplied are stored in bank 10, bank 1, and bank 2 in the same manner as described above. And, it is managed by the possession anchor information that the first bank used is 4, the last bank used is 2, and the number of banks used is 9, and the GOP possession anchor queue holds GOP ID 2 The anchor bank uses three banks from bank 4, the GOP ID3 owned anchor bank uses three banks from bank 7, and the GOP ID4 owned anchor bank uses three banks from bank 10. The use of is managed.

  Next, the stream reproduction process 1 executed by the decoder 122 will be described with reference to the flowchart in FIG.

  In step S601, the decode controller 153 of the decoder 122 determines whether a new GOP has been supplied to the input processing unit 151. If it is determined in step S601 that a new GOP is not supplied, the process proceeds to step S604.

  In step S602, the process 1 at the time of stream input, which will be described later, is executed using the flowchart of FIG.

  In step S603, the decode controller 153 controls the input of stream data to the stream buffer 131-1, based on the information in the stream buffer GOP queue described with reference to FIG.

  In step S601, when it is determined that a new GOP is not supplied, or after the processing in step S603 ends, in step S604, the decode controller 153 has a timing other than the timing of the decoding processing for display. On the basis of whether or not the anchor frame decoding start command is supplied, it is determined whether or not the decoding process of the anchor frame of the GOP instructed to start decoding is possible.

  If it is determined in step S604 that the anchor frame can be decoded, in step S605, the decode controller 153 determines that the anchor frame of the GOP instructed to start decoding is stored in the anchor bank of the frame memory 131-3. It is determined whether or not it is held.

  If it is determined in step S605 that the anchor frame of the GOP that is instructed to start decoding is not held, in step S606, the decode controller 153 executes the anchor frame decoding executed in the process 1 at the time of stream input in step S602. Based on the scheduling by the scheduling process (described later with reference to FIG. 58), the selector 152, the selector 155, the selector 156, and the decoding processing unit 154 are controlled to be supplied to the stream buffer 131-1 and still decoded. Controls decoding of missing anchor frames. The decoding processing unit 154 executes the decoding process of the anchor frame supplied from the selector 152 using the reference image supplied from the selector 156 and supplies the decoded processing to the selector 155. The selector 155 stores the baseband image data of the anchor frame obtained by decoding in a predetermined bank position of the frame memory 131-3.

  If it is determined in step S604 that the decoding process of the anchor frame is not possible, if it is determined in step S605 that the anchor frame of the GOP instructed to start decoding is held, or the process of step S606 In step S607, the decode controller 153 determines whether output of any frame is requested based on the control signal supplied from the CPU 121.

  If it is determined in step S607 that output of any frame has been requested, output processing to be described later is executed in step S608 using FIG. 60 to FIG. 62 or FIG. 68 to FIG.

  If it is determined in step S607 that output of any frame has not been requested, or after the processing in step S608 is completed, the decoding controller 153 finishes supplying the stream to the input processing unit 151 in step S609. It is judged whether it was done. If it is determined in step S609 that the stream supply has not been completed, the process returns to step S601, and the subsequent processes are repeated.

  If it is determined in step S609 that the supply of the stream has been completed, in step S610, the decode controller 153 determines whether the reproduction process for the supplied stream has been completed. If it is determined in step S610 that the supplied stream reproduction process has not been completed, the process returns to step S604, and the subsequent processes are repeated. If it is determined in step S610 that the supplied stream reproduction process has been completed, the process ends.

  By such processing, the decoder 122 preferentially decodes the anchor frame included in the transferred GOP, and the retained anchor frame that is at least a part of the anchor frame is retained in the retained anchor bank of the frame memory 131-3. Therefore, it is possible to reduce the number of decoding required when the output of any frame is instructed, improving the response, and comparing with the case where all anchor frames are decoded and held in the memory bank in advance. Thus, display response such as random playback and scrub playback in as wide a range as possible with a small memory capacity, or transient playback in which playback in the forward and reverse directions is continuously commanded in a short section can be improved. it can.

  Next, with reference to the flowchart of FIG. 56, the process 1 at the time of stream input executed in step S602 of FIG. 55 will be described.

  In step S631, the decode controller 153 of the decoder 122 determines whether the picture input to the input processing unit 151 is an I picture. If it is determined in step S631 that the input picture is an I picture, the process proceeds to step S633 described later.

  When it is determined in step S631 that the input picture is not an I picture, in step S632, the decode controller 153 determines whether or not the picture input to the input processing unit 151 is a P picture.

  If it is determined in step S632 that the input picture is a P picture, the process proceeds to step S635 described later. If it is determined in step S632 that the input picture is not a P picture, that is, if it is determined that the input picture is a B picture, the process proceeds to step S636 described later.

  If it is determined in step S631 that the input picture is an I picture, in step S633, the decode controller 153 determines the GOP ID and the number of anchor frames from the GOP header information described with reference to FIG. get.

  In step S634, the retained anchor bank management process described later with reference to FIG. 57 is executed.

  If it is determined in step S632 that the input picture is a P picture, or after the processing in step 634 is completed, anchor frame decoding schedule processing described later with reference to FIG. 58 is executed in step S635.

  If it is determined in step S632 that the input picture is not a P picture, that is, the input picture is a B picture, or after the processing in step 635 is completed, in step S636, FIG. 59 is used. A picture management process using a stream buffer GOP queue described later is executed.

  In step S637, the decode controller 153 determines whether the picture input to the input processing unit 151 is the last picture of the GOP. If it is determined in step S637 that the input picture is not the last picture of the GOP, the process returns to step S631 and the subsequent processes are repeated. If it is determined in step S637 that the input picture is the last picture of the GOP, the process returns to step S602 in FIG. 55 and proceeds to step S603.

  By such processing, the owned anchor bank is managed, the decoding order of anchor frames is scheduled, and the input picture is managed.

  Next, the retained anchor bank management process executed in step S634 in FIG. 56 will be described with reference to the flowchart in FIG.

  In step S661, the decode controller 153 obtains the number of retained anchor banks necessary for the input GOP from the GOP header information described with reference to FIG.

  Specifically, when the retained anchor bank is set as an anchor bank every other picture from the I picture, the number of retained anchor banks necessary for the input GOP is the number of anchor banks of the GOP. For example, when the number of anchor banks of the GOP is 5, the anchor banks for 3 frames are required.

  In step S662, the decode controller 153 determines the sum of the number of owned anchor banks currently used in the frame memory 131-3 and the number of retained anchor banks necessary for the input GOP as the possessed prepared in the frame memory 131-3. It is determined whether the number is less than the number of anchor banks. If it is determined in step S662 that the total number of anchor banks currently in use and the number of anchor banks necessary for the input GOP is smaller than the number of anchor banks prepared in the frame memory 131-3, That is, the number of retained anchor banks that are not currently used in the frame memory 131-3 is greater than the number of retained anchor banks required for the input GOP, and thus any of the retained anchor banks currently retained in the retained anchor bank. If it is determined that there is no need to delete the anchor frame, the process proceeds to step S667 described later.

  If it is determined in step S662 that the total number of anchor banks currently in use and the number of anchor banks necessary for the input GOP is greater than the number of anchor banks prepared in the frame memory 131-3, That is, since the number of possessed anchor banks that are not currently used in the frame memory 131-3 is smaller than the number of retained anchor banks required for the input GOP, any of the retained anchor banks currently retained in the retained anchor bank When it is determined that it is necessary to delete the anchor frame, in step S663, the decode controller 153 queues the GOP ID of the input GOP at the head of the GOP holding anchor queue described with reference to FIG. It is closer to the GOP ID of the information queued at the end than the GOP ID of the information To determine whether or not.

  In step S663, it is determined that the GOP ID of the input GOP is closer to the GOP ID of the information queued at the tail than the GOP ID of the information queued at the head of the GOP holding anchor queue. In this case, in step S664, the decode controller 153 POPs the information queued at the head of the GOP holding anchor queue.

  In step S663, the GOP ID of the input GOP is not closer to the GOP ID of the information queued at the tail than the GOP ID of the information queued at the head of the GOP holding anchor queue, that is, GOP If it is determined that the value is close to the GOP ID of the information queued at the head of the retained anchor queue, in step S665, the decode controller 153 POPs the information queued at the tail of the GOP retained anchor queue.

  After the process of step S664 or step S665 is completed, in step S666, the decode controller 153 updates the retained anchor information described with reference to FIG. 52, the process returns to step S662, and the subsequent processes are repeated.

  If it is determined in step S662 that the total number of anchor banks currently in use and the number of anchor banks necessary for the input GOP is smaller than the number of anchor banks prepared in the frame memory 131-3, That is, the number of retained anchor banks that are not currently used in the frame memory 131-3 is greater than the number of retained anchor banks required for the input GOP, and thus any of the retained anchor banks currently retained in the retained anchor bank. If it is determined that there is no need to delete the anchor frame, in step S667, the decode controller 153 generates GOP holding anchor information of the input GOP.

  In step S668, the decode controller 153 determines whether or not the number of owned anchor banks currently in use is zero.

  If it is determined in step S668 that the number of retained anchor banks currently in use is 0, in step S669, the decode controller 153 pushes the GOP retained anchor information of the input GOP into the GOP retained anchor queue.

  If it is determined in step S668 that the number of retained anchor banks currently in use is not 0, in step S670, the decode controller 153 determines that the GOP ID of the input GOP is queued at the head of the GOP retained anchor queue. It is determined whether or not the value is closer to the GOP ID of the information queued at the end than the GOP ID of the existing information.

  In step S670, it is determined that the GOP ID of the input GOP is closer to the GOP ID of the information queued at the tail than the GOP ID of the information queued at the head of the GOP holding anchor queue. In this case, in step S671, the decode controller 153 pushes the GOP possession anchor information of the input GOP at the head of the GOP possession anchor queue.

  In step S670, it is determined that the GOP ID of the input GOP is not closer to the GOP ID of the information queued at the tail than the GOP ID of the information queued at the head of the GOP holding anchor queue. In this case, in step S672, the decode controller 153 pushes the GOP possession anchor information of the input GOP at the tail of the GOP possession anchor queue.

  After the process of step S669, step S671, or step S672 is completed, in step S673, the decode controller 153 updates the retained anchor information described with reference to FIG. 52, and the process returns to step S634 of FIG. The process proceeds to step S635.

  By such processing, frames stored in a predetermined number of owned anchor banks are managed so that responses such as scrub playback and transient playback can be improved in a GOP as wide as possible.

  That is, in this process, in the case of seamless GOP input, when the reserved anchor bank for the GOP to be displayed is secured, the retained anchor bank for the farthest GOP is released, and a new GOP The retained anchor frame is overwritten. As a result, in the case of seamless GOP input with a simple management method, it is guaranteed that the anchor frame of the currently displayed GOP will not be lost, and smooth playback with variable speed playback becomes possible. In addition, even if the number of input anchor frames of each GOP is different, the retained anchor bank can be used as effectively as possible. As a result, a larger number of GOP possession anchor frames can be stored in the possession anchor bank, so that a response such as scrub reproduction or transient reproduction can be improved in a wide range of GOPs with a simple management method. .

  Next, anchor frame decoding schedule processing executed in step S635 of FIG. 56 will be described with reference to the flowchart of FIG.

  In step S701, the decode controller 153 determines whether or not the input picture is a retained anchor frame.

  If it is determined in step S701 that the input picture is not a retained anchor frame, that is, a non-retained anchor frame, in step S702, the decode controller 153 determines that the input picture is in the same GOP of the input non-retained anchor frame. Whether there is a retained anchor frame, in other words, whether the input non-retained anchor frame is necessary as a reference image for decoding the retained anchor frame in the same GOP. Determine whether.

  In step S702, there is no retained anchor frame after the input non-retained anchor frame in the same GOP, that is, the input non-retained anchor frame decodes the retained anchor frame in the same GOP. If it is determined that it is not necessary as a reference image, the process returns to step S635 in FIG. 56 and proceeds to step S636.

  When it is determined in step S701 that the input picture is a retained anchor frame, or in step S702, a retained anchor frame exists behind the input non-retained anchor frame in time in the same GOP. In other words, if it is determined that the input non-retained anchor frame is necessary as a reference image for decoding the retained anchor frame in the same GOP, in step S703, the decode controller 153 determines that the input picture The bank position of the reference bank in the frame memory 131-3 of the decoded baseband image data is set.

  Specifically, for the retained anchor frame, the decode controller 153 uses the frame memory 131-3 based on the GOP retained anchor information of the GOP retained anchor queue set in the retained anchor bank management process described with reference to FIG. Is set as the storage destination of baseband image data after decoding, and for non-owner anchor frames, the non-owner anchor bank is set as the storage destination of baseband image data after decoding. Set.

  In step S704, the decode controller 153 pushes the set information to the anchor frame decode queue, and the process returns to step S635 in FIG. 56 and proceeds to step S636.

  By such processing, decoding of the anchor frame is scheduled.

  Next, a picture management process using the stream buffer GOP queue executed in step S636 in FIG. 56 will be described with reference to the flowchart in FIG.

  In step S731, the decode controller 153 determines whether the picture input to the stream buffer is an I picture. If it is determined in step S731 that the picture is not an I picture, the process proceeds to step S736 described later.

  If it is determined in step S731 that the picture is an I picture, in step S732, the decode controller 153 determines whether or not there is an empty stream buffer GOP queue.

  If it is determined in step S732 that there is no free space in the stream buffer GOP queue, in step S733, the decode controller 153 determines whether the GOP information stored in the stream buffer GOP queue is to be deleted first. POP information. Specifically, for example, when the stream buffer GOP queue is composed of FIFO, the GOP information with the earliest PUSH time is POPed, and the stream buffer GOP queue is updated with new data. If the GOP information that is farthest from the currently playing GOP is popped, the GOP that has the GOP ID farthest from the GOP ID of the currently playing GOP is popped. The

  If it is determined in step S732 that the stream buffer GOP queue is empty, or after the processing in step S733 is completed, in step S734, the decode controller 153 adds the GOP input to the stream buffer to the stream buffer GOP queue. PUSH GOP information of

  In step S735, the decode controller 153 acquires the GOP header information and writes it as GOP information in the stream buffer GOP queue.

  When it is determined in step S731 that the picture is not an I picture, or after the process of step S735 is completed, in step S736, the decode controller 153 corresponds to the decoded picture described with reference to FIG. Information is generated and written in the GOP information.

  In step S737, the decode controller 153 reorders the decoding related information as necessary. Specifically, each picture is supplied to the stream buffer in the order of stream order, that is, IBBPBBP..., But in the stream buffer GOP queue, the arrangement of the pictures in the GOP is BBBBBP. The reorder process is executed so that the display order is as follows.

  After the process of step S737 is completed, the process returns to step S636 of FIG. 56 and proceeds to step S637.

  Through such processing, each GOP supplied to the stream buffer 131-1 and picture data included in those GOPs are managed.

  Next, the output process 1 executed in step S608 of FIG. 55 will be described with reference to the flowcharts of FIGS.

  In step S761, based on the control signal supplied from the CPU 121, the decode controller 153 determines whether the requested output is a picture within the GOP range in which the retained anchor frame has already been decoded. To do.

  In step S761, output is requested when it is determined that the retained anchor frame is not a picture within the GOP range in which the retained anchor frame has already been decoded, that is, out of the GOP range in which the retained anchor frame has already been decoded. When the playback start position is instructed, in step S762, the decoding controller 153 executes normal decoding processing in order from the reference image, outputs the processing, and the processing returns to step S608 in FIG. Proceed to

  Specifically, since the GOP including the frame requested to be output is supplied to the stream buffer 131-1 via the input processing unit 151, the decode controller 153 determines that the frame requested to be output is an I picture. , P picture, or B picture, the selector 152, the decoding processing unit 154, the selector 155, and the selector 156 are controlled to execute the decoding process, and the selector 157 To output decoded baseband image data.

  That is, when the frame requested to be output is an I picture, the decode controller 153 controls the selector 152 to supply the I picture requested to be output from the stream buffer 131-1 to the decode processing unit 154 for decoding. Then, the data is supplied to the frame memory 131-3 via the selector 155, and the selector 157 is controlled to output the decoded baseband image data. When the frame requested to be output is a P picture or a B picture, the decode controller 153 controls the selector 152 and the selector 156 so that the decode processing unit 154 first decodes necessary reference image data, After controlling the selector 155 to store the reference image data in a predetermined bank of the frame memory 131-3, the selector 152 and the selector 156 are controlled to refer to the frame requested to be output by the decoding processing unit 154. The image is decoded with reference to the image and supplied to the frame memory 131-3 via the selector 155, and the selector 157 is controlled to output the decoded baseband image data.

  If it is determined in step S761 that the requested output is a picture within the GOP range in which the retained anchor frame has already been decoded, in step S763, the decode controller 153 controls the control supplied from the CPU 121. Based on the signal, it is determined whether or not the requested output is a retained anchor frame.

  If it is determined in step S763 that the requested output is a retained anchor frame, in step S764, the decode controller 153 controls the selector 155, and from the retained anchor bank of the frame memory 131-3, The corresponding retained anchor frame is read and output, and the process returns to step S608 in FIG. 55 and proceeds to step S609.

  If it is determined in step S763 that the requested output is not the possessed anchor frame, in step S765, the decode controller 153 determines that the output is requested based on the control signal supplied from the CPU 121. It is determined whether the frame is a non-owner anchor frame. If it is determined in step S765 that the output is not requested for the non-owned anchor frame, the process proceeds to step S770 described later.

  If it is determined in step S765 that the output is requested to be a non-owned anchor frame, in step S766, the decode controller 153 outputs the output to the B / non-owned anchor display bank of the frame memory 131-3. It is determined whether the requested non-owner anchor frame is stored.

  If it is determined in step S766 that the non-owner anchor frame requested for output is not stored in the B / non-owner anchor display bank, in step S767, the decode controller 153 selects the B / non-owner anchor display bank. , It is set as the storage destination of the baseband image after decoding the corresponding non-owned anchor frame.

  In step S768, the decode controller 153 refers to the decoding related information of the corresponding non-retained anchor frame in the stream buffer GOP queue, refers to the reference image indicated by the forward reference index number, and selects the corresponding non-retained anchor frame. It is decoded and stored in the B / non-owner anchor display bank of the frame memory 131-3.

  If it is determined in step S766 that the non-owner anchor frame requested to be output is stored in the B / non-owner anchor display bank, or after the processing of step S768 is completed, the decode controller 153 is determined in step S769. Controls the selector 155 to read out and output the corresponding non-owned anchor frame from the B / non-owned anchor display bank of the frame memory 131-3, and the process returns to step S608 in FIG. Proceed to

  If it is determined in step S765 that the output is not requested for the non-owned anchor frame, in step S770, the decode controller 153 determines whether the output is requested for the first B picture of the GOP. Judge whether or not. If it is determined in step S770 that the output is requested not for the B picture at the beginning of the GOP, that is, a B picture for which a reference image exists in the GOP other than the head of the GOP, The process proceeds to step S779 described below.

  If it is determined in step S770 that the output is requested for the first B picture of the GOP, in step S771, the decode controller 153 determines that the B / non-owner anchor display bank outputs the requested B picture. It is determined whether a picture is stored. If it is determined in step S771 that the B picture requested to be output is stored in the B / non-owner anchor display bank, the process proceeds to step S778 described later.

  If it is determined in step S771 that the B picture that is requested to be output is not stored in the B / non-owner anchor display bank, in step S772, the decode controller 153 displays the corresponding B picture in the owner anchor bank. It is determined whether or not both reference images are stored. If it is determined in step S772 that both reference images of the corresponding B picture are stored in the retained anchor bank, the process proceeds to step S776 described later.

  If it is determined in step S772 that both reference images of the corresponding B picture are not stored in the retained anchor bank, the decode controller 153 outputs an output to the non-retained anchor bank for B picture display in step S773. It is determined whether one reference image of the requested B picture is stored. If it is determined in step S773 that one reference image of the B picture requested to be output is stored in the B picture display non-owned anchor bank, the process proceeds to step S776 described later.

  If it is determined in step S773 that one reference image of the B picture requested to be output is not stored in the B picture display non-owned anchor bank, the decode controller 153 displays the B picture display non-owned anchor bank in step S774. The non-owner anchor bank is set as the storage destination of the baseband image after decoding the non-owner anchor frame that is the reference image of the corresponding B picture.

  In step S775, the decoding controller 153 refers to the decoding related information, controls the selector 152 to supply the non-owned anchor frame serving as the reference image to the decoding processing unit 154, and, if necessary, the selector 156. And the baseband image data corresponding to the retained anchor frame stored in the retained anchor bank of the frame memory 131-3 is supplied to the decode processing unit 154. The decoding processing unit 154 decodes the non-owned anchor frame that becomes the reference image and supplies the decoded non-owned anchor frame to the selector 155. The decode controller 153 controls the selector 155 to store the non-owned anchor frame serving as the decoded reference image in the B picture display non-owned anchor bank.

  If it is determined in step S772 that both reference images of the corresponding B picture are stored in the retained anchor bank, in step S773, the B picture requested to be output to the non-retained anchor bank for B picture display When it is determined that one of the reference images is stored, or after the processing of step S775 is finished, in step S776, the decode controller 153 decodes the B non-owned anchor display bank into the corresponding B picture. It is set as the storage destination for the subsequent baseband image.

  In step S777, the decode controller 153 refers to the decode related information, controls the selector 152 to supply the corresponding B picture to the decode processing unit 154, and controls the selector 156 as necessary. A stored anchor frame serving as a reference image of the corresponding B picture stored in the owned anchor bank of the frame memory 131-3 or a non-owned anchor bank for B picture display of the frame memory 131-3; The non-owner anchor bank decoded in S775 is supplied to the decode processing unit 154. The decode processing unit 154 decodes the corresponding B picture and supplies it to the selector 155. The decode controller 153 controls the selector 155 to store the decoded B picture in the B / non-owner anchor display bank.

  When it is determined in step S771 that the B picture that is requested to be output is stored in the B / non-owner anchor display bank, or after the processing of step S777 is completed, in step S778, the decode controller 153 The selector 157 is controlled to read out and output the corresponding B picture from the B / non-owner anchor display bank of the frame memory 131-3, and the process returns to step S608 in FIG. 55 and proceeds to step S609. .

  If it is determined in step S770 that the output is not requested for the B picture at the head of the GOP, that is, it is a B picture for which a reference image exists in the GOP other than the head of the GOP, in step S779. The decode controller 153 determines whether or not the B picture requested to be output is stored in the B / non-owner anchor display bank. If it is determined in step S779 that the B picture requested to be output is stored, the process proceeds to step S785 described later.

  If it is determined in step S779 that the B picture requested to be output is not stored in the B / non-owner anchor display bank, in step S780, the decode controller 153 stores the B picture non-owner anchor bank. It is determined whether one reference picture of the B picture requested to be output is stored. If it is determined in step S780 that one reference image of the B picture requested to be output is stored in the B picture display non-owner anchor bank, the process proceeds to step S783 described later.

  If it is determined in step S780 that one reference image of the B picture requested to be output is not stored in the B picture display non-owned anchor bank, in step S781, the decode controller 153 displays the B picture display The non-owner anchor bank is set as the storage destination of the baseband image after decoding the non-owner anchor frame that is the reference image of the corresponding B picture.

  In step S782, the decode controller 153 refers to the decode related information, controls the selector 152 to supply the non-owned anchor frame serving as the reference image to the decode processing unit 154, and, if necessary, the selector 156. And the retained anchor frame stored in the retained anchor bank of the frame memory 131-3 is supplied to the decode processing unit 154. The decoding processing unit 154 decodes the non-owned anchor frame that becomes the reference image and supplies the decoded non-owned anchor frame to the selector 155. The decode controller 153 controls the selector 155 to store the non-owned anchor frame serving as the decoded reference image in the B picture display non-owned anchor bank.

  In step S780, when it is determined that one reference image of the B picture requested to be output is stored in the B picture display non-owned anchor bank, or after the process of step S782 is completed, in step S783 The decoding controller 153 sets the B / non-owner anchor display bank as a storage destination of the baseband image after decoding the corresponding B picture.

  In step S784, the decoding controller 153 refers to the decoding related information, controls the selector 152 to supply the corresponding B picture to the decoding processing unit 154, and controls the selector 156 as necessary. A stored anchor frame that is a reference image of the corresponding B picture stored in the retained anchor bank of the frame memory 131-3 or a non-owned anchor bank for B picture display of the frame memory 131-3; The non-owner anchor bank decoded in S782 is supplied to the decode processing unit 154. The decode processing unit 154 decodes the corresponding B picture and supplies it to the selector 155. The decode controller 153 controls the selector 155 to store the decoded B picture in the B / non-owner anchor display bank.

  If it is determined in step S779 that the B picture requested to be output is stored, or after the processing in step S784 is completed, the decode controller 153 controls the selector 157 in step S785 to control the frame memory. The corresponding B picture is read out from the B / non-owner anchor display bank 131-3 and output, and the process returns to step S608 in FIG. 55 and proceeds to step S609.

  By such processing, decoding processing is executed using baseband image data stored in advance in the frame memory 131-3, so that the response from playback output command to playback output is improved. be able to.

  By the way, the timing of the forward transfer described above differs depending on the reproduction direction and reproduction speed, the number of GOPs that can be stored in the memory 131, and the like.

  A specific example of the timing of the forward transfer will be described with reference to FIGS.

  Here, this is a case of a LongGOP in which an I or P picture appearance period M = 3 and the number of pictures in a GOP N = 15, and the time taken to transfer 1 GOP data to the stream buffer 131-1 is displayed in two frames. It is assumed that the decoder 122 can decode three pictures at the time required to display one frame regardless of the I picture, the P picture, and the B picture. Here, the timing of the forward transfer when the continuous reproduction processing of the stream data or the clip file is executed will be described.

  In the decoding process, in order to decode at least one of the first B0 picture or B1 picture of a certain GOP, an anchor frame of the previous GOP is necessary in the order of forward reproduction. Therefore, during playback in the forward direction, how many frames need to be transferred relative to the playback timing of the frame displayed at the beginning of each GOP is controlled as the timing of forward transfer. On the other hand, at the time of playback in the reverse direction, the B0 picture or the B1 picture of the GOP that is played back before that (the GOP that is the next GOP in the order of playback in the forward direction) is played first. How many frames ahead should be transferred with respect to the playback timing, or when the B0 and B1 pictures are not played, with respect to the playback timing of the first displayed frame of each GOP, Controlled as the timing of forward transfer.

  With reference to FIGS. 63 to 68, the playback direction and playback speed in the playback process of the stream file, and the timing of forward transfer will be described.

  First, with reference to FIG. 63, a case where normal direction 1 × speed reproduction is performed will be described.

  For example, when the forward transfer of 3 frames for display is executed, the data of GOP_ID2 is forward transferred at the timing of the output request for the B12 picture of GOP_ID1. At this time, the P14 picture of the GOP before being used as a reference image for decoding the B0 picture is stored in the retained anchor frame, and the retained anchor included in GOP_ID2 before the output request for the first B0 picture of GOP_ID2 Since the decoding of the frame is completed, the reproduction process can be executed seamlessly.

  Also, for example, when the forward transfer for 2 frames of display is executed, the data of GOP_ID2 is forwarded and transferred at the output request timing of the B13 picture of GOP_ID1. At this time, the P14 picture of the GOP before being used as a reference image for decoding the B0 picture is stored in the retained anchor frame, and the retained anchor frame included in GOP_ID2 before the output request for the B0 picture at the head of GOP_ID2 Among them, since the decoding of the I2 picture used as the reference image for decoding the B0 picture is completed, the reproduction process can be executed seamlessly.

  Further, for example, when the forward transfer for one display frame is executed, the data of GOP_ID2 is forward transferred at the timing of the output request for the P14 picture of GOP_ID1. At this time, the P14 picture of the GOP before being used as a reference image for decoding the B0 picture is stored in the retained anchor frame, and the retained anchor frame included in GOP_ID2 before the output request for the B0 picture at the head of GOP_ID2 Among them, since the decoding of the I2 picture used as the reference image for decoding the B0 picture is completed, the reproduction process can be executed seamlessly.

  If the forward transfer is not executed, the I2 picture used as a reference image for decoding the B0 picture among the retained anchor frames included in the GOP_ID2 within the display 1 frame period from the output request of the first B0 picture of the GOP_ID2 and Since the decoding of the displayed B0 picture is completed, it is possible to execute the playback process seamlessly.

  Therefore, in the case where the normal direction 1 × speed reproduction is performed, the forward transfer is not necessarily required. In this case, considering the transient reproduction, the required number of anchor banks is at least three.

  Next, with reference to FIG. 64, description will be given of a case where reverse direction 1 × speed, that is, −1 × speed playback is performed.

  For example, when a forward transfer of 2 frames for display is executed (specifically, for example, a forward transfer of 2 frames is executed based on the B1 picture of GOP_ID2 as GOP_ID1), the B3 picture of GOP_ID2 The data of GOP_ID1 is forwarded and transferred at the timing of the output request. At this time, the decoding of the retained anchor frame included in GOP_ID1 is completed before the output request of the P14 picture displayed first in GOP_ID1, and the B1 of GOP_ID2 is earlier than the output request timing of the B1 picture of GOP_ID2. Since the P14 picture of GOP_ID1, which is the reference image of the picture, is decoded, it is possible to execute the playback process seamlessly.

  However, for example, when the forward transfer for one display frame is executed, the data of GOP_ID1 is forward transferred at the timing of the output request for the I2 picture of GOP_ID2. At this time, the decoding of the retained anchor frame included in GOP_ID1 is completed before the output request of the P14 picture displayed first in GOP_ID1, but within the display 1 frame from the output request timing of the B1 picture of GOP_ID2, Since the P14 picture of GOP_ID1, which is the reference picture of the B1 picture of GOP_ID2, is not decoded, the playback process cannot be executed seamlessly.

  Therefore, in the case where reverse 1x (-1x) playback is performed, in order to seamlessly display at the boundary of GOP, forward transfer is performed in the GOP (forward playback sequence) Thus, 2 frames of display are required for the timing when the B1 picture of the next GOP) is reproduced. In this case, considering the transient reproduction, the required number of anchor banks is at least six.

  Therefore, for example, in order to perform transient reproduction of −1 to + 1 × speed seamlessly, the number of anchor banks required is at least six, and there is no need for forward transfer during forward reproduction, but in the reverse direction At the time of reproduction, it is necessary to forward-transfer 4 frames for display.

  Next, with reference to FIG. 65, a case where the double speed in the positive direction is performed will be described.

  When the forward picture is double speed and the displayed picture is B1, B3, P5... In GOP_ID1, the GOP before being used as a reference picture for decoding the B0 picture is used even if forward transfer is not executed. The P14 picture is stored in the retained anchor frame, and as a reference image for decoding the B0 picture of the retained anchor frames included in GOP_ID2 within the display 1 frame period from the output request for the first B0 picture of GOP_ID2. Since the decoding of the I2 picture to be used and the B0 picture to be displayed is finished, it is possible to execute the playback process seamlessly.

  Even in the case where the display picture is I2, B4, B6... In GOP_ID1 at double speed in the forward direction, even if the forward transfer is not executed, before being used as a reference image for decoding the B1 picture. The G14 P14 picture is stored in the retained anchor frame, and the B1 picture decoding reference among the retained anchor frames included in GOP_ID2 within the display 1 frame period from the output request of the first B1 picture of GOP_ID2 Since the decoding of the I2 picture used as the image and the displayed B1 picture is completed, the reproduction process can be executed seamlessly.

  Therefore, in the case where the normal direction double speed reproduction is performed, the forward transfer is not necessarily required. In this case, considering the transient reproduction, the required number of anchor banks is at least three.

  Next, with reference to FIG. 66, a description will be given of the case where reverse double speed, that is, -2 speed reproduction is performed.

  For example, in -2 × speed display, the displayed picture is B13, P11, B9... In GOP_ID3, and two frames are displayed at the timing when the B0 picture or B1 picture of the GOP that is played back before is played back. When the forward transfer is executed, the data of GOP_ID2 is forwarded and transferred at the timing of the output request for the P5 picture of GOP_ID3. At this time, the decoding of the retained anchor frame included in GOP_ID3 is completed before the output request for the P14 picture that is first displayed in GOP_ID2, and within one frame from the output request for the B1 picture in GOP_ID3, the GOP_ID3 Since the P14 picture of GOP_ID2, which is the reference image of the B1 picture, is decoded and the B1 picture of GOP_ID3 is decoded, it is possible to execute the playback process seamlessly.

  And, for example, in -2 × speed display, the display picture is B12, B10, P8... In GOP_ID3, and the display is performed at the timing when the B0 picture or B1 picture of the GOP that is played back before is played back. When the forward transfer for two frames is executed, the data of GOP_ID2 is forward transferred at the timing of the output request for the P4 picture of GOP_ID3. At this time, before the output request of the B13 picture displayed first in GOP_ID2, decoding of the retained anchor frame included in GOP_ID3 is completed, and the output request timing of B0 picture of GOP_ID3 is earlier than B0 of GOP_ID3. Since the P14 picture of GOP_ID2, which is the reference image of the picture, is decoded and the B0 picture of GOP_ID3 is decoded within one frame from the output request of the B0 picture of GOP_ID3, it is possible to execute the playback process seamlessly.

  However, in any case, when the forward transfer for one display frame is executed, the B0 picture or B1 picture of GOP_ID3 cannot be decoded in time, so that the playback process cannot be executed seamlessly.

  Therefore, in the case where reverse double speed (-2 times normal speed) playback is performed, in order to perform seamless display at the GOP boundary, forward transfer is performed by using GOP (order of normal playback) Thus, 3 frames of display are required for the timing when the B0 picture or B1 picture of the next GOP) is reproduced. In this case, considering the transient reproduction, the required number of anchor banks is at least six.

  Therefore, for example, in order to perform transient reproduction of −2 to + 2 × speed seamlessly, the number of anchor banks required is at least six, and there is no need for forward transfer during forward reproduction, but in the reverse direction At the time of reproduction, it is necessary to perform forward transfer for two frames of display with respect to the timing at which the GOP B0 picture or B1 picture reproduced immediately before is reproduced.

  Next, with reference to FIG. 67, description will be given of a case where the triple speed in the forward direction is performed.

  When the display picture is B0, B3, B6... In the forward triple speed and GOP_ID2, the GOP before being used as a reference picture for decoding the B0 picture is used even if forward transfer is not executed. The P14 picture is stored in the retained anchor frame, and as a reference image for decoding the B0 picture of the retained anchor frames included in GOP_ID2 within the display 1 frame period from the output request for the first B0 picture of GOP_ID2. Since the decoding of the I2 picture to be used and the B0 picture to be displayed is finished, it is possible to execute the playback process seamlessly.

  And even when the forward picture is B1, B4, B7... In the forward direction 3 × speed and the displayed picture is B1, B4, B7..., Before being used as a reference picture for decoding the B1 picture. The G14 P14 picture is stored in the retained anchor frame, and the B1 picture decoding reference among the retained anchor frames included in GOP_ID2 within the display 1 frame period from the output request of the first B1 picture of GOP_ID2 Since the decoding of the I2 picture used as the image and the displayed B1 picture is completed, the reproduction process can be executed seamlessly.

  Even when the display picture is I2, P5, P8, etc. in GOP_ID2 at the triple speed in the forward direction, even if no forward transfer is executed, the output request for the first I2 picture in GOP_ID2 Since the decoding of the I2 picture that is the retained anchor frame included in GOP_ID2 is completed within the period, it is possible to seamlessly execute the reproduction process.

  Accordingly, the forward transfer is not always necessary even in the case where the forward triple speed reproduction is performed. In this case, considering the transient reproduction, the required number of anchor banks is at least three.

  Note that the P11 picture is continuously decoded in the illustrated decoding order. Among these, the first decoding is a decoding process scheduled to decode the P14 picture that is the possessed anchor frame, and the P14 picture is decoded at a timing when the decoding process is not performed for the display process. Baseband image data corresponding to the P11 picture that is executed and decoded and generated in advance is stored in the non-owner anchor bank. On the other hand, the later decoding is executed to decode the B picture for which display is instructed, and is executed in response to the B picture output request, and corresponds to the P11 picture generated by decoding. Baseband image data to be stored is stored in a non-owned anchor bank for B picture display.

  Next, with reference to FIG. 68, a description will be given of a case where reverse 3 × speed, that is, −3 × playback is performed.

  For example, the display picture is B12, B9, B6... In GOP_ID3 in -3 × speed display, and the display frame is advanced by two frames with respect to the timing when the GOP B0 picture played back one time is played back. When the transfer is executed, the data of GOP_ID2 is forward-transferred at the output request timing of the B6 picture of GOP_ID3. At this time, before the output request of the B12 picture displayed first in GOP_ID2, the decoding of the retained anchor frame included in GOP_ID2 is completed, and within one frame from the output request of the B0 picture of GOP_ID3, the GOP_ID3 Since the P14 picture of GOP_ID2, which is the reference picture of the B0 picture, is decoded and the B0 picture of GOP_ID3 is decoded, it is possible to execute the playback process seamlessly.

  However, when forward transfer for one frame of display is executed under this condition, since the decoding of the B0 picture of GOP_ID3 is not in time, the playback process cannot be executed seamlessly.

  And, for example, in -3 × speed display, the displayed picture is B13, B10, B7... In GOP_ID3, and for the timing when the B1 picture of the GOP that is played back before is played back, two frames are displayed. When the forward transfer is executed, the data of GOP_ID2 is forward transferred at the timing of the output request for the B7 picture of GOP_ID3. At this time, the decoding of the retained anchor frame included in GOP_ID2 is completed before the output request for the B13 picture displayed first in GOP_ID2, and within one frame from the output request for the B1 picture in GOP_ID3, the GOP_ID3 Since the P14 picture of GOP_ID2, which is the reference image of the B1 picture, is decoded and the B1 picture of GOP_ID3 is decoded, it is possible to execute the playback process seamlessly.

  However, at this time as well, when the forward transfer for one display frame is executed, the BOP picture of GOP_ID3 cannot be decoded in time, so that the playback process cannot be executed seamlessly.

  On the other hand, for example, when the display picture is P14, P11, P8... In GOP_ID3 at -3 × speed display, neither the B0 picture nor the B1 picture is displayed. If the transfer is executed, the data of GOP_ID2 is transferred forward at the timing of the output request of the P5 picture of GOP_ID3. At this time, since the decoding of the retained anchor frame included in GOP_ID2 is completed before the output request of the P14 picture displayed first in GOP_ID2, if the retained anchor bank of GOP_ID3 is not deleted, seamless playback processing is executed. Is possible.

  However, if the forward transfer is not executed under these conditions, the P14 picture of GOP_ID2 cannot be decoded in time, and the playback process cannot be executed seamlessly.

  Therefore, in the case where reverse 3x speed (-3x speed) playback is performed, in order to seamlessly display at the boundary of GOP, forward transfer is performed by GOP (forward playback sequence) that is played back one time before. In order, 2 frames of display are required for the timing at which playback of a picture to be played back, whichever is the first BOP picture or G1 picture of the next GOP), or B0 picture Alternatively, when none of the B1 pictures are reproduced, one display frame is required for the timing at which the reproduction of the P14 picture that is displayed first in the GOP is commanded. In this case, considering the transient reproduction, the required number of anchor banks is at least six.

  Therefore, for example, in order to perform transient playback at -3 to +3 times speed seamlessly, the number of possessed anchor banks is at least six, and forward transfer is not necessary during forward playback, but in the reverse direction At the time of playback, playback of a picture to be played back first is selected from either the B0 picture or the B1 picture of the GOP that is played back immediately before (the GOP that is the next GOP in the forward playback order). If one of the B0 picture or B1 picture is not played back, the display is advanced by one frame or two frames with respect to the timing when the playback of the first picture displayed in the GOP is commanded. Transfer is required.

  Next, with reference to FIGS. 69 to 72, the playback direction and playback speed in the clip file playback process, and the timing of forward transfer will be described.

  When playing back a clip file, the number of anchor banks required and the minimum required advance transfer timing differ depending on the structure of the clip file.

  For example, as shown in FIG. 69, when a clip stream composed of 6 frames from the beginning of the GOP is played at 1-speed, each clip is clip B if forward transfer of 2 frames is executed. And within 14 frames from the output request of the B0 picture that is first displayed in clip C, the P14 picture of the previous GOP (GOP_ID3 or GOP_ID5) that is the reference image of the B0 picture of each clip is decoded. Since the B0 picture is decoded with reference to them, it is possible to execute the reproduction process seamlessly.

  However, for example, as shown in FIG. 70, each clip consists of the last two frames of a GOP, ie, B13 and P14 pictures, and the first four frames of the next GOP, ie, B0, B1, I2, and so on. When a clip stream composed of B3 pictures is played back at 1x speed, seamless playback processing cannot be executed even if forward transfer for two frames is executed. Specifically, when forward transfer for two frames is executed, in clip B, a P11 picture that is a reference image of a B13 picture is displayed within one frame from the output request for the B13 picture that is first instructed to be displayed. The P13 picture is decoded, and the B13 picture is decoded with reference to them. However, in the clip C, the P11 picture and the P14 picture which are the reference pictures of the B13 picture from the output request of the B13 picture to be displayed first are displayed. Since it takes time for one display frame to be decoded, the B13 picture cannot be decoded in time, and the playback process cannot be executed seamlessly. That is, in this case, forward transfer for 3 frames is required.

  For example, as shown in FIG. 71, clip A is composed of 6 frames from the beginning of GOP_ID2 following GOP_ID1, and clip B is composed of the last P14 picture of GOP_ID3 and 5 frames from the beginning of GOP_ID4. When clip C is composed of 6 frames from the beginning of GOP_ID6 following GOP_ID5 and clip stream consisting of clip A, clip B, and clip C is played at 1x speed, forward transfer for 3 frames is executed. For example, since a necessary picture is decoded within one frame from the output request of the picture to be displayed first in each clip, it is possible to execute the reproduction process seamlessly. On the other hand, when forward transfer for two frames is executed, the B0 picture of clip C cannot be decoded within one frame from the output request of the B0 picture that is first displayed in clip C. Therefore, the playback process cannot be executed seamlessly.

  For example, as shown in FIG. 72, clip A is composed of the last 4 frames of GOP_ID1 and 2 frames from the beginning of GOP_ID2, and clip B is composed of 6 frames from the beginning of GOP_ID4 following GOP_ID3. When clip C is composed of 6 frames from the beginning of GOP_ID6 following GOP_ID5 and clip stream consisting of clip A, clip B, and clip C is played at 1x speed, forward transfer for 3 frames is executed. Then, since the necessary pictures are decoded within one frame from the output request of the picture to be displayed for the first time in each clip, it is possible to execute the reproduction process seamlessly. On the other hand, when the forward transfer for 2 frames is executed, the display is first commanded in each clip clip within one frame from the output request of the picture that is first displayed in each clip. Since the picture to be reproduced cannot be decoded, the reproduction process cannot be executed seamlessly.

  As described above, in clip reproduction, the required amount of forward transfer differs depending on the clip pattern. That is, the larger the amount of forward transfer, the higher the probability that decoding can be executed without delay. In this case, the storage capacity of the stream buffer 131-1 needs to be increased. That is, there is a trade-off between the memory capacity and the probability that decoding can be executed without delay. For example, in the case of a −1 to + 1 × speed reproduction of a clip file composed of a clip having a minimum clip length of 6 frames, it is preferable to perform forward transfer for about 3 frames of display.

  Next, with reference to FIGS. 73 and 74, the state of each bank of the decode, display, and frame memory will be described.

  FIG. 73 is a diagram showing the state of each bank of the decoding, display, and frame memory in the case of -2 speed reproduction of a stream. The minimum number of owned anchor banks is six in the -2 speed reproduction of a stream. Here, it is assumed that the decoder 122 can execute the decoding process of 3 to 4 frames during one frame table, and the forward transfer for the display 3 frames is executed.

  When an output request for a P5 picture of GOP_ID6 is requested, baseband image data generated by decoding the I2, P8, and P14 pictures that are the anchor frames of GOP_ID6 are stored in the anchor anchor banks 1 to 3. Then, the stream input of GOP_ID5 is started together with the output request of the P5 picture of GOP_ID6. At this time, since it is confirmed that there is no data stored in the retained anchor banks 4 to 6 by the retained anchor bank management process described above, the retained anchor of GOP_ID5 is requested before the output request of the last B1 picture of GOP_ID6. All the I2, P8, and P14 pictures that are frames are decoded, and the corresponding baseband image data is stored in the retained anchor banks 4 to 6. At that time, the P5 picture and P11 picture, which are non-owned anchor frames, are decoded for use as reference images, and the corresponding baseband image data is stored in the non-owned anchor bank.

  Then, the decoding process is performed on the frame requested to be output by the picture output request according to each picture type. For example, when displaying the retained anchor frame, the baseband image data stored in the retained anchor bank is output as it is. When displaying non-retained anchor frames, display frame decoding is performed using the baseband image data stored in the retained anchor bank as a reference image. When displaying B pictures, if necessary, for B picture display The decoded non-owned anchor frame is stored in the non-owned anchor bank and used as a reference image, and the display frame is decoded. The baseband image data for displaying the B picture and the non-owned anchor bank is B -Stored in the non-owner anchor display bank and output. In this way, the last B1 picture of GOP_ID6 and each picture of GOP_ID5 are decoded and output in time for display.

  Next, the stream input of GOP_ID4 is started together with the output request of the B4 picture of GOP_ID5. At this time, all data is stored in the retained anchor banks 1 to 6 by the retained anchor bank management process, and it is confirmed that the stored data is GOP_ID6 and GOP_ID5 data. It is detected that the GOP ID number is GOP_ID6. Therefore, when the GOP_ID4 stream is input, the GOP_ID6 data stored in the possession anchor banks 1 to 3 is deleted, and all the I2, P8, and P14 pictures that are the possession anchor frames of GOP_ID4 are decoded, and the last B0 of GOP_ID5 Prior to the picture output request, the corresponding baseband image data is stored in the retained anchor banks 1 to 3.

  Then, the same decoding process as in the last B1 picture of GOP_ID6 and each picture of GOP_ID5 is executed, so that the last B0 picture of GOP_ID5 and each picture of GOP_ID5 are in time for display. Decoded and output.

  As described above, in the -2 speed reproduction of the stream, transient reproduction can be supported by storing the baseband image data of the anchor frame for 2 GOP in the frame memory 131-3. For example, if all five anchor frames are stored in the frame memory 131-3, a total of 12 frames are required, 10 reference banks for anchor frames and 2 frames for displaying B pictures. End up. On the other hand, if every other frame has an anchor frame, it holds 6 frames of owned anchor banks, 1 frame of non-owned anchor banks, 1 frame of non-owned anchor banks for B picture display, B / non-owned anchor display Since it is sufficient to provide a total of 10 frames for 2 banks, the number of banks provided in the frame memory 131-3 can be reduced by 2 frames compared to the case where all anchor frames are stored.

  FIG. 74 is a diagram showing the state of each bank of the decoding, display, and frame memory in the case of ± 2 × speed transient playback of a clip stream.

  In FIG. 47, clip file A is composed of P8 picture of GOP_ID1 to B4 picture of GOP_ID2, clip file B is composed of B0 picture of GOP_ID4 following GOP_ID3 to P11 picture of GOP_ID2, and clip file A is followed by clip file A A description will be given of reproduction of a clip stream in which B is reproduced. However, it is assumed that GOP_ID2 and GOP_ID4 latter half of GOP_ID4 which are unnecessary for reproduction of the clip file are not input to the memory 131.

  In the ± 2 × speed transient reproduction of a clip stream constituted by such clips, the minimum number of possessed anchor banks is nine. Here, it is assumed that the decoder 122 can execute the decoding process of 3 to 4 frames during one frame table, and that the forward transfer for the display of 3 frames is executed.

  When playback is performed at +2 times normal speed (forward direction) in the portion corresponding to clip file A, when an output request for P14 picture of GOP_ID1 is made, possession of I2, P8, P14 pictures and GOP_ID2 that are anchor frames of GOP_ID1 Baseband image data generated by decoding an I2 picture that is an anchor frame is stored in the retained anchor banks 1 to 4.

  Then, together with the output request for the P14 picture of GOP_ID1, the stream input of GOP_ID3 and GOP_ID4 of clip file B is started. At this time, it is confirmed that there is no data stored in the retained anchor banks 5 to 9 by the retained anchor bank management process described above, so the B0 picture of GOP_ID4, which is the first picture displayed in the clip file B, is displayed. Prior to the output request, the I2, P8, and P14 pictures that are the retained anchor frames of GOP_ID3 and the I2 and P8 pictures that are the retained anchor frames of GOP_ID4 are all decoded, and the corresponding baseband image data is stored in the retained anchor banks 5 to 5. 9 is stored. At that time, each P5 picture and P11 picture, which are non-owner anchor frames, are decoded for use as reference images, and the corresponding baseband image data is stored in the non-owner anchor bank. Then, the frame requested to be output by the picture output request is decoded according to each picture type in the same manner as described above.

  When the playback direction is reversed when the display of the B4 picture of clip B is commanded, the GOP displayed next is GOP_ID2, but the possessed anchor frames of GOP_ID1 and GOP_ID2 of clip A are retained. Since it is stored in the anchor banks 1 to 4, it is not necessary to input a new stream. Then, after the I2 picture and B0 picture of clip B are displayed, the B3 picture and B1 picture of GOP_ID2 of clip A are displayed, and the playback direction is reversed again. At this time, the GOP to be displayed next is GOP_ID4. However, since the retained anchor frames of GOP_ID3 and GOP_ID4 of clip B are stored in the retained anchor banks 5 to 9, it is not necessary to input a new stream.

  In transient playback, when the playback direction is reversed and the baseband image data of the frame commanded for display is present in the B / non-owner anchor display bank, the baseband is not re-decoded and Image data is output. Specifically, at the time of the BOP picture output request of GOP_ID4 after the first inversion described with reference to FIG. 74, the baseband image data corresponding to the B0 picture is stored in the B / non-owner anchor display bank 1 So there is no need to decode.

  In playback of a clip file, the number of anchor frames included differs depending on the configuration of the clip stream, and therefore the possessed anchor frames required to support transient playback differ. Basically, even if the number of GOP anchor frames constituting each clip is different, the number of possessed anchor banks that can store 4 GOP anchor frames in the retained anchor bank at any playback position is secured. When the retained anchor banks for each GOP are packed and set by the retained anchor bank management process, smooth transient reproduction can be executed.

  In the above description, the case where the retained anchor frame is set every other picture from the I picture has been described. However, the retained anchor frame may be set every other number of pictures.

  FIG. 75 shows a GOP holding / non-holding anchor frame configuration diagram when the holding anchor frame is every two pictures, three pictures, or every four pictures.

  FIG. 76 shows that the retained anchor frame is every two pictures, three pictures, or four pictures, and in the frame memory 131-3, the reference bank for X frames and the display bank for two frames, that is, X + 2 frames. It is a bank allocation diagram in the frame bank.

  Reference banks 1 to X-3, which are both owned and non-owned anchor banks, use both owned anchor banks and non-owned anchor banks, and are used as reference images for decoding owned anchor frames and non-owned anchor frames. Baseband image data corresponding to a frame is stored. The baseband image data corresponding to the possessed anchor frame stored in the owned / unowned anchor combined bank is not deleted or overwritten unless the GOP data is deleted, but stored in the retained / nonowned anchor combined bank. The baseband image data corresponding to the non-retained anchor frame may be overwritten with the baseband image data corresponding to the other retained anchor frame after the role as the reference image ends. Then, similarly to the case described with reference to FIG. 51, the non-owner anchor bank stores baseband image data corresponding to the non-owner anchor frame used as a reference image for decoding the retained anchor frame. Then, two frames of non-retained anchor banks for display for storing the baseband image of the non-retained anchor frame used as a reference image when the displayed B picture or P picture is decoded are required. The B / non-owner anchor display bank, which is a display-only bank, is the same as that described with reference to FIG.

  When anchor frames are held every 2 pictures, 3 pictures, or every 4 pictures, the possessed anchor bank necessary for the input GOP is stored in step S661 of the retained anchor bank management process described with reference to FIG. The number of numbers is different.

  Next, with reference to FIG. 77, a description will be given of an anchor frame decoding procedure when anchor frames are held every two pictures.

  The baseband image data generated by decoding the I2 picture that is the possessed anchor frame is stored in the bank that also possesses and does not possess the anchor, and then the baseband image that is generated by decoding the P5 picture that is the retained anchor frame. Since the band image data is a reference image of the non-owned anchor frame, the band image data is stored in the bank that holds both the owned and non-owned anchors. Then, since the baseband image data generated by decoding the P8 picture that is a non-owned anchor frame is a reference image of the owned anchor frame, it is stored in the non-owned anchor bank. Next, the baseband image data generated by decoding the P11 picture that is the possessed anchor frame is stored in the retained / non-owned anchor combined bank. Here, since the baseband image data corresponding to the P5 picture that is the reference image of the P8 picture that is the stored non-owned anchor frame has already finished its role as the reference image, it corresponds to the P11 picture. The baseband image data is overwritten and stored on the baseband image data corresponding to the P5 picture of the owned / non-owned anchor combined bank.

  In this way, it is possible to hold baseband image data corresponding to as many GOP possession anchor frames as possible without wasting the number of reference banks.

  Next, the decoding processing procedure executed using the baseband image data corresponding to the retained anchor frame stored in the retained anchor bank as described with reference to FIG. 77 will be described with reference to FIG.

  For example, when a B7 picture that is decoded using a non-owned anchor frame as a reference image is decoded, a P5 picture that is a non-owned anchor frame is a baseband corresponding to an I2 picture stored in the owned / non-owned anchor combined bank. It is decoded with reference to the image data and stored in the non-owner anchor bank for display. Next, the P8 picture that is the non-owner anchor frame is decoded with reference to the baseband image data corresponding to the P5 picture stored in the display non-owner anchor bank, and is displayed in the display non-owner anchor bank. Stored. The B7 picture is decoded with reference to the baseband image data corresponding to the P5 picture and the P8 picture stored in the non-owner anchor bank for display, stored in the non-owner anchor display bank, and output. Is done.

  Even when the anchor frame is held every 3 pictures or every 4 pictures, the decoding process is executed basically in the same manner as described with reference to FIGS. 77 and 78.

  Next, the output process 2 executed in step S608 of FIG. 55 when an anchor frame is held every 2 pictures, 3 pictures, or 4 pictures will be described with reference to the flowcharts of FIGS.

  In steps S811 to S813, processing similar to that in steps S761 to S763 in FIG. 60 is executed.

  That is, it is determined whether or not the requested anchor frame is a picture within the GOP range where the retained anchor frame has already been decoded, and is not a picture within the GOP range where the retained anchor frame has already been decoded. In this case, normal decoding processing is executed in order from the reference image.

  If the retained anchor frame is a picture within the GOP range that has already been decoded, it is determined whether the requested output is the retained anchor frame.

  If it is determined in step S813 that the requested output is a retained anchor frame, in step S814, the decode controller 153 controls the selector 155 to retain / non-retained anchors in the frame memory 131-3. The corresponding retained anchor frame is read from the dual-purpose bank and output, and the process returns to step S608 in FIG. 55 and proceeds to step S609.

  If it is determined in step S813 that the requested output is not a retained anchor frame, in step S815, the decode controller 153 determines that the output is requested based on the control signal supplied from the CPU 121. It is determined whether the frame is a non-owner anchor frame. If it is determined in step S815 that the output is not requested for the non-owned anchor frame, the process proceeds to step S823 described later.

  If it is determined in step S815 that the output is requested for a non-owned anchor frame, in step S816, the decode controller 153 outputs the output to the B / non-owned anchor display bank of the frame memory 131-3. It is determined whether the requested non-owner anchor frame is stored.

  If it is determined in step S816 that the non-owned anchor frame requested for output is not stored in the B / non-owned anchor display bank, in step S817, the decode controller 153 determines that the non-owned anchor frame requested for output. It is determined whether the reference image of the frame is only the retained anchor frame.

  If it is determined in step S817 that the reference image of the non-owned anchor frame requested to be output is not only the retained anchor frame, in step S818, the decode controller 153 selects one of the non-held anchor banks for display. Is set as the storage destination of the baseband image after decoding of the non-owned anchor frame that becomes the reference image of the corresponding non-owned anchor frame.

  In step S819, the decoding controller 153 refers to the decoding related information, controls the decoding of the non-retained anchor frame serving as the reference image, and displays the decoded baseband image data generated as a non-retained anchor bank for display. Control storage of That is, the decode controller 153 controls the selector 152 to supply a non-owned anchor frame serving as a reference image to the decode processing unit 154 and also controls the selector 156 to hold / non-hold the frame memory 131-3. The baseband image data corresponding to the possessed anchor frame stored in the anchor combined bank is supplied to the decode processing unit 154. The decoding processing unit 154 decodes the non-owned anchor frame serving as the reference image using the baseband image data corresponding to the owned anchor frame, and supplies the decoded non-owned anchor frame to the selector 155. The decode controller 153 controls the selector 155 to store the non-owned anchor frame serving as the decoded reference image in the non-held anchor bank for display in the frame memory 131-3.

  In step S817, when it is determined that the reference image of the non-retained anchor frame requested to be output is only the retained anchor frame, or after the process of step S819 ends, in step S820, the decode controller 153 The non-owner anchor display bank is set as the storage destination of the baseband image after decoding the corresponding non-owner anchor frame.

  In step S821, the decode controller 153 refers to the decoding related information of the corresponding non-owned anchor frame in the stream buffer GOP queue, refers to the reference image indicated by the forward reference index number, and selects the corresponding non-owned anchor frame. It is decoded and stored in the B / non-owner anchor display bank of the frame memory 131-3.

  If it is determined in step S816 that the non-owner anchor frame requested to be output is stored in the B / non-owner anchor display bank, or after the process of step S821 is completed, the decode controller 153 is determined in step S822. Controls the selector 155 to read out and output the corresponding non-owned anchor frame from the B / non-owned anchor display bank of the frame memory 131-3, and the process returns to step S608 in FIG. Proceed to

  If it is determined in step S815 that the output is not requested to be a non-owned anchor frame, in step S823, the decode controller 153 determines whether the output is requested for the first B picture of the GOP. Judge whether or not. If it is determined in step S823 that the output is not requested for the B picture at the head of the GOP, that is, it is a B picture for which a reference image exists in the GOP other than the head of the GOP, The process proceeds to step S832, which will be described later.

  If it is determined in step S823 that the output is requested for the first B picture of the GOP, in step S824, the decode controller 153 determines that the B / non-owner anchor display bank outputs the requested B picture. It is determined whether a picture is stored. If it is determined in step S824 that the B picture requested to be output is stored in the B / non-owner anchor display bank, the process proceeds to step S831 described later.

  If it is determined in step S824 that the B picture that is requested to be output is not stored in the B / non-owner anchor display bank, in step S825, the decode controller 153 determines that the It is determined whether or not both reference images of the B picture to be stored are stored. If it is determined in step S825 that both reference images of the corresponding B picture are stored in the retained anchor bank, the process proceeds to step S829 described later.

  In step S825, when it is determined that both reference images of the corresponding B picture are not stored in the owned / non-owned anchor combined bank, in step S826, the decode controller 153 displays the display non-owned anchor bank. It is determined whether one reference picture of the B picture requested to be output is stored. If it is determined in step S826 that one reference image of the B picture requested to be output is stored in the display non-owner anchor bank, the process proceeds to step S829 described later.

  If it is determined in step S826 that one reference image of the B picture requested to be output is not stored in the display non-owner anchor bank, in step S827, the decode controller 153 displays the display non-owner anchor bank. Is set as the storage destination of the baseband image after decoding of the non-owned anchor frame that becomes the reference image of the corresponding B picture.

  In step S828, the decode controller 153 refers to the decode related information, controls the selector 152 to supply the non-owned anchor frame serving as the reference image to the decode processing unit 154, and, if necessary, the selector 156. And the baseband image data corresponding to the owned anchor frame or the non-owned anchor frame stored in the owned / non-owned anchor combined bank of the frame memory 131-3 is supplied to the decode processing unit 154. The decoding processing unit 154 decodes a non-owned anchor frame that becomes a reference image using the supplied reference image, and supplies the decoded non-owned anchor frame to the selector 155. The decode controller 153 controls the selector 155 to store the non-owned anchor frame serving as the decoded reference image in the display non-owned anchor bank.

  If it is determined in step S825 that both reference images of the corresponding B picture are stored in the owned / non-owned anchor combined bank, output is requested to the display non-owned anchor bank in step S826. When it is determined that one reference image of the B picture is stored, or after the process of step S828 is finished, in step S829, the decode controller 153 sets the B / non-owned anchor display bank to the corresponding B picture. Is set as the storage destination of the baseband image after decoding.

  In step S830, the decoding controller 153 refers to the decoding related information, controls the selector 152 to supply the corresponding B picture to the decoding processing unit 154, and controls the selector 156 as necessary. Stored in the owned anchor frame serving as a reference image of the corresponding B picture stored in the owned / non-owned anchor combined bank of the frame memory 131-3, or stored in the non-owned anchor bank for display of the frame memory 131-3 The non-owner anchor bank decoded in step S828 is supplied to the decoding processing unit 154. The decode processing unit 154 decodes the corresponding B picture using the supplied reference image and supplies the decoded B picture to the selector 155. The decode controller 153 controls the selector 155 to store the decoded B picture in the B / non-owner anchor display bank.

  In step S824, when it is determined that the B picture that is requested to be output is stored in the B / non-owner anchor display bank, or after the process of step S830 ends, in step S831, the decode controller 153 The selector 157 is controlled to read out and output the corresponding B picture from the B / non-owner anchor display bank of the frame memory 131-3, and the process returns to step S608 in FIG. 55 and proceeds to step S609. .

  If it is determined in step S823 that the output is not requested for the B picture at the head of the GOP, that is, it is a B picture for which a reference image exists in the GOP other than the head of the GOP, in step S832. The decode controller 153 determines whether or not the B picture requested to be output is stored in the B / non-owner anchor display bank. If it is determined in step S832 that the B picture requested to be output is stored, the process proceeds to step S843 to be described later.

  If it is determined in step S832 that the B picture requested to be output is not stored in the B / non-owner anchor display bank, in step S833, the decode controller 153 determines one of the B pictures requested to be output. It is determined whether the reference image is a retained anchor frame. If it is determined in step S833 that one reference picture of the B picture requested to be output is a retained anchor frame, the process proceeds to step S838 described later.

  If it is determined in step S833 that none of the reference pictures of the B picture requested to be output are owned anchor frames, in step S834, the decode controller 153 requests the display non-owned anchor bank to output. It is determined whether or not both reference pictures of the B picture are stored. If it is determined in step S834 that both reference images of the B picture requested to be output are stored in the B picture display non-owned anchor bank, the process proceeds to step S841 described later.

  If it is determined in step S834 that both reference images of the B picture requested to be output are not stored in the display non-owner anchor bank, in step S835, the decode controller 153 It is determined whether one reference image of the B picture requested to be output is stored. If it is determined in step S835 that one reference image of the B picture requested to be output is stored in the non-display anchor bank for display, the process proceeds to step S839 described later.

  In step S835, if it is determined that none of the reference images of the B picture requested to be output are stored in the non-display anchor bank for display, the decode controller 153 determines in step S836 that the two display non-display anchor banks. The possessed anchor bank is set as a storage destination of baseband images after decoding of the two non-retained anchor frames that are reference images of the corresponding B picture.

  In step S837, the decode controller 153 refers to the decode related information, controls the selector 152 to supply the non-owned anchor frame serving as the reference image to the decode processing unit 154, and, if necessary, the selector 156. And the reference image data such as the retained anchor frame stored in the retained anchor bank of the frame memory 131-3 is supplied to the decode processing unit 154. The decoding processing unit 154 decodes two non-owned anchor frames that become reference images using the supplied reference image data, and supplies the decoded non-owned anchor frames to the selector 155. The decode controller 153 controls the selector 155 to store the non-owned anchor frame serving as the decoded reference image in the B picture display non-owned anchor bank, and the process proceeds to step S841 described later.

  If it is determined in step S833 that one reference picture of the B picture requested to be output is a retained anchor frame, in step S838, the decode controller 153 requests the display non-retained anchor bank to output. It is determined whether one reference image of the B picture is stored. If it is determined in step S835 that one reference image of the B picture requested to be output is stored in the non-display anchor bank for display, the process proceeds to step S841 described later.

  If it is determined in step S835 that one reference image of the B picture requested to be output is stored in the display non-owner anchor bank, or in step S838, the output is output to the display non-owner anchor bank. When it is determined that one reference image of the requested B picture is not stored, in step S839, the decode controller 153 sets the display non-owned anchor bank as one reference image of the corresponding B picture. Is set as the storage destination of the baseband image after decoding of the non-owned anchor frame.

  In step S840, the decode controller 153 refers to the decode related information, controls the selector 152 to supply the non-owned anchor frame serving as the reference image to the decode processing unit 154 and, if necessary, the selector 156. And the reference image data such as the retained anchor frame stored in the retained anchor bank of the frame memory 131-3 is supplied to the decode processing unit 154. The decode processing unit 154 decodes a non-owned anchor frame that becomes a reference image using the supplied reference image data, and supplies the decoded non-owned anchor frame to the selector 155. The decode controller 153 controls the selector 155 to store the non-owned anchor frame serving as the decoded reference image in the B picture display non-owned anchor bank.

  If it is determined in step S834 that both reference images of the B picture requested to be output are stored in the display non-owner anchor bank, output is requested to the display non-owner anchor bank in step S838. When it is determined that one of the reference images of the B picture stored is stored, or after the process of step S837 or step S840 is completed, in step S841, the decode controller 153 selects the B / non-owner anchor display bank. , It is set as the storage destination of the baseband image after decoding the corresponding B picture.

  In step S842, the decode controller 153 refers to the decode related information, controls the selector 152 to supply the corresponding B picture to the decode processing unit 154, and controls the selector 156 as necessary. The possessed anchor frame that is the reference image of the corresponding B picture stored in the retained anchor bank of the frame memory 131-3, or the non-owned anchor bank stored in the display-unowned anchor bank of the frame memory 131-3 Is supplied to the decoding processing unit 154. The decode processing unit 154 decodes the corresponding B picture using the supplied reference image data and supplies the decoded B picture to the selector 155. The decode controller 153 controls the selector 155 to store the decoded B picture in the B / non-owner anchor display bank.

  If it is determined in step S832 that the B picture requested to be output is stored, or after the process of step S842 is completed, the decode controller 153 controls the selector 157 in step S843 to control the frame memory. The corresponding B picture is read out from the B / non-owner anchor display bank 131-3 and output, and the process returns to step S608 in FIG. 55 and proceeds to step S609.

  By such processing, even when the anchor frame is held every 2 pictures, 3 pictures, or 4 pictures, the decoding process is performed using the baseband image data stored in advance in the frame memory 131-3. Since it is executed, the frame memory is effectively used to store as many GOP possession anchor frames as possible, and playback output from the playback output command in normal stream playback, clip playback variable speed playback and transient playback In addition to improving the response until the playback is performed, it is possible to widen the range of the playback start position where the response from the playback output command to the playback output becomes higher in scrub playback and the like as much as possible.

  In addition, when the anchor frame is held every 2 pictures, 3 pictures, or every 4 pictures, the number of times of decoding necessary for displaying one frame is larger than when the anchor frame is held every other picture. Probability is high. For this reason, the decoder 122 has a higher performance when the anchor frame is held every two, three or four pictures than when the anchor frame is held every other picture, that is, displays one frame. It is more preferable that the number of frames that can be decoded is large during this period.

  In this way, by preferentially decoding and holding a part of the anchor frames without holding all the anchor frames, it is possible to effectively use the frame memory and to make as many GOPs as possible. The possessed anchor frame can be accumulated. Further, as described above, by performing decode scheduling and bank management, it is possible to improve the response from the reproduction output command to the reproduction output.

  On the other hand, when all the anchor frames are held, more frame memories are required than when a part of the anchor frames is preferentially decoded and held. For example, if all anchor frames are held with the same number of owned anchor frames, the number of anchor frames stored in the owned anchor bank is lower than when a part of the anchor frames is preferentially decoded and held. Since only a small number of GOP possession anchor frames can be held, the range of the reproduction start position where the response from the reproduction output command to the reproduction output becomes high becomes narrow. During scrub playback, if you can store many GOP anchor frames in the owned anchor bank, you can widen the playback start position range so that the response until playback is output is increased, and the actual frame The rate can be improved.

  When all anchor frames are retained, for example, in clip playback, the number of retained anchor frames necessary to enable transient playback differs depending on the clip stream configuration, and sufficient retained anchors are available. When the number of frames cannot be prepared, the reproduction may not be in time for the transient reproduction, and the display image may freeze.

  That is, in order to prevent the display from freezing during the transient reproduction of the clip stream, it is preferable to leave the retained anchor bank without being overwritten as much as possible. Therefore, if the owned anchor bank is set to all anchor frames, depending on the number of owned anchor banks, overwriting of the anchor frame may occur during clip stream transient playback such as ± 2x speed or ± 3x speed. Resulting in.

  Therefore, in particular, in the transient reproduction of the clip stream, it is preferable to set only a part of the anchor frame as the retained anchor frame so that the anchor frame is not overwritten as much as possible even if the retained anchor bank is small.

  In particular, when the decoding capability is at a level at which decoding processing of about 3 to 4 frames can be performed in the period of one frame display, if every other anchor frame is set as a holding anchor frame, the decoding response and the holding anchor bank It is possible to achieve both suppression of the number and is preferable.

  Referring to FIG. 82, in the same clip stream as described with reference to FIG. 74, all anchor frames are held anchor frames, and each of the banks of decoding, display, and frame memory in the case of ± 2 × speed transient playback is used. The state will be described.

  That is, in FIG. 82, similar to the case of FIG. 47, the clip file A is composed of the P8 picture of GOP_ID1 to the B4 picture of GOP_ID2, and the clip file B is composed of the B0 picture of GOP_ID4 and the P11 picture of GOP_ID2 following GOP_ID3. A description will be given of the reproduction of a clip stream in which the clip file B is reproduced after the clip file A. However, it is assumed that GOP_ID2 and GOP_ID4 latter half of GOP_ID4 which are unnecessary for reproduction of the clip file are not input to the memory 131.

  Here, it is assumed that the number of frames that can be stored in the frame memory is the same as in FIG. 47, but the non-owned anchor bank for B picture display is not necessary. It is assumed that there are 11 frames, which is 2 frames more than the above. Here, it is assumed that the decoder 122 can execute the decoding process of 3 to 4 frames during one frame table, and that the forward transfer for the display of 3 frames is executed.

  When playback is performed at +2 times normal speed (forward direction) in the portion corresponding to clip file A, when an output request for a P14 picture of GOP_ID1 is made, I2, P5, P8, P11, and P14 pictures that are possessed by GOP_ID1 The baseband image data generated by decoding the I2 and P5 pictures, which are the retained anchor frames of GOP_ID2, are stored in the retained anchor banks 1 to 7.

  Then, together with the output request for the P14 picture of GOP_ID1, the stream input of GOP_ID3 and GOP_ID4 of clip file B is started. At this time, it is confirmed that there is no data stored in the retained anchor banks 8 to 11 by the retained anchor bank management process described above, but the I2, P5, P8, P11, and P14 pictures that are retained anchor frames of GOP_ID3 Since the number of banks is insufficient to store all the baseband image data corresponding to, the baseband image data corresponding to the retained anchor frames of GOP_ID1 is deleted from the retained anchor banks 1 to 5, and the retained anchor frames of GOP_ID3 I2, P5, P8, P11, and P14 pictures are decoded, and baseband image data corresponding to these pictures are stored in the retained anchor banks 8 to 11 and the retained anchor bank 1.

  Subsequently, the I2, P5, P8, and P11 pictures that are the possessed anchor frames of GOP_ID4 are decoded, and the baseband image data corresponding to these are stored in the retained anchor banks 2 to 5.

  When the playback direction is reversed when the display of the B4 picture of clip B is commanded, the next GOP to be displayed is GOP_ID2, but possessing GOP_ID1 necessary for decoding the frame of GOP_ID2 Since the baseband image data corresponding to the anchor frame has been deleted from the retained anchor banks 1 to 5, it is necessary to decode the retained anchor frame of GOP_ID1 and store it in the retained anchor bank. It is detected that GOP_ID1 and GOP ID numbers that are required to secure possession anchor banks are separated by GOP_ID4, and that GOP_ID1 and GOP ID numbers that are separated next are GOP_ID3. . Therefore, the GOP_ID4 data stored in the retained anchor banks 2 to 5 and the GOP_ID3 data stored in the retained anchor banks 8 to 1 are deleted, and decoding of the retained anchor frame of GOP_ID4 is started. However, since the next frame to be displayed is the I2 picture of GOP_ID4, when the data of GOP_ID4 is deleted from the possessed anchor bank, the I2 picture of GOP_ID4 cannot be displayed.

  On the other hand, in order to save the number of possessed anchor frames required per 1 GOP, in the frame memory bank management in which only a part of the anchor frames are retained anchor banks, there is an opportunity that the anchor frames are deleted due to overwriting. Therefore, it is possible to prevent the reproduced image from freezing even during transient reproduction.

  Thus, by storing only a part of the anchor frame as the possessed anchor frame and storing the anchor frame of a wide range of GOPs in the frame memory, the frame memory can be reduced when the decoding capability is the same. In addition, by storing only a part of the anchor frame as the possessed anchor frame and storing the anchor frame of a wide range of GOPs in the frame memory, higher speed reproduction can be performed without causing the freeze of the reproduced image, Smooth forward / reverse inversion reproduction (transient reproduction) at higher speed reproduction can be performed, and scrub reproduction can quickly output a wider range of images.

  Furthermore, it goes without saying that in the playback apparatus 101, the interval between anchor frames stored in the frame memory 131-3 may be made variable in accordance with the decoding capability of the decoder 122.

  Incidentally, in the processing described with reference to FIGS. 44 to 82, when new GOP data is supplied to the stream buffer 131-1, or already supplied to the stream buffer 131-1, When the GOP decoding process that does not store the retained anchor frame corresponding to is started, it is detected whether or not the retained anchor bank is empty, and if there is not the required number of empty banks, the GOP_ID of the input GOP The GOP possession anchor frame with the most distant GOP_ID number is deleted until the required number of frames are available, the new GOP possession anchor frame is decoded, and the corresponding baseband image data is retained by the possession anchor bank. Was supposed to be stored.

  In this process, since the GOP and anchor bank corresponding to the anchor frame to be erased are determined based on the state of the anchor bank at the time when the head of the GOP with the stream is input, for example, as described with reference to FIG. For example, the baseband image data corresponding to the GOP possession anchor frame necessary for the next display is erased from the possession anchor bank, and the display cannot be performed, or the anchor frame of the GOP is re-decoded. The response could get worse.

  That is, in the processing described with reference to FIGS. 44 to 82, when new data is pushed in the stream buffer GOP queue, the decode controller 153 has the GOP_ID number farthest from the GOP_ID number of the GOP currently being reproduced. It has been described that GOP information having POP is POP. In this case, when the decode related information added to the head of the pushed data is acquired, the schedule is performed based on the information. Therefore, when the head of the GOP data is input, the management of the anchor bank is performed in GOP units. Executed. Then, when an anchor frame is input, a reserved anchor bank that is secured is allocated, and after the decoding process is executed at a predetermined timing (a period in which the decoding process for display is not executed), the obtained baseband is obtained. Image data is stored in the assigned anchor bank.

  For example, as shown in FIG. 83, ten owned anchor banks are provided, and bank 1 to bank 3 store baseband image data corresponding to GOP (N-1) owned anchor frames. 4 to Bank 6 store baseband image data corresponding to the GOP (N) possessed anchor frame, and Banks 7 to 9 store baseband image data corresponding to the GOP (N + 1) retained anchor frame. A case where new GOP data is supplied in the stored state will be described. For example, when GOP (N + 3) is supplied, the baseband image data corresponding to the GOP (N-1) possession anchor frame is deleted, and the GOP (N + 3) possession anchor frame is supported in banks 1 to 3. Baseband image data to be stored is stored. On the other hand, when GOP (N-3) is supplied, the baseband image data corresponding to the anchor frame of GOP (N + 1) is deleted, and GOP (N-3) is stored in banks 10 to 2. Baseband image data corresponding to the retained anchor frame is stored.

  By the way, as shown in FIG. 84, for example, when a display error occurs, the fifth frame and the tenth frame of GOP (N + 1) exist as frames waiting to be displayed under the control of the decode controller 153. Next, in a state where the 8th frame of GOP (N-1) is to be decoded and waiting to be displayed, GOP (N-3) is input and corresponds to the possessed anchor frame of GOP (N + 1) When baseband image data is deleted from the owned anchor bank, the 5th and 10th frames of the GOP (N + 1) waiting to be displayed cannot be displayed, or the GOP (N + 1) owned anchor frame is Due to the time required for decoding, the display may be slow.

  On the other hand, when new data is pushed, not only the currently playing GOP, but also the GOP that is waiting for the display command after the decoding of the anchor frame is completed, or already included in the decoding schedule For GOPs that have the GOP_ID number that is farthest from the GOP_ID number of the currently playing GOP, control is performed so that the GOP_ID number is not POP. More preferably.

  Referring to FIGS. 85 to 91, when new data is pushed, not only the GOP currently being played back, but also the GOP in a state where the decoding of the anchor frame is finished and waiting for the display command, or already decoded. As for the GOP included in the schedule, a case will be described in which control is performed so that even a GOP having the GOP_ID number farthest from the GOP_ID number of the GOP currently being reproduced is not POPped.

  Here again, the decode controller 153 is selected not every anchor frame but every other anchor frame from the I picture or every few frames as described with reference to FIG. 49, for example. Only the anchor frame is set as the possessed anchor frame, and the selector 152 is controlled so that the decoding processing unit 154 decodes in advance during the idle time of the decoding process before the B picture is decoded.

  As described above, the decoding processing unit 154 decodes one frame with a sufficiently short time (for example, about 1/3 to 1/4 of the display time of one frame) with respect to the display time of one frame. Is possible. Accordingly, the decode controller 153 schedules the decode timing not in units of 1 GOP but in units of frames so that the number of retained anchor frames that can be held in the frame memory 131-3 is decoded in advance. Then, the selector 152, the selector 155, and the selector 156 are controlled so that the decoded anchor frame is supplied to and held in a predetermined bank of the frame memory 131-3.

  When new data is pushed, not only the currently playing GOP but also the GOP that is waiting for the display command after the decoding of the anchor frame is finished, or the GOP already included in the decoding schedule, Even when the GOP having the GOP_ID number farthest from the GOP_ID number of the currently playing GOP is controlled so as not to be POP, compared to the case described with reference to FIGS. The information erasing method, information erasing timing, and anchor bank information adding timing differ from the retained anchor bank.

  In order to realize such control, whether or not the GOP corresponding to the information to be deleted from the retained anchor bank is a GOP including a frame in the display schedule, and whether or not the GOP is a GOP in the decoding schedule. It is necessary to judge whether.

  Therefore, the decoding schedule is performed at the time when the retained anchor frame is input, but in order to make a space in the retained anchor bank in advance, a part of the stored data is not erased, and when the retained anchor frame is decoded, An empty bank of an anchor bank shall be secured.

  That is, as shown in FIG. 85, ten anchor banks are provided, and bank 1 to bank 3 store baseband image data corresponding to the GOP (N-1) anchor frames. 4 to Bank 6 store baseband image data corresponding to the GOP (N) possessed anchor frame, and Banks 7 to 9 store baseband image data corresponding to the GOP (N + 1) retained anchor frame. When GOP (N-3) is supplied in the stored state, first, when decoding the I2 picture that is the retained anchor frame to be decoded first, the bank 10 that is an empty bank of the retained anchor bank is secured. The baseband image data corresponding to the I2 picture obtained by decoding is stored.

  At this time, P5 picture and B10 picture, which are frames included in GOP (N + 1), are waiting for a display command, and P8 picture, which is a frame included in GOP (N-1), has already been decoded. Since it is included in the schedule, the baseband image data corresponding to the GOP (N + 1) and GOP (N-1) possessed anchor frames is not deleted. That is, in this state, what can be deleted from the possessed anchor bank is baseband image data corresponding to the retained anchor frame of GOP (N).

  Therefore, when the P8 picture that is the retained anchor frame decoded next to the I2 picture is decoded in the GOP (N-3), an empty bank of the retained anchor bank is secured, so that as shown in FIG. N) baseband image data corresponding to the possessed anchor frame is deleted, and banks 4 to 6 become empty banks. Then, baseband image data corresponding to the P8 picture and the P14 picture obtained by decoding are stored in the banks 4 and 5.

  In this way, by protecting the baseband image data corresponding to the retained anchor frame included in GOP (N + 1) so that it is not deleted, the frame waiting for display included in GOP (N + 1) Can be displayed immediately.

  As shown in FIG. 87, ten owned anchor banks are provided, and bank 1 to bank 3 store baseband image data corresponding to the GOP (N-1) owned anchor frames. 4 to Bank 6 store baseband image data corresponding to the GOP (N) possessed anchor frame, and Banks 7 to 9 store baseband image data corresponding to the GOP (N + 1) retained anchor frame. When GOP (N-3) is supplied in the stored state (the retained anchor bank is the same as that in FIG. 85 described above), first, decoding of the I2 picture that is the retained anchor frame that is decoded first. Sometimes, the baseband image data corresponding to the I2 picture obtained by obtaining and decoding the bank 10 which is a vacant bank of the possessed anchor bank is secured. There are stored.

  When baseband image data corresponding to an I2 picture is stored, a P5 picture that is a frame included in GOP (N + 1) waits for a display command, and P8 that is a frame included in GOP (N-1). From the state in which the picture is already included in the decoding schedule, the P5 picture that is the frame included in GOP (N + 1) is displayed, and the P8 picture that is the frame included in GOP (N-1) is waiting to be displayed. When it becomes a state, the baseband image data corresponding to the GOP (N-1) retained anchor frame cannot be deleted, but not only the baseband image data corresponding to the GOP (N) retained anchor frame, The baseband image data corresponding to the GOP (N + 1) possessed anchor frame can also be deleted. Therefore, in this state, the GOP (N + 1) having the GOP_ID number far from the newly supplied GOP (N−3) is deleted from the possessed anchor bank.

  In other words, since the timing for securing the vacant anchor bank is immediately before the decoding process, it is highly possible that many erasable retained anchor banks can be detected, and the necessary frames cannot be displayed. In addition to reducing the possibility, the baseband image data corresponding to the possessed anchor frame of the GOP in the vicinity of the newly input GOP can be left in the retained anchor bank as much as possible.

  Therefore, when the P8 picture that is the retained anchor frame decoded next to the I2 picture is decoded in the GOP (N-3), an empty bank of the retained anchor bank is secured, so that as shown in FIG. Since the baseband image data corresponding to the possessed anchor frame of (N + 1) is deleted and the banks 7 to 9 become empty banks, the baseband image data corresponding to the P8 picture and the P14 picture obtained by decoding are Stored in bank 7 and bank 8.

  In this way, when there are a plurality of GOPs corresponding to the retained anchor frames that can be deleted, the processing is separated from the newly supplied GOP (N-3) in the same manner as the processing described with reference to FIGS. The baseband image data of the retained anchor frame included in the GOP having the GOP_ID number is preferentially deleted from the retained anchor bank.

  Further, in the processing described with reference to FIGS. 44 to 82, since the retained anchor frames are written in the retained anchor bank in GOP units, information on the number of anchor frames included in the GOP is necessary as decoding related information. . Compared to this case, in the processing described with reference to FIGS. 85 to 88, since the retained anchor frame is written to the retained anchor bank for each frame instead of the GOP unit, the anchor included in the GOP is used as decoding related information. No information on the number of frames is required.

  That is, in the processing described with reference to FIGS. 85 to 88, even when a stream without information on the number of anchor frames is decoded, the owned anchor bank is managed with simple control to improve the display response. In addition, it is possible to reduce the possibility of occurrence of a situation where display is impossible.

  Next, referring to the flowchart of FIG. 89, only the decoding schedule is performed when the retained anchor frame is input, and a part of the stored data is not erased in order to make a space in the retained anchor bank in advance. A stream reproduction process 2 executed by the decoder 122 when a vacant bank of the retained anchor bank is secured at the time of decoding the retained anchor frame will be described.

  In step S901, the decode controller 153 of the decoder 122 determines whether a new GOP has been supplied to the input processing unit 151. If it is determined in step S901 that no new GOP is supplied, the process proceeds to step S904.

  In step S902, the process 2 at the time of stream input, which will be described later with reference to the flowchart of FIG. 90, is executed.

  In step S903, the decode controller 153 controls the input of stream data to the stream buffer 131-1, based on the information in the stream buffer GOP queue described with reference to FIG.

  If it is determined in step S901 that no new GOP is supplied, or after the processing in step S903 is completed, the decoding controller 153 has a timing other than the timing of the decoding processing for display in step S904. On the basis of whether or not the anchor frame decoding start command is supplied, it is determined whether or not the decoding process of the anchor frame of the GOP instructed to start decoding is possible.

  If it is determined in step S904 that the anchor frame can be decoded, in step S905, the decode controller 153 determines that the anchor frame of the GOP instructed to start decoding is stored in the anchor bank of the frame memory 131-3. It is determined whether or not it is held.

  If it is determined in step S905 that the anchor frame of the GOP instructed to start decoding is not held, in step S906, the decode controller 153 performs anchor frame decoding processing to be described later with reference to FIG.

  If it is determined in step S904 that the anchor frame cannot be decoded, if it is determined in step S905 that the anchor frame of the GOP instructed to start decoding is held, or the process in step S906 In step S907, the decode controller 153 determines whether output of any frame is requested based on the control signal supplied from the CPU 121.

  If it is determined in step S907 that output of any frame has been requested, the output processing described with reference to FIGS. 60 to 62 or 68 to 70 is executed in step S908.

  If it is determined in step S907 that output of any frame has not been requested, or after the processing in step S908 is completed, the decoding controller 153 finishes supplying the stream to the input processing unit 151 in step S909. It is judged whether it was done. If it is determined in step S909 that the supply of the stream has not been completed, the process returns to step S901, and the subsequent processes are repeated.

  If it is determined in step S909 that the supply of the stream has been completed, in step S910, the decode controller 153 determines whether the reproduction process of the supplied stream has been completed. If it is determined in step S910 that the supplied stream reproduction process has not been completed, the process returns to step S904, and the subsequent processes are repeated. If it is determined in step S910 that the reproduction process for the supplied stream has been completed, the process ends.

  By such processing, the decoder 122 preferentially decodes the retained anchor frame that is at least a part of the anchor frames included in the transferred GOP. As a result, the number of decodes required for the process can be reduced, the response is improved, and a random range of as wide a range as possible with a smaller memory capacity than when all the anchor frames are pre-decoded and held in the memory bank. Display response such as playback, scrub playback, or transient playback that continuously commands forward and reverse playback in a short section can be improved, and there is a possibility that a situation in which display cannot be performed may occur. Can be lowered. Even when the number of anchor banks is not included in the decoding related information, such control can be executed.

  Next, referring to the flowchart in FIG. 90, the process 2 at the time of stream input executed in step S902 in FIG. 89 will be described.

  In step S931, the decode controller 153 of the decoder 122 determines whether the picture input to the input processing unit 151 is an I picture or a P picture. If it is determined in step S931 that the input picture is not an I picture or a P picture, the process proceeds to step S933 described below.

  If it is determined in step S931 that the input picture is an I picture or a P picture, the anchor frame decoding schedule process described with reference to FIG. 58 is executed in step S932.

  If it is determined in step S931 that the input picture is not an I picture or a P picture, that is, the input picture is a B picture, or after the process of step 632 ends, in step S933, the process proceeds to FIG. A picture management process using the stream buffer GOP queue described with reference to FIG.

  In step S934, the decode controller 153 determines whether the picture input to the input processing unit 151 is the last picture of the GOP. If it is determined in step S935 that the input picture is not the last picture of the GOP, the process returns to step S931, and the subsequent processes are repeated. If it is determined in step S934 that the input picture is the last picture of the GOP, the process returns to step S902 in FIG. 89 and proceeds to step S903.

  In this way, at the time of stream input, only the anchor frame decoding process and the picture management process by the stream buffer GOP queue are executed, and the owned anchor bank management process is not executed.

  Next, the anchor frame decoding process executed in step S906 in FIG. 89 will be described with reference to the flowchart in FIG.

  In step S951, the decode controller 153 determines whether or not the possessed anchor bank is empty. If it is determined in step S951 that the retained anchor bank is empty, the process proceeds to step S960 described below.

  If it is determined in step S951 that there is no vacancy in the retained anchor bank, in step S952, the decode controller 153 determines whether or not all GOPs retained in the retained anchor bank have been examined. If it is determined in step S952 that all GOPs held in the retained anchor bank have been examined, the process proceeds to step S958 described later.

  If it is determined in step S952 that all the GOPs held in the retained anchor bank have not been examined, in step S953, the decode controller 153 determines whether the GOP retained in the retained anchor bank can still be deleted. Extract one GOP that has not been checked.

  In step S954, the decode controller 153 determines whether the GOP is a GOP including a frame included in the decode schedule. If it is determined in step S954 that the GOP includes a frame included in the decoding schedule, the process returns to step S952, and the subsequent processes are repeated.

  If it is determined in step S954 that the GOP does not include a frame included in the decode schedule, the decode controller 153 determines in step S955 whether or not the GOP is a GOP including a frame to be displayed. To do. If it is determined in step S955 that the GOP includes a frame scheduled to be displayed, the process returns to step S952, and the subsequent processes are repeated.

  If it is determined in step S955 that the GOP does not include the display-scheduled frame, in step S956, the decode controller 153 includes the GOP including the frame included in the decode schedule and the display-scheduled frame. Among the GOPs, it is determined whether the GOP is located farthest from the next GOP to be supplied. If it is determined in step S956 that the GOP is not located farthest from the next supplied GOP, the process returns to step S952, and the subsequent processes are repeated.

  If it is determined in step S956 that the GOP is located farthest from the next GOP to be supplied, in step S957, the decode controller 153 deletes the GOP from the owned anchor bank. It is determined as a GOP corresponding to image data.

  If it is determined in step S952 that all GOPs held in the retained anchor bank have been examined, in step S958, the decode controller 153 determines whether there is a GOP to be deleted. If it is determined in step S958 that there is no GOP to be deleted, the process returns to step S906 in FIG. 89 and proceeds to step S907.

  In other words, if the baseband image data corresponding to the retained anchor frame included in the GOP including the frame included in the decoding schedule and the GOP including the frame to be displayed is deleted from the retained anchor bank, the playback output is immediately frozen. However, since the retained anchor frame decoding process is executed in advance, the decoding output is not executed at this timing. May not be affected. Therefore, when there is no anchor bank that can be deleted, the retained anchor frame is not decoded.

  If it is determined in step S958 that there is a GOP to be deleted, in step S959, the decode controller 153 stores the baseband image data corresponding to the retained anchor frame included in the GOP determined as the GOP to be deleted. Delete from anchor bank.

  If it is determined in step S951 that there is a vacancy in the retained anchor bank, or after the processing in step S959 is completed, in step S960, the decode controller 153 reserves a vacant area in the retained anchor bank.

  In step S961, the decode controller 153 allocates the secured anchor bank, decodes the anchor frame, and the process returns to step S906 in FIG. 89 and proceeds to step S907.

  In this way, immediately before the decoding process of the retained anchor frame, a process for securing the retained anchor bank is executed for each frame, and other than the GOP including the frame included in the decoding schedule and the frame scheduled to be displayed. When the GOP exists, the baseband image data corresponding to the retained anchor frame included in the GOP is deleted.

  Accordingly, the display response is improved in the decoding process, and the possibility that a situation in which display cannot be performed occurs is reduced. Further, since the information attached to the stream to be decoded need only be GOP_ID, it is possible to reduce the analysis processing for acquiring additional information for the stream to be decoded.

  In the above-described processing, a flag group for reading indicating whether or not the compressed encoded data recorded in the HDD 16 is valid as data to be read from the HDD 16, and whether or not it is effective in decoding scheduling. Decoding flag group indicating display, flag group for display indicating whether or not it is effective in scheduling for displaying decoded data, etc. are appropriately provided as metadata, and a series of flag groups are set according to playback speed and direction. It is also possible to manage scheduling by updating automatically.

  At this time, it is also possible to manage a series of scheduling and flag group update information used in the past variable-speed playback processing as separate scheduling metadata (history information). It may be described as syntax inside or separately recorded on the HDD 16 or the like as a recording medium.

  Also, the number of decoders, the number of banks, the decoder ID, and the like can be managed as metadata (configuration history information). Furthermore, it is possible to manage the playback speed, playback direction, and the like as metadata (playback history information). At this time, these metadata may be described as syntax in the compressed and encoded data as needed, or may be separately recorded on the HDD 16 or the like as a recording medium.

  By referring to such metadata (history information), scheduling processing performed in the past can be reused, and scheduling processing can be executed more accurately and at high speed.

  Note that such metadata may be managed by an external device as a database, for example.

  In the above-described embodiment, even when the decoder 22 to decoder 24 or the decoder 122 does not completely decode the compressed encoded data recorded in the HDD 16 (decodes halfway), The invention is applicable.

  Specifically, for example, when the decoder 22 to the decoder 24 or the decoder 122 only performs decoding and inverse quantization on the variable length code and does not perform the inverse DCT transform, or performs the inverse quantization but the variable length code. The present invention can be applied even when decoding is not performed for. In such a case, for example, the decoder 22 to the decoder 24 or the decoder 122 needs history information indicating, for example, up to which stage (for example, the inverse quantization stage) in the encoding process and the decoding process. May be generated in accordance with the data and output in association with incompletely decoded data.

  Further, in the above-described embodiment, incompletely encoded data (for example, data that has been subjected to DCT transform and quantization but not subjected to variable length encoding processing) is stored in the HDD 16. The history information of the encoding process and the decoding process is stored as necessary, and the decoder 22 to the decoder 24 or the decoder 122 performs the incomplete encoding supplied based on the control of the CPU 20 or the CPU 121. The present invention can also be applied to a case where decoded data can be decoded and converted into a baseband signal.

  Specifically, the decoder 22 to the decoder 24 or the decoder 122 performs, for example, incompletely encoded data that has been subjected to DCT conversion and quantization but not subjected to variable length encoding processing. On the other hand, the present invention can be applied even when only inverse DCT transform and inverse quantization are performed and decoding with respect to a variable length code is not performed.

  In such a case, for example, the CPU 20 or the CPU 121 acquires the history information of the encoding process and the decoding process stored in the HDD 16 in association with the incompletely encoded data, and stores these information in the information. Based on this, it may be possible to perform decoding scheduling by the decoders 22 to 24 or the decoder 122.

  Further, in the above-described embodiment, the HDD 16 stores incompletely encoded data and, if necessary, history information of the encoding process and the decoding process. The present invention can be applied even when the decoder 122 does not completely decode the supplied incompletely encoded data (decodes halfway) based on the control of the CPU 20 or the CPU 121.

  Also in such a case, for example, the CPU 20 or the CPU 121 acquires the history information of the encoding process and the decoding process stored in the HDD 16 in association with the incompletely encoded data, and these information Based on the above, decoding scheduling by the decoders 22 to 24 or the decoder 122 may be performed. Further in this case, the decoder 22 to decoder 24 or the decoder 122 generates history information of the encoding process and the decoding process as necessary, and outputs the history information in association with the incompletely decoded data. You may be able to.

  In other words, even when the decoder 22 to the decoder 24 or the decoder 122 performs partial decoding (performs a part of the decoding process) based on the control of the CPU 20 or the CPU 121, The invention is applicable, and the CPU 20 or the CPU 121 acquires the history information of the encoding process and the decoding process stored in the HDD 16 in association with the incompletely encoded data, and based on these information, Decoding scheduling can be performed by the decoder 22 to the decoder 24 or the decoder 122. The decoder 22 to the decoder 24 or the decoder 122 generates the history information of the encoding process and the decoding process as necessary, You may enable it to output corresponding to the completely decoded data.

  Further, the history information of the encoding process and the decoding process may be further recorded in the HDD 16 in association with the compression encoded stream data, and the CPU 20 or the CPU 121 may store the compressed encoded stream data. The decoding scheduling may be performed based on the history information of the encoding process and the decoding process. Furthermore, even when the decoder 22 to the decoder 24 or the decoder 122 can decode the stream data that has been compression-coded based on the control of the CPU 20 or the CPU 121 and convert it into a baseband signal, The history information of the encoding process and the decoding process may be generated as necessary, and may be output in association with the baseband signal.

  In the above-described embodiment, the description has been given on the assumption that each playback device has a plurality of or one decoder. However, even when the decoders are configured as independent devices, The invention is applicable.

  At this time, the decoder configured as an independent device receives the compressed encoded data, decodes it, displays or outputs it, and supplies the compressed encoded data in the same manner as described above. Received, partially decoded up to the middle stage, output to the outside along with encoding and decoding history information, or supplied with partially encoded data, decoded, and converted to a baseband signal Then, the data may be output to the outside, supplied with partially encoded data, partially decoded up to an intermediate stage, and output to the outside together with encoding and decoding history information.

  Furthermore, in the above-described embodiment, the CPU 11 and the CPU 20 or the CPU 121 are configured in different forms, but the configuration of the CPU is not limited to this. For example, the CPU 11 and the CPU 20 or the CPU 121 are connected to the playback device 1 or A configuration in which the CPU is configured as one CPU that controls the entire playback apparatus 101 is also conceivable. Further, even when the CPU 11 and the CPU 20 or the CPU 121 are independently configured, the CPU 11 and the CPU 20 or the CPU 121 may be configured as one chip.

  Further, when the CPU 11 and the CPU 20 or the CPU 121 are configured independently, at least a part of the processing executed by the CPU 11 in the above-described embodiment can be executed by the CPU 20 or the CPU 121, for example, in a time division manner. Alternatively, at least a part of the processing executed by the CPU 20 or the CPU 121 may be executed by the CPU 11 in a time division manner, for example. That is, a processor capable of distributed processing may be used for the CPU 11 and the CPU 20 or the CPU 121.

  Further, for example, the playback device 1 is configured to be connectable to a network, and in the above-described embodiment, at least a part of the processing executed by the CPU 11, CPU 20, or CPU 121 is performed by another device connected via the network. It may be configured to be executed by the CPU.

  Similarly, in the above-described embodiment, the memory 13 and the memory 21 are configured in different forms. However, the present invention is not limited to this, and the memory 13 and the memory 21 are configured as one memory in the playback device 1. Forms are also conceivable.

  Furthermore, in the above-described embodiment, a case has been described in which modules such as the HDD 16, the decoder 22 to the decoder 24, or the decoder 122 are connected via a bridge and a bus and integrated as a playback device. However, the present invention is not limited to this, for example, when some of these components are connected from the outside by wire or wirelessly, or these components are mutually connected in various connection forms. It can also be applied to the case where it is connected to.

  Here, the case where MPEG is used as the codec method is described as an example, but it goes without saying that the present invention can also be applied to the case of performing codec processing with frame correlation. For example, AVC (Advanced Video Coding) / H. The present invention is applicable to H.264.

  Note that the AVC / H.264 B picture does not necessarily use the forward and backward bi-directional reference images. Even if prediction is performed using two reference images from the past, Although prediction may be performed using a single reference image, the present invention can be applied in consideration of such a case.

  The series of processes described above can be executed by hardware or can be executed by software. In this case, the processing described above is executed by a personal computer 201 as shown in FIG.

  In FIG. 92, a CPU (Central Processing Unit) 211 performs various processes according to a program stored in a ROM (Read Only Memory) 212 or a program loaded from a storage unit 218 to a RAM (Random Access Memory) 213. Execute. The RAM 213 also appropriately stores data necessary for the CPU 211 to execute various processes.

  The CPU 211, ROM 212, and RAM 213 are connected to each other via an internal bus 214. An input / output interface 215 is also connected to the internal bus 214.

  The input / output interface 215 includes an input unit 216 including a keyboard and a mouse, a display including a CRT and an LCD, an output unit 217 including a speaker, a storage unit 218 including a hard disk, a modem, a terminal adapter, and the like A communication unit 219 is connected. The communication unit 219 performs communication processing via various networks including a telephone line and CATV.

  A drive 220 is connected to the input / output interface 215 as necessary, and a magnetic disk 231 (including a flexible disk), an optical disk 232 (CD-ROM (Compact Disk-Read Only Memory), DVD (Digital Versatile Disk)) A magneto-optical disk 233 (including MD (Mini-Disk) (trademark)), or a semiconductor memory 234 or the like is appropriately mounted, and a computer program read therefrom is stored in the storage unit 218 as necessary. Installed.

  When a series of processing is executed by software, a program constituting the software is installed from a network or a recording medium.

  As shown in FIG. 92, this recording medium is distributed to provide a program to the user separately from the computer. The magnetic disk 231, the optical disk 232, the magneto-optical disk 233, or the semiconductor on which the program is recorded is distributed. It is configured by a package medium including a memory 234 and the like.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

  In the present specification, the term “system” represents the entire apparatus constituted by a plurality of apparatuses.

  Furthermore, in the above-described embodiment, the case where the compressed stream data is stored in the HDD 16 has been described. However, the present invention is not limited to this, and for example, an optical disk, a magneto-optical disk, a semiconductor memory, a magnetic disk, etc. The present invention can also be applied to the case of decoding stream data recorded on various recording media.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a block diagram which shows the structure of the reproducing | regenerating apparatus. FIG. 2 is a block diagram illustrating a detailed configuration of a decoder in FIG. 1. It is a flowchart for demonstrating a control process. It is a flowchart for demonstrating the process 1 performed for every flame | frame. It is a flowchart for demonstrating an input stream state change process. 10 is a flowchart for explaining decode schedule processing 1; It is a figure for demonstrating MPEG LONG GOP. It is a figure for demonstrating the processing unit in which decoding is performed by one decoder. It is a figure for demonstrating the information accumulate | stored in an input picture queue. It is a figure for demonstrating the information accumulate | stored in a display order information queue. It is a figure for demonstrating the information accumulate | stored in an I / P picture decoding queue. It is a figure for demonstrating the information accumulate | stored in a display order setting queue. It is a figure for demonstrating the timing of a decoding and a display. It is a figure for demonstrating the timing of a decoding and a display. It is a flowchart for demonstrating an input process. It is a flowchart for demonstrating a display phase determination process. It is a flowchart for demonstrating the schedule determination process with time information. 5 is a flowchart for explaining frame control processing 1; It is a flowchart for demonstrating an I picture and P picture decoding process. It is a flowchart for demonstrating a B picture decoding process. It is a figure for demonstrating the schedule of a decoding and a display. It is a figure for demonstrating the schedule of a decoding and a display. 5 is a flowchart for explaining a thinning process 1; It is a flowchart for demonstrating a time information reset process. It is a figure for demonstrating the schedule of the decoding after thinning | decimation in the case of 2 times speed, and a display. FIG. 10 is a diagram for explaining a decoding and display schedule after thinning in the case of −2 times speed. It is a figure for demonstrating the schedule of the decoding after thinning | decimation in the case of 4 times speed, and a display. FIG. 6 is a diagram for explaining a decoding and display schedule after thinning in the case of -4 × speed. It is a figure for demonstrating the schedule of the decoding after a thinning | decimation in the case of 5 times speed, and a display. It is a figure for demonstrating the schedule of the decoding after thinning | decimation in the case of -5 times speed, and a display. It is a figure for demonstrating the bank management at the time of normal reproduction | regeneration. It is a figure for demonstrating the bank management at the time of double speed reproduction | regeneration. It is a figure for demonstrating the bank management at the time of -1 time-speed reproduction | regeneration. It is a figure for demonstrating the bank management at the time of -2 speed reproduction | regeneration. It is a flowchart for demonstrating an underflow process. It is a figure for demonstrating the time counter when the underflow has not generate | occur | produced. It is a figure for demonstrating correction of the time counter when an underflow generate | occur | produces. It is a flowchart for demonstrating 1 frame delay processing. It is a flowchart for demonstrating the process 2 performed for every flame | frame. 10 is a flowchart for explaining decode schedule processing 2; 10 is a flowchart for explaining a thinning process 2; 10 is a flowchart for explaining frame control processing 2; 10 is a flowchart for explaining a thinning process 3; It is a block diagram which shows the different structure of a reproducing | regenerating apparatus. It is a flowchart for demonstrating the GOP transfer control process of CPU121. FIG. 45 is a block diagram showing a configuration of the decoder of FIG. 44. It is a figure for demonstrating the header information of GOP. It is a figure for demonstrating a stream buffer GOP queue. It is a figure for demonstrating a holding anchor frame and a non-holding anchor frame. It is a figure for demonstrating the stream buffer GOP queue. It is a figure for demonstrating a bank structure. It is a figure for demonstrating a GOP holding | maintenance anchor queue. It is a figure for demonstrating management of a possession anchor bank. It is a figure for demonstrating management of a possession anchor bank. 10 is a flowchart for explaining stream reproduction processing 1; It is a flowchart for demonstrating the process 1 at the time of stream input. It is a flowchart for demonstrating possession anchor bank management processing. It is a flowchart for demonstrating an anchor frame decoding schedule process. It is a flowchart for demonstrating the management process of the picture using a stream buffer GOP queue. 5 is a flowchart for explaining output processing 1; 5 is a flowchart for explaining output processing 1; 5 is a flowchart for explaining output processing 1; It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the specific example of the timing of a forward transfer. It is a figure for demonstrating the state of each bank of a decoding, a display, and a frame memory. It is a figure for demonstrating the state of each bank of a decoding, a display, and a frame memory. FIG. 5 is a configuration diagram of a GOP possession / non-retention anchor frame when the possession anchor frame is every two pictures, three pictures, or every four pictures. It is a figure for demonstrating the bank allocation when the possession anchor frame is every 2 pictures, 3 pictures, or 4 pictures. It is a figure for demonstrating decoding of a possession anchor frame when a possession anchor frame is made into 2 pictures. It is a figure for demonstrating decoding of B picture when a possession anchor frame is set to 2 pictures. 10 is a flowchart for explaining output processing 2; 10 is a flowchart for explaining output processing 2; 10 is a flowchart for explaining output processing 2; It is a figure for demonstrating the case where all the anchor frames are made into a possession anchor frame. It is a figure for demonstrating the process when a new GOP is supplied. It is a figure for demonstrating the failure which generate | occur | produces when the flame | frame of display waiting exists. It is a figure for demonstrating the process when the frame of the display waiting frame and the frame of the decoding schedule completed. It is a figure for demonstrating the process when the frame of the display waiting frame and the frame of the decoding schedule completed. It is a figure for demonstrating the process when the frame of the display waiting frame and the frame of the decoding schedule completed. It is a figure for demonstrating the process when the frame of the display waiting frame and the frame of the decoding schedule completed. 10 is a flowchart for explaining stream reproduction processing 2; It is a flowchart for demonstrating the process 2 at the time of stream input. It is a flowchart for demonstrating an anchor frame decoding process. It is a block diagram which shows the structure of a personal computer.

Explanation of symbols

  11 CPU, 16 HDD, 101 playback device, 121 CPU, 122 decoder, 131 memory, 131-1 stream buffer, 131-3 frame memory, 152 selector, 153 decoding controller, 154 decoding processing unit, 155, 156, 157 selector

Claims (12)

In an information processing apparatus that decodes an encoded stream,
A holding means for holding data generated by decoding for a plurality of frames; a decoding means for decoding the encoded stream using the holding means;
Supply means for supplying the encoded stream to the decoding means;
Control means for controlling processing executed by the supply means and the decoding means,
The supply means supplies, to the decoding means, a reference frame that is referred to for decoding the predetermined frame in the encoded stream prior to a timing at which the predetermined frame is decoded by the decoding means. And
When the decoding means decodes any reference frame, the holding means does not have a new data storage area, and the decoding means decodes the data corresponding to the reference frame held by the holding means. The first frame that has been output but has not been output, the second frame that is required to decode the first frame, or the third frame that has been determined to be decoded by the decoding means, or the When there is data corresponding to a fifth frame different from any of the fourth frames necessary for decoding the third frame, the data corresponding to the fifth frame is deleted . The encoded stream has a GOP structure;
The information processing apparatus according to claim 1, wherein the holding unit holds data corresponding to a predetermined frame that is not continuous among the reference frames in one GOP. The holding means is used when a storage area for X frames for holding data generated by decoding the reference frame and a P picture or B picture other than the predetermined frame are decoded and output. The information processing apparatus according to claim 2, further comprising a storage area for two frames. The storage area for X frames is:
A first storage area for one frame for holding data generated by decoding the P picture other than the predetermined frame, which is used for decoding the predetermined frame;
A second storage area for one frame for holding data generated by decoding the P picture other than the predetermined frame used for decoding the B picture;
The information processing apparatus according to claim 3, further comprising: a third storage area for X-2 frames for holding data generated by decoding the predetermined frame. When the decoding unit decodes any of the reference frames, there is no storage area for new data in the third storage area, and the data stored in the third storage area is not stored in the holding unit. The information processing apparatus according to claim 4, wherein when the fifth frame is present, the fifth frame is deleted from the third storage area. The storage area for X frames is:
A first storage area for one frame for holding data generated by decoding the P picture other than the predetermined frame, which is used for decoding the I picture included in the predetermined frame; ,
A second frame of 2 frames for holding data generated by decoding the P picture other than the predetermined frame, which is used for decoding the P picture or the B picture other than the predetermined frame. Storage area,
X-3 frames for holding the predetermined frame and data generated by decoding the P picture other than the predetermined frame used for decoding the P picture included in the predetermined frame The information processing apparatus according to claim 3, comprising: a third storage area. When the decoding unit decodes any of the reference frames, there is no storage area for new data in the third storage area, and the data stored in the third storage area is not stored in the holding unit. The information processing apparatus according to claim 6, wherein when the fifth frame exists, the fifth frame is deleted from the third storage area. In an information processing method of an information processing apparatus for decoding an encoded stream,
Providing a reference frame to be referred to for decoding the predetermined frame of the encoded stream to a decoder prior to a timing at which the predetermined frame is decoded;
Scheduling the decoding process of the reference frame;
Determine whether there is a storage area for new data in the holding unit that holds data generated by decoding for a plurality of frames,
There is no storage area for new data in the holding unit, and the data corresponding to the reference frame held by the holding unit is decoded by the decoder but is not output, or the first frame or the first frame The second frame required to decode the frame, the third frame determined to be decoded by the decoder, or the fourth frame required to decode the third frame. If there is data corresponding to a fifth frame different from any of them, delete the data corresponding to the fifth frame,
When there is a storage area for new data in the holding unit, or when the fifth data is deleted from the holding unit, a reference frame for decoding the predetermined frame is decoded based on a schedule. ,
An information processing method including a step of decoding the predetermined frame by using data corresponding to the reference frame generated by decoding when output of data corresponding to the predetermined frame is requested. A program for causing a computer to execute processing for decoding an encoded stream,
Providing a reference frame to be referred to for decoding the predetermined frame of the encoded stream to a decoder prior to a timing at which the predetermined frame is decoded;
Scheduling the decoding process of the reference frame;
Determine whether there is a storage area for new data in the holding unit that holds data generated by decoding for a plurality of frames,
There is no storage area for new data in the holding unit, and the data corresponding to the reference frame held by the holding unit is decoded by the decoder but is not output, or the first frame or the first frame The second frame required to decode the frame, the third frame determined to be decoded by the decoder, or the fourth frame required to decode the third frame. If there is data corresponding to a fifth frame different from any of them, delete the data corresponding to the fifth frame,
When there is a storage area for new data in the holding unit, or when the fifth data is deleted from the holding unit, a reference frame for decoding the predetermined frame is decoded based on a schedule. ,
When output of data corresponding to the predetermined frame is requested, to cause a computer to execute a process including a step of decoding the predetermined frame using data corresponding to the reference frame generated by decoding Program.   A recording medium on which the program according to claim 9 is recorded. In an information processing apparatus that decodes an encoded stream,
A holding means for holding data generated by decoding for a plurality of frames; a decoding means for decoding the encoded stream using the holding means;
Supply means for supplying the encoded stream to the decoding means;
Control means for controlling processing executed by the supply means and the decoding means,
The supply means supplies, to the decoding means, a reference frame that is referred to for decoding the predetermined frame in the encoded stream prior to a timing at which the predetermined frame is decoded by the decoding means. And
When the decoding means decodes any reference frame, the holding means does not have a data storage area corresponding to the new reference frame, and the decoding means decodes the data held by the holding means. If there is data corresponding to a third frame that is different from any of the first frame that is output but is not output or the second frame that is required to decode the first frame, An information processing apparatus that deletes data corresponding to the third frame. In an information processing apparatus that decodes an encoded stream,
A holding means for holding data generated by decoding for a plurality of frames; a decoding means for decoding the encoded stream using the holding means;
Supply means for supplying the encoded stream to the decoding means;
Control means for controlling processing executed by the supply means and the decoding means,
The supply means supplies, to the decoding means, a reference frame that is referred to for decoding the predetermined frame in the encoded stream prior to a timing at which the predetermined frame is decoded by the decoding means. And
When the decoding means decodes any reference frame, the holding means does not have a data storage area corresponding to the new reference frame, and the decoding means decodes the data held by the holding means. If there is data corresponding to a third frame that is different from either the first frame that is determined to be decoded or the second frame that is required to decode the first frame, the first frame An information processing apparatus that deletes data corresponding to the third frame.

Images