JP2006148987A - Switching regulator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a step-up switching regulator circuit for outputting an input voltage while boosting in which an input power supply is protected against deterioration and breakage, and a choke coil and a switching power transistor are protected against deterioration and breakage. <P>SOLUTION: The switching regulator comprises a first signal generating circuit 27 operating on the voltage of an input power supply 6 to generate a first pulse P1 having a predetermined pulse width, a second signal generating circuit 1 operating on a boosted output to generate a second pulse P2 having a pulse width corresponding to the boosted output, and a circuit 2 for driving a switching means 26 by selecting any one of the first pulse P1 or the second pulse P2 depending on the boosted output. The second signal generating circuit 1 comprises an error amplifier output voltage limit circuit 34 for limiting the pulse width of the second pulse P2 regardless of the boosted output for a predetermined pulse limit period after the second pulse P2 is selected by the drive circuit 2 and protects the input power supply and the switching means 26 against deterioration and breakage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology for reducing an inrush current when a switching power supply circuit is started in a step-up switching power supply circuit that boosts and outputs an input voltage.

  In recent years, with the miniaturization of electronic devices, batteries are generally used as power supply sources for the electronic devices. Since the voltage of the battery varies depending on the discharge time (use time), it is usually necessary to stabilize the voltage by incorporating a switching power supply circuit in the electronic device. Also, in order to achieve long-time operation, there has been an increasing demand for operation with a lower battery voltage in recent years.

An example of a conventional switching power supply circuit is (Patent Document 1).
Japanese Patent Publication No. 7-34650

  However, in the configuration of (Patent Document 1), oscillation starts with a large pulse width immediately after startup, and when oscillation starts with a large pulse width immediately after circuit startup, the input power source that drives the switching power supply circuit A large current is required as the input power supply current that flows out. Further, this large input power source current becomes an inrush current, and when a battery is used as the input power source, if a large current is consumed at the time of startup, the battery may be deteriorated or damaged.

  Therefore, even when a startup oscillation circuit that operates even at a low input voltage is used, an inrush current immediately after startup can be prevented, and the choke coil and switching power transistor that are components of the switching power supply circuit can be protected from deterioration and damage. The configuration shown in FIGS. 9 and 10 can be considered as the power supply circuit.

  The switching power supply circuit shown in FIG. 9 is configured to be driven by an input power supply current I6 from the input power supply 6 and to output an output voltage to the output terminal 25. The switching means 26 includes a switching power transistor 5 constituted by an N-type MOS, a choke coil 7, a rectifying diode 8, and an output smoothing capacitor 9.

  The gate signal input to the power transistor 5 is any one of the first pulse P1 generated at the output of the first signal generation circuit 27 and the second pulse P2 generated at the output of the second signal generation circuit 1. These are selected by the drive circuit 2 to drive the power transistor 5 of the switching means 26. Switching of the drive circuit 2 is controlled by the output voltage monitor circuit 4. Reference numeral 11 is a reference voltage.

  The drive circuit 2 supplies either the output signal of the second signal generation circuit 1 or the output of the first signal generator 27, which is an example of an oscillator that performs pulse width control based on the output voltage, to the gate of the power transistor 5. . The pulse width of the output signal of the second signal generating circuit 1 changes so that the divided voltage V21 obtained by dividing the output voltage at the output terminal 25 by the resistor 21 approaches the target voltage value.

  The starting oscillator 26 includes a constant current source 13, a capacitor 14, a ring oscillator 15, a comparator 16, inverters 17, 18 and 19, and an AND circuit 20.

This will be described in more detail based on FIG.
Immediately after startup, the capacitor 14 is charged by the constant current source 13. As a result, the voltage (b) of the terminal voltage of the capacitor 14 increases with a predetermined slope as shown in FIG. Further, the node voltage (a) of the ring oscillator 15 also starts to oscillate as shown in FIG.

The series circuit of the inverters 17, 18, and 19 uses the node voltage (a) of the ring oscillator 15 as an input signal, and a signal (d) having a constant pulse width is generated at the output as shown in FIG.
The output of the comparator 16 in which the voltage (b) is applied to the non-inverting input (+) and the node voltage (a) of the ring oscillator 15 is applied to the inverting input (−) is as shown in the signal (c) of FIG. In addition, it operates in the same phase as the signal (d), and the pulse width gradually increases as the voltage (b) increases, and remains at the “H” level after the capacitor 14 is charged to a predetermined value. It becomes a state.

  Therefore, the output (e) of the AND circuit 20 that receives the signal (d) and the signal (c) is such that the signal (c) has a pulse width larger than that of the signal (d) during initial charging as shown in FIG. Since the signal is small, the pulse width gradually increases, and after the predetermined charging, the signal (c) remains at the “H” level, so that the operation with a constant pulse width (d) becomes dominant. The pulse width becomes constant, and as a result, the output (e) performs a soft start operation.

  Therefore, immediately after startup, the drive circuit 2 supplies the output (e) of the soft start operation to the gate of the power transistor 5, and then supplies the output signal of the second signal generation circuit 1 to the gate of the power transistor 5. Therefore, even when a forced oscillation circuit that operates even at a low input voltage is used as the second signal generation circuit 1, an inrush current from the input power supply 6 to the switching means 26 can be prevented, and the input power supply 6 And the choke coil 7 and the power transistor 5 can be protected.

  During the operation of the first signal generator 27 in FIG. 9, since a soft start operation in which the switching pulse width gradually increases is performed, an inrush current from the input power supply 6 to the switching means 26 can be prevented. There arises a problem that an inrush current flows at the timing when the drive circuit 2 switches the gate signal to the output of the second signal generation circuit 1 that performs the pulse width control by the output voltage. The occurrence of this problem will be described with reference to FIG.

  In FIG. 11, 30 is an error amplifier, 12 is a reference voltage, 31 is a PWM comparator, 32 is a triangular wave oscillation circuit constituted by the ring oscillator 15, etc., and 33 is a maximum duty ratio setting voltage.

Here, the duty ratio indicates the following ratio in the pulse output from the PWM comparator 31.
Duty ratio = (“H” pulse width) / (pulse period)
Hereinafter, the term duty ratio is used under this definition.

  Immediately after activation of the switching power supply circuit, the first signal generator 27 performs a ft start operation as described above to boost the output voltage, and is configured by an error amplifier 30, a triangular wave oscillation circuit 32, and a PWM comparator 31. In order to reach the threshold voltage of the output voltage monitor circuit 4 that is the operation lower limit voltage of the signal generation circuit, switching control is switched from the first signal generation circuit 27 to the control side of the PWM comparator 31 when the drive circuit 2 is switched.

  At this time, the error amplifier 30, the reference voltage 12, the PWM comparator 31, and the triangular wave generation circuit 32 start to be activated for the first time, and thus it takes a certain time until they are completely activated. During this startup time, the output of the error amplifier 30 is indefinite, and as a result, the duty ratio of the pulse output from the PWM comparator 31 is also indefinite. Even after the error amplifier 30, the reference voltage 12, the PWM comparator 31, and the triangular wave generation circuit 32 are activated, the voltage at the inverting input terminal of the error amplifier 30 determined by the boosted output voltage and the resistor 21 is lower than the reference voltage 12. The output of the error amplifier 30 is stuck to the “H” level. The duty ratio of the pulse output from the PWM comparator 31 changes according to the output voltage level of the error amplifier 30.

  Specifically, as shown in FIG. 11, the output of the error amplifier 30, the triangular wave oscillation circuit 32, and the maximum duty setting voltage 31 are input to the PWM comparator 31 to generate a duty signal. Immediately after the error amplifier 30 is started up, as described above, the output of the error amplifier 30 is stuck to “H”, so that it is higher than the peak voltage of the triangular wave output of the triangular wave oscillation circuit 32. For this reason, the duty ratio of the pulse that is the output of the PWM comparator 31 is the maximum duty ratio determined by the maximum duty setting voltage 33 and the triangular wave oscillation circuit 32.

  That is, immediately after the error amplifier 30 is activated, the switching power transistor 5 is switched with a pulse having the maximum duty ratio, and an inrush current flows from the input power supply 6 when the switching power transistor 5 is turned on. The inrush current at this time causes deterioration and damage of the input power supply 6 and deterioration and damage of the choke coil 7 and the switching power transistor 5.

After the inrush current flows, when the boosted output voltage rises and reaches a predetermined control voltage, the error amplifier 30 enters a virtual ground state, and the inrush current is also eliminated.
An object of this invention is to provide the switching power supply circuit which can reduce a rush current and can protect a switching means.

  The switching power supply circuit according to claim 1 of the present invention is a step-up switching power supply circuit that switches an input voltage by a switching means to boost and output the voltage, and operates with the input voltage and has a predetermined pulse width. A first signal generating circuit that outputs a first pulse; a second signal generating circuit that operates with the boosted output and outputs a second pulse having a pulse width corresponding to the boosted output; and And a driving circuit that selects one of the first pulse and the second pulse to drive the switching means, and the second signal generation circuit has the driving circuit configured to drive the second pulse. The pulse width of the second pulse is limited regardless of the boosted output only for a predetermined pulse limiting period after selection.

  The switching power supply circuit according to a second aspect of the present invention is the switching power supply circuit according to the first aspect, wherein the second signal generation circuit is in a pause state when the driving circuit selects the first pulse, The pulse limiting period is set to at least a period until the second signal generating circuit stably operates.

  A switching power supply circuit according to a third aspect of the present invention is the switching power supply circuit according to the second aspect, wherein the second signal generation circuit sets the pulse limit period by a counter circuit or a CR delay circuit.

  According to a fourth aspect of the present invention, there is provided the switching power supply circuit according to the first aspect, wherein the second signal generation circuit is configured not to generate the second pulse during the pulse limiting period.

  A switching power supply circuit according to a fifth aspect of the present invention is the switching power supply circuit according to the first aspect, wherein the second signal generation circuit is configured such that the second signal generation circuit is the second signal as time passes after the driving circuit selects the second pulse. The pulse width of this pulse is configured to be gradually increased.

  According to the present invention, the inrush current can be reduced, the input power supply can be protected, and the choke coil and the switching power transistor constituting the switching means can be protected.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
In addition, the same code | symbol is attached | subjected and demonstrated to what has the effect | action similar to what was demonstrated in FIG.

(Embodiment 1)
1, FIG. 2, FIG. 3 and FIG. 4 show (Embodiment 1) of the present invention.
The switching means 26 driven by the input power supply 6 includes a switching power transistor 5, a choke coil 7, a rectifying diode 8, and an output smoothing capacitor 9. A signal input to the gate of the power transistor 5 is selected by the drive circuit 2. The input of the drive circuit 2 is supplied with a first pulse P1 generated by the first signal generation circuit 27 and a second pulse P2 generated by the second signal generation circuit 1. The switching control of the drive circuit 2 operating with the boosted output generated at the output terminal 25 as the power supply voltage is switched by the output voltage monitor circuit 4 monitoring the boosted output voltage of the output terminal 25 of the switching means 26.

  Here, the first signal generation circuit 27 operates by applying a power supply voltage from the input power supply 6 through the power supply line 101, and outputs a first pulse P1 having a predetermined pulse width. The second signal generation circuit 1 operates by applying the boosted output voltage of the output terminal 25 as a power supply via the power supply line 102, monitors the output of the output voltage monitor circuit 4, and the drive circuit 2 performs the second operation. The pulse width of the second pulse P2 is output with the pulse width limited without depending on the boosted output voltage of the output terminal 25 for a predetermined pulse limiting period after the selection of the pulse P2, and then the boosted output of the output terminal 25 is output. The second pulse P2 having a pulse width corresponding to the voltage is output.

The operation at the time of starting the switching power supply circuit configured as described above will be described.
Immediately after starting the switching power supply circuit, the boosted output voltage of the output terminal 25 is
(Voltage of input power supply 6-forward voltage Vf of rectifying diode 8)
For example, when the input power source 6 is a series of two dry batteries, assuming that the end voltage of one dry battery is 0.8 volts, the boosted output voltage immediately after startup is 1.6 volts-0.2 volts. = 1.4 volts.

  Since this low voltage is lower than the operation lower limit voltage of the second signal generation circuit 1, the second signal generation circuit 1 does not operate immediately after starting. For this reason, it is necessary to increase the output voltage through another path. For this reason, the first signal generating circuit 27 that can operate even when the input power supply 6 is a direct power supply and the final voltage of the two dry batteries is 1.6 volts is used.

  Immediately after activation of the switching power supply circuit, the first signal generating circuit 27 operable at this low power supply voltage outputs a first pulse P1 having a predetermined duty ratio, and the gate of the power transistor 5 is connected via the drive circuit 2. In the interval in which the first pulse P1 is applied and switched and the power transistor 5 is turned on, current flows from the input power source 6 to the choke coil 7 to accumulate energy, and the power transistor 5 is turned off. In the section, the energy accumulated in the choke coil 7 is transferred to the output smoothing capacitor 9 through the rectifying diode 8, and the output voltage rises.

  The output voltage rises by the switching operation of a pulse having a predetermined duty ratio output from the series of first signal generation circuits 27. When the output voltage rises and reaches the threshold voltage of the output voltage monitor circuit 4, which is an operable voltage of the second signal generation circuit 1, the drive circuit 2 is switched to the second signal generation circuit 1 side.

  Since the duty ratio of the output pulse of the second signal generation circuit 1 is limited without being determined only by the boosted output voltage of the output terminal 25 during a predetermined period immediately after the switching, FIG. It is possible to suppress a jump in the duty ratio of the pulse at the connection timing as described in the above.

  After the predetermined period, the restriction on the duty ratio of the output pulse of the second signal generation circuit 1 is released, but the duty of the pulse from the release until the switching power supply circuit is started and the steady state is reached. The ratio change is to be determined by the loop frequency characteristics of the entire switching power supply circuit including the second signal generating circuit 1, the power transistor 5, the choke coil 7, the rectifying diode 8, and the output smoothing capacitor 9. The duty ratio of the output pulse of the second signal generation circuit 1 gradually increases, reaches a steady state, and does not pass through a region where the pulse duty ratio is high.

  As a result, the on-time of the power transistor 5 is limited, and the inrush current from the input power supply 6 can be reduced. As a result, the input power supply 6 can be protected, and the choke coil 7 and the switching power transistor 5 can be protected.

The second signal generation circuit 1 is configured as shown in FIG.
12 is a reference voltage, 30 is an error amplifier, 31 is a PWM comparator that generates a PWM signal, 32 is a triangular wave oscillation circuit, 33 is a maximum duty ratio setting voltage, and 34 is an error that limits the output of the error amplifier 30 over a predetermined period. An amplifier output voltage limiting circuit 21 is a resistor that determines the output voltage.

  When the switching power supply circuit is started, the voltage is switched and boosted by the first pulse P1 having a predetermined duty ratio of the first signal generation circuit 27, and the output voltage monitor circuit 4 causes the drive circuit 2 to become the second signal generation circuit. Until it switches to the 1 side, it operates as described in FIG. Immediately after this switching, the second signal generation circuit 1, that is, the reference voltage 12, the error amplifier 30, the PWM comparator 31, and the triangular wave oscillation circuit 32 start to operate. I need it.

  In addition, since the voltage of the inverting input terminal of the error amplifier 30 determined by the boosted output voltage and the resistor 21 is lower than the reference voltage 12 even after these blocks are activated, the operation of the error amplifier 30 is as follows. The output voltage of the error amplifier 30 tends to be “H” level, that is, the maximum voltage that can be output as the error amplifier 30. When the error amplifier output voltage limiting circuit 34 is not provided, if the “H” level of the output of the error amplifier 30 is transmitted to the PWM comparator 31 in the subsequent stage, the output of the error amplifier 30 as shown in FIG. The voltage becomes 44, which is higher than the maximum duty ratio setting voltage 43, and the duty ratio of the second pulse P2 output from the PWM comparator 31 is 45 and the output of the triangular wave oscillation circuit 32. The maximum duty ratio is determined only by the maximum duty ratio setting voltage 43.

  On the other hand, in the configuration in which the error amplifier output voltage limiting circuit 34 is provided, as shown in FIG. 3B, a predetermined period (FIG. 3) immediately after the drive circuit 2 is switched to the second signal generation circuit 1 side. 3 (b) period A), the output voltage of the error amplifier 30 is limited to a predetermined low voltage, and after the end of the period A, the limitation on the output voltage of the error amplifier 30 is released.

  In the period A, since the duty ratio of the second pulse P2 output from the PWM comparator 31 is limited to a low value, the inrush current can be suppressed in the period A.

  After the output voltage of the error amplifier 30 is released, the period starts to the period B. However, since the output voltage of the error amplifier 30 is limited to a predetermined low voltage in the period A, the output voltage of the error amplifier 30 at the start of the period B is Start with a predetermined low voltage.

  The duty ratio increases from this state toward the steady state. This operation is composed of an error amplifier 30, a PWM comparator 31, a switching power transistor 5, a choke coil 7, an output smoothing capacitor 9, and a resistor 21. The output voltage of the error amplifier 30 increases at a response speed determined by the loop frequency characteristics of the entire switching power supply circuit. With this increase, the duty ratio of the output pulse of the PWM comparator 31 gradually increases, the output voltage also increases, and reaches the steady state C period.

  In this way, since it reaches from the start to the steady state without passing through the high duty ratio region, the inrush current is suppressed. As a result, the input power source 6 is protected, and the choke coil 7 and the switching power transistor 5 are switched. It is possible to protect.

FIG. 4 shows the error amplifier output voltage limiting circuit 34 in FIG.
35 is a counter, 36 is an S-R latch, 37 is an error amplifier output limiting circuit, and 48 is a clock generated from the triangular wave oscillation circuit 32 of FIG.

  Since the error amplifier output voltage limiting circuit 34 is configured in this way, when the boosted output voltage rises by the first signal generation circuit 27 and reaches the threshold voltage of the output voltage monitor circuit 4, the SR latch 36 is set, The error amplifier output limiting circuit 37 operates to limit the output of the error amplifier 30 to a predetermined voltage. At the same time, the counter 35 starts counting for a predetermined period with the clock 48.

  When the counter 35 finishes counting a predetermined period, the SR latch 36 is reset, the error amplifier output limiting circuit 37 stops operating, and the output limitation of the error amplifier 30 is released.

(Embodiment 2)
FIG. 5 shows another example of the error amplifier output voltage limiting circuit 34 in FIG.
Reference numeral 38 is an inverter, 39 is a switch transistor, 40 is a delay time setting capacitor, 41 is a delay time setting resistor, 42 is a Schmitt buffer, 36 is an S-R latch, and 37 is an error amplifier output limiting circuit.

  Since the error amplifier output voltage limiting circuit 34 is configured in this way, when the boosted output voltage rises by the first signal generation circuit 27 and reaches the threshold voltage of the output voltage monitor circuit 4, the SR latch 36 is set, When the error amplifier output limiting circuit 37 operates and the output of the error amplifier 30 is limited to a predetermined voltage, the switch transistor 39 is turned off, and the delay time setting by the CR of the delay time setting resistor 41 and the delay time setting capacitor 40 is set. Charging to the capacity 40 is started.

  When the voltage of the delay time setting capacitor 40 exceeds the threshold voltage of the Schmitt buffer 42, the SR latch 36 is reset, the error amplifier output limiting circuit 37 stops operating, and the output limitation of the error amplifier 30 is released.

(Embodiment 3)
6 and 7 show another example of the error amplifier output voltage limiting circuit 34 in FIG.
Reference numeral 35 denotes a counter, 36 denotes an S-R latch, 46 denotes an error amplifier output switch transistor, and 48 denotes a clock generated from the triangular wave oscillation circuit 32 of FIG.

  Since the error amplifier output voltage limiting circuit 34 is configured in this way, when the boosted output voltage rises by the first signal generation circuit 27 in FIG. 2 and reaches the threshold voltage of the output voltage monitor circuit 4, the SR latch 36 is When set, the error amplifier output switch transistor 46 is turned on, and the output of the error amplifier 30 is brought into conduction with the ground. At the same time, the counter 35 starts counting for a predetermined period with the clock 48. When the counter 35 finishes counting a predetermined period, the SR latch 36 is reset, the error amplifier output switch transistor 46 is turned off, and the output restriction of the error amplifier 30 is released.

FIG. 7 shows a change in the duty ratio immediately after the drive circuit 2 is switched to the second signal generation circuit 1 side.
The output voltage of the error amplifier 30 is electrically connected to the ground for a predetermined period (period A in FIG. 7). After the period A ends, the restriction on the output voltage of the error amplifier 30 is released. In the period A, since the duty ratio of the pulse output from the PWM comparator 31 is limited to zero, the inrush current can be suppressed in the period A. After the output voltage of the error amplifier 30 is released, the process proceeds to the period B. However, since the output voltage of the error amplifier 30 is conducted to the ground voltage in the period A, the output voltage of the error amplifier 30 is the ground voltage at the start of the period B. Start with The duty ratio increases from this state toward the steady state. This operation is composed of an error amplifier 30, a PWM comparator 31, a switching power transistor 5, a choke coil 7, an output smoothing capacitor 9, and a resistor 21. The output voltage of the error amplifier 30 increases at a response speed determined by the loop frequency characteristics of the entire switching power supply circuit. With this increase, the duty ratio of the output pulse of the PWM comparator 31 gradually increases, the output voltage also increases, and reaches the steady state C period.

  In this way, the current reaches from the start to the steady state without passing through the high duty ratio region, so that the inrush current is suppressed. As a result, the input power supply 6 is protected, and the choke coil 7 and the switching power transistor 5 are protected. It becomes possible.

(Embodiment 4)
FIG. 8 shows a specific configuration of the first signal generator 27 of (Embodiment 1) shown in FIG.

  13 is a constant current source, 14 is a capacitor, 15 is a ring oscillator, 16 is a comparator, 17, 18 and 19 are inverters, and 20 is an AND circuit. These components form a first signal generating circuit 27. Yes.

  Immediately after starting the switching power supply circuit, the capacitor 14 is charged by the constant current source 13. Thereby, the capacitor voltage (b) rises as shown in FIG. By the ring oscillator, the voltages at the nodes (a) and (d) operate as shown in FIG. 10, and (d) operates with a constant pulse width. On the other hand, the output (c) of the comparator 16 with (a) and (b) as inputs operates in the same phase as (d), which operates with a constant pulse width, and the capacitor voltage (b) rises. As a result, the pulse width gradually increases and remains high after the capacitor 14 is charged to a predetermined value. Therefore, the output (e) of the AND circuit that receives the output (c) of the comparator 16 that operates with a constant pulse width (d) and operates in the same phase as the (d) is the output of the comparator 16 at the initial charging time. (C) operates with a constant pulse width, and the pulse width is smaller than that in (d), so it becomes dominant and the pulse width gradually increases. After a predetermined charge, the output (c) of the comparator 16 becomes “H”. Since the level remains, the operation (d) operating with a constant pulse width becomes dominant and the pulse width becomes constant. As a result, the output (e) of the AND circuit 20 performs a soft start operation. As described above, the duty ratio of the output pulse of the first signal generation circuit 27 that operates immediately after the switching power supply circuit is activated gradually increases, so that the inrush current during the operation of the first signal generation circuit can also be reduced.

Since the operation after the output voltage rises and the drive circuit 2 is switched to the second signal generation circuit 1 is the same as that in the first embodiment, the description is omitted here.
In this way, since it reaches from the start to the steady state without passing through the high duty ratio region, the inrush current is suppressed. As a result, the input power source 6 is protected, and the choke coil 7 and the switching power transistor 5 are switched. It is possible to protect.

  The present invention can contribute to the improvement of the reliability of various portable devices equipped with a switching power supply circuit that can be used in low input voltage applications.

The circuit diagram which shows the switching power supply circuit which concerns on (Embodiment 1) of this invention More specific circuit diagram of the same embodiment Explanatory drawing of maximum duty ratio operation and duty ratio time change of the same embodiment Configuration diagram of error amplifier output voltage limiting circuit of the same embodiment Error amplifier output voltage limiting circuit according to (Embodiment 2) of the present invention Error amplifier output voltage limiting circuit according to (Embodiment 3) of the present invention Change diagram of duty ratio time of the same embodiment The circuit diagram which shows the switching power supply circuit which concerns on (Embodiment 4) of this invention The circuit diagram explaining the problem to be solved by the invention Waveform diagram showing the soft start operation of FIG. Illustration of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 2nd signal generation circuit 2 Drive circuit 4 Output voltage monitor circuit 5 Switching power transistor 6 Input power supply 7 Choke coil 8 Rectifier diode 9 Output smoothing capacity 25 Output terminal 26 Switching means 27 1st signal generation circuit P1 1st Pulse P2 Second pulse 34 Error amplifier output voltage limiting circuit 35 Counter circuit 36 SR latch 37 Error amplifier output limiting circuit 41 Delay time setting resistor 42 Schmitt buffer

Claims (5)

A step-up switching power supply circuit that switches an input voltage by a switching means to step up and output the voltage,
A first signal generating circuit that operates with the input voltage and outputs a first pulse having a predetermined pulse width;
A second signal generation circuit that operates with the boost output and outputs a second pulse having a pulse width corresponding to the boost output;
A drive circuit that selects one of the first pulse and the second pulse in accordance with the boost output and drives a switching unit; and the second signal generation circuit includes:
A switching power supply circuit configured to limit a pulse width of the second pulse for a predetermined pulse limit period after the drive circuit selects the second pulse without depending on the boost output. The second signal generation circuit includes:
2. The switching according to claim 1, wherein the driving circuit is in a pause state when the first pulse is selected, and the pulse limit period is set to at least a period until the second signal generation circuit stably operates. Power supply circuit. The second signal generation circuit includes:
The switching power supply circuit according to claim 2, wherein the pulse limit period is set by a counter circuit or a CR delay circuit. The second signal generation circuit includes:
The switching power supply circuit according to claim 1, wherein the second pulse is not generated in the pulse limit period. The second signal generation circuit includes:
2. The switching power supply circuit according to claim 1, wherein a pulse width of the second pulse is gradually increased as time elapses after the drive circuit selects the second pulse.

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