JP2006141829A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which eliminates the useless processing for handling the abnormality which otherwise may be started attributed to the state of the communication between the microcomputer for the game control and the microcomputer for the put-out control. <P>SOLUTION: After the reception confirmation signal indicating the inputting of the number of prize balls signal and the prize ball REQ signal into the CPU 371 for the put-out control is turned ON, when the reception confirmation signal off state monitoring time passes before the reception confirmation signal is turned off (YES at step S308), with the conditions that the full capacity error signal or the ball exhaustion error signal are not inputted (NO at step S310), a put-out communication abnormality informing signal is transmitted to a performance control board to execute the abnormality informing performance that enables the specification of the abnormality with the CPU for the performance control. Such procedure can eliminate the useless processing for handling the abnormality which otherwise may be started when no problem exists clearly in the put-out operation itself. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention enables a player to play a predetermined game by launching a game medium into a game area, and a function of paying out a prize game medium based on a predetermined payout condition being satisfied, The present invention relates to a gaming machine provided with a payout means having a function of paying out game media in response to a loan request.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a ball striking device, and a game medium is won in a prize area such as a prize opening provided in the game area, and each of these prize holes is provided. When a game medium is detected with a prize opening switch, a predetermined number of prize game media may be paid out to the player. Further, a variable display unit capable of changing the display state is provided, and configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display result (big hit symbol) There is something that was done.

  Note that the game value means that the state of the variable winning ball device provided in the gaming area of the gaming machine is an advantageous state for a player who is easy to win, and the right for becoming an advantageous state for the player. For example, to generate a premium game medium payout condition.

  In a ball and ball game machine such as a pachinko game machine, the combination of a display result of a variable display unit for displaying a special symbol with a predetermined specific display result is usually referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win.

  In this type of gaming machine, the progress of the game is controlled by a game control microcomputer composed of a microcomputer or the like, and a payout control microcomputer composed of a microcomputer or the like that performs control for paying out a prize game medium such as a pachinko ball. Some computers are provided, and the following control is performed by bidirectional communication between the game control microcomputer and the payout control microcomputer (for example, see Patent Document 1). The game control microcomputer side stores information that can specify the number of prize game media to be paid out based on the establishment of the payout conditions. Then, based on the stored number of payouts, a prize ball command signal specifying the number of payouts of a predetermined number of prize game media is outputted to the payout control microcomputer, and the payout control microcomputer has been outputted. A payout process is executed in which the payout means controls the payout means to pay out the prize game medium specified by the prize ball command signal.

Further, in this conventional gaming machine, when a prize ball command signal from the game control microcomputer is input to the payout control microcomputer, an input confirmation signal (prize ball BUSY signal) is based on the input. Is output from the payout control microcomputer to the game control microcomputer. This input confirmation signal is a signal that can indicate that the payout control microcomputer has input the prize ball command signal and that the payout operation according to the prize ball command signal is being executed. When such an input confirmation signal is output, the game control microcomputer performs a subtraction process for subtracting the number of payouts designated by the prize ball command signal from the number of payouts to be paid out as described above. The game control microcomputer determines that the payout control microcomputer is in an abnormal state when a communication abnormal state occurs in which the payout processing signal is output continuously for an abnormally long time. An abnormal state handling process (predetermined error handling) corresponding to the above is executed.
JP 2004-73515 A (paragraph numbers 0164,0165, FIG. 32)

  However, the conventional gaming machine as described above has the following problems. For example, in the state where communication is abnormal as described above, such as a state in which the prize game medium storage tray is full and payout of the prize game medium is stopped, there is no obvious problem with the payout operation itself. Even if it exists, it is determined that the payout control microcomputer is in an abnormal state, and an abnormal state handling process is performed. For this reason, there is a possibility that useless abnormal state handling processing may be performed due to the communication state between the game control microcomputer and the payout control microcomputer.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to perform wasteful abnormal state handling processing due to the communication state between the game control microcomputer and the payout control microcomputer. An object of the present invention is to provide a gaming machine that can be prevented from being played.

  In order to achieve the above object, according to the first aspect of the present invention, a player can play a predetermined game by firing a game medium (for example, a game ball) into the game area (for example, the game area 7). And a prize game medium (for example, award) based on the fact that a predetermined payout condition (for example, a winning ball is awarded to the left winning entrance 29, the right dropping entrance 30, the left winning entrance 33, and the right winning entrance 39) is established. A payout means (eg, a ball payout device) having a function of paying out a ball (ball) and a function of paying out a rental game medium (eg, a ball rental) in response to a predetermined loan request (eg, operating the ball rental switch 60c). 97) (for example, a pachinko gaming machine 1), the prize ball command signal (for example, for controlling the progress of the game and designating the payout number of the prize game medium and commanding the payout of the prize game medium) ,award Game control microcomputer (for example, peripheral circuits such as CPU 56, ROM 54, RAM 55, I / O port unit 57, etc.) for outputting a number signal and a prize ball REQ signal, and a game control in which the game control microcomputer is mounted An effect device (for example, a variable display device 9, a ceiling frame) that performs a game effect in accordance with a substrate (for example, the main substrate 31) and a display control signal (for example, an effect control signal) output from the game control microcomputer. Display control microcomputer (for example, presentation control CPU 101, ROM, RAM, I / O port, etc.) for controlling the lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the decoration lamp 25, the speaker 27, etc. Circuit) and the payout hand based on a prize ball command signal transmitted from the game control microcomputer A payout control microcomputer (for example, a payout control CPU 371, a peripheral circuit such as a ROM, a RAM, and an I / O port) that controls the ball payout device 97 and the payout control microcomputer are mounted. A payout control board (for example, a payout control board 37), a launching means (for example, a hitting ball launching device provided with a launching motor 94) for launching a game medium toward the game area, and a firing operation control of the launching means are performed. A launch control means (for example, a launch control CPU mounted on the launch control board 91), a launch control board (eg, launch control board 91) on which the launch control means is mounted, and provided outside the gaming machine A signal that is output from the gaming device (for example, the card unit 50) to the payout control board and that is output in response to the loan request (for example, the card unit 50). A relay board (e.g., interface board 66) that relays a connection confirmation signal (e.g., VL signal) output in response to the start of power supply to the gaming device. The relay board is not mounted with any capacitor, the payout control board is provided with a photocoupler (for example, photocoupler 151) on the signal line of the connection confirmation signal, and the photocoupler is provided on the payout control board. Capacitors (for example, capacitors 150a and 150b) connected to the light emission side signal line are provided, and the launch control means turns off the connection confirmation signal input to the payout control board via the photocoupler. (For example, the VL signal output from the photocoupler 151 is sent by the signal branching means 37a to the launch control board 9). When the VL signal branched and input to the input port 372f of the payout control board 37 and input to the launch control board 91 is turned off (NO in step S701), the launching operation of the launching means is stopped. Including a firing operation stop control means (for example, a function of a firing control CPU that sets unrotated data in the firing motor excitation pattern buffer when the VL signal is off in step S701), and the game control When the power supply to the gaming machine is stopped, the microcomputer for backup uses backup storage means for storing data for specifying the control state by the gaming control microcomputer for a predetermined period (for example, the contents when the power supply is stopped) And when the power supply to the gaming machine is restored The game state recovery means for recovering the control state by the game control microcomputer based on the data stored in the backup storage means (for example, a function of the CPU 56, which executes steps S81 to S84) And a payout number storage means (for example, a total prize ball number storage buffer in the RAM 55: step included in the backup storage means for storing information that can specify the number of prize game media to be paid out based on the establishment of the payout condition) S219) and a prize ball command signal output means for outputting the prize ball command signal to the payout control microcomputer based on the number of payouts stored in the payout number storage means (for example, the CPU 56 executes step S232) And a portion for outputting a prize ball command signal from the output circuit 67) and the payout The payout memory number subtraction means (for example, a function of the CPU 56, which performs a subtraction process for subtracting the payout number designated by the prize ball command signal from the payout number stored in the number storage means, and the total number of winning balls in step S316b) A portion for subtracting the contents of the prize ball number buffer from the storage buffer), and the payout control microcomputer is means for storing data for specifying a control state by the payout control microcomputer, the game When the power supply to the machine is stopped, the payout control storage means (for example, the RAM mounted on the payout control board 37) that does not store the data in backup and the payout means are controlled, and the prize ball command signal A prize game medium payout control means (for example, a payout control CPU 3) that executes a payout process for paying out a specified number of payout game media. 1 is a function for setting the number indicated by the award ball number signal in the step S551c in the award ball unpaid number counter and executing the payout control execution process (step S655) to execute the award ball payout). The game medium payout control means for controlling the payout means to execute the ball lending process for paying out the game media based on the loan request (for example, a function of the payout control CPU 371 and waiting for payout start) A portion for executing lending paying by setting the unpaid-off number counter to 25 in step S836 of the process (step S740) and executing a payout motor stop waiting process (step S741) and a payout passing wait process (step S742)) And an input confirmation signal (for example, reception confirmation signal) for a predetermined period based on the input of the prize ball command signal. Input confirmation signal output means (for example, a function of the payout control CPU 371 that turns on the reception confirmation signal in step S546) to be output to the game control microcomputer, and the payout processing by the prize game medium payout control means In-operation signal output means (for example, a function of the payout control CPU 371 for outputting a signal during operation (for example, a payout operation signal) to the game control microcomputer during execution of the second main control communication processing (In step S532b), the payout operation in-progress signal is turned on in step S551d, and the payout operation in-progress signal is turned off in step S554 of the third main control communication processing (step S532c). The confirmation signal output means is conditioned on the condition that the ball lending process by the rental game medium payout control means is not executed. The input confirmation signal is transmitted to the game control microcomputer (for example, when the BRDY signal is OFF in step S542, a reception confirmation signal and a payout operation signal are output), and the payout memory number subtracting means The subtraction process is performed based on the fact that the control microcomputer has input the operating signal (for example, after the payout operating signal is determined to be on in step S313, the prize ball timer is 0 in step S314). When it is determined, the game control microcomputer executes the step S316b when the input confirmation signal does not stop even after a predetermined period of time has elapsed after inputting the input confirmation signal (for example, step S283). After the reception confirmation signal is determined to be ON in step S308, when it is determined in step S308 that the prize ball management timer is 0 , An abnormality determining means (for example, a function of the CPU 56) that determines that an abnormal state has occurred on condition that the payout by the payout means is not in a stopped state (for example, a full tank error signal or a ball out error signal is not input). In step S283, it is determined that the reception confirmation signal is ON, and in step S308, it is determined that the prize ball management timer is 0. Then, in step S310, the full error signal and the out-of-ball error signal are input. A portion for determining that an abnormality has occurred when the abnormality is not detected) and for causing the display control microcomputer to notify that the abnormality has occurred when the abnormality determination means determines that an abnormality has occurred. Abnormality notification control signal output means (for example, CPU) for outputting the abnormality notification control signal (for example, payout communication abnormality notification signal) 6 after setting the payout communication abnormality notification signal in step S311 and inputting the input confirmation signal in step S721 of the special symbol command control process (step S27) and the input confirmation signal. The prize ball command signal output regulation for regulating the output of the prize ball command signal output means by the prize ball command signal output means regardless of the number of prize game media stored in the payout number storage means until the in-operation signal is stopped. Means (for example, the function of the CPU 56, and in step S316a of the award ball waiting process 2 (step S233), the payout operation signal off determination time value is set in the award ball timer, and the award ball waiting process 3 (step S234). Until the prize ball timer is determined to be 0 in step S273, control is performed so that step S276 is not executed. A portion for restricting the execution of step S232).

  According to a second aspect of the present invention, the game control microcomputer is configured to instruct to initialize the payout control microcomputer when the abnormality determination means determines that the abnormal state has occurred. Initialization instruction signal output means (for example, a function of the CPU 56, which outputs a reset initialization signal (eg, a payout initialization signal), sets the payout initialization signal in step S311 and outputs it to the payout control board 37) The payout control microcomputer initializes the payout control microcomputer when the initialization instruction signal is input (for example, a signal relating to prize ball payout control and data such as a flag). Clear the value of the main control communication code used in the main control communication process to 0 and execute the main control communication process. Initialization means (for example, a function of the payout control CPU 371) that initializes the control state by software, such as newly enabling execution from processing, or initialization from the power-on state by system reset Then, when the initialization signal is turned on in step S767a of the error processing (step S656), the signal relating to the winning ball payout control and the data such as the flag are cleared, and then the value of the main control communication code is set to 0. (Step S767b, step S767c)) is further included.

  According to a third aspect of the present invention, there is provided a game control connection confirmation signal indicating that the game control microcomputer is connected to the payout control microcomputer as power supply to the game machine is started. For example, a game control connection confirmation signal output means for outputting a connection confirmation signal A) to the payout control microcomputer (for example, a function of the CPU 56 and an output corresponding to the connection confirmation signal A in step S12 or step S82) And setting the contents of the port buffer to a value corresponding to the ON state of the connection confirmation signal A, and further including an output process (step S33), wherein the payout control microcomputer receives the game control connection confirmation signal. When not input (for example, step S544 of the main control communication normal process (step S531)) When the connection confirmation signal A is determined to be in an OFF state), a payout process prohibiting means for prohibiting the execution of the payout process (for example, a function of the payout control CPU 371 and the main control communication normal process (step S531)) A portion that terminates the processing when it is determined in S544 that the connection confirmation signal A is in an off state.

  According to a fourth aspect of the present invention, a payout control connection confirmation signal (for example, indicating that the payout control microcomputer is connected to the game control microcomputer when power supply to the game machine is started). , A connection control signal output means for outputting a connection confirmation signal B) to the game control microcomputer (for example, a function of the payout control CPU 371 for turning on the connection confirmation signal B in step S610) The game control microcomputer does not input the payout control connection confirmation signal (for example, it is determined that the connection confirmation signal B is off in step S250 of the prize ball transmission process (step S232)). The prize ball command signal output means for prohibiting the prize ball command signal output means from outputting the prize ball command signal. It further includes a prohibiting means (for example, a function of the CPU 56 that terminates the process when the connection confirmation signal B is determined to be in the OFF state in step S250 of the prize ball transmission process (step S232)). .

  In the invention of claim 5, the game control microcomputer determines that the reception confirmation signal is on in step S283 of the award ball waiting process 2 (step S233) when the input confirmation signal is input. And when the prize ball timer is determined to be 0 in step S293), the output of the prize ball command signal is stopped (for example, the prize ball REQ in step S299 of the prize ball waiting process 2 (step S233)). The signal is turned off).

  According to a sixth aspect of the present invention, the prize ball command signal output means is a means for outputting the prize ball command signal, and is a payout number signal (for example, a prize ball number signal) for designating the number of payouts of the game medium. The payout number signal output means for outputting the payout number signal and the take-in request signal (for example, a prize ball REQ signal) for requesting the take-in of the payout number signal. A prize ball number signal and a prize ball REQ signal are output in a prize ball transmission process (step S232) (step S254, step S255)), and the payout control microcomputer receives the take-in request When the signal is input, the payout number signal is captured (for example, if the prize ball REQ signal is on in step S545a of the main control communication normal process (step S531)). When the number indicated by the award ball number signal is set in the award ball unpaid number counter in step S551c of the second main control communication process (step S532b), and the game control microcomputer inputs the input confirmation signal In step S283 of the award ball waiting process 2 (step S233), the reception confirmation signal is turned on, and the award ball timer is determined to be 0 in step S293. In this case, the output of the prize ball command signal is stopped by turning off the prize ball REQ signal in step S299).

  In the invention of claim 7, the payout control microcomputer outputs the input confirmation signal by the input confirmation signal output means (for example, received in step S546 of the main control communication normal processing (step S531)). After the confirmation signal is turned on, when the output of the prize ball command signal by the prize ball command signal output means does not stop even after a predetermined period (for example, in the second main control communication processing (step S532b)) When the prize ball REQ signal is OFF in step S551 and the main control communication control timer 1 is determined to be 0 in step S551b), a prize for executing control for notifying that an abnormal state has occurred. Ball command signal abnormality notifying means (for example, a function of the payout control CPU 371, step S532 of the second main control communication processing (step S532b)) Set the prize balls REQ signal error bit 52, and further comprising a display control processing portion for displaying the "5" in the error display LED374 in step S791 in (step S658)).

  In the invention according to claim 8, the game control microcomputer has a period in which the input confirmation signal output from the input confirmation signal output means is not input after the prize ball command signal is output. Period measurement means for measuring (for example, a prize ball management timer in which a reception confirmation signal ON monitoring time value is set) and when the period measured by the period measurement means has passed a predetermined period (for example, a prize ball waiting process 2) (When the prize ball management timer becomes 0 in step S287 of step S233), the data indicating the period measured by the period measuring means is initialized, and the data indicating the output state of the prize ball command signal is initialized. Initialization (for example, clearing signals related to prize ball control, timers, flags, etc. in step S289 of the prize ball waiting process 2 (step S233)) ), The prize ball command signal re-output means for re-outputting the prize ball command signal (for example, the function of the CPU 56, and the value of the prize ball process code is set in step S290 of the prize ball waiting process 2 (step S233)). The prize ball transmission process (step S232) is executed again by setting the value to 0, and the prize ball waiting process 1 (step S231) is executed in the next prize ball control process (step S202). Step S254), and a portion that outputs a prize ball number signal and a prize ball REQ signal in step S255).

  According to a ninth aspect of the present invention, the gaming machine detects whether or not a predetermined amount or more of the game medium supplied to the payout means is secured, and the payout control is performed when the amount is less than the predetermined amount. A game medium running out detecting means (for example, a ball running out switch 187) for outputting a game medium running out signal (for example, a detection signal from the ball running out switch 187) to the microcomputer for use, and a game medium paid out by the paying out means are stored. Whether or not a predetermined amount or more of game media is stored in the storage unit (for example, the surplus ball receiving tray 4), and when the amount exceeds the predetermined amount, a storage state detection signal ( For example, it further comprises storage state detection means (for example, a full tank switch 48) for outputting a full tank switch 48 detection signal), and the dispensing control microcomputer. When the game media out signal is input (for example, YES in step S762 of error processing (step S656)), or when the storage state detection signal is input (for example, step of error processing (step S656)). In step S757, a full error bit is set in step S758 of the error processing (step S656), which is a function of the abnormality detection payout processing prohibition means (for example, the payout control CPU 371) that prohibits the execution of the payout processing. Alternatively, the ball running out error bit is set in step S763, the portion that prohibits the payout process by completing YES in step S541 of the main control communication normal process (step S531), and the game medium When a cut signal is input or when the storage state detection signal is input A payout stop state signal output means (for example, a payout control CPU 371) for outputting a payout stop state signal (for example, a full tank error signal, a ball run out error signal) indicating that the payout process is stopped to the game control microcomputer. And the full error signal is turned on in step S759 of error processing (step S656), the full error signal is turned off in step S761, and the ball break error signal is outputted in step S764 of error processing (step S656). A portion that turns on and turns off the ball-out error signal in step S766), and that the gaming control microcomputer is in a state where the payout by the payout means is stopped based on the input of the payout stop state signal. Payout state determination means for determining (for example, the function of the CPU 56) And a portion that determines whether or not a full-fill error signal or a ball-out error signal is input in step S310 of the award ball waiting process 2 (step S233), and the abnormality notification control signal output means includes: A stop state notification control signal (for example, a full tank error notification signal, for informing the display control microcomputer that the stop state has occurred when the payout state determination means determines that the stop state is detected) It is determined that a full error signal or a full ball error signal has been input in step S310 of the function for outputting a ball shortage error notification signal (for example, award ball waiting process 2 (step S233), and a full tank error is detected in step S310a. When the signal is input, a full-tank error notification signal is set in step S310b. Set the burn out error signal when the Tan'era signal is not inputted filled with 10a, and having a special symbol command control processing portion transmitted in step S721 in (step S27) to effect control board 80).

  In the invention according to claim 1, when the ball lending process by the lending game medium payout control means is not executed, a predetermined period based on the input of the prize ball command signal by the payout control microcomputer, An input confirmation signal is output to the game control microcomputer. After the input confirmation signal is input to the game control microcomputer by the payout control microcomputer, the payout by the payout means is not stopped when the input confirmation signal does not stop even after a predetermined period. Then, it is determined that an abnormal condition has occurred. For this reason, even when the input confirmation signal is output continuously for an abnormally long period, when the payout operation itself is in a state where there is no obvious problem such as payout by the payout means being stopped. The game control microcomputer does not determine that the payout control microcomputer is in an abnormal state. Therefore, it is possible to prevent unnecessary abnormal state handling processing from being performed due to the communication state between the game control microcomputer and the payout control microcomputer.

  Further, a payout operation in-progress signal is output to the game control microcomputer while the payout control microcomputer is executing the payout process, and a prize ball command signal output means until the in-operation signal is stopped in the game control microcomputer. The prize ball command signal is output after the payout processing by the payout control microcomputer is completed, and the prize ball command signal is reliably transferred by the payout control microcomputer. it can.

  In the invention according to claim 2, when the abnormality determining means determines that an abnormal state has occurred, an initialization instruction signal for instructing initialization of the payout control microcomputer is provided. The communication abnormal state can be automatically recovered based on the output of the output to the output and the payout control microcomputer is initialized, and the payout control can be executed smoothly.

  In the invention according to claim 3, when the payout control microcomputer does not input a game control connection confirmation signal, that is, when the game control microcomputer is not connected to the payout control microcomputer, On the control microcomputer side, there is a possibility that it is unclear whether or not the payout number subtraction process according to the input confirmation signal can be normally performed by communication with the payout control microcomputer side. In such a case, since the execution of the payout process is prohibited, it is possible to prevent an error from occurring in the storage information on the number of payouts of the prize game medium in the payout number storage means, thereby allowing an excessive amount of the prize game media. Can be prevented.

  In the invention according to claim 4, the game control microcomputer receives the input confirmation signal in a state where the prize ball command signal is not output, that is, the game control microcomputer and the payout control microcomputer. Whether the payout amount subtraction process according to the input of the input confirmation signal can be normally performed on the game control microcomputer side by the communication with the payout control microcomputer side in the communication abnormal state between It may be in an unknown state. In such a case, the game control connection confirmation signal output means prohibits the game control connection confirmation signal output means from outputting on the game control microcomputer side, so that the payout process is prohibited on the payout control microcomputer side. Therefore, it is possible to prevent an error from occurring in the storage information on the number of prize game media to be paid out in the payout number storage means, thereby preventing excessive payout of the prize game medium.

  In the invention according to claim 5, when the input confirmation signal is inputted, that is, when the prize ball command signal is confirmed to be inputted, the prize ball command signal is stopped immediately. When the control state in the microcomputer is unstable, the payout control microcomputer inputs an input confirmation signal and then inputs an award ball command signal multiple times. Can be prevented.

  In the invention according to claim 6, when the input confirmation signal is input, that is, when it is confirmed that the payout number signal is input, the take-in request signal is immediately stopped. When the control state in the computer is unstable, the payout control microcomputer inputs an input confirmation signal, and then inputs an acquisition request signal multiple times. Can be prevented. In addition, when the take-in request signal is input, the payout control microcomputer performs processing for taking in the payout number signal, and when the game control microcomputer inputs the input confirmation signal, the payout number signal is output. The output of the prize ball command signal is stopped by stopping the output of the take-in request signal. For this reason, when checking whether or not the prize ball command signal is stopped on the payout control microcomputer side, it is only necessary to check whether or not a take-in request signal is output, and the payout for designating the number of payouts of game media. Since it is not necessary to confirm in detail what value the numerical signal has, the processing load on the payout control microcomputer can be reduced.

  Further, in the invention according to claim 7, after outputting the input confirmation signal in response to the prize ball command signal, an abnormal state occurs when the output of the prize ball command signal does not stop after a predetermined period of time. Therefore, it is possible to recognize that such an abnormal state has occurred, and to prevent excessive payout of prize game media.

  Further, in the invention according to claim 8, since the prize ball command signal is re-output when the period during which the input confirmation signal outputted based on the prize ball command signal is not input has passed a predetermined period, The payout process according to the prize ball command signal can be surely performed.

  In the invention according to claim 9, when the game medium running out signal is input to the payout control microcomputer or when the storage state detection signal is input, the execution of the payout process is prohibited, and the game control microcomputer The payout stop state signal indicating that the payout process is stopped is output to Then, based on the input of the payout stop state signal by the game control microcomputer, it is determined that the payout by the payout means is in the stop state, and the display control microcomputer is notified that the stop state has occurred. Since the stop state notification control signal is output, the player can grasp the abnormal state.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  First, an overall configuration of a bullet ball gaming machine which is an example of a gaming machine will be described. FIG. 1 is a front view of a ball game machine as viewed from the front. In the following embodiments, a pachinko gaming machine will be described as an example of a gaming machine, but the present invention is not limited to this, and other gaming machines such as a coin gaming machine and a slot machine, for example. In other words, the present invention can be applied to any game machine that can play a game using a game medium and pays out a prize game medium based on the fact that a payout condition is established by the game.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). And a structure including:

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 includes, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, since the symbol display area and the start memory display area are provided separately, the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the start memory number may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9. However, a display (special symbol start memory display) for displaying the start memory number may be provided separately from the variable display device 9. Good.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing a large winning opening (variable winning ball apparatus). Of the winning balls guided to the back of the game board 6 from the opening / closing plate 20, the winning balls that have entered one (V winning area: special area) are detected by the V count switch 22, and all winning balls from the opening / closing plate 20 are counted. It is detected by the switch 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball enters the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of game balls that have entered the gate 32 is provided. Each time there is an entry to the gate 32, the normal symbol start memory display 41 increments the LED to be lit by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a left drop winning opening 29, a right drop winning opening 30, a left winning opening 33, and a right winning opening 39 as a plurality of winning openings, and each winning opening 29, 30, 33, 39 of the game ball is provided. Winning prizes are detected by a left drop prize opening switch 29a, a right drop prize opening switch 30a, a left prize opening switch 33a, and a right prize opening switch 39a, respectively. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning.

  In addition, the game balls won in the winning holes 29, 30, 33, 39, the start winning hole 14 and the grand prize opening are led to a winning ball passage as a passage for discharging the gaming balls and provided in each winning opening. Detected by a winning opening switch. The winning ball passages continuing from the respective winning openings are configured to merge at a predetermined position, and to discharge the gaming balls won in all the winning openings through the confluence passage as a passage of the joined gaming balls.

  Decorative lamps 25 blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 is provided at the bottom for discharging the game balls that have not won a prize to the back of the pachinko gaming machine 1. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit while paying out a prize ball is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the refill ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter, referred to as a card unit 50) that enables ball lending by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 50, a card A card insertion indicator lamp indicating that a card is inserted into the unit 50, a card insertion slot into which a card as a recording medium is inserted, and a card reader / writer mechanism provided on the back surface of the card insertion slot are inspected. In some cases, a card unit lock for releasing the card unit 50 is provided.

  Further, the pachinko gaming machine 1 includes a hitting ball launching device (not shown) that hits a game ball and launches it in the game area 7. A game ball fired from the ball striking device enters the game area 7 through the ball striking rail, and then descends the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol starts variable display (variation) on the variable display device 9 if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When a game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stopping is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball enters the gate 32 and is detected by the gate switch 32a, the normal symbol display unit 10 enters a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 are increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol, which is disadvantageous for the player. Change from state to advantageous state. It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 2, on the back side of the gaming machine, a variable display control unit 49 including an effect control board 80 on which an effect control microcomputer for controlling the variable display device 9 is mounted, a game control microcomputer, and the like are mounted. A game control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. In addition to controlling the variable display device 9, the effect control microcomputer controls the variable display device 9 provided on the game board 6, various decoration LEDs, the normal symbol start memory display 41, the decoration lamp 25, and the frame side. The lighting control of the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c provided to the speaker 27 and the generation of sound from the speaker 27 are controlled.

  For driving various decoration LEDs provided on the game board 6, normal symbol start memory display 41, decoration lamp 25, top frame lamp 28a, left frame lamp 28b and right frame lamp 28c provided on the frame side. The drive circuit is mounted on a lamp driver board 35 that is electrically connected to the effect control board 80. A drive circuit for driving the speaker 27 is mounted on a sound control board 70 that is electrically connected to the effect control board 80.

  Further, a power supply board 910 on which a power supply circuit for generating DC30V, DC21V, DC12V and DC5V is mounted and a launch control board 91 for controlling the hitting ball launching apparatus described above are provided. Although most of the power supply substrate 910 overlaps with the main substrate 31, there is an exposed portion that is exposed so as to be visible from the outside without overlapping the main substrate 31. In this exposed portion, electric power to each electrical component control board (main board 31, presentation control board 80, payout control board 37, launch control board 91) of the pachinko gaming machine 1 and each electrical component provided in the gaming machine A power switch as a power supply permission means for executing or shutting off the supply, and a storage content holding means included in the main board 31 and the payout control board 37 (for example, a backup RAM capable of holding the contents even when the power supply is stopped) A clear switch (not shown here and shown as a clear switch 921 in FIG. 4) is provided as an operation means for clearing the backup data stored in.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. In addition, an information terminal board (information output board) 34 provided with terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game ball stored in the storage tank 38 passes through the guide rail, and reaches the ball payout device 97 (see FIG. 4) covered with the payout case 40A through the curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 is stopped. The ball break switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage. (Proximate part). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize and game balls based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device 97 is stopped, the operation of the ball payout device 97 is stopped, and the driving of the hitting ball launching device is also stopped.

  FIG. 3 is a front view (FIG. 3 (A)) and a cross-sectional view (FIG. 3 (B)) showing the ball dispensing device 97 covered with the dispensing case 40A. The ball dispensing device 97 is fixed to the lower portion of the passage body installed below the ball break switch 187. The passage body has a ball passage 293 for flowing down two rows of game balls whose flow-down direction is converted into the left-right direction by a curve saddle. A ball break switch 187 is installed on the upstream side of the ball passage 293. In practice, a ball break switch 187 is installed in each ball passage 293. The ball break switch 187 detects the presence or absence of a game ball in the ball passage. When the ball break switch 187 no longer detects a game ball, the rotation of the payout motor 292 in the ball payout device 97 is stopped to play the game ball. The payout of is immobilised.

  Also, the ball break switch 187 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball passage 293.

  In the ball payout device 97, a payout motor 292 using a stepping motor pays out one winning ball or one game ball based on a ball lending request, for example, by rotating a cam. Further, below the ball payout device 97, for example, a payout count switch 301 by a proximity switch is provided. Each time one game ball falls from the ball payout device 97, the payout count switch 301 is turned on. That is, the payout count switch 301 detects a game ball actually paid out from the ball payout device 97. Therefore, the payout control microcomputer can count the number of game balls actually paid out by the detection signal of the payout count switch 301.

  In this embodiment, the ball payout device 97 is configured to perform both prize ball payout and ball lending. That is, this is a dual-use type ball payout device for paying out both premium game media and rental game media. A ball payout device for paying out a winning ball and a ball payout device for lending a ball may be provided separately. When separately provided, the payout means is composed of a ball payout device for paying out a prize ball and a ball payout device for lending a ball. Furthermore, for example, it may be configured to change the direction of rotation of the cam or sprocket so as to separate the winning ball payout and the ball lending. The present invention can be applied to any structure other than the structure).

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. 4 also shows a payout control board 37, an effect control board 80, a launch control board 91, and the like. On the main board 31, a basic circuit (corresponding to a game control microcomputer) 53 for controlling the pachinko gaming machine 1 in accordance with a program, a gate switch 32a, a start port switch 14a, a V count switch 22, a count switch 23, a left drop prize An input driver circuit 58 for supplying signals to the basic circuit 53 from the mouth switch 29a, the right drop winning mouth switch 30a, the left winning mouth switch 33a, the right winning mouth switch 39a, and the clear switch 921, and the variable winning ball apparatus 15 A solenoid 16 that opens and closes, a solenoid 21 that opens and closes the opening and closing plate 20, and a solenoid circuit 59 that drives a solenoid 21A for switching a path in the special prize opening according to a command from the basic circuit 53 are mounted.

  The gate switch 32a, the start opening switch 14a, the V count switch 22, the count switch 23, the left drop winning opening switch 29a, the right falling winning opening switch 30a, the left winning opening switch 33a, the right winning opening switch 39a, etc. What is called a sensor may be used. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. Each of the start opening switch 14a, the V count switch 22, the count switch 23, the left dropping winning opening switch 29a, the right dropping winning opening switch 30a, the left winning opening switch 33a, and the right winning opening switch 39a that performs winning detection is detected as winning. It is also a means.

  Note that the winning detection means may be configured to collectively detect the respective game balls that have won separately a plurality of winning openings. In addition, even if a passing gate such as the gate switch 32a is used, if a prize ball is to be paid out, a game ball entering the passing gate becomes a win, and a switch ( For example, the gate switch 32a) serves as a winning detection means. Furthermore, in this embodiment, a game ball won in the V winning area is detected by the V count switch 22 and also by the count switch 23, but may be detected only by the V count switch 22. When a game ball won in the V winning area is detected only by the V count switch 22, the number of game balls won in the big prize opening is the number detected by the V count switch 22 and the number detected by the count switch 23. , The sum of

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 performs a control operation in accordance with a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as a storage means (variation data storage means for storing fluctuation data) used as a work memory, and a program. A CPU 56 and an I / O port unit 57 are included. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built in, and the ROM 54 and the I / O port unit 57 may be externally attached or built in.

  Since the CPU 56 executes control according to the program stored in the ROM 54, the CPU 56 executes (or performs processing) hereinafter, specifically, the CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on substrates other than the main substrate 31. Thus, the CPU 56 constitutes a game control microcomputer. When the ROM 54 and the RAM 55 are not built in the CPU 56, the game control microcomputer is constituted by the ROM 54, the RAM 55, and the basic circuit 53 including the CPU 56.

  A RAM (which may be a CPU built-in RAM) 55 is a backup RAM that is partially or entirely backed up by a backup power source created in the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the power supply of the backup power supply is disabled). In particular, the control state of the payout control such as at least data corresponding to the game state, that is, the control state of the game control microcomputer, the data indicating the number of unpaid prize balls, and the data indicating the output state of the output signal related to the payout control is specified. The data is stored (backup stored) in the backup RAM.

  Note that the data according to the control state of the microcomputer for game control is to restore the control state of the game control before the occurrence of a power failure, etc., based on the data when it is recovered after a power failure, etc. Necessary data. Further, the data for specifying the control state of the payout control includes the output state of various output signals such as a prize ball command signal based on the data when recovered after a power failure or the like, and the control state of the payout control This data is necessary to restore the system before a power outage occurs. For example, among the data specifying the control state of the payout control stored in the backup, the data specifying the output state of various output signals such as a prize ball command signal is data indicating the output state of each output port. Data indicating the output status of each output port is backed up and stored together with other control data as data specifying the control status of the payout control when a power failure occurs, and in this way at the time of recovery after a power failure Based on the data indicating the output state of each output port stored in the backup, the output state of various signals is restored.

  The hitting ball launching device that hits and launches the game ball includes a launch motor 94 that is controlled by a circuit on the launch control board 91, and launches the game ball toward the game area 7 as the launch motor 94 rotates. The launch control board 91 is for controlling the launch operation by the ball striking device by outputting a drive signal to the launch motor 94 in accordance with the operation amount of the operation knob 5. The launch control board 91 is connected to the wiring from the operation knob 5 and to the launch motor 94. The firing control board 91 fires a hit ball at a speed corresponding to the operation amount by adjusting the driving force of the firing motor 94 according to the operation amount of the operation knob 5.

  In this embodiment, the effect control microcomputer mounted on the effect control board 80 performs display control of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board 6, and the frame side Display control of the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. The effect control microcomputer mounted on the effect control board 80 also performs display control of the variable display device 9 that variably displays the special symbol and the normal symbol display 10 that variably displays the normal symbol. Such control by the effect control microcomputer is executed based on a control signal such as an effect control signal (display control signal) received from the game control microcomputer.

  Further, in this embodiment, a power supply monitoring circuit 920 that detects the occurrence of a power supply stop to the gaming machine and outputs a power-off signal to the CPU 56 is provided. The power monitoring circuit 920 monitors the power supply voltage supplied from the power supply board 910, and outputs a power cut-off signal when the power supply is stopped when the voltage drops below a predetermined voltage.

  FIG. 5 is a block diagram showing components related to payout of prize balls (prize game media) and rental balls (rental game media) such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, a payout control microcomputer including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer is a one-chip microcomputer and has at least a built-in RAM. Further, unlike the RAM 55 on the main board 31, the RAM is not backed up by a power source. The payout control CPU 371, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute a payout control microcomputer. Accordingly, the payout control microcomputer is realized by a payout control CPU 371, a payout control microcomputer including a RAM, a ROM, and an I / O port, but is mainly realized by a payout control CPU 371 that executes control according to a program. The

  Detection signals from the full tank switch 48 and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. Further, detection signals from the ball break switch 187 and the payout motor position sensor 295 are input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 292, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . The payout control CPU 371 of the payout control board 37 stops payout processing when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. To do. Furthermore, when the detection signal from the full tank switch 48 indicates a full tank state, the ball launching from the ball striking device is stopped.

  When there is a win, the output circuit 67 of the main board 31 receives a prize ball REQ signal (prize ball request signal) for making a prize ball payout request and a prize ball indicating the number of prize balls to be paid out as a prize ball command signal. A number signal is output (turns on). The award ball number signal is composed of 4-bit data (binary 4-digit data) and is output by four signal lines. Note that the ON state of the signal, that is, the output state is a state where the signal is significant, and turning ON means that the signal receiving side is instructed to start some processing based on the signal. To do. For example, when the prize ball number signal indicating the number of prize balls and the prize ball REQ signal are turned on, the payout control microcomputer recognizes the number of prize balls paid out indicated by the prize ball number signal. Means command.

  The winning ball number signal is input to the I / O port 372e via the input circuit 373A. The prize ball REQ signal is also a fetch request signal for requesting the payout control microcomputer to fetch the prize ball number signal. When the winning ball REQ signal and the winning ball number signal are input via the I / O port 372e, the payout control CPU 371 controls to drive the ball paying device 97 to pay out the number of game balls indicated by the winning ball number signal. I do. From the main board 31 to the payout control board 37 is a signal indicating that the main board is connected to the power source, and the main board 31 (game control microcomputer) is the payout control board 37 (payout control microcomputer). A connection confirmation signal A, which is a signal indicating that the connection is established, is transmitted. The connection confirmation signal A is output to the payout control board 37 via the output circuit 67. Further, a signal indicating that the payout control board 37 is connected to the power source is sent from the payout control board 37 to the main board 31, and the payout control board 37 (the payout control microcomputer) is connected to the main board 31 (game control). The connection confirmation signal B, which is a signal indicating that it is connected to the microcomputer), is transmitted.

  The connection confirmation signal A is generated when the power of the pachinko gaming machine 1 is turned on and power is supplied to the main board 31 (specifically, when step S12 or step S82 of the main process shown in FIG. 13 is executed). (I) Output is started, and thereafter, when the power of the pachinko gaming machine 1 is cut off and the supply of power to the main board 31 is cut off, the output is stopped. Further, the connection confirmation signal B is generated when the power of the pachinko gaming machine 1 is turned on and power is supplied to the payout control board 37 (specifically, when step S610 of the main process shown in FIG. 38 is executed). ) The output is started, and then the output is stopped when the power of the pachinko gaming machine 1 is cut off and the supply of power to the payout control board 37 is cut off. The prize ball REQ signal and the prize ball number signal correspond to prize ball command signals for designating the number of payouts.

  Further, when the payout control microcomputer receives the prize ball command signal, it transmits a reception confirmation signal indicating that it has been received to the main board 31. This reception confirmation signal is a signal output based on the prize ball command signal being input to the payout control microcomputer. That is, the reception confirmation signal has a function as an input confirmation signal that is output based on the prize ball command signal being input to the payout control microcomputer. The reception confirmation signal is transmitted to the main board 31 via the output port 372b of the payout control board 37 and the output circuit 373B. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port unit 57.

  Further, when the payout control microcomputer is executing a prize ball payout process, the payout control microcomputer indicates a payout process (payout operation) through the output port 372b and the output circuit 373B. A payout operation in-progress signal is transmitted as a processing signal. This payout operation in-progress signal is a signal that is output based on the winning ball command signal being input to the payout control microcomputer. In other words, the payout operation in-progress signal also has a function as an input confirmation signal that is output based on the input of the prize ball command signal to the payout control microcomputer.

  The payout control CPU 371 receives, via the output port 372b, a prize ball information signal indicating the number of prize balls to be paid out (number of prize balls) and a ball lending number signal indicating the number of balls lent. Output terminal 160). A driver circuit is provided outside the output port 372b, but is not shown in FIG. In addition, door opening switches 161A and 161B are connected to the terminal board 160 (frame external terminal board).

  Further, the payout control CPU 371 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing lighting / extinguishing is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control board 37 to the payout motor 292 is transmitted to the payout motor 292 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. The interface board (relay board) 66 is connected to a balance display board 60 on which a frequency display LED 60a, a ball lending LED 60b, a ball lending switch 60c, and a return switch 60d provided in the vicinity of the hitting ball supply tray 3 are mounted. .

  From the balance display board 60 to the card unit 50, a ball lending switch signal indicating that the ball lending switch 60c has been operated and a return switch signal indicating that the return switch 60d has been operated in accordance with the player's operation are interfaced. It is given through the substrate 66. Further, a balance display signal indicating a balance of the prepaid card and a ball lending display signal are given from the card unit 50 to the balance display board 60 via the interface board 66. Between the card unit 50 and the payout control board 37, a connection confirmation signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal (PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection confirmation signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  Note that no capacitor is mounted on the interface board 66, and photocouplers 66a and 66b are mounted on the signal lines of the EXS signal and the PRDY signal output from the payout control board 37 on the interface board 66, respectively. The Photocouplers 66c and 66d are mounted on the signal lines of the BRDY signal and the BRQ signal output from the card unit 50 on the interface board 66, respectively. However, no photocoupler is mounted on the signal line of the VL signal output from the card unit 50 on the interface board 66, and only the VL signal output from the card unit 50 to the payout control board 37 is passed. .

  Further, a capacitor 150 is mounted on the signal line of the VL signal on the payout control board 37, and the photocoupler 151 mounted on the signal line of the VL signal is based on the fact that the output level of the VL signal has reached a predetermined level. The VL signal is output. As shown in FIG. 6, the photocoupler 151 includes a light emitting unit 151a and a light receiving unit 151b. The light emitting unit 151a emits light based on the input of the VL signal, and the light emission is transmitted to the light receiving unit 151b. An electric signal (in this case, a VL signal) is output based on the detected result. In this embodiment, the electrical signal output from the photocoupler 151 is branched and input to the input port 372f and the launch control board 91.

  As described above, since the signal between the card unit 50 and the payout control board 37 is configured to be transmitted via the photocoupler, when either the card unit 50 or the payout control board 37 breaks down. For example, a signal with an abnormal level can be prevented from being transmitted. Among these signals, the transmission line of the connection confirmation signal (VL signal) is compared with the transmission line of other signals having a function as a mere signal line, compared with the power line (the photocoupler of the transmission path of other signals). Therefore, it is necessary to stabilize the power supply, and a capacitor 150 for stabilizing the power supply is provided in addition to the photocoupler.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control CPU 371 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50 and a ball lending switch signal based on the operation of the ball lending switch is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50 and, when detecting the falling of the BRQ signal from the card unit 50, drives the payout motor 292 to give a predetermined number of balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, when the BRDY signal from the card unit 50 is not in the ON state, when a prize ball command signal is received from the game control microcomputer, the prize ball payout control is executed. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  The power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  FIG. 6 is an explanatory diagram showing details of a broken line portion of FIG. 5 which is a detailed portion of the photocoupler 151 and the capacitor 150 mounted on the payout control board 37. As described above, the signal line of the VL signal on the payout control board 37 is connected in order of the capacitor 150 including the capacitor 150a and the capacitor 150b, the resistor 152, the photocoupler 151 including the light emitting unit 151a and the light receiving unit 151b. Yes.

  The VL signal input from the card unit 50 via the interface board 66 passes the VL signal to the resistor 152 and the photocoupler 151 based on the fact that the output level of the VL signal has reached a predetermined level by the capacitor 150a and the capacitor 150b. Let The capacitors 150a and 150b monitor whether or not a predetermined voltage has been reached in order to stabilize the voltage. In this embodiment, since the signal line of the VL signal is connected to the frequency display LED 60a and the ball lending LED 60b mounted on the balance display substrate 60 and used as a power source, even when these are driven simultaneously, It is provided to prevent the voltage of the signal from becoming unstable and to stabilize the voltage of the VL signal.

  The photocoupler 151 causes the light emitting unit 151a to emit light based on the input of the electric signal (in this case, the VL signal), and the electric signal based on the light receiving unit 151b detecting the light emission by the light emitting unit 151a. (In this case, a VL signal) is output to electrically insulate the payout control board 37 and the card unit 50 from each other. That is, by providing the photocoupler 151, even when the VL signal output from the card unit 50 is short-circuited, the payout operation can be performed stably.

  In this embodiment, the signal line for the VL signal on the payout control board 37 includes a signal line for connecting the VL signal output from the photocoupler 151 to the input port 372f of the payout control board 37, and launch control. A signal branch means 37a that can be branched and input to a signal line connected to the substrate 91 is provided. A VL signal output from the photocoupler 151 by the signal branching means 37a and a discharge control microcomputer and a launch control means mounted on the launch control board 91 (for example, a launch control CPU mounted on the launch control board 91, Peripheral circuits such as ROM, RAM, and I / O port).

  Further, the launch control means mounted on the launch control board 91 enables the game ball launching operation by the hitting ball launching device based on the input of the VL signal from the photocoupler 151, and from the photocoupler 151. When the VL signal is not input, the game ball launching operation by the hitting ball launching device is controlled to be disabled.

  As described above, in this embodiment, the capacitor 150 is not mounted on the interface board 66 but mounted on the signal line of the VL signal of the payout control board 37. In the interface board disclosed in FIG. 11 of Japanese Patent Laid-Open No. 2001-347054, since a capacitor is mounted, an illegal circuit in which a circuit for illegally inputting a signal to the payout control microcomputer is provided on the interface board. There is a problem that it is difficult to detect when a board is created and a regular interface board and an illegal board are exchanged.

  If the interface board is replaced with an unauthorized board, no game balls have been won in the multiple winning slots provided on the game board, or no card lending request has been made. A circuit for inputting a signal for executing a payout operation to the payout control board is created by forging the interface board, and the payout operation is executed by an external operation (eg, button, wireless communication, etc.). There is a possibility that an act of generating a signal and illegally acquiring a game medium (for example, a game ball, a game medal, etc.) may be executed. Moreover, when producing such an illegal board | substrate, a capacitor | condenser is needed in order to stabilize a signal.

  In this embodiment, since a regular board is created without providing a capacitor on the interface board 66 from the beginning, it is possible to prepare whether or not the board is an unauthorized board simply by checking whether or not the capacitor is mounted. Discoverable. Further, when the capacitor 150 of the signal line of the VL signal is mounted on the payout control board 37, the photocoupler 151 is also mounted on the payout control board 37 so that it is useless between the interface board 66 and the payout control board 37. It is possible to eliminate the reciprocation of the signal path, save the space of the back mechanism in the pachinko gaming machine 1, and reduce the number of wires.

  In this embodiment, although the VL signal from the photocoupler 151 mounted on the launch control board 91 is inputted, the game ball launching operation by the hitting ball launching device is made possible. The signal line of the VL signal may be branched above, and one may be connected to the payout control board 37 and the other may be connected to the launch control board 91. In this case, a photocoupler may be mounted on the signal line of the VL signal on the launch control board 91.

  FIG. 7 is a block diagram illustrating a circuit configuration example of the effect control board 80, the lamp driver board 35, and the sound control board 70. The lamp driver board 35 and the sound control board 70 are not equipped with a microcomputer. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a ROM (not shown), and the input driver 102 and the input port according to the strobe signal (effect control INT signal) from the main board 31. The symbol control signal is received via 103. Further, the production control CPU 101 causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD, based on the symbol control signal. The VDP 109 is sometimes called a GCL (graphic controller LSI).

  Further, the production control CPU 101 outputs sound number data to the sound control board 70 via the output port 104 and the output driver 110. A bus (including an address bus, a data bus, and a control signal line such as a write / read signal) that is input / output to / from the effect control CPU 101 is extended to the lamp driver board 35 via the bus driver 105.

  In the lamp driver board 35, the bus connected to the effect control CPU 101 is connected to the output port 352 and the expansion port 353 via the bus receiver 351. A signal for driving each lamp output from the output port 352 is amplified by the lamp driver 354 and supplied to each lamp. Further, a signal for driving each LED output from the output port 352 is amplified by the LED driving circuit 355, and each lamp 28a, 28b, 28c, 25 (the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the decoration). Lamp 25, etc.). In addition, a signal for driving each LED output from the output port 352 is amplified by the LED driving circuit 355 and supplied to each LED (normal symbol start memory display 41 and the like). Then, a signal for driving the effect driving means 357 such as an effect movable member is amplified by the drive circuit 356 and supplied to the effect driving means 357. However, in the case of this embodiment, the production drive means 357 is not actually provided, and a drive circuit 356 is provided for the purpose of giving the lamp driver board 35 versatility as will be described later. ing.

  In this embodiment, the lamp / LED and the effect driving means 357 provided in the gaming machine are controlled by an effect control microcomputer including an effect control CPU 101 mounted on the effect control board 80. Further, data for controlling the variable display device 9, the normal symbol display 10, the lamp / LED and the like are stored in the ROM. The effect control CPU 101 controls the variable display device 9, the normal symbol display 10, the lamp / LED, and the like based on the data stored in the ROM. Then, the lamp / LED and the effect driving means 357 are driven via the output port 352 mounted on the lamp driver substrate 35 and the respective drive circuits. Therefore, when changing the model, if the production control board 80 is replaced with a new model, the model change can be realized without replacing the lamp driver board 35.

  Although the production control board 80, the lamp driver board 35, and the sound control board 70 are independent boards, they are installed in a single box on the back of the gaming machine, for example. Further, the expansion port 353 is installed in consideration of the case where the number of lamps / LEDs and the like is increased when changing the model, but it may not be installed. The drive circuit 356 may not be provided when there are no movable members for the production, but when changing the model, considering the case where the movable members for the production are installed, the movable for the production is provided. It is preferably provided even when no member is present.

  In the voice control board 70, the sound number data from the effect control board 80 is input to the voice synthesis IC 703 by a digital signal processor, for example, via the input driver 702. The voice synthesis IC 703 reads data corresponding to the sound number data from the voice data ROM 704 mounted on the voice data board 70 </ b> A, generates voice and sound effects corresponding to the read data, and outputs them to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. In this embodiment, the voice data ROM 704 is mounted on the voice data board 70A, which is a board different from the voice control board 70, but the voice data ROM 704 may be mounted on the voice control board 70. Good. In that case, the audio data board 70A is unnecessary.

  The data corresponding to the sound number data stored in the sound data ROM 704 is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a special symbol fluctuation period). When the voice number IC 703 receives the sound number data, the voice synthesis IC 703 performs sound output control according to the corresponding data in the voice data ROM 704. The sound output control according to the corresponding data is continued until the next sound number data is input. When the next sound number data is input, the speech synthesis IC 703 performs sound output control according to the data in the sound data ROM 704 corresponding to the newly input sound number data.

  In this embodiment, the sound and sound output from the speaker 27 are controlled by the effect control microcomputer including the effect control CPU 101, but the effect control microcomputer has a sound number on the sound control board 70. Output data. In the voice control board 70, the voice data ROM 704 stores a large amount of data for realizing voice and sound effects that can appear as the game progresses, and these data are associated with the sound number data. . Therefore, the production control microcomputer can realize the sound output control only by outputting the sound number data. Note that the sound number data is, for example, 1-byte data, and is transferred to the sound control board 70 via a serial signal line or a parallel signal line.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagrams of FIGS. FIG. 8 is a block diagram showing a DC voltage generating part in the power supply substrate 910. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), AC power (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply board 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911. Note that the transformer 911 may be provided outside the power supply board 910 instead of on the power supply board 910.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, the effect control board 80, and the launch control board 91), and is used by each electric component control board and mechanism component in the gaming machine. To generate a voltage. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V), and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the + 5V line and the backup + 5V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 8), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Therefore, when the power supply to the gaming machine from the outside is stopped, the direct current voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 9, AC24V output from the transformer 911 is supplied to the connector 922A as it is. Further, the VLP is supplied to the connector 922B through a fuse F01 as an overcurrent prevention unit that prevents overcurrent supply. Further, a series body of an LED (LD01) and a resistor (R01) is connected between the connector 922B side of the fuse F01 and the ground (ground potential).

  VSL is supplied to the connector 922A via the fuse F02. A series body of an LED (LD02) and a resistor (R02) is connected between the connector 922A side of the fuse F02 and the ground. The VSL is supplied to the connector 922B through the fuse F03. A series body of an LED (LD03) and a resistor (R03) is connected between the connector 922B side of the fuse F03 and the ground. Further, the VSL is supplied to the connector 922C through the fuse F04. A series body of an LED (LD04) and a resistor (R04) is connected between the connector 922C side of the fuse F04 and the ground.

  VDD is supplied to the connector 922A via the fuse F05. A series body of an LED (LD5) and a resistor (R05) is connected between the connector 922A side of the fuse F05 and the ground. Further, VDD is supplied to the connector 922B via the fuse F06. A series body of an LED (LD06) and a resistor (R06) is connected between the connector 922B side of the fuse F06 and the ground. Further, VDD is supplied to the connector 922C through the fuse F07. A series body of an LED (LD07) and a resistor (R07) is connected between the connector 922C side of the fuse F07 and the ground.

  VCC is supplied to connector 922A through fuse F08. A series body of an LED (LD08) and a resistor (R08) is connected between the connector 922A side of the fuse F08 and the ground. Also, VCC is supplied to the connector 922B via the fuse F09. A series body of an LED (LD09) and a resistor (R09) is connected between the connector 922B side of the fuse F09 and the ground. Furthermore, VCC is supplied to the connector 922C through the fuse F10. A series body of an LED (LD10) and a resistor (R10) is connected between the connector 922C side of the fuse F10 and the ground.

  The cable connected to the connector 922A is connected to the payout control board 37. The cable connected to the connector 922B side is connected to the effect control board 80. The cable connected to the connector 922C is connected to the main board 31. Therefore, VBB is also supplied to the connector 922C.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a clear switch signal at a low level (ON state) is output and transmitted to the main board 31 via the connector 922C. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided other than the power supply board 910 in the gaming machine.

  Further, the fuses F01 to F10 are not of a detachable (replaceable) type but of a type fixed to the power supply substrate 910. That is, it is installed on the board (in this example, the power supply board 910) so as not to be replaced. When the fuses F01 to F10 are of a replaceable type, the fuse is replaced when a malfunction such as a short circuit failure occurs in the power supply board 910 or the electrical component control board, and the cause of the true malfunction is unknown. There is a risk that the gaming machine will be returned to the movable state. In that case, it is predicted that the defect will recur immediately. However, if the fuses F01 to F10 are of a non-replaceable type, when a problem occurs in the power supply board 910, the fuse F01 to F10 are guided to an action of searching for a true cause of the problem.

  When the LEDs (LD01 to LD10) as shown in FIG. 9 are provided on the power supply board 910, if no trouble such as a short circuit failure occurs in the power supply board 910 and each power supply component control board, Each LED (LD01 to LD10) is in a lighting state. In other words, if each LED (LD01 to LD10) is in a lighting state, it can be seen that there is no problem such as a short circuit failure in the power supply board 910 and each electric component control board.

  FIG. 10 is a block diagram showing the CPU 56, reset circuit 65, and power supply monitoring circuit 920 on the main board 31. As shown in FIG. 10, a power-off signal from the power supply monitoring circuit (power supply monitoring means) 920, that is, a detection signal from the power supply monitoring means is input to the CPU 56 via the inverting circuit 943 and the input port 572. . Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 572.

  According to such a configuration, the central processing unit (CPU 56) of the game control microcomputer can be prevented from entering a multiple interrupt state. In other words, for example, when a detection signal from the power supply monitoring means is input to the non-maskable interrupt terminal of the central processing unit, for example, by repeatedly turning on and off the power supply many times, When a non-maskable interrupt signal is further input to the processing unit and a multiple interrupt state occurs, the central processing unit enters a runaway state, but the detection signal from the power monitoring means is input to the input port, and the detection signal is input to the input port. This prevents the central processing unit from entering multiple interrupt states even if the power is turned on and off many times in order to shift to power supply stop processing when the central processing unit determines that Can be That.

  As a result, it is possible to prevent the central processing unit from running out of control and being initialized, and it is possible to prevent a problem that the specific gaming state (big hit gaming state) is likely to be targeted by the player when the central processing unit is initialized. More specifically, when the central processing unit is initialized, a random counter for determining a missed hit from that point in time starts counting up from an initial value (for example, “0”). For example, the count-up start time from “0”) can be grasped, and the hit ball is won at the start winning opening 14 in consideration of the time until the value corresponding to the jackpot is counted up (start win) Then, by detecting with the start port switch 14a, the count value associated with the start winning is extracted at the moment when the value corresponding to the big hit is counted up. However, in the present invention, since multiple interruptions of the central processing unit can be prevented and initialization of the central processing unit can be avoided, such a problem can be prevented.

  Since the power supply monitoring circuit 920 is mounted on the main board 31, a power supply monitoring means can be installed near the CPU 56 to which a power-off signal is input, and the stoppage of power supply is reliably recognized by the game control microcomputer. To be able to.

  The power monitoring circuit 920 includes a power monitoring IC 902. The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output because power supply is stopped. Specifically, the power-off signal is set to a low level. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used.

  The predetermined value for the power monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while. In addition, since the power monitoring IC 902 is higher than the voltage for driving circuit elements such as the CPU 56 (+5 V in this example), the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop.

  When the voltage of the + 12V power supply decreases, the switch output starts to turn on. However, if the power supply voltage is monitored by monitoring the + 30V power supply voltage that drops earlier than + 12V, and the power supply is stopped, the power is output before the switch output turns on. It is possible to enter a supply recovery waiting state and not detect the switch output.

  The reset circuit 65 includes a reset IC 651. When the power is turned on, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to a high level when the predetermined time has elapsed. That is, the reset signal (system reset signal) is raised to a high level to make the CPU 56 operable. The reset signal is input to the reset terminal of the CPU 56 via the inverting circuits 942 and 941.

  In addition, the reset IC 651 monitors the power supply voltage of the VSL that is the same as the power supply voltage monitored by the power supply monitoring circuit 920, and the voltage value is a predetermined value (from the power supply voltage value at which the power supply monitoring circuit 920 outputs a power-off signal). If the value is less than or equal to the lower value, the output is set to low level. Accordingly, the CPU 56 performs a predetermined power supply stop process in response to the power-off signal from the power supply monitoring circuit 920, and then the system is reset. That is, the operation is completely stopped. Accordingly, the reset circuit 65 corresponds to second power supply monitoring means for outputting the detection signal at a timing later than the timing at which the power supply monitoring means outputs the detection signal. In this example, the state in which the second power supply monitoring unit outputs the detection signal is a state in which the reset signal is set to a low level.

  The CPU 56 used in this embodiment includes a non-maskable interrupt terminal (NMI terminal) used to generate a non-maskable interrupt (NMI), and an interrupt (external interrupt; mask) from the outside of the CPU 56. An interrupt terminal (INT terminal) used to generate a possible interrupt). When the signal input to the NMI terminal falls to a low level, a non-maskable interrupt occurs. That is, the program counter of the CPU 56 is changed to the start address of the non-maskable interrupt process, and the CPU 56 enters a state of executing the instruction set at the start address of the non-maskable interrupt process.

  Further, when a signal input to the INT terminal falls to a low level, an external interrupt is generated. That is, the program counter of the CPU 56 is changed to the start address of the external interrupt process, and the CPU 56 enters a state of executing the instruction set at the start address of the external interrupt process.

  In this embodiment, non-maskable interrupts and external interrupts are not used. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors. Therefore, the input levels of the NMI terminal and the INT terminal are always at a high level, and there is a possibility that the input level of the NMI terminal and the INT terminal falls due to noise or the like, and an interrupt is generated, as compared with the terminal open state. To reduce.

  FIG. 11 and FIG. 12 are explanatory diagrams showing an example of output port assignment in the game control microcomputer. As shown in FIG. 11, the output port 0 has a prize ball command signal (award ball number signal, prize ball REQ signal), a connection confirmation signal A, a payout initialization signal, and an effect control board 80 transmitted to the payout control board 37. This is an output port of the effect control INT signal (strobe signal) for the effect control signal transmitted to the. Further, 8-bit data of the effect control signal transmitted to the effect control board 80 is output from the output port 1. The effect control INT signal is a signal for instructing the effect control microcomputer to take in the 8-bit data of the effect control signal, and the payout initialization signal instructs the payout control microcomputer to initialize. It is a signal for.

  Further, from the output port 2, a solenoid (large winning opening door solenoid) 21 for opening and closing the opening / closing plate 20 of the large winning opening, a solenoid (large winning opening guide plate solenoid) 21A for switching a path in the large winning opening, In addition, a drive signal for a solenoid (ordinary electric accessory solenoid) 16 for opening and closing the variable winning ball apparatus 15 is output. Then, various information output signals from the output port 3 to the information terminal board 34 and the terminal board 160 via the information output circuit 64, that is, output data of information related to control, are output. A signal for instructing the microcomputer for notification of an abnormal condition related to the payout of the prize ball is output.

  FIG. 13 is an explanatory diagram showing an example of bit assignment of input ports in the game control microcomputer. As shown in FIG. 13, the left winning port switch 33a, the right winning port switch 39a, the left dropping winning port switch 29a, the right dropping winning port switch 30a, and the start port switch 14a are respectively set in bits 0 to 7 of the input port 0. Detection signals of the count switch 23, the V count switch 22, and the gate switch 32a are input. In addition, bits 0 to 6 of the input port 1 respectively include a power-off signal from the power supply monitoring circuit 920, a reception confirmation signal from the payout control board 37, a detection signal of the clear switch 921 from the power supply board 910, and a payout control board. 37, a connection confirmation signal B from the payout control board 37, a payout operation in-progress signal from the payout control board 37, a full tank error signal from the payout control board 37 (a signal indicating the detection state of the full tank switch 48), and an out of ball error from the payout control board 37 A signal (a signal indicating the detection state of the ball break switch 187) is input. The detection signal from each switch is logically inverted by the input driver circuit 58.

  Next, the operation of the gaming machine will be described. FIG. 14 is a flowchart showing a main process executed by the game control microcomputer on the main board 31. When power is turned on for the gaming machine, a reset signal for notifying the start of power supply is output from the power supply board 910 to the main board 31. After the CPU 56 mounted on the main board 31 executes a security check process that is a process for confirming whether the contents of the program are valid when the input level of the reset terminal to which the reset signal is input becomes a high level. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4).

  Next, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM 55 is set in an accessible state (step S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes a normal initialization process (steps S10 to S14). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. Note that in the input port 1, the clear switch signal is in the high level. Also, for example, the game store clerk can easily execute the initialization process by starting the power supply to the gaming machine (for example, turning on the power switch 914) while the clear switch 921 is turned on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped (Step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such a protection process has not been performed, the CPU 56 executes an initialization process.

  Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, 2). Note that such a confirmation method is merely an example. For example, a flag indicating that the data protection process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that there is a backup, it may be determined that there is backup.

  If it is determined that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process executed at the time of power-on that is not when the power supply is recovered from the stop of the power supply (the processes in steps S10 to S14) Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control microcomputer and the control state of the electric component control means such as the effect control microcomputer to the state when the power supply is stopped. Do. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S81), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S82). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S81 and S82, the saved contents of the work area that should not be initialized remain. The portion that should not be initialized is, for example, a portion in which data (such as a special symbol process flag) indicating a gaming state before stopping power supply or data indicating the number of unpaid is set.

  Further, the CPU 56 sets the start address of the backup command transmission table stored in the ROM 54 as a pointer (step S83), and power is supplied to the sub-boards (the payout control board 37 and the effect control board 80) according to the contents. Control is performed such that a control signal indicating the recovery is transmitted (step S84). Then, the process proceeds to step S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by unauthorized means. Therefore, it is difficult to aim at the timing at which the count value of the counter matches the jackpot determination value. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12). By the processing of step S11 and step S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total prize ball number storage buffer, a special symbol process flag, a winning ball flag, a ball An initial value is set to a flag for selectively performing processing according to the control state, such as a cut flag or a payout stop flag.

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  Then, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated every predetermined time (for example, 2 ms) (step S15). That is, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the execution of the initialization process (steps S10 to S14) is completed, the display random number update process (step S17) and the initial value random number update process (step S18) are repeatedly executed in the main process. The CPU 56 disables the interrupt when the display random number update process and the initial value random number update process are executed (step S16), and interrupts when the display random number update process and the initial value random number update process are finished. The permission state is set (step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. It is. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). In a game control process described later, when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set even when the display random number update process and the initial value random number update process are performed by the timer interrupt process described later. This is to avoid conflict with the processing in the timer interrupt processing. That is, if a timer interrupt is generated during the processing of steps S17 and S18 and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt disabled state is set during the processes of steps S17 and S18.

  Next, the game control process will be described. FIG. 15 is a flowchart showing the timer interrupt process. When the timer interrupt occurs during execution of the main process, specifically, during the execution of the loop process of step S16 to step S19, the CPU 56 starts the timer interrupt process in response to the occurrence of the timer interrupt. The game control process shown in steps S20 to S34 in FIG. 15 is executed.

  In the timer interrupt process, the CPU 56 first executes a power-off detection process for detecting whether or not a power-off signal has been output (whether or not it has been turned on) (step S20). Next, through the input driver circuit 58, the gate switch 32a, the start port switch 14a, the count switch 23, the left drop winning port switch 29a, the right drop winning port switch 30a, the left winning port switch 33a, the right winning port switch 39a, etc. These switch detection signals are input, and their state is determined (switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of a switch timer provided corresponding to each switch is incremented by one.

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S22). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S23 and S24).

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control signal related to the special symbol in a predetermined area of the RAM 55 and sending the effect control signal (special symbol command control process: step S27). In addition, processing for setting the effect control signal related to the normal symbol in a predetermined area of the RAM 55 and sending the effect control signal is performed (normal symbol command control processing: step S28).

  Furthermore, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 performs a winning ball process for setting the number of winning balls based on detection signals from the left dropping winning port switch 29a, the right dropping winning port switch 30a, the left winning port switch 33a, the right winning port switch 39a, and the like. Execute (Step S30). Specifically, a winning ball is placed on the payout control board 37 in response to detection of winning based on turning on the left dropping winning opening switch 29a, the right dropping winning opening switch 30a, the left winning opening switch 33a, the right winning opening switch 39a and the like. A prize ball command signal such as a prize ball number signal indicating the number is output. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a prize ball command signal such as a prize ball number signal indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start-winning memory | storage number (step S31). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S32). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, and the CPU 56 outputs the contents related to the solenoid in the RAM area of the output port 3 (see FIG. 11) to the output port. (Step S33: Output processing). Thereafter, the interrupt permission state is set (step S34), and the process ends.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 2 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set. It may be executed in the main process.

  16 and 17 are flowcharts illustrating an example of the power-off detection process in step S20. In the power-off detection process, the CPU 56 first checks whether or not a power-off signal is output (whether it is in an on state) (step S450). If it is in the on state, the power supply stop process after step S452 is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process for saving the game state is executed.

  In the power supply stop process, the CPU 56 stores the backup specified value (“55H” in this example) in the backup flag (step S452). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S453 to S461). That is, first, the clear data (00) is set in the checksum data area (step S453), and the checksum calculation start address is set in the pointer (step S454). Also, the number of checksum calculations is set (step S455).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S456). The calculation result is stored in the checksum data area (step S457), the pointer value is incremented by 1 (step S458), and the value of the checksum calculation count is decremented by 1 (step S459). Then, the processes in steps S456 to S459 are repeated until the value of the checksum calculation count becomes 0 (step S460).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S461). Then, the inverted data is stored in the checksum data area (step S462). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S482). When the power-off signal is turned off, the execution address at power-on (address in step S1) is set as the return address and the return command is executed (step S483).

  When the power supply is stopped by the above process, the power supply stop process in steps S452 to S481 is executed, and data indicating that the power supply has been executed (specified value with backup and checksum) is backed up. Stored in the RAM, the RAM access is disabled, the output port is cleared, and the timer interrupt for executing the game control process is disabled.

  When the power-off signal is turned off, the process returns to step S1. In this case, since the data indicating that the power supply stop process has been executed is set, the game state restoration process in steps S81 to S84 is executed, and the control data that has been backed up in the RAM 55 is restored to the game state. Next to being used as control data at the time, control is executed from a control state such as a signal output state before stopping power supply when the gaming state is restored based on this control data. Therefore, when the detection signal from the power supply monitoring unit is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The connection confirmation signal A transmitted to the payout control board 37 is set to the off state by the process of clearing the output port. Further, in the setting of the work area in steps S82 and S12, the content of the output port buffer corresponding to the connection confirmation signal A is set to a value corresponding to the ON state of the connection confirmation signal A. When the output process of step S33 is executed, the contents of the output port buffer are output to the output port, so that the connection confirmation signal A to the payout control board 37 is turned on. Accordingly, the connection confirmation signal A is output (turned on) when the main board 31 rises. Note that the connection confirmation signal A is also output when the power supply is recovered from an instantaneous power interruption or the like.

  Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. A switch timer is used to measure the predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates an on state. As shown in FIG. 18, the switch timer is provided by the number n of detection signals. In the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports.

  FIG. 19 is a flowchart illustrating a processing example of the switch processing in step S21 in the game control processing. In the switch process, the CPU 56 first inputs data input to the input port 0 (see FIG. 13) (step S101). Next, “8” is set as the processing number (step S102), and the address of the switch timer for the left winning mouth switch 33a is set in the pointer (step S103). Then, a switch check processing subroutine is called (step S104).

  FIG. 20 is a flowchart showing a switch check subroutine. In the switch check processing subroutine, the CPU 56 sets port input data, in this case, input data from the input port 0, as a “comparison value” (step S121). Further, clear data (00) is set (step S122). Then, the switch timer pointed to by the pointer (switch timer address is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S124). Data of input port 0 is set as the comparison value. In this case, the detection signal of the left winning mouth switch 33a is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S125), that is, if the detection signal of the left prize opening switch 33a is in the ON state, the value of the switch timer is incremented by 1 (step S127). If the value after addition is not 0, the addition value is returned to the switch timer (steps S128 and S129). When the value after addition becomes 0, the addition value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased further.

  If the value of the carry flag is “0” (step S125), that is, if the detection signal of the left winning port switch 33a is in the OFF state, clear data is set in the switch timer (step S126). That is, if the detection signal is off, the value of the switch timer returns to zero.

  Thereafter, the CPU 56 adds 1 to the pointer (switch timer address) (step S130) and subtracts 1 from the number of processes (step S131). If the number of processes is not 0, the process returns to step S122 (step S132). Then, the processes of steps S122 to S132 are repeated.

  The processes of steps S122 to S132 are repeated for the number of processes, that is, 8 times, and during that time, the switch detection signal input to the 8 bits of the input port 0 is sequentially checked whether it is on or off. If processing is performed and the switch is on, the value of the corresponding switch timer is incremented by one.

  In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Accordingly, the switch timer is incremented by 1 every 2 ms.

  Next, a payout control signal transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 21 is an explanatory diagram showing an example of the contents of a control signal output from the game control microcomputer to the payout control microcomputer and a control signal input to the game control microcomputer from the payout control microcomputer. is there. In this embodiment, a plurality of types of control signals are exchanged between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 21, the connection confirmation signal A is output when the main board 31 rises, and is a signal for notifying the payout control board 37 that the main board 31 has risen (connection confirmation signal for the main board 31). ). Further, as described above, the connection confirmation signal A is turned off when the power-off is detected, and is also used as a signal for notifying the dispensing control board 37 that the main board 31 has detected the power-off. .

  The connection confirmation signal B is output when the dispensing control board 37 rises, and is a signal for notifying the main board 31 that the dispensing control board 37 has risen (connection confirmation signal for the dispensing control board 37). The connection confirmation signal B is also a signal for notifying that the main board 31 is turned off when the power is turned off and that the main board 31 is turned off.

  The prize ball REQ signal becomes a low level (output state = on state) at the time of a prize ball payout request and becomes a high level (stop state = off state) at the end of the payout request (that is, a trigger for a prize ball payout request). Signal). The award ball number signal is a signal output for designating the number (1 to 15) of game balls for which a payout request is made. It can also be said that the prize ball REQ signal is a signal requesting the payout control board 37 (the payout control microcomputer) to receive the prize ball number signal.

  As for the reception confirmation signal, the payout control board 37 (the payout control microcomputer) has received a prize ball REQ signal and a prize ball number signal, that is, a prize ball command signal, with respect to the main board 31 (game control microcomputer). And is used to confirm on the main board 31 side that such a prize ball command signal has been received by the payout control board 37. The reception confirmation signal becomes high level (on state) when the prize ball command signal is received. In the payout operation signal, the payout control board 37 (payout control microcomputer) is executing a prize ball payout process (payout operation) after the reception confirmation signal is output to the main board 31 (game control microcomputer). It is a signal for notifying (indicating) that there is. The payout operation in-progress signal is also a signal for notifying (indicating) that the payout control board 37 has completed the award ball payout process (payout operation) to the main board 31. The payout operation in-progress signal is at a high level (on state) during execution of the payout process, and is at a low level (off state) when the payout process is completed.

  The full tank error signal is a signal for notifying (indicating) to the game control microcomputer that the detection signal of the full tank switch 48 has been input to the payout control board 37. The full tank error signal becomes high level (ON state) when the detection signal of the full tank switch 48 is input to the dispensing control board 37, and low level (OFF state) when the detection signal of the full tank switch 48 stops. )become. The ball break error signal is a signal for notifying (indicating) to the game control microcomputer that the detection signal of the ball break switch 187 has been input to the payout control board 37. The ball break error signal becomes high level (ON state) when the detection signal of the ball break switch 187 is input to the payout control board 37, and low level (OFF) when the detection signal of the ball break switch 187 stops. State).

  The payout initialization signal is a signal for notifying (indicating) to the payout control microcomputer that the payout control state is to be initialized. The payout initialization signal indicates that the game control microcomputer outputs the award ball REQ signal and the award ball number signal to the payout control board 37, and indicates that the payout control microcomputer has received the award ball number signal. After confirming that the signal has been turned on, when the reception confirmation signal does not turn off even after a lapse of a predetermined period, it becomes high level (on state), and after the lapse of a predetermined period, it becomes low level (off state) )become.

  Each control signal described above may be configured so that the output state or the on state and the stop state or the off state can be distinguished, and the above logic may be reversed in polarity. In other words, the logic of the output state of each control signal is a positive logic system (high active) that is in the output state or on state when the signal is high level, and in the stop state or off state when the signal is low level. System) and a negative logic system (low active system) that is in the stopped state or off state when the signal is high level, and that is in the output state or on state when the signal is low level. May be. Such logic of the control signal is applicable to all the control signals described in this embodiment, including the control signal described above.

  FIG. 22 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 22, the connection confirmation signal A, the prize ball REQ signal, and the prize ball number signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. Further, the reception confirmation signal, the payout operation in-progress signal, the connection confirmation signal B, the full tank error signal, and the ball shortage error signal are output by the payout control CPU 371 via the output circuit 373B and to the CPU 56 via the input circuit 68. Entered. The connection confirmation signal A, the connection confirmation signal B, the prize ball REQ signal, the reception confirmation signal, and the payout operation in-progress signal are each 1-bit data and are transmitted through one signal line. Since 1 to 15 award ball number signals are designated, it is composed of 4-bit data and transmitted through four signal lines. In the case of this embodiment, the reception confirmation signal and the payout operation in-progress signal are output as separate signals through different signal paths.

  The full tank error signal and the ball shortage error signal are output by processing of the payout control CPU 371 as another example of the full tank switch 48 and the ball shortage switch 187 input to the payout control board 37, respectively. The detection signal may be branched for input to the main board 31 in the payout control board 37, and the branched signal may be output to the main board 31 without being processed by the payout control CPU 371. Further, as described above, the detection signals of the full switch 48 and the ball break switch 187 are not sent from the payout control board 37 to the main board 31 but are directly inputted to the main board 31 from each switch. Also good.

  FIG. 23 is a flowchart showing an example of the prize ball processing in step S30. In the prize ball process, the CPU 56 executes a prize ball number addition process (step S201) and a prize ball control process (step S202).

  In the prize ball number adding process, a prize ball number table shown in FIG. 24 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “6”) is set in the top address of the winning ball number table, and then a switch timer for each switch of the winning opening that will pay out the winning ball by winning (see FIG. 18). Are sequentially set in pairs.

  FIG. 25 is a flowchart showing the prize ball number adding process in step S201. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (step S211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S212). Next, the upper address (8 bits) of the switch timer is set in the check pointer (step S213). The upper addresses of all check timers are the same.

  Then, the value of the pointer is incremented by 1 (step S214), and the address of the switch timer is obtained based on the data set in the check pointer and the data of the address pointed to by the pointer (lower address of the switch timer). The switch timer value is loaded (step S215). Note that the value loaded first is the value of the switch timer corresponding to the left winning opening switch 33a (see FIG. 24), and here, the value of the pointer is incremented by 1 (step S216).

  Next, the CPU 56 compares the value of the loaded switch timer with the ON determination value (for example, “2”) (step S217). If they match, the process proceeds to step S218. Migrate to The value of the switch timer is incremented by 1 when it is confirmed that the switch is turned on by the switch processing in step S21. Since the switch process is started every 2 ms, the switch timer value becomes “2” if the switch is turned on continuously for 4 ms. That is, when the on determination value is “2”, if the switch is continuously turned on for 4 ms, the value of the switch timer matches the on determination value.

  In step S218, data at the address pointed to by the pointer (in this case, a prize ball is loaded, and the loaded value is set as a prize ball addition value. The prize ball addition value (number data) is stored in a 16-bit RAM area. Is added to the contents of the total prize-ball number storage buffer (step S219), and the total prize-ball number storage buffer is formed in the backup RAM. The content of the winning ball number storage buffer is set to 65535 (= FFFF (H)) (steps S220 and S221).

  In step S223, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S214 (step S223).

  FIG. 26 is a flowchart showing the prize ball control process in step S202. In the prize ball control process, the CPU 56 executes any one of steps S231 to S234 according to the value of the prize ball process code.

  FIG. 27 is a flowchart showing the prize waiting process 1 (step S231) executed when the value of the prize ball process code is zero. In the award ball waiting process 1, the CPU 56 checks whether the reception confirmation signal or the payout operation in-progress signal is on (step S241). At this stage, since the reception confirmation signal or the payout operation in-progress signal should not be in the on state, if the reception confirmation signal or the payout operation in progress signal is in the on state, the abnormal payout notification signal Is set (step S242), the connection confirmation signal A is turned off (step S243), and the process is terminated. As a result, an abnormal payout notification signal is output to the effect control board 80 in a special symbol command control process (step S25) described later.

  When the connection confirmation signal A is turned off, the payout process by the payout control CPU 371 is prohibited as will be described later with reference to FIG. In the state where the prize ball command signal is not output because the prize ball transmission process shown in FIG. 28 is not executed, that is, in the state where the prize ball waiting process 1 is executed, in step S241, When the payout operation in-progress signal is received, an abnormal communication state has occurred between the game control microcomputer and the payout control microcomputer. At this time, the payout number subtraction process according to the reception of the reception confirmation signal cannot be normally performed. Therefore, in the award ball waiting process 1 in FIG. 27, when a reception confirmation signal or a payout operation in-process signal is received, the process from step S241 to step S243 is executed and the process is terminated, and the award ball in FIG. By not proceeding to the transmission process and the award ball waiting process 2 in FIG. 29, the payout number subtraction process is prohibited on the CPU 56 side.

  If the reception confirmation signal or the payout operation in-progress signal is not ON in step S241, the output of the winning ball number signal is cleared to 0 (step S244). Further, it is confirmed whether or not the prize ball timer is 0 (step S245). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (step S246), and the process is terminated. The prize ball timer is a timer for measuring the time required for prize ball processing. At this stage, if the value of the prize ball timer is not 0, the next prize ball after the previous payout process is completed. Waiting time until the REQ signal is turned on (this is a time for providing an interval between the ON periods of a plurality of prize ball REQ signals when prize ball payout is continuously executed, and is set in step S278. Is not finished).

  If the value of the prize ball timer is 0 in step S245, the CPU 56 checks the contents of the total prize ball number storage buffer (step S247). If the value of the total prize ball number storage buffer is 0, the process is terminated. If the value of the total prize ball number storage buffer is not 0, the value of the prize ball process code is set to 1 (step S248), and the process is terminated. To do.

  FIG. 28 is a flowchart showing a prize ball transmission process (step S232) executed when the value of the prize ball process code is 1. In the prize ball transmission process, the CPU 56 first checks whether or not the connection confirmation signal B is in an on state (step S250). If the connection confirmation signal B is not in the on state, the winning ball transmission process is terminated without executing the following process. On the other hand, if the connection confirmation signal B is ON in step S250, it is confirmed whether or not the content of the total prize ball number storage buffer is smaller than the prize ball number signal maximum value (“15” in this embodiment). (Step S251). If the content of the total prize ball number storage buffer is greater than or equal to the prize ball number signal maximum value in step S251, the prize ball number signal maximum value is set in the prize ball number buffer (step S252). If the content of the total prize ball number storage buffer is smaller than the prize ball number signal maximum value in step S251, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S253).

  Thereafter, a prize ball number signal designating the number of prize balls to be paid out set in the prize ball quantity buffer is output (step S254), the prize ball REQ signal is turned on (step S255), and the prize ball process code is set. The value is set to 2 (step S256), and the process is terminated.

  In this embodiment, the maximum value of the winning ball number signal is “15”. Accordingly, a prize ball number signal designating a maximum number of payouts of “15” is transmitted to the payout control board 37. In the award ball transmission process, when the game control microcomputer has not received the connection confirmation signal B, that is, when the payout control microcomputer is not connected to the game control microcomputer, the CPU 56 side Thus, the payout amount subtraction process in response to the reception of the reception confirmation signal cannot be performed. In such a case, since the process of step S254 and step S255 is not executed by ending the prize ball transmission process without executing the following process in step S250, the game control microcomputer side outputs a prize ball command signal. Is prohibited.

  FIGS. 29, 30, and 31 are flowcharts showing the award ball waiting process 2 (step S233) executed when the value of the award ball process code is 2. In the award ball waiting process 2, the CPU 56 checks whether or not a reception confirmation flag is set (step S281). Here, the reception confirmation flag is a flag indicating that the prize ball command signal has been received by the payout control microcomputer, and is set in step S297 described later when the reception confirmation signal is received. .

  If the reception confirmation flag is set in step S281, the process proceeds to step S301 in FIG. On the other hand, if the reception confirmation flag is not set in step S281, it is confirmed whether or not a payout operation waiting flag is set (step S282). Here, the payout operation waiting flag is a flag indicating that the payout operation waiting signal is received after receiving the reception confirmation flag, and will be described later with reference to FIG. 30 when the reception confirmation signal is turned off. Is set in step S313. If the payout operation waiting flag is set in step S282, the process proceeds to step S315 in FIG. On the other hand, if the payout operation waiting flag is not set in step S282, it is confirmed whether the reception confirmation signal is on (step S283).

  If the reception confirmation signal is not turned on in step S283, the CPU 56 resets the reception confirmation determination flag if the reception confirmation determination flag is set (step S284). Here, the reception confirmation determination flag counts the reception confirmation signal on determination time value as the ON time duration of the reception confirmation signal that can be determined that the reception confirmation signal has been output (turned on). This flag is set in step S292 to be described later. In step S284, the reception confirmation determination flag is reset because the reception confirmation determination flag is reset and the reception confirmation signal on determination time value is being measured and the reception confirmation signal on determination time value is not reached. This is because when the signal is turned off, it can be determined that the signal is noise, and it is necessary to cancel the timing state of the reception confirmation signal on determination time value.

  Next, the CPU 56 confirms whether or not the reception confirmation monitoring flag is set (step S285). Here, the reception confirmation monitoring flag is a flag indicating whether or not the reception confirmation signal is monitored to be in an on state (in an off state) for an abnormally long time, and is described later in step S286. Set by.

  When the reception confirmation monitoring flag is not set in step S285, the CPU 56 sets the reception confirmation monitoring flag, sets the reception confirmation signal on monitoring time value in the prize ball management timer (step S286), and waits for a prize ball. 2 is finished. Here, the prize ball management timer is a timer provided separately from the above-mentioned prize ball timer, and the reception confirmation signal ON monitoring time value indicates whether the reception confirmation signal is in an ON state for an abnormally long time (OFF state). It is a value used to monitor whether or not The reception confirmation signal on monitoring time value is based on the standard time from when the prize ball command signal is transmitted until the reception confirmation signal is turned on, and is longer than the standard time. A value (predetermined period) at which it is possible to determine that an abnormality has occurred in the state is predetermined. Accordingly, the reception confirmation signal is kept off after the prize ball command signal is transmitted, and when the time when the reception confirmation signal does not turn on reaches the reception confirmation signal on monitoring time value, the communication state of the reception confirmation signal is set. It is determined that an abnormality has occurred. In this way, by setting the reception confirmation signal on monitoring time value in the prize ball management timer, the reception confirmation signal on monitoring time by the prize ball management timer can be measured.

  On the other hand, when the reception confirmation monitoring flag is set in step S285, the CPU 56 confirms the value of the prize ball management timer (step S287). If the value is not 0, the value of the prize ball management timer is decreased by 1. (Step S288), the award ball waiting process 2 ends. On the other hand, when the value of the prize ball management timer becomes 0 in step S287, the CPU 56 determines that the reception confirmation signal has been turned off for an abnormally long time, and the prize ball REQ signal, prize ball number signal, and Then, the signals related to the prize ball control such as the reception confirmation monitoring flag, the data such as the timer, the flag, etc. are cleared (reset) (step S289), the value of the prize ball process code is set to 0 (step S290), Processing 2 ends. Thus, when it is determined that the reception confirmation signal has been off for an abnormally long time, the prize ball process code of FIG. 27 is used in the next prize ball control process in accordance with the value of the prize ball process code becoming zero. The waiting process 1 is executed, and the prize ball control process is initialized. That is, the winning ball control process is executed again and the winning ball control signal is retransmitted.

  Further, when the CPU 56 determines that the reception confirmation signal is turned on in the above-described step S283, the CPU 56 checks whether or not the above-described reception determination confirmation flag is set (step S291). When it is determined that the reception confirmation determination flag is not set, the CPU 56 sets the reception confirmation determination flag and sets the reception confirmation signal ON determination time value in the prize ball timer (step S292). move on. Thereby, the reception confirmation signal ON determination time by the prize ball timer can be measured. On the other hand, when it is determined in step S291 that the reception confirmation determination flag is set, the CPU 56 checks the value of the prize ball timer (step S293). Decrease (step S294) and proceed to step S285 described above.

  Here, after step S292 or step S294 is executed, the process proceeds to step S285, and until it is determined in step S293 that the value of the prize ball timer has become 0, the award ball waiting process 2 The example in which the subtraction of the step S288 prize ball management timer is performed every time is executed. However, the present invention is not limited to this. When it is determined in step S283 that the reception confirmation signal is in the ON state, after executing step S292 or step S294, the award ball waiting process 2 is executed without executing the subsequent processes. You may make it complete | finish.

  When the value of the prize ball timer becomes 0 in step S293, it is determined that the reception confirmation flag has been turned on, and the following processing is executed. The reception confirmation monitoring flag and the reception confirmation determination flag are reset (step S295). Then, the CPU 56 sets the reception confirmation signal OFF monitoring time value in the prize ball management timer (step S296). Here, the reception confirmation signal off monitoring time value is a value used for monitoring whether or not the reception confirmation signal is in an off state (on state) for an abnormally long time. The reception confirmation signal off monitoring time value is based on the standard time from when the reception confirmation signal is turned on to when it is turned off, and is longer than the standard time, and is apparent in the communication state of the reception confirmation signal. Is predetermined to a value (predetermined period) at which it can be determined that an abnormality has occurred. Therefore, the ON state continues for the reception confirmation signal after the prize ball command signal is transmitted, and when the reception confirmation signal OFF monitoring time value reaches the time when the reception confirmation signal does not enter the OFF state, the communication state of the reception confirmation signal is set. It is determined that an abnormality has occurred. In this way, by setting the reception confirmation signal off monitoring time value in the prize ball management timer, the reception confirmation signal off monitoring time by the prize ball management timer can be measured.

  Next, a reception confirmation flag is set (step S297), and the contents of the prize ball number buffer (the number of prize balls paid out to the payout control microcomputer) are subtracted from the contents of the total prize ball number storage buffer (step S298). . The process executed in step S298 is a process of subtracting the number of prize balls to be paid specified by the prize ball number signal included in the prize ball command signal output from the number of prize balls stored in the total prize ball number storage buffer. Yes, hereinafter referred to as subtraction processing.

  Then, the CPU 56 turns off the prize ball REQ signal (step S299), and sets a reception confirmation signal off judgment time value for judging whether or not the reception confirmation signal is turned off in the prize ball timer (step S300). ), The award ball waiting process 2 ends. Here, the reception confirmation signal off determination time value is that the output of the reception confirmation signal is surely stopped (turned off) if the game control microcomputer continues the off state of the reception confirmation signal for the time indicated by the value. This is a value for determination.

  If the reception confirmation flag is set in step S297 in response to reception of the reception confirmation signal, it is determined in step S281 that the reception confirmation flag is set, and the process proceeds to step S301 in FIG. Whether or not is turned off is checked (step S301). When the reception confirmation signal is not turned off, the CPU 56 checks the value of the prize ball management timer (step S308). If the value is not 0, the value of the prize ball management timer is decreased by 1 (step S309), and the prize is awarded. The ball waiting process 2 ends. On the other hand, when the value of the prize ball management timer becomes 0 in step S308, the CPU 56 determines that the reception confirmation signal has been turned on for an abnormally long time, and the full error signal and the out-of-ball error signal. Based on the state, it is confirmed whether or not the full switch 48 or the ball break switch 187 is turned on (step S310).

  When the full tank switch 48 or the full ball switch 187 is in the ON state in step S310, for example, it is caused by the fact that the payout of the prize ball is disabled (stopped) due to the full tank or the full ball. The payout of the prize ball is stopped and the communication is in an abnormal state, but there is no obvious problem with the payout operation itself, so it is determined that the error state has occurred in the payout control microcomputer. Without performing the processing, the processing for informing the effect control microcomputer that the lower pan is full or the ball is out of state is executed.

  That is, it is confirmed whether or not a full tank error signal is input (step S310a). If a full tank error signal is input, a full tank error notification signal is set (step S310b). On the other hand, if the full tank error signal is not input in step S310a, the ball shortage error notification signal is set assuming that the ball shortage error signal has been input (step S310c). Thereby, the full tank error notification signal and the ball shortage error notification signal are output to the effect control board 80 in the special symbol command control process (step S25) described later.

  On the other hand, when the full switch 48 or the ball break switch 187 is not turned on in step S310, it is a communication abnormal state in which it is unknown whether there is any obvious problem with the payout operation itself. It is determined that an abnormality has occurred in the computer, and a payout communication abnormality notification signal and a payout initialization signal are set (step S311). As a result, a payout initialization signal is output to the payout control microcomputer, and a payout communication abnormality notification signal is output to the effect control board 80 in a special symbol command control process (step S25) described later.

  The effect control CPU 101 of the effect control board 80 that has received the above-described abnormal payout notification signal, full tank error signal, ball run out error signal, payout communication error notification signal, and payout operation error notification signal described later is a variable display device. 9 and an abnormality notification effect capable of specifying an abnormal state related to a reception confirmation signal such as the generation of an abnormality notification sound from the speaker 27 and the like. Thereby, it becomes possible to easily grasp that such an abnormal state has occurred. Further, the abnormality notification effect is not limited to the image display and sound generation as described above, and a predetermined lamp may be controlled to emit light, and among the display, sound generation, and light emission, You may make it carry out by any one, the combination of any two, or all the combinations.

  As described above, when the CPU 101 of the effect control board 80 receives the above-described abnormal payout notification signal, full tank error signal, out of ball error signal, payout communication error notification signal, and payout operation error notification signal described later, an error notification effect is provided. When a full tank error signal and a full ball error signal are input, the full error signal or the full ball error signal is continuously input for a predetermined period on the production control microcomputer side. When it is determined that the abnormality has occurred, an abnormality notification effect may be controlled. That is, the period for which the full error notification signal and the ball shortage error notification signal are input is counted on the production control microcomputer side, and the abnormality notification effect is controlled based on the fact that the predetermined period has been reached. It may be.

  In addition, when it is determined in step S310 that a full tank error signal or a ball shortage error signal has been input, a full tank error signal is received when the ball shortage error signal and the ball shortage error signal have been input for a predetermined period of time. Alternatively, a ball break error signal may be output to the effect control board 80. That is, the game control microcomputer side counts the period during which the full-fill error signal and the ball-out error signal are input, and based on the fact that the predetermined period has been reached, A ball break error signal may be output.

  Further, when the detection control signal input to the full tank switch 48 continues for a predetermined period on the payout control microcomputer side, a full tank error signal is displayed. May be output to the main board 31. That is, the period during which the detection signal of the full tank switch 48 and the detection signal of the ball break switch 187 are input is counted on the payout control microcomputer side, and the full tank error signal based on the fact that the predetermined period has been reached, Alternatively, a ball break error signal may be output to the main board 31.

  The payout initialization signal is a control signal for canceling the abnormal state in the payout control microcomputer, and is output to the payout control board 37 by being set in step S311.

  Then, in order to newly transmit a prize ball number signal and a prize ball REQ signal as prize ball command signals, data such as a prize ball control signal, a timer, and a flag are cleared (step S312a). After the value of the ball process code is set to 0 (step S312b), the award ball waiting process 2 is terminated. As a result, when it is determined that the reception confirmation signal has been in an on state for an abnormally long time in an abnormal communication state in which it is unclear whether or not the payout operation itself is clearly problematic, the value of the winning ball process code is 0. Accordingly, the award ball waiting process 1 in FIG. 27 is executed in the next award ball control process, and the award ball control process is initialized. Thus, a new prize ball command signal is transmitted by newly executing the prize ball control process from the prize ball waiting process 1, and the prize ball control is newly performed.

  In this embodiment, the award ball waiting process 1 is newly executed when it is determined that there is an abnormal communication state in which it is unknown whether there is an obvious problem with the payout operation itself. The subtraction process described above is performed by transmitting a command signal. However, the present invention is not limited to this, and when it is determined that there is an obvious problem in the payout operation itself, a new communication abnormality state is determined. When transmitting a prize ball command signal, the above-described subtraction process may be controlled not to be performed. For example, a step of setting a predetermined flag when the prize ball process code is set to 0 in step S312b, a step of bypassing execution of step S289 when the flag is set, and bypassing execution of step S289 A step of resetting the predetermined flag described above may be provided. Further, when a new prize ball command signal is transmitted when it is determined that the communication abnormality state in which it is unclear whether or not there is any obvious problem with the payout operation itself, the number of prize balls paid out once subtracted in step S289 is calculated. Control may be performed so that a new subtraction process is performed by returning to the original (for example, adding the number once subtracted to the number of prize balls stored in the total prize ball number storage buffer).

  If it is determined in step S301 that the reception confirmation signal is off, the CPU 56 checks the value of the prize ball timer (step S302). If the value is not 0, the CPU 56 sets the value of the prize ball timer. Decrease by 1 (step S303) and proceed to step S308 described above.

  Here, in the process after the reception confirmation signal is received, after step S303 is executed, the process proceeds to step S308 until the value of the prize ball timer is determined to be 0 by step S302. In the meantime, the example in which the prize ball management timer is subtracted every time the prize ball waiting process 2 is executed in step S309 has been described. However, the present invention is not limited to this, and if it is determined in step S301 that the reception confirmation signal is in the OFF state, a process of ending the award ball waiting process 2 may be executed after executing step S303.

  When the value of the prize ball timer becomes 0 in step S302, the CPU 56 determines that the reception confirmation signal has been turned off, and proceeds to step S304. The CPU 56 sets the payout-operation-in-signal-on monitoring time value in the prize ball management timer (step S304). The payout operation signal on-monitoring time value is a value used to monitor whether the payout operation in-progress signal is not in an on state for an abnormally long time (in an off state). The payout operation signal on monitoring time value is based on a standard time from when the award ball REQ signal is turned off to when the payout operation signal is turned on, which is longer than the standard time, and is paid out. The value is determined in advance (predetermined period) so that it is possible to determine that an abnormality has clearly occurred in the communication state of the operating signal. Accordingly, the off-state continues for the payout operation signal after the prize ball REQ signal is turned off, and when the time during which the payout operation signal does not turn on reaches the payout operation signal on monitoring time value, the payout operation is performed. It is determined that an abnormality has occurred in the communication state of the medium signal. Thus, by setting the payout operation signal on monitoring time value in the prize ball management timer, the payout operation signal on monitoring time by the prize ball management timer can be measured.

  Next, the CPU 56 resets the reception confirmation flag (step S305), and sets the above-described payout operation waiting flag (step S306). As a result, a waiting state for receiving a payout operation signal is entered. Then, the CPU 56 sets the payout operation signal ON determination time value in the prize ball timer (step S307), and ends the prize ball waiting process 2. Here, the payout operation signal on determination time value is determined by the CPU 56 that the payout operation in-progress signal is output (turned on) if the on state of the payout operation signal continues for the time indicated by the value. It is a value for. As a result, it is possible to measure the on-time signal on determination time by the prize ball timer.

  If the payout operation waiting flag is set in step S306 in response to the stop of the reception confirmation signal, it is determined in step S282 that the payout operation wait flag is set, and the process proceeds to step S313 in FIG. Check if the medium signal is on. When the payout operation in-progress signal is on, the process proceeds to step S314 described later. On the other hand, when the payout operation in-progress signal is not turned on in step S313, the value of the prize ball management timer set in step S304 described above is confirmed (step S318). The value is decremented by 1 (step S319), and the award ball waiting process 2 ends.

  When the value of the prize ball management timer becomes 0 in step S318, the CPU 56 determines that the payout operation in-progress signal has been off for an abnormally long time, and receives a prize ball number signal, a payout operation waiting flag, and the like. Each of the signals relating to the prize ball control, the timer, the flag, etc. is cleared (reset) (step S320), the value of the prize ball process code is set to 0 (step S321), and the prize ball waiting process 2 is terminated. As a result, when it is determined that the payout operation in-progress signal has been in an off state for an abnormally long time, the prize ball process code is set to 0 in accordance with the prize ball process code value of 0 in the next prize ball control process. The ball waiting process 1 is executed, and the prize ball control process is initialized. As a result, the prize ball command signal is retransmitted when the prize ball control process is executed again.

  If the CPU 56 determines that the payout operation in-progress signal is on in step S313, the CPU 56 checks the value of the prize ball timer (step S314). If the value is not 0, the CPU 56 decrements the value of the prize ball timer by 1 (step S314). S315), the process proceeds to step S318 described above. When the value of the prize ball timer becomes 0 in step S314, the CPU 56 sets the payout operation signal off monitoring time value in the prize ball management timer (step S316). Here, the payout operation signal off monitoring time value is a value provided to monitor whether or not the payout operation signal is in an off state for an abnormally long time, and the payout operation signal is in the on state. The standard time until the completion of the award ball payout operation is set as a reference, and is set in advance to a value that is longer than the standard time and that can clearly determine that an abnormality has occurred in the communication status of the payout operation signal. ing. Therefore, when the payout operation signal is turned on, the on state continues, and when the time during which the payout operation signal is not turned off reaches the payout operation signal off monitoring time value, the communication status of the payout operation signal It is determined that an abnormality occurred. In this way, by setting the payout operation signal off monitoring time value in the prize ball management timer, the payout operation signal off monitoring time by the prize ball management timer can be measured.

  Next, the CPU 56 sets a payout operation signal off determination time value in the prize ball timer (step S316a). The payout operation signal off determination time value indicates that the payout operation signal is no longer output (turned off) if the game control microcomputer continues the off state of the payout operation signal for the time indicated by the value. This is a value to check. Then, the value of the prize ball process code is set to 3 (step S317), and the prize ball waiting process 2 is ended.

  FIG. 32 is a flowchart showing the award ball waiting process 3 (step S234) executed when the value of the award ball process code is 3. In the award ball waiting process 3, the CPU 56 checks whether or not the payout operation in-progress signal has been turned off (step S271). If it is not in the off state, it is confirmed whether or not the value of the above-mentioned prize ball management timer has become 0 (step S277). If the value of the prize ball management timer is not 0, the value of the prize ball management timer is decreased by 1 (step S278), and the prize ball waiting process 3 is ended. On the other hand, when the value of the prize ball management timer becomes 0 in step S277, it is determined that an abnormality has clearly occurred in the communication state of the above-mentioned payout operation signal because the payout operation signal off monitoring time has elapsed. A is turned off (step S279), and a payout operation abnormality notifying signal which is an effect control signal for instructing that such communication or more has occurred is set (step S280). 3 is finished. Although not shown in the drawing, the connection confirmation signal A in the OFF state in step S279 and the state in which the payout operation abnormality notification signal is set in step S280 are set under predetermined conditions (for example, the payout operation in-progress signal is It is released when it has been turned off. The same applies to signals for notifying other abnormal states (an abnormal payout notification signal, a full tank error signal, a ball running out error signal, and a payout communication abnormality notification signal).

  The CPU 56 checks the value of the prize ball timer when the payout operation in-progress signal is turned off in step S271 (step S273), and if the value is not 0, the value of the prize ball timer is decreased by 1 (step S274). End the process. When the value of the prize ball timer becomes 0, the prize ball REQ waiting time is set in the prize ball timer on the assumption that the payout operation in-progress signal has been turned off (step S275). Then, the value of the prize ball process code is set to 0 (step S276), and the process is terminated. As described above, the award ball REQ waiting time is a waiting time until the next award ball REQ signal is turned on (when award ball payout is continuously executed, a plurality of award ball REQ signals are turned on) Is a time for providing an interval).

  Through the above processing, the game control microcomputer stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The total award ball number storage buffer corresponds to a prize game medium number data storage means for storing stored contents for at least a predetermined period by a backup power source as a fluctuation data storage means when power supply to the gaming machine is stopped.

  Further, the game control microcomputer transmits a prize ball command signal for designating a payout number of a predetermined number of prize balls to the payout control microcomputer based on the number of prize balls stored in the prize ball number buffer. . Here, the predetermined number is 15 if the number of prize balls stored in the prize ball number buffer is 15 or more, and if it is less than 15, the prize balls stored in the total prize ball number storage buffer. Is a number. Then, when a predetermined condition that the reception confirmation signal is turned on is satisfied, a subtraction process for subtracting the number of payouts of the prize ball designated by the prize ball command signal from the number of prize balls stored in the total prize ball number storage buffer is performed. Do.

  In this embodiment, the predetermined condition for executing the subtraction process is when a reception confirmation signal is received from the payout control microcomputer. When the reception confirmation signal is turned on, the payout control microcomputer has not yet paid out the number of prize balls designated by the prize ball command signal. If configured to perform subtraction processing of the total prize ball number storage buffer when the winning ball payout is completed, an illegal act of restoring the power supply after illegally stopping the power supply of the gaming machine during paying the winning ball As a result, a large number of prize balls are illegally paid out. For example, if 15 prize ball payouts are instructed by a prize ball command signal, when 10 prize ball payouts are made, if the power supply is restored after illegally stopping the power supply of the gaming machine Since the contents of the total number of winning ball storage buffer are not subtracted at all, it is assumed that the ten winning balls are not paid out even though ten winning balls are actually paid out. The ball control will continue.

  However, in this embodiment, when the payout operation in-progress signal is turned on, that is, when the payout control microcomputer receives the prize ball command signal and transmits the reception confirmation signal, the total prize ball number storage buffer subtraction process Since the above is executed, the above fraud can be prevented.

  Next, the special symbol command control process executed in step S27 of FIG. 15 will be described. FIG. 33 is a flowchart showing the special symbol command control process. In the special symbol command control process, the CPU 56 performs an effect control signal (abnormality notification command signal: abnormal payout notification signal, command for controlling the abnormality notification effect by step S311, step S280, step S242, step S310b, step S310c, etc.). It is checked whether or not there is a transmission request for an effect control signal based on the setting of the full tank error signal, the ball running out error signal, the payout communication abnormality notification signal, and the payout operation abnormality notification signal) (step S720). When it is determined that there is a transmission request, the CPU 56 notifies the production control board 80 of the production control signal (for example, an abnormal payout notification signal, a full tank error signal, a ball out error signal, a payout communication abnormality notification). Signal, payout operation abnormality notification signal, etc.) are transmitted (step S721), and the process is terminated.

  On the other hand, when it is determined in step S720 that there is no transmission request, the CPU 56 sets a control signal other than an effect control signal for instructing control of an abnormality notification effect such as a control signal for variable display of a special symbol, for example. It is confirmed whether or not there is a transmission request for an effect control signal based on the result (step S722). When it is determined in step S722 that there is a transmission request, the CPU 56 gives an effect control signal (for example, an effect control signal such as a control signal for variable display of special symbols) to the effect control board 80. ) Is transmitted (step S723), and the process ends. By performing such processing, the effect control signal set as described above is transmitted from the main board 31 to the effect control board 80.

  In this embodiment, as the prize game medium number storage means for storing the total number of prize game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of the prize game media in an identifiable manner stores the number of prizes for each prize area, or the number of prizes for each prize area (for example, the same number of prize balls) (for example, , 14 winning holes corresponding to the number of 6 winning balls, 10 left winning hole 29 corresponding to the number of 10 winning balls, right falling winning port 30, left winning port 33, right winning port 39, 15 winning balls It is also possible to memorize the number of winnings to the big winning opening corresponding to the number, and the number of winnings for which the winning ball payout has not ended yet).

  FIG. 34 is a timing chart showing an example of the output state of the payout control signal. Here, "6 pieces" are detected by switches for detecting a winning (for example, a left dropping winning opening switch 29a, a right dropping winning opening switch 30a, a left winning opening switch 33a, a right winning opening switch 39a, a start opening switch 14a, and a count switch 23). A case will be described in which a winning corresponding to “15” winning balls is detected after a winning corresponding to “15” winning balls is detected. As described above, when a winning is detected, the number of winning balls corresponding to the winning is added to the total winning ball number storing buffer in the winning ball number adding process.

  As shown in FIG. 34, when a winning according to “6” winning balls is detected, the CPU 56 loses the content of the total winning ball number storage buffer to 0 and the connection confirmation signal B is ON. Based on the fact, the award ball REQ signal is set to the output state (ON state = low level), and the award ball number signal indicating 6 is set to the output state (see steps S254 and S255). When the prize ball REQ signal and the prize ball number signal are simultaneously output, the prize ball command signal is output. The payout control microcomputer receives the prize ball number signal by outputting the prize ball REQ signal.

  Upon receiving the prize ball REQ signal, the payout control CPU 371 outputs a reception confirmation signal indicating that the prize ball command signal has been received (turned on), and then stops outputting the reception confirmation signal after a predetermined time (off). State). When the output of the reception confirmation signal is stopped, a payout operation in-progress signal indicating that a prize ball is being paid out (in the payout operation) is turned on (changed from the off state to the on state), and the payout motor 292 is driven to execute a payout process of six prize balls indicated by the prize ball number signal. Then, in response to the reception confirmation signal being turned on, the CPU 56 subtracts the contents of the prize ball number buffer (step S298) and sets the prize ball REQ signal to a stopped state (off state: high level). (Step S299). By setting the prize ball REQ signal to the stop state, the prize ball command signal is stopped.

  When the payout operation in-progress signal remains on, it indicates that the payout process (payout operation) is being executed. When the payout process for the six prize balls is completed, the payout control CPU 371 turns off the payout operation in-progress signal. When the payout operation in-progress signal falls (change from the on state to the off state), a payout completion signal indicating that the execution of the payout process (payout operation) has ended is output (turned on).

  When the CPU 56 confirms that six prize balls have been paid out based on the payout completion signal due to the turn-off signal being turned off, the CPU 56 stops the output of the prize ball number signal (step S31). (See S271, Step S241, Step S244). When the payout process based on the winnings corresponding to the six winning balls is completed, the CPU 56 sets the winning ball REQ signal to the output state based on the fact that the content of the total winning ball number storage buffer is not 0, and 15 The prize ball number signal shown is output. In this manner, the output of the prize ball command signal is prohibited until the payout operation in-progress signal is turned off. That is, if it is confirmed in step S241 in FIG. 27 that the payout operation in-progress signal is OFF and it is not confirmed in step S245 that the prize ball REQ waiting time has elapsed, the next prize ball transmission process is executed. Since the prize ball number signal and the prize ball REQ signal are not output, the output of the prize ball command signal is prohibited until the payout operation in-progress signal is turned off. In other words, the CPU 56 performs a subtraction process for subtracting the number of prize balls to be paid out according to the reception confirmation signal (step S298) and stops outputting the prize ball command signal by stopping the output of the prize ball REQ signal ( After step S299), even when there is a remaining number of payouts stored after the subtraction process, the on-state output of the payout operation signal is stopped (NO in step S241), and the winning ball REQ waiting time is reached. Until the time elapses (YES in step S245), the output of the next prize ball command signal is prohibited.

  In this embodiment, as shown in FIG. 34, the payout process based on the “15” prize balls generated later ends the payout process based on the winning according to the “6” prize balls. Wait until. That is, when a plurality of winnings are continuously generated, the CPU 56 confirms the payout of the winning ball based on the previous winning by the paying operation in-progress signal, and waits until the winning ball REQ waiting time elapses. Wait for a prize ball payout request to be issued. In other words, the prize ball command signal transmission means in the game control microcomputer is stored in the prize game medium number storage means (in this example, the total prize ball number storage buffer) after the subtraction process by the prize game medium number storage number subtraction means. When the number of unpaid premium game media has been stored, the payout processing of premium game media with the number of prize balls paid out specified by the prize ball command signal is completed, and the following waiting time has passed. The prize ball command signal is output.

  Next, the operation of the payout control microcomputer (the payout control CPU 371 and peripheral circuits such as ROM and RAM) will be described. FIG. 35 is an explanatory diagram showing an example of output port assignment in the payout control microcomputer. As shown in FIG. 35, the output port 0 is an output port for outputting a signal of each phase supplied to the payout motor 292 by the stepping motor. Further, the output port 1 has a payout operation in-progress signal, a ball out LED 52, a prize ball LED 51, a reception confirmation signal, prize ball information output to the outside of the gaming machine, ball rental information, gaming machine error information, and a connection confirmation signal B. Is an output port.

  The output port 2 is an output port for outputting each segment of the error display LED 374 using a 7-segment LED. The output port 3 is an output port for outputting an EXS signal and a PRDY signal to the card unit 50, a full tank error signal and a ball breakage error signal to the main board 31, and a main board unconnected error signal to the launch control board 91. is there. The main board non-connection error signal is a signal for notifying the launch control CPU mounted on the launch control board 91 that the connection confirmation signal A from the main board 31 has been turned off.

  FIG. 36 is an explanatory diagram showing an example of bit assignment of input ports in the payout control microcomputer. As shown in FIG. 36, a 4-bit prize ball number signal is input to bits 0 to 3 of the input port 0, and a connection confirmation signal A (power supply cutoff) from the main board 31 is input to bits 4 to 7, respectively. Signal), a prize ball REQ signal from the main board 31, a detection signal from the ball break switch 187, and a detection signal from the payout motor position sensor 295 are input. Further, the detection signal of the payout count switch 301, the operation signal from the error release switch 375, and the detection signal of the full switch 48 are input to bits 0 to 2 of the input port 1, respectively. The VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 3 to 5 of the input port 1, respectively. A payout initialization signal from the main board 31 is input to bit 0 of the input port 2.

  FIG. 37 is a timing diagram for explaining communication between the payout control microcomputer of the gaming machine and the card unit 50. The payout control microcomputer turns on the PRDY signal when power supply to the gaming machine is started and the payout operation is possible. When the power supply is started, the card unit 50 turns on the VL signal as a connection confirmation signal. When a card is received in the card unit 50 and a ball lending switch signal is input by operating the ball lending switch, the card unit 50 outputs a BRDY signal to the payout control microcomputer. That is, the BRDY signal is turned on. When a predetermined delay time elapses from this point, the card unit 50 outputs a BRQ signal to the payout control microcomputer. That is, the BRQ signal is turned on.

  Then, when the payout control microcomputer turns on the EXS signal for the card unit 50 and detects the fall (off) of the BRQ signal from the card unit 50, the payout motor 292 is driven to set a predetermined number (for example, 25). ) Rental balls to the player. When the payout is completed, the payout control microcomputer causes the EXS signal to the card unit 50 to fall. That is, the EXS signal is turned off.

  Next, the operation of the payout control microcomputer will be described. FIG. 38 is a flowchart showing a main process executed by the payout control microcomputer. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S601). Next, the interrupt mode is set to interrupt mode 2 (step S602), and a stack pointer designation address is set to the stack pointer (step S603). The payout control CPU 371 initializes the built-in device register (step S604), initializes the CTC and PIO (step S605), and sets the RAM to an accessible state (step S606).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S604 and the process in step S605, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. The timer interruption process includes a payout control process for controlling the payout means (including a process for driving the ball payout device 97 at least in response to a command signal related to paying out a prize ball from the main board 31, and a ball payout device in response to a ball lending request. The process which drives 97 may be included.) Is performed.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on CTC channel 3 (CH3) count-up is an interrupt generated when the CPU internal clock (system clock) is counted down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase.

  Next, the payout control CPU 371 executes normal initialization processing (steps S607 to S609). In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S607). In addition, initial values are set in flags and counters in the RAM area. Then, a CTC register provided in the payout control CPU 371 is set so that a timer interruption is periodically performed (step S608). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since interruption is prohibited in step S601 of the initial setting process, an interrupt is permitted before the initialization process is completed (step S609). Thereafter, the connection confirmation signal B is turned on (step S610), and loop processing is started.

  As described above, in this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, a payout control process (steps S651 to S658) is executed in the timer interrupt process.

  FIG. 39 is a flowchart showing an example of timer interrupt processing executed by the payout control CPU 371. In the timer interrupt process, a payout control process (steps S651 to S658) is executed. In the payout control process, the payout control CPU 371 first executes a switch process (step S651). The switch process is the same as the switch process in the game control microcomputer. If the state of the input port for inputting the detection signal of each switch is ON, the switch timer provided for each switch Add 1 to the value.

  Next, the payout control CPU 371 executes a payout motor control process (step S652). In the payout motor control process, when the payout motor 292 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed. And the prepaid card unit control process which communicates with the card unit 50 is performed (step S653).

  Next, the payout control CPU 371 executes main control communication processing for communicating with the game control microcomputer of the main board 31 (step S654). Further, payout control execution processing is performed for performing control for paying out a ball in response to a ball lending request from the card unit 50, and performing control for paying out the number of prize balls indicated by the prize ball number signal from the main board 31. This is executed (step S655).

  The payout control CPU 371 executes error processing for detecting various errors (step S656). Further, an information output process for outputting prize ball information and ball rental information output to the outside of the gaming machine is executed (step S657). In addition, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S658). In the display control process, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball REQ signal is on. Further, when the prize ball REQ signal is turned off, control for turning off the prize ball LED 51 is performed.

  Similarly to the game control microcomputer, a RAM area (output port buffer) corresponding to the output state of the output port is provided, and the payout control CPU 371 outputs the contents of the output port buffer to the output port ( Step S659). The output port buffer is a payout motor control process (step S652), a prepaid card unit control process (step S653), a main control communication process (step S654), an information output process (step S657), and a display control process (step S658). Updated.

  FIG. 40 is a flowchart showing the payout motor control process in step S652. In the payout motor control process, the payout control CPU 371 executes any one of steps S521 to S526 according to the value of the payout motor control code.

  In the payout motor normal process (step S521) executed when the value of the payout motor control code is 0, the payout control CPU 371 sets the pointer at the head address of the table stored in the ROM. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 292 at the time of ball payout is sequentially set. Yes.

  In the payout motor activation preparation process (step S522) executed when the value of the payout motor control code is 1, the payout control CPU 371 sets bits 0 to 3 of the output port 0 buffer corresponding to the output state of the output port 0. Performs processing such as setting the initial value of the excitation pattern.

  In the payout motor slow-up process (step S523) executed when the value of the payout motor control code is 2, the payout control CPU 371 starts the rotation of the payout motor 292 more smoothly than in the case of the constant speed process. Bit 0 of the output port 0 buffer corresponding to the output state of the output port 0 by reading the contents of the payout motor excitation pattern table at a long interval and gradually approaching the time interval in the case of constant speed processing. Set to ~ 3. At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the pointer value is incremented by one.

  In the payout motor constant speed process (step S524) executed when the value of the payout motor control code is 3, the payout control CPU 371 periodically reads the content of the payout motor excitation pattern table and outputs the output state of the output port 0. Are set to bits 0 to 3 of the output port 0 buffer corresponding to.

  In the payout motor brake process (step S525) executed when the value of the payout motor control code is 4, the payout control CPU 371 has a longer interval than in the case of the constant speed process in order to stop the payout motor 292 smoothly. In addition, bits 0 to 3 of the output port 0 buffer corresponding to the output state of the output port 0 are read out at a time interval that gradually moves away from the time interval in the case of constant speed processing. Set to.

  In the ball biting payout motor brake process (step S526) executed when the value of the payout motor control code is 5, the payout control CPU 371 smoothes the payout motor 292 in the case of rotation for releasing the ball biting. In order to stop, the payout motor excitation pattern is longer than the rotation of the payout motor 292 for releasing the ball biting, and gradually away from the time interval in the case of constant speed processing. The contents of the table are read and set to bits 0 to 3 of the output port 0 buffer corresponding to the output state of output port 0.

  FIG. 41 is a flowchart showing the main control communication process in step S654. In the main control communication process, the payout control CPU 371 executes one of steps S531, S532a, S532b, S532c, and S533 according to the value of the main control communication control code.

  FIG. 42 is a flowchart showing a main control communication normal process (step S531) executed when the value of the main control communication control code is zero. In the main control communication normal process, the payout control CPU 371 ends the process without executing the subsequent processes if the error bit is on (step S541). The error bit is a bit in an error flag that is set when it is detected that various errors have occurred. In step S541, if even one bit in the error flag is set, it is determined that the error bit is set. When the error bit is set as described above, the error display LED 374 notifies that an error state as an abnormal state has occurred according to the type of the error bit, as will be described later.

  If the BRDY signal is on, the payout control CPU 371 ends the process without executing the subsequent processes (step S542). That the BRDY signal is on means that a ball lending request is generated from the card unit 50. That is, when a ball lending request is generated, communication with the game control microcomputer of the main board 31 does not proceed. Furthermore, when the ball payout operation is being performed, that is, when a ball lending operation flag to be described later is set, the processing is terminated without executing the subsequent processing (step S543). Therefore, even when the ball payout operation is in progress, communication with the game control microcomputer of the main board 31 does not proceed. If the connection confirmation signal A from the main board 31 is in the off state, the process is terminated without executing the subsequent processes (step S544).

  As described above, when the payout control microcomputer does not receive the connection confirmation signal A, that is, when the game control microcomputer is not connected to the payout control microcomputer, the CPU 56 receives the reception confirmation signal. In this state, the subtraction process for the number of payouts cannot be performed. In such a case, the payout process by the payout control CPU 371 is prohibited by terminating the process without executing the processes in and after step S544.

  If the conditions in steps S541 to S543 are not satisfied and the connection confirmation signal A is in the on state, the payout control CPU 371 confirms whether or not the prize ball REQ signal that has been in the on state has been received (step). S545a). When the prize ball REQ signal is not in the on state, the processing is terminated without executing the subsequent processing. On the other hand, when the prize ball REQ signal is in the on state in step S545a, the payout control CPU 371 checks the detection signals of the full tank switch 48 and the ball break switch 187, so that the full tank error state or the ball It is confirmed whether or not it is a cutting error state (step S545b). Whether or not a full tank error state or a ball shortage error state has occurred may be determined by checking whether a full tank error bit and a ball shortage error bit, which will be described later, are set. If it is determined in step S545b that the full error state or the out-of-ball error state has not occurred, it is determined that the winning ball number signal is to be captured (actual capturing is executed in step S551c described later), and the reception confirmation signal is turned on. To output (step S546). Specifically, the bit corresponding to the reception confirmation signal in the output port buffer corresponding to the output state of the output port 1 is set to the on state. On the other hand, when it is in the full tank error state or the ball shortage error state in step S545b, the process is terminated without executing the subsequent processes. As a result, in a full stop error state or a payout stop state such as a ball shortage error state, it is difficult to pay out a prize ball, and therefore no reception confirmation signal is output.

  When the reception confirmation signal is turned on in step S546, the prize ball REQ signal monitoring time value is set in the main control communication control timer 1 (step S547a). Here, the main control communication control timer 1 is one of the main control communication control timers used for monitoring the time related to the communication of the main board 31 with the game control microcomputer. The prize ball REQ signal monitoring time value is a value used to monitor whether or not the prize ball REQ signal has been on for an abnormally long time. The prize ball REQ signal monitoring time value is based on a standard time from when the prize ball REQ signal is turned on to when it is turned off, and is longer than the standard time. The value is determined in advance so that it can be clearly determined that an abnormality has occurred. Therefore, when the prize ball REQ signal is turned on and the prize ball REQ signal remains on for a time that reaches the prize ball REQ signal monitoring time value, the communication status of the prize ball REQ signal is abnormal. Judged to have occurred. As described above, the prize ball REQ signal monitoring time value is set in the main control communication control timer 1, whereby the prize ball REQ signal can be monitored.

  Next, the reception confirmation signal output time value is set in the main control communication control timer 2 (step S547b). Here, the main control communication control timer 2 is one of the main control communication control timers. The reception confirmation signal output time value is a value of time for monitoring the reception confirmation signal in the on state and turning it off after a predetermined time. After the reception confirmation signal is turned on, the reception confirmation signal output time value is determined after the award ball payout number is set in the award ball unpaid number counter in step S551c described later based on the turn-off of the prize ball REQ signal. The time until the payout operation in-progress signal is turned on in 551d, which will be described later, is set in advance after the award ball payout number is set in the award ball unpaid number counter in step S551c. As described above, the reception confirmation signal output time value is set in the main control communication control timer 2, so that the time for setting the reception confirmation signal to the OFF state in synchronization with the change to the ON state of the payout operation in-progress signal is set. It becomes possible. Then, the value of the main control communication control code is set to 1 (step S548), and the process ends.

  FIG. 43 is a flowchart showing the first main control communication in-process (step S532a) executed when the value of the main control communication control code is 1. In the first main control communication processing, the payout control CPU 371 checks whether or not the reception confirmation signal is in an ON state (for example, when the numerical data of the main control communication control timer is data being measured). (It is determined that the reception confirmation signal is in an ON state) (step S550a). On the other hand, if the reception confirmation signal is on in step S550a, the value of main control communication control timer 2 is decremented by 1 (step S550b). The payout control CPU 371 checks whether the value of the main control communication control timer 2 is 0 (step S550c). If the value of the main control communication control timer 2 is not 0, the process is terminated. On the other hand, when the value of the main control communication control timer 2 becomes 0 in step S550c, the reception confirmation signal is turned off (step S550d), the value of the main control communication control code is set to 2 (step S550e), and the process ends. To do.

  FIG. 44 is a flowchart showing the second main control communication in-process (step S532b) executed when the value of the main control communication control code is 2. In the second main control communication process, the payout control CPU 371 checks whether or not the prize ball REQ signal is turned off (step S551). When in the off state, the number of winning balls indicated by the winning ball number signal is set in an unpaid number counter as a means for counting and storing the number of unpaid out of the number of winning balls designated by the winning ball command signal (step) S551c). As described above, when the number of prize balls is set in the unpaid-out number counter, a prize that is a flag indicating that the operation of paying out prize balls is being executed in step S632 of the payout start waiting process in FIG. 48 described later. The ball operating flag will be set. The unpaid-off number counter is formed in a volatile (not backed up) RAM area. Then, the payout control CPU 371 turns on the payout operation in-progress signal (step S551d), sets the value of the main control communication control code to 3 (step S551e), and ends the process.

  If the prize ball REQ signal is not turned off in step S551, the value of the main control communication control timer 1 is decremented by 1 (step S551a). If the value of the main control communication control timer 1 is 0 (step S551b), it is determined that the prize ball REQ signal needs to be turned off, but it has not been turned off. The bit is set (step S552), and the process ends. In this way, when the time during which the award ball REQ signal is turned on and the on state continues has reached the award ball REQ signal monitoring time set in step S547a described above, the award ball REQ signal error bit is set. As a result, it is notified that an abnormality has occurred in the communication state of the prize ball REQ signal.

  FIG. 45 is a flowchart showing the third main control communication in-process (step S532c) executed when the value of the main control communication control code is 3. In the third main control in-communication process, the payout control CPU 371 is set with a prize ball operating flag (set in step S842 described later), which is a flag indicating that an operation of paying out a prize ball is being executed. If it is not set, that is, if the winning ball operation is not being executed, a process for turning off the payout operation in-progress signal is performed (step S554). Specifically, the bit corresponding to the payout operation in-progress signal in the output port buffer corresponding to the output state of the output port 1 is set to the OFF state. Also, a prize ball number signal off monitoring time for monitoring that the prize ball number signal is turned off is set in the main control communication control timer 3 (step S555). Here, the main control communication control timer 3 is one of the main control communication control timers. The prize ball number signal off monitoring time is based on the standard time from when the payout operation signal is turned off to when the prize ball number signal is turned off, and is longer than the standard time. The value is determined in advance so that it can be clearly determined that an abnormality has occurred in the communication state of the number signal. Therefore, if the time during which the prize ball number signal is not turned off after the payout operation in progress signal is turned off reaches the prize ball number signal off monitoring time, it is determined that an abnormality has occurred in the communication state of the prize ball number signal. . Then, the value of the main control communication control code is set to 4 (step S556), and the process ends.

  FIG. 46 is a flowchart showing main control communication end processing (step S533) executed when the value of the main control communication control code is 4. In the main control communication end process, the payout control CPU 371 checks whether or not the prize ball number signal has been turned off (step S561). If it becomes an OFF state, it will transfer to step S565.

  If the prize ball number signal is not in the OFF state in step S561, the value of the main control communication control timer 3 is decremented by 1 (step S562), and whether or not the value of the main control communication control timer 3 has become zero. Is confirmed (step S563). If the value of the main control communication control timer 3 is 0, the prize ball number signal error bit is set in the error flag, assuming that the prize ball number signal has not been turned off within the monitoring time (step S564), and step S565. Migrate to As described above, when the time during which the prize ball number signal is not turned off after the turn-out signal is turned off reaches the prize ball number off monitoring time, the prize ball number signal error bit is set, It is notified that an abnormality has occurred in the communication state of the ball number signal. In step S565, the value of the main control communication control code is set to 0, and the process ends.

  FIG. 47 is a flowchart showing the payout control execution process of step S655. In the payout control execution process, the payout control CPU 371 confirms that the detection signal of the payout count switch 301 is turned on (step S731), and decrements the value of the unpaid-out number counter by 1 (step S732). Thereafter, any one of steps S740 to S742 is executed according to the value of the payout control code.

  FIG. 48 is a flowchart showing the payout start waiting process (step S740) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (step S831). The error bit in the error flag includes a main board non-connection error bit. The main board non-connection error is set when the connection confirmation signal from the main board 31 is in an off state. That is, the payout control microcomputer starts substantial control on condition that the connection confirmation signal A is turned on after power supply to the gaming machine is started.

  If the BRDY signal is not on (step S832), processing for paying out a prize ball after step S841 is executed. If the BRDY signal is on (step S832) and the BRQ signal that is a ball lending request signal is on (step S833), the EXS signal is turned on (step S834). The EXS signal is a signal (ball lending completion signal) for notifying the card unit 50 that a ball lending request has been accepted.

  After turning on the EXS signal, the payout control CPU 371 sets a ball lending operation in progress flag (step S835). Then, “25” is set in the unpaid number counter (step S836), and “25” is set in the payout motor rotation number buffer (step S837).

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S652). That is, in the payout motor control process, control is performed to rotate the payout motor 292 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S838), the value of the payout control code is set to 1 (step S839), and the process is terminated.

  In step S841, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S841). If 0, the process ends. In the unpaid number counter, in step S551c in the main control communication normal process, that is, when the prize ball REQ signal is turned off after receiving the prize ball REQ signal from the game control microcomputer of the main board 31, A value other than 0 (the number indicated by the prize ball number signal) is set. Accordingly, when the value of the unpaid-out number counter is not 0, a winning ball moving flag is set (step S842). Then, the value of the unpaid number counter is set in the payout motor rotation number buffer (step S843), and the process proceeds to step S838.

  FIG. 49 is a flowchart showing a payout motor stop waiting process (step S741) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S851). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and whether the payout operation is completed by checking the flag in step S851. You can check whether or not.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control timer (step S852). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 292 until it passes through the payout count switch 301. Then, the value of the payout control code is set to 2 (step S853), and the process ends.

  FIG. 50 is a flowchart showing a payout passing waiting process (step S742) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first subtracts 1 from the value of the payout control timer (step S861). Then, the value of the payout control timer is confirmed (step S862). If the value is not 0, that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out in step S862, the value of the unpaid-out number counter is confirmed (step S863). If the payout operation is normally executed, all the game balls paid out by the payout motor 292 pass through the payout count switch 301 before the payout control timer times out, and an unpaid-out counter is obtained by the processing of steps S731 and S732. The value of is 0. When the value of the unpaid-out number counter indicates a positive value, it means that the number of game balls actually paid out is less than the planned payout number (insufficient payout). Further, when the value of the unpaid-out number counter indicates a negative value, it means that the number of game balls actually paid out is larger than the planned payout number (excessive payout or excessive payout).

  In step S863, the payout control CPU 371 sets the internal state indicating that the payout process is in progress to a state where the payout process is not being performed when the value of the unpaid-out number counter is not a positive value (if the payout is not insufficient). change. Specifically, when the ball lending operation is being executed, that is, when the ball lending operation flag is set (step S864), the ball lending operation flag is reset (step S865), The EXS signal for the card unit 50 is turned off (step S866). If the ball lending operation flag is not set in step S864, that is, if the award ball operation flag indicating that the award ball operation is being executed is set, the award ball operation flag is set. Reset (step S867).

  Thereafter, the re-payout operation counter is cleared (step S868), the value of the payout control code is set to 0 (step S869), and the process ends. Note that when the payout operation is normally executed, the process of step S868 is unnecessary, but after the corrected payout process described later is executed, the process of step S868 is required. Further, in this embodiment, it is considered that the payout process is normally completed even when the payout is excessive. However, when the payout is excessive, an error may be reported to notify that.

  When it is confirmed in step S863 that the value of the unpaid-out number counter is a positive value, the payout control CPU 371 performs control for the corrected payout process in steps S870 to S875. Here, a maximum of two re-payout operations are performed until the number of game balls to be paid out is paid out. An error bit is set when the number of game balls to be paid out is not paid out even after two re-payout operations are performed.

  In step S870, the payout control CPU 371 checks whether or not the value of the re-payout operation counter is 2. If the value of the re-payout operation counter is not 2, the value of the unpaid-out number counter is set in the payout motor rotation number buffer (step S871), and the value corresponding to the payout motor start preparation process (““ 1 ") is set (step S872). Further, the value of the re-payout operation counter is incremented by 1 (step S873), the value of the payout control code is set to 1 (step S874), and the process is terminated. The processes in steps S871, S872, and S874 are the same as the processes in steps S837 to S839 in the payout start waiting process, although the values set in the payout motor rotation frequency buffer are different.

  When it is confirmed in step S870 that the value of the re-payout operation counter is 2, the payout control CPU 371 sets a payout count switch non-passing error bit (payout case error bit) in the error flag (step S875). ), The process is terminated.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control microcomputer is based on the detection signal from the payout count switch 301 as the payout detection means, in the volatile storage means (in this example, unpaid When it is detected that a prize game medium that is less than the number of prize balls that is stored in the number counter is detected, the payout is limited to a predetermined number of times (in this example, twice). Let the means pay out the insufficient prize game media. In this embodiment, if the payout shortage is not resolved even after performing the retry operation for paying out the insufficient prize game media twice, the payout case error bit is set and an error is being generated. (Step S875), the payout case error bit may be set when the shortage of payout is detected for the first time.

  In the payout control process, the error bit is checked only in the payout start waiting process shown in FIG. In the payout motor stop waiting process shown in FIG. 49 and the payout waiting process shown in FIG. 50, the error bit is not checked. Therefore, after the process of step S837 or step S843 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. Then, after the payout of the number of balls or prize balls set in step S837 or step S843 is completed, the payout process thereafter is determined by a check in step S831 (for example, designated by a prize ball number signal). When the payout of prize game media based on the number of prize balls paid out is completed). The error bit in the error flag includes an error bit indicating that the connection confirmation signal from the main board 31 has been turned off. Therefore, even when the connection confirmation signal is turned off, the game ball payout process is stopped at a time when it is best to turn it off.

  In the payout control microcomputer, unlike the game control microcomputer, the RAM is not backed up. When power is backed up, for example, even if a power failure occurs, when the power is restored from the power failure, the game balls that have not been paid out are based on the value of the unpaid number counter stored in the RAM that has been backed up. Can be paid out. However, if the RAM is not backed up, information indicating unpaid game balls will be lost if a power failure occurs, resulting in a disadvantage to the player. Therefore, even if an error occurs, by paying out as many game balls as possible, it is possible to prevent the player from being disadvantaged as much as possible.

  FIG. 51 is a timing chart for explaining the ball biting detection process executed in the payout motor control process (step S652). In the payout motor constant speed process (step S524) in the payout motor control process, the payout control CPU 371 monitors the detection signal of the payout motor position sensor 295. The detection signal of the payout motor position sensor 295 is turned on twice every time the payout motor 292 makes one rotation, for example. In order for the detection signal to be output twice each time the payout motor 292 makes one rotation, in the payout motor 292, two locations (in relation to the axis) in the portion that receives light from the light emitting part in the payout motor position sensor 295. A reflector is provided at a symmetrical position. The output of the light receiving unit in the dispensing motor position sensor 295 is used as a detection signal.

  Accordingly, the payout control CPU 371 gives an excitation pattern having a number of steps of 1/2 or more to the payout motor 292, but the detection signal of the payout motor position sensor 295 does not turn on. Actually, it can be determined that the payout motor 292 is not rotating due to foreign matter such as dust adhering to the payout motor 292 and clogging of the game ball (ball biting has occurred).

  In this embodiment, the payout motor 292 rotates once when receiving an excitation pattern for 16 steps. Then, for example, as shown in FIG. 55, the payout control CPU 371 checks the detection signal of the payout motor position sensor 295 every time an excitation pattern for 8 steps is given to the payout motor 292. It is determined whether or not it is rotating. And if it is the same state five times continuously (the detection signal OFF state of the dispensing motor position sensor 295 is five times continuous or the on state is five times continuous), it is determined that the ball biting has occurred, and the dispensing motor control process The ball biting release process is executed.

  FIG. 52 is a timing chart for explaining the ball biting release process executed in the payout motor control process (step S652). The payout control CPU 371 repeats a process of rotating the payout motor 292 at a high speed and a process of rotating at a medium speed a predetermined number of times (for example, 9 times) in the ball biting release process. Each time an excitation pattern for 8 steps is given to the payout motor 292, the detection signal of the payout motor position sensor 295 is checked to determine whether or not the payout motor 292 is rotating. When it is determined that the rotation of the payout motor 292 has been recovered by the detection signal, the ball biting release process is terminated and the normal payout process is returned to.

  If there is no change in the detection signal of the payout motor position sensor 295 even if the high speed rotation process and the medium speed rotation process are executed a predetermined number of times, the ball biting error bit (payout case error bit) in the error flag ) Is set. When the payout case error bit is set, the payout control CPU 371 does not drive the payout motor 292. When the payout case error bit is reset (see step S756 in FIG. 54), the payout control CPU 371 returns to a state in which the payout motor 292 can be driven.

  Thus, the payout control microcomputer includes a drive state monitoring means for monitoring the operating state of the payout means, and a drive stop means for stopping the drive of the payout means when the drive state monitoring means detects a malfunction of the payout means. Including.

  Next, error processing will be described. FIG. 53 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. 53, when the connection confirmation signal A from the main board 31 is turned off (for example, when the signal line is disconnected, or when the communication state of the payout operation signal shown in FIG. 32 is abnormal). The payout control CPU 371 performs control to display “1” on the error display LED 374 as a main board non-connection error. Note that the communication state of the payout operation signal shown in FIG. 32 is abnormal (the abnormal state in which the payout operation signal received on the game control microcomputer side does not enter the OFF state even after a predetermined time has elapsed since the ON state. ), A signal line for individually transmitting a signal indicating an abnormal state is provided without using the connection confirmation signal A so that the type of abnormal state can be recognized on the payout control CPU 371 side. Good. When the disconnection of the payout count switch 301 or a ball clogging occurs in the payout count switch 301, control is performed to display “2” on the error display LED 374 as the payout switch abnormality detection error 1. The disconnection of the payout count switch 301 or the occurrence of ball clogging at the payout count switch 301 is determined by the detection signal of the payout count switch 301 not being turned off.

  When the detection signal of the payout count switch 301 is turned on even though the game ball is not paying out, control is performed to display “3” on the error display LED 374 as the payout switch abnormality detection error 2. . If the rotation of the payout motor 292 is abnormal or the detection signal of the payout count switch 301 does not turn on even though the game ball is paid out, “4” is displayed on the error display LED 374 as a payout case error. Control the display. When the prize ball REQ signal is turned on at an incorrect timing, control is performed to display “5” on the error display LED 374 as a prize ball REQ signal error.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit unconnected error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S653). When the prize ball number signal is turned on at an incorrect timing, control is performed to display “0” on the error display LED 374 as a prize ball number signal error.

  In the error state described above, the error state is canceled without transmitting a control signal for returning the error state from the main board 31. In addition, since the display of the error display LED 374 stops when the error state is released, the cause of the error state can be specified when the error state is entered, and an error can be detected without transmitting a control signal from the main board 31. Since the display of the display LED 374 is stopped, the number of control signals transmitted from the main board 31 can be reduced, and the control burden on the game control microcomputer can be reduced.

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, a prize ball REQ signal error, or a prize ball number signal error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375. Is output (when turned on), the payout control microcomputer returns to the state before the error occurred.

  54 and 55 are flowcharts showing the error processing in step S656. In error processing, the payout control CPU 371 checks the error flag, and the set bits are only payout switch abnormality detection error 2, payout case error, prize ball REQ signal error, prize ball number signal error (4 It is confirmed whether it is only one of the bits or only any combination of the four (or all four) (step S750). If only those bits are set, it is confirmed whether or not the operation signal from the error release switch 375 has been turned on (step S751). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S752). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S753). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S757. If the timer before error recovery is set, the value of the timer before error recovery is reduced by 1 (step S754), and if the value of the timer before error recovery becomes 0 (step S755), the payout switch error in the error flag The bits of detection error 2, payout case error, prize ball REQ signal error, and prize ball number signal error are reset (step S756), and the process proceeds to step S757.

  As described above, the error state (which is in the payout prohibited state as shown in step S831 in FIG. 48) is released based on the operation of the error release switch 375. Processing can be activated.

  When the processing of step S756 is executed, error bits that are not set are among the bits of the payout switch abnormality detection error 2, the payout case error, the prize ball REQ signal error, and the prize ball number signal error. In some cases, there is no problem even if the error bit that is not in the set state is reset.

  That is, when the process of step S756 is executed and the payout case error bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIG. 50), and the number of unpaid pieces When the value of the counter is not 0, a game ball payout retry operation is started. That is, when the payout control execution process in step S655 is executed next, if the payout passing waiting process in step S742 is executed, the repayout process is performed again. For example, if a prize ball payout process has been performed and the value of the unpaid-out number counter is not 0, the process proceeds from step S863 to step S870. When the error bit is reset in error processing, the value of the re-payout operation counter is cleared. That is, 0. Accordingly, it is determined in step S870 that the re-payout operation counter is not 2, and the process for starting the re-payout process after step S872 is executed again, and the re-payout process is executed. If the shortage of payout is not solved even after the two re-payout processes are executed, the error state is entered again.

  As described above, the payout control microcomputer pays out a game ball when the payout count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the number of game media paid out is still less than the planned payout number Is detected (see steps S863 and S870), the control state related to the payout is shifted to the error state, and the correction payout control is performed again on the condition that the error release signal is output from the error release switch 375 in the error state. The correction payout control restart process is executed.

  Further, in the payout passing waiting process shown in FIG. 50, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when the error return time after operation elapses) (steps S751, S756). That is, the state of the payout case error (payout shortage error) is not automatically canceled based on the fact that the game ball has passed the payout count switch 301, etc. Is not released. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset by hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, the number of unpaid items The counter value is also cleared. However, in this embodiment, since the payout control microcomputer is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, and the player is It is possible not to give a disadvantage.

  Further, even during the execution of the re-payout operation in the error state, the processes in steps S731 and S732 are being executed. That is, even when an error related to payout occurs, if the game ball passes the payout count switch 301, the value of the unpaid-out number counter is subtracted. Therefore, the value of the unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  In this embodiment, the unpaid-out number data that has not been paid out of the planned number of payouts is managed by the unpaid-out number counter at the time of paying out a prize ball or at the time of lending a ball. And a counter for managing unpaid-out number data may be divided at the time of paying out a rental ball. When the counter for managing the unpaid-out number data is divided, in the processing of steps S731 and S732, the value of the prize ball payout counter is subtracted at the time of paying out the winning ball, and the value of the counter for lending payout is set at the time of paying out the rental ball. The value is subtracted. That is, in the payout control microcomputer, the prize unpaid number storage means for performing a subtraction process for subtracting the prize game medium number data based on the detection output of the payout detection means, and the loan unpaid based on the detection output of the payout detection means The lending unpaid-out number storage means for performing the subtraction process for subtracting the number data is realized separately. In addition, when neither the prize ball payout nor the rental ball payout is issued, it is preferable that the premium unpaid number storage means executes the subtraction process.

  In step S757, the payout control CPU 371 checks the detection signal of the full switch 48. If the detection signal of the full tank switch 48 is output (if it is on), the full tank error bit in the error flag is set (step S758), and the main board is turned on by setting the full tank error signal to the on state. (Step S759). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (step S760), and the full tank error signal is turned off to stop the output of the full tank error signal (step S761).

  Also, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S762). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S763), and the ball break error signal is turned on. It outputs to the board | substrate 31 (step S764). If the detection signal of the ball break switch 187 is in the off state, the ball break error bit is reset (step S765), and the ball break error signal is turned off by stopping the ball break error signal (step S766). . When the ball break error bit is set, in the display control process of step S658, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state.

  Then, the payout control CPU 371 checks whether or not the above-described payout initialization signal is on (step S767a). If the payout initialization signal is not on, the process proceeds to step S768a described later. On the other hand, if the payout initialization signal is in the ON state, the payout control CPU 371 receives a signal relating to the prize ball payout control and data such as a flag in order to initialize the subtracted prize ball payout control state. Clear (step S767b). Then, the payout control CPU 371 sets the value of the main control communication code used in the main control communication process of FIG. 41 to 0 in order to newly execute the prize ball payout control (step S767c). Thus, when the above-described payout initialization signal is turned on, the payout control state is initialized in software such that the main control communication process can be newly executed from the main control communication normal process. When such initialization is performed, for example, when an abnormality occurs in the communication state of a signal output from the payout control board 37 such as a reception confirmation signal or a payout operation in-progress signal, the communication state is automatically restored. It becomes possible.

  Further, the payout control CPU 371 checks the state of the connection confirmation signal A from the main board 31 (step S768a). If the connection confirmation signal A is not output (if it is in the off state), the main board unconnected error The bit is set (step S768b), and the main board non-connection error signal is turned on and output to the firing control board 91 (step S768c). If the connection confirmation signal is output (if it is on), the main board unconnected error bit is reset (step S768d), and the main board unconnected error signal is turned off (step S768e).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (step S770), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S771). If the value of the switch timer corresponding to the payout count switch 301 is equal to or shorter than the switch-on maximum time, the payout switch abnormality detection error 1 bit is reset (step S772). Note that the value of each switch timer is incremented by 1 if the state of the input port to which the detection signal of each switch is input is switched on in the switch processing of step S651, and cleared by 0 if it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout count switch 301 has exceeded the maximum switch-on time means that the payout count switch 301 has been turned on beyond the maximum switch-on time. It is determined that the game ball is clogged at the disconnection of the count switch 301 or at the portion of the payout count switch 301.

  In addition, when the value of the switch timer corresponding to the payout count switch 301 becomes a switch-on determination value (for example, “2”) (step S773), the payout control CPU 371 performs the ball lending operation flag and the winning ball operation. If both the middle flags are in the reset state, the game ball passes through the payout count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (steps S774 and S775). If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S776).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S777). If the VL signal is not input (if it is in the OFF state), the prepaid card unit not yet out of the error flags is displayed. A connection error bit is set (step S778). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S779).

  In the display control process in step S658, the error display LED 374 performs notification by display (numeric or alphabetic display) corresponding to the error bit in the error flag. In this embodiment, the game control microcomputer mounted on the main board 31 and the payout control microcomputer mounted on the payout control board 37 perform bi-directional communication with respect to prize ball payout, but a communication error occurs. Notification can be made by the LED 374 for error display. As a communication error, a main board non-connection error due to the connection confirmation signal A from the main board 31 being turned off, and a prize ball REQ signal error in which the prize ball REQ signal is turned on at an incorrect timing (see steps S551 to S552). And a prize ball number signal error (see steps S561 to S564) in which the prize ball number signal is turned on at an incorrect timing. If a communication error such as a main board non-connection error occurs, this is indicated. The launch motor 94 is transmitted to the launch control board 91, and the launch motor 94 is disabled by the launch control CPU mounted on the launch control board 91. That is, the game ball cannot be launched into the game area 7. Therefore, the game does not proceed even though a communication error such as a main board unconnected error has occurred.

  Of the communication errors, the main control disconnection error, the prize ball REQ signal error, and the prize ball number signal error excluding the abnormality in the communication state of the payout operation signal are detected on the payout control microcomputer side. Therefore, even if the game control microcomputer and the payout control microcomputer perform two-way communication with respect to the prize ball payout, a communication error can be detected without increasing the burden on the game control microcomputer.

  In this embodiment, the main board non-connection error is automatically eliminated when the connection confirmation signal is turned on (see steps S768a and S768d), but the condition that the error release switch 375 is further operated is added. Thus, the error state may be eliminated.

  Further, in this embodiment, a communication error is notified in distinction from a communication error with the card unit 50 (prepaid card unit non-connection error and prepaid card unit communication error) and other errors (see FIG. 53). . Therefore, a communication error between the game control microcomputer and the payout control microcomputer is easily identified.

  In this embodiment, the fact that an error relating to payout has occurred is notified by the error display LED 374 mounted on the payout control board 37 installed on the backside of the gaming machine. You may mount an alerting | reporting means in the other location (For example, the payout unit in which the ball payout apparatus 97 etc. were concentratedly arranged). Furthermore, you may make it alert | report by the indicator (for example, prize ball LED51) installed in the front side of the gaming machine. In the display control process, the payout control CPU 371 normally notifies that the award ball LED 51 is turned on when the award ball REQ signal is on, and the award ball LED 51 is turned off when the award ball REQ signal is off. However, when an error relating to payout occurs, for example, the prize ball LED 51 is blinked to notify that an error related to payout has occurred in a different manner from the normal. If an error is notified by a display device installed on the front side of the gaming machine, the game shop clerk can more easily recognize the occurrence of the error. Moreover, you may use together the alerting | reporting by LED 374 for error display, and the alerting | reporting by the indicator installed in the front side of the gaming machine.

  56 and 57 are flowcharts showing the display control process of step S658. In the error processing, the payout control CPU 371 first checks whether or not an error bit is set (step S780). If the error bit has been set, the error bit that has been set is specified, and a process for controlling the display of the error display LED 374 in a manner corresponding to the error bit is executed.

  If the set error bit is the main control unconnected error bit indicating that the connection confirmation signal A from the main board 31 is turned off (step S782), “1” is set in the error display LED 374. The display process is executed (step S783).

  If the set error bit is the above-described disconnection of the payout count switch 301 or the payout switch abnormality detection error 1 bit indicating that the ball is clogged in the payout count switch 301 (step S784), an error display is displayed. The process of displaying “2” on the LED 374 is executed (step S785).

  If the set error bit is a payout switch abnormality detection error 2 bit indicating that the detection signal of the payout count switch 301 is turned on even though the above-described game ball payout operation is not being performed (step S786). Then, a process of displaying “3” on the error display LED 374 is executed (step S787).

  A payout case error bit indicating that the set error bit indicates the abnormal rotation of the payout motor 292 described above or that the detection signal of the payout count switch 301 has not been turned on even though the game ball has been paid out. If so (step S788), a process of displaying “4” on the error display LED 374 is executed (step S789).

  If the set error bit is a prize ball REQ signal error bit indicating that the prize ball REQ signal is turned on at the above-described incorrect timing (step S790), “5” is displayed on the error display LED 374. The process is executed (step S791).

  If the set error bit is the above-described full-bottom state of the lower pan, that is, the full-tank error bit indicating that the full-tan switch 48 is turned on (step S792), the error display LED 374 is set to “6”. Is displayed (step S793).

  If the set error bit is the above-described supply ball shortage state, that is, the ball break error bit indicating that the ball break switch 187 has been turned on (step S794), the error display LED 374 is set to “7”. Is executed (step S795a), and the ball break LED output bit of the output port 1 buffer is set (step S795b). On the other hand, if the ball break error bit is not set, the ball break LED output bit of the output port 1 buffer is reset (step S795c).

  If the set error bit is a prepaid card unit unconnected error bit indicating that the VL signal from the card unit 50 is turned off (step S796), “8” is displayed on the error display LED 374. The process is executed (step S797).

  If the set error bit is a prepaid card unit communication error bit indicating that communication with the card unit 50 has been performed at the above-described incorrect timing (step S798), a process of displaying “9” on the error display LED 374 Is executed (step S799).

  If the prize ball is being paid out (the prize ball operating flag in the payout control state flag is set) in step S780 (step S781a), the prize ball LED output bit in the output port 1 buffer is set (step S781b). On the other hand, if the prize ball is not paid out, the prize ball LED output bit in the output port 1 buffer is reset (step S781c).

  FIG. 58 is a flowchart showing a launch control process executed by the launch control CPU mounted on the launch control board 91. In the firing control process, the firing control CPU, when the VL signal from the card unit 50 is in an off state (no prepaid card is connected), when the full tank switch 48 is in an on state (bottom pan full), or If the main board non-connection error signal transmitted when the connection confirmation signal A from the main board 31 is off (main board is not connected) in the payout control board 37 is on, the process proceeds to step S708 ( Steps S701 to S703). If the prepaid card is not connected, the lower plate is not full, and the main board unconnected error signal is not in the ON state, the process proceeds to step S704. In step S704, the firing control CPU confirms whether or not the operation knob 5 is operated (whether or not the firing control signal is on). If it is in the on state, the process proceeds to step S705, and if it is not in the on state, the process proceeds to step S708.

  In step S705, the firing control CPU adds 1 to the firing motor excitation pattern counter. Then, data corresponding to the value of the excitation pattern counter is read from the emission motor excitation pattern table stored in the ROM mounted on the emission control board 91 (step S706). Further, the read data is set in the firing motor excitation pattern buffer (step S707). In the firing motor excitation pattern table, the excitation pattern data (shooting motors φ1 to φ4) for each step for rotating the firing motor 94 is sequentially set.

  As described above, since the firing motor 94 is disabled when the prepaid card is not connected, the main board is not connected, and the lower plate is full, the game proceeds even though they are generated. There is no end to it. Even when other error conditions such as a prize ball REQ signal error in which the prize ball REQ signal is turned on at an improper timing, the firing motor 94 is disabled so that the game area 7 of the game ball is moved to. You may be in a state that can not be fired.

  Next, in this embodiment, the control operation when the power supply to the pachinko gaming machine 1 is stopped due to a power failure or the like during the execution of the prize ball payout operation by the payout motor 292 will be described in comparison with the conventional example. . Referring to FIG. 34, for example, when it is assumed that the power supply is stopped during the payout operation of six or fifteen prize balls, as shown in FIG. When the CPU 56 performs a subtraction process for subtracting the number of prize balls to be paid out in response to the rising of the reception confirmation signal (step S298), the output of the prize ball REQ signal is stopped (step S299) to thereby receive a prize ball command signal. Control to stop is performed. For this reason, since the prize ball command signal is already stopped at the time when the payout operation by the payout motor 292 is executed, the prize ball command signal is already stopped when the power supply is stopped.

  As described above, when the power supply to the pachinko gaming machine 1 is stopped due to a power failure or the like, data specifying the control state including the output state of the prize ball command signal is backed up and paid out on the main board 31 side. On the control board 37 side, data for specifying the control state is not backed up and stored. For this reason, when the power supply is restored after the power supply is stopped as described above, only the control state that is backed up and stored on the main board 31 side is effective. When the prize ball REQ signal is stopped, the backup-stored data regarding the prize ball command signal includes a prize ball command signal indicating that the prize ball number signal is in an output state and the prize ball REQ signal is in a stopped state. The data identifies the stop state. As shown in steps S545a to S548 in FIG. 42, the payout control CPU 371 does not advance the payout control unless the award ball REQ signal is output, so the award ball REQ signal as described above is in a stopped state. Even if the control state is restored based on the backup data specifying the stop state of the prize ball command signal, the payout operation is not executed again from the beginning. In other words, when the power supply to the pachinko gaming machine 1 is stopped due to a power failure or the like in the middle of the execution of the prize ball payout operation, it is possible to prevent excessive prize balls from being paid out based on the backup data.

  When the payout control in the conventional pachinko gaming machine is executed with respect to the present embodiment, as described below, the pachinko gaming machine is caused by a power failure or the like in the middle of the award ball payout operation. When the power supply to is stopped, excessive payout of prize balls based on the backup data cannot be prevented. FIG. 60 is a timing chart showing an example of an output state of a payout control signal in a conventional pachinko gaming machine.

  FIG. 60 shows an example of the output state of a payout control signal in the same control state as in FIG. In the conventional case, the connection confirmation signal is only a signal transmitted from the game control microcomputer to the payout control microcomputer. Further, in the conventional case, when the prize ball BUSY signal that is a single signal that functions as a reception confirmation signal when rising to the ON state and then functions as a payout operation signal, rises to the ON state, A subtraction process is performed to subtract the stored number of payouts.

  However, in this conventional case, the output state (on state) of the prize ball REQ signal is maintained until the payout operation is completed and the prize ball BUSY signal is turned off. That is, the output state (on state) of the prize ball command signal is maintained until the payout operation is completed and the prize ball BUSY signal is turned off. Therefore, when the subtraction process is performed and the output state of the prize ball command signal is still maintained, that is, when the power supply to the gaming machine is stopped due to a power failure or the like in the middle of the execution of the payout control, after the subtraction process The state in which the output state of the prize ball command signal is maintained is backed up and stored on the game control microcomputer side. As a result, when the power supply is restored, the payout process is executed again from the beginning based on the prize ball command signal whose output state is maintained even after the subtraction process, so that the prize game medium is excessively paid out. .

  Compared to such a conventional example, in the case of this embodiment, as shown in FIG. 34, when the subtraction process is performed in response to the rising of the reception confirmation signal, the output of the winning ball REQ signal is stopped. Therefore, when the supply of power to the pachinko gaming machine 1 is stopped due to a power failure or the like in the middle of execution of the winning ball payout operation, the payout operation is executed again from the beginning. It is possible to prevent excessive payout of prize balls based on backup data.

  FIG. 59 is a block diagram showing an example of output of test signals from the payout control board 37. As shown in FIG. FIG. 59 also shows the test terminal board 200 and the test apparatus 210. As shown in FIG. 59, in the payout control board 37, the detection signal from the payout count switch 301 and the payout operation in-progress signal output to the main board 31 are branched, and the branched signals are logical product circuits. (AND circuit) 376 is input. Therefore, the AND circuit 376 can output a prize ball count signal indicating that the prize ball has been paid out when the payout count switch 301 detects the payout of the game ball while the payout operation signal is being output. .

  In the payout control board 37, the prize ball count signal is output to a connector 377 provided on the payout control board 37. The connector 377 also outputs a test signal other than the prize ball count signal. The connector 377 is mounted only on the gaming machine used for the test. That is, a gaming machine that is not used for the test has a test signal output path such as a wiring pattern or a through hole, but the connector 377 is not mounted. Therefore, it is not necessary to provide the connector 377 for all the payout control boards 37, and the cost spent for testing the gaming machine is reduced. In addition, since it is not necessary to attach the connectors to all the payout control boards 37 by soldering or the like, the work efficiency for testing the gaming machine is improved. Further, since a wiring pattern and a through hole for outputting a test signal are provided in all the gaming machines, a connector 377 is attached to connect the test terminal board 200 when performing inspection after being installed in the game shop. It's easy to do. Therefore, in this embodiment, the connector 377 may not be provided. In other words, any means such as a wiring pattern for externally outputting the winning ball count signal from the AND circuit 376 may be provided, and the connector 377 may or may not be provided.

  Further, a prize ball count signal may be output from the main board 31 to the outside. That is, an AND circuit 376 is provided on the main board 31, and a detection signal from the payout count switch 301 is input to one input terminal of the AND circuit 376 and a payout operation in-progress signal is input to the other input terminal of the AND circuit 376. Then, an output signal (prize ball count signal) from the AND circuit 376 is output to the outside through the wiring pattern of the main board 31.

  The test terminal board 200 includes a connector 202 for inputting a test signal from a connector 377 mounted on the dispensing control board 37, a test signal output circuit 203, and a connector 204 for connecting to the test apparatus 210. ing. The test signal output circuit 203 includes an IC, a buffer circuit, and the like for selecting a test terminal used for signal output from a plurality of test terminals provided in the connector 204.

  The test apparatus 210 collects various test signals. At the time of the test, for example, a personal computer or the like is connected to the test apparatus 210. Accordingly, various data such as collecting data by various test signals input to the test apparatus 210 with a personal computer and displaying information for use in a test such as the number of awarded balls on the display unit of the personal computer. The calculation of the data can be performed.

  The ball payout device 97 is configured to perform both a prize ball payout and a ball payout, and a payout count switch 301 detects both a game ball due to a prize ball payout and a game ball due to a ball payout. As shown in FIG. 59, a payout control CPU 371 is installed by installing an AND circuit 376 that passes the detection signal of the payout count switch 301 when the payout operation in-progress signal output during the winning ball operation is on. The prize ball count signal as the test signal can be created without being involved.

  Next, communication of effect control signals between the game control microcomputer mounted on the main board 31 and the effect control microcomputer mounted on the effect control board 80, and effect control of the effect control microcomputer Signal reception will be described.

  FIG. 61 is an explanatory diagram showing signal lines of an effect control signal transmitted from the main board 31 to the effect control board 80. As shown in FIG. 61, in this embodiment, the effect control signal is transmitted from the main board 31 to the effect control board 80 through the eight signal lines of the symbol control signals CD0 to CD7. An effect control INT signal signal line for transmitting a strobe signal (effect control INT signal) is also wired between the main board 31 and the effect control board 80.

  In this embodiment, the effect control signal has a 2-byte configuration, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always “1”, and the first bit (bit 7) of the EXT data is always “0”. Note that such a command form is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  As shown in FIG. 62, 8-bit effect control signal data (design control signals CD0 to CD7) of the effect control signal is output in synchronization with the effect control INT signal. The effect control microcomputer mounted on the effect control board 80 detects, for example, that the effect control INT signal connected to the interrupt terminal of the microcomputer has risen, and generates 1-byte data by interrupt processing. Start the import process. Therefore, when viewed from the effect control microcomputer, the effect control INT signal corresponds to a capture signal that triggers the capture of the effect control signal data. It is assumed that when the 2-byte data is received, the effect control signal can be received. Note that the effect control INT signal may have a polarity opposite to that shown in FIG.

  FIG. 63 is a flowchart showing command analysis processing for analyzing the effect control signal received by the effect control microcomputer. The effect control signal received from the main board 31 is stored in the command reception buffer in the RAM mounted on the effect control board 80. In the command analysis process, the effect control microcomputer is stored in the command reception buffer. Check the contents of the command.

  In the command analysis process, the effect control microcomputer first checks whether or not a reception command is stored in the command reception buffer (step S911). If the reception command is stored in the command reception buffer, the effect control microcomputer reads the reception command from the command reception buffer (step S912). On the other hand, if the received command is not stored in the command receiving buffer, the process is terminated.

  If the received effect control signal is an effect control signal designated by a special symbol (step S913), the effect control microcomputer stores data indicating the special symbol included in the effect control signal in the special symbol storage area in the RAM. (Step S914).

  If the received effect control signal is an effect control signal designating a variation pattern of a special symbol that is variably displayed on the variable display device 9 (step S915), the effect control microcomputer uses the EXT data (variation pattern) of the command. Is stored in the variation pattern data storage area in the RAM mounted on the effect control board 80 (step S916), and the variation pattern reception flag is set (step S917). If the received command read in step S912 is another production control signal, an abnormality notification signal (abnormal payout notification signal, full tank error signal, ball out error signal, payout communication error notification signal, payout operation error notification signal) ) (Step S918).

  If it is an abnormality notification signal, the effect control microcomputer performs abnormality notification according to the content of the received abnormality notification signal (step S919). Note that the abnormality notification according to the content of the received abnormality notification signal is an abnormal state related to the reception confirmation signal such as the image display on the variable display device 9 and the generation of the abnormality notification sound from the speaker 27 as described above. This is control for providing an identifiable abnormality notification effect. Thereby, it becomes possible to easily grasp that such an abnormal state has occurred. If it is not an abnormality notification signal in step S918, a flag corresponding to the received command is set (step S920).

As described above, in this embodiment, when the game control microcomputer detects an abnormality related to communication with the payout control microcomputer, an abnormality related to communication has occurred due to the variable display device 9, the speaker 27, and the like. Is notified. As described above, when the payout control microcomputer detects an abnormality related to communication with the game control microcomputer, the payout control microcomputer controls the error display LED 374 to indicate that an abnormality related to communication has occurred. .
(Second example of the first embodiment)
Next, a second example of the first embodiment will be described. In the second example, the above-described subtraction process (step S298 in FIG. 29 in the first example) executed in the game control microcomputer is executed when the above-described payout operation in-progress signal is received. An example of control will be described. In the second example shown below, points different from the first example will be mainly described in order to avoid overlapping description with the first example described above.

  FIG. 64 is a flowchart showing a part of the award ball waiting process 2 (step S233) according to the second example of the first embodiment (a part corresponding to FIG. 29 of the first example). FIG. 64 is a drawing that replaces FIG. 29 of the first example. In FIG. 64, steps having the same functions as those in FIG. 29 are denoted by the same reference numerals as those in FIG. FIG. 64 differs from FIG. 29 in that step S298 of the subtraction process shown in FIG. 29 is not provided. That is, in the case of the second example, after setting the reception confirmation flag in step S297, the winning ball REQ signal is turned off in step S299 without performing the subtraction process.

  FIG. 65 is a flowchart showing another part (the part corresponding to FIG. 31 of the first example) of the award ball waiting process 2 (step S233) according to the second example of the first embodiment. In FIG. 65, steps having the same functions as those in FIG. 31 are denoted by the same reference numerals as in FIG. 31, and redundant description will not be repeated as much as possible. FIG. 65 differs from FIG. 31 in that a step of subtraction processing for performing the same processing as step S298 shown in FIG. 29 is provided between step S316a and step S317.

  In the case of the second example, when it is confirmed in step S314 that the value of the prize ball timer has become 0, that is, when it is determined that the payout operation in-progress signal has been turned on, the total prize ball number storage buffer in step S316b. Subtraction processing for subtracting the contents of the winning ball number buffer (the winning ball payout number commanded to the payout control microcomputer) is performed from the contents of. Thus, in the case of the second example, in the game control microcomputer, when the payout operation in-progress signal output from the payout control microcomputer is input (when received), the subtraction process is performed. is there.

  FIG. 66 is a flowchart showing the award ball waiting process 3 (step S234) according to the second example of the first embodiment. FIG. 66 is a drawing that replaces FIG. 32 of the first example. 66, steps having the same functions as those in FIG. 32 are denoted by the same reference numerals as in FIG. 32, and redundant description will not be repeated as much as possible. FIG. 66 differs from FIG. 32 in that, instead of steps S279 and S280 shown in FIG. 32, steps S278a to S278g that perform the same processes as steps S310 to S310c and steps S311 to S312b of FIG. Is a point provided.

  In the case of the second example, when it is confirmed in step S277 that the value of the prize ball management timer has become 0, that is, when the payout operation in progress signal is on for an abnormally long time, Then, based on the state of the ball-out error signal, it is determined whether or not the full switch 48 or the ball-out switch 187 is turned on (step S278a).

  When the full tank switch 48 or the full ball switch 187 is in the ON state in step S278a, for example, it is caused by the fact that the payout of the prize ball is disabled (stopped) due to the full tank or the full ball. The payout of the prize ball is stopped and the communication is abnormal, but there is no obvious problem with the payout operation itself, so it is determined that there is an error in the payout control microcomputer. Without performing the processing, the processing for causing the production control microcomputer to notify that the lower pan is full or the ball is out is executed.

  That is, it is confirmed whether or not a full tank error signal is input (step S278ea). If a full tank error signal is input, a full tank error notification signal is set (step S278f). On the other hand, if a full tank error signal is not input in step S278e, a ball shortage error notification signal is set assuming that a ball shortage error signal has been input (step S278g). Thus, the full symbol error notification signal and the ball shortage error notification signal are output to the effect control board 80 in the special symbol command control process (step S25).

  On the other hand, when the full switch 48 or the ball break switch 187 is not turned on in step S278a, it is a communication abnormal state in which it is unknown whether or not there is a clear problem in the payout operation itself. It is determined that an abnormality has occurred in the computer, and a payout operation abnormality notification signal and a payout initialization signal are set (step S278b). As a result, a payout initialization signal is output to the payout control microcomputer, and a payout operation abnormality notification signal is output to the effect control board 80 in the special symbol command control process (step S25).

  The effect control CPU 101 of the effect control board 80 that has received the full tank error signal, the ball running out error signal, and the payout operation abnormality notification signal described above displays an image on the variable display device 9 and an abnormality from the speaker 27. Control is performed to provide an abnormality notification effect that can specify an abnormal state related to a reception confirmation signal such as the generation of notification sound. Thereby, it becomes possible to easily grasp that such an abnormal state has occurred. Further, the abnormality notification effect is not limited to the image display and sound generation as described above, and a predetermined lamp may be controlled to emit light, and among the display, sound generation, and light emission, You may make it carry out by any one, the combination of any two, or all the combinations.

  The payout initialization signal is a control signal for canceling the abnormal state in the payout control microcomputer, and is output to the payout control board 37 when set in step S278b.

  Then, in order to newly transmit a prize ball number signal and a prize ball REQ signal as prize ball command signals, signals such as a prize ball control signal, a timer, and a flag are cleared (step S278c). After the value of the ball process code is set to 0 (step S278d), the award ball waiting process 2 is terminated. As a result, when it is determined that the reception confirmation signal has been in an on state for an abnormally long time in an abnormal communication state in which it is unknown whether or not the payout operation itself is obviously problematic, the value of the winning ball process code is 0. Accordingly, the award ball waiting process 1 in FIG. 27 is executed in the next award ball control process. Thus, a new prize ball command signal is transmitted by newly executing the prize ball control process from the prize ball waiting process 1, and the prize ball control is newly performed.

  In this embodiment, the award ball waiting process 1 is newly executed when it is determined that there is an abnormal communication state in which it is unknown whether there is an obvious problem with the payout operation itself. The subtraction process described above is performed by transmitting a command signal. However, the present invention is not limited to this, and when it is determined that there is an obvious problem in the payout operation itself, a new communication abnormality state is determined. When transmitting a prize ball command signal, the above-described subtraction process may be controlled not to be performed. For example, a step of setting a predetermined flag when the prize ball process code is set to 0 in step S278d, a step of bypassing execution of step S316b when the flag is set, and bypassing execution of step S316b A step of resetting the predetermined flag described above may be provided. Also, when a new prize ball command signal is transmitted when it is determined that the communication abnormal state in which it is unclear whether or not there is an obvious problem with the payout operation itself, the number of prize balls paid out once subtracted in step S316b is determined. Control may be performed so that a new subtraction process is performed by returning to the original (for example, adding the number once subtracted to the number of prize balls stored in the total prize ball number storage buffer).

  In the second example of the above-described embodiment, the example in which the game control microcomputer stops outputting the prize ball REQ signal when receiving the reception confirmation signal has been described. However, the present invention is not limited to this, and the game control microcomputer may perform control to stop the output of the prize ball REQ signal when the payout operation in-progress signal is received. For example, when the on-state of the payout operation signal is confirmed in step S314 in FIG. 65, the game control microcomputer executes a step of turning off the prize ball REQ signal after step S316b is executed, for example. . In this case, the payout control microcomputer turns off the reception confirmation signal at 550d in FIG. 43, and then executes step S551c to step S551e without executing step S551 in FIG. The number counter is set and a payout operation in-progress signal is output. If such a configuration is adopted, the prize ball command signal (prize ball REQ signal) is stopped immediately when the payout operation in-progress signal is input, so that the prize ball BUSY signal is turned off when the prize ball BUSY signal is turned off. Since the prize ball command signal is stopped earlier than in the case of the prior art in which the ball command signal is stopped, for example, the control state in the payout control microcomputer is unsatisfactory due to the unstable power supply voltage. When stable, the payout control microcomputer can be prevented from excessively paying out the prize game medium if the award ball command signal is input a plurality of times after the reception confirmation signal is input. Furthermore, when the signal output state is stored as in this embodiment, a prize ball command signal is output when the power supply to the gaming machine is stopped due to a power failure or the like in the middle of execution of the payout control. This makes it difficult to store the current state as a backup, and prevents excessive payout of prize balls based on the backup storage when the power supply is restored.

  As described above, when control is performed to stop the output of the prize ball REQ signal when the game control microcomputer receives the payout operation in-progress signal, the main control communication of the prize ball REQ signal monitoring time value in step S547a of FIG. The setting to the control timer 1 is executed after outputting the payout operation in-progress signal as described above. Then, the prize ball REQ signal error is monitored by performing the same processing as in steps S551a to S552 without executing step S551 in FIG. If such a configuration is adopted, after outputting a payout operation in response to the prize ball command signal, the output of the prize ball command signal (prize ball REQ signal) does not stop even after a predetermined period of time has passed. Since control for notifying that an abnormal state has occurred is executed, it can be recognized that such an abnormal state has occurred, and excessive payout of prize balls can be prevented.

  Further, in the above embodiment, the payout control microcomputer determines that the prize ball payout has ended when it detects that the payout motor 292 has rotated by the planned payout number, but the number of times detected by the payout motor position sensor is scheduled to be paid out. When the number is reached, it may be determined that the prize ball payout has ended. That is, the payout control microcomputer determines whether or not the payout is completed by detecting the operation amount of the payout means (in this example, the rotation amount of the payout motor 292 or the number of detections by the payout motor position sensor). It may be configured.

  Furthermore, in the above embodiment, the payout control microcomputer confirms that the game ball has been paid out based on the detection signal of the payout count switch 301, but the game is based on the output signal of the payout motor position sensor. You may make it confirm that the ball | bowl was paid out.

  Also, the payout control microcomputer detects the operation amount of the drive unit (for example, payout motor 292, cam, etc.) of the payout means, and whether or not an abnormality related to payout (payout unit error) has occurred based on the detection. It may be configured to determine whether or not. With such a configuration, it is possible to reliably detect an abnormality relating to payout.

  In the above embodiment, the ball payout device 97 is configured to execute both ball lending and prize ball payout. However, even if the mechanism for lending the ball and the mechanism for paying the prize ball are independent, The invention can be applied.

  In the above-described embodiment, the payout prohibition state is set when the ball is out of play or the lower pan is full. However, when other payouts are not preferable or the payout cannot be performed, You may set it in a payout prohibition state. For example, the payout prohibition state may be set also when the glass door frame 2 is in an open state and a detection signal is output from a door opening switch for detecting this.

  In each of the above-described embodiments, the recording medium used in the recording medium processing apparatus (card unit 50) is a magnetic card (prepaid card). However, the recording medium is not limited to a magnetic card, and is a non-contact type or a contact type. An IC card may be used. In addition, when the recording medium processing device is configured to be able to identify the recording information based on the identification code, the recording medium can be read at least by the recording medium processing device such as an identification code that can identify the recording information It may be something that can be recorded on. Furthermore, the recording medium may be a medium on which a predetermined information recording symbol such as a barcode is printed so as to be readable. The shape of the recording medium is not limited to the card shape, and may be any shape such as a disk shape, a spherical shape, or a chip shape.

It is the front view which looked at the bullet ball game machine from the front. It is the rear view which looked at the gaming machine from the back. It is the front view and sectional drawing which show a ball dispensing apparatus. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the component relevant to payout of a prize ball and a rental ball. It is explanatory drawing which shows the detail of the photocoupler and capacitor which are mounted in the payout control board. It is a block diagram showing a configuration example of an effect control board, a lamp driver board and a sound control board. It is a block diagram which shows the structural example of a power supply board. It is a block diagram which shows the structural example of a power supply board. It is a block diagram which shows CPU, a reset circuit, and a power supply monitoring circuit in a main board | substrate. It is explanatory drawing which shows the bit allocation example of the output port in the microcomputer for game control. It is explanatory drawing which shows the bit allocation example of the output port in the microcomputer for game control. It is explanatory drawing which shows the bit allocation example of the input port in the microcomputer for game control. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a power-off detection process. It is a flowchart which shows a power-off detection process. It is explanatory drawing which shows the buffer used by switch processing. It is a flowchart which shows an example of a switch process. It is a flowchart which shows an example of a switch check process. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a flowchart which shows a prize ball process. It is explanatory drawing which shows the structural example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball waiting processing 1. It is a flowchart which shows a prize ball transmission process. It is a flowchart which shows the winning ball waiting process 2. FIG. It is a flowchart which shows the winning ball waiting process 2. FIG. It is a flowchart which shows the winning ball waiting process 2. FIG. It is a flowchart which shows prize ball waiting processing 3. It is a flowchart which shows a special symbol command control process. It is a timing chart which shows the example of the output state of a control signal. It is explanatory drawing which shows the example of bit allocation of the output port in the microcomputer for payout control. It is explanatory drawing which shows the example of bit allocation of the input port in the microcomputer for payout control. It is a timing diagram for demonstrating communication between a prepaid card unit and a game machine. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a payout motor control process. It is a flowchart which shows a main control communication process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows a 1st main control communication process. It is a flowchart which shows a 2nd main control communication process. It is a flowchart which shows the 3rd main control communication process. It is a flowchart which shows a main control communication end process. It is a flowchart which shows payout control execution processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a timing diagram for explaining a ball biting detection process. It is a timing diagram for demonstrating a ball biting cancellation | release process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows a display control process. It is a flowchart which shows a display control process. It is a flowchart which shows the discharge control process which CPU for discharge control performs. It is a block diagram which shows an example of the output of a test signal. It is a timing chart which shows the example of the output state of the control signal in the conventional pachinko game machine. It is explanatory drawing which shows an example of the signal form of an effect control signal. It is a flowchart which shows an error process. It is a timing chart which shows the relationship between the 8-bit control signal and INT signal which comprise an effect control signal. It is a flowchart which shows the command analysis process which CPU for production control performs. It is a flowchart which shows the prize ball waiting process 2 by the 2nd example of 1st Embodiment. It is a flowchart which shows the prize ball waiting process 2 by the 2nd example of 1st Embodiment. It is a flowchart which shows the prize ball waiting process 3 by the 2nd example of 1st Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pachinko machine 3 Hit ball supply tray 4 Surplus ball receiving tray 5 Operation knob 7 Game area 9 Variable display device 25 Decoration lamp 27 Speaker 28a Top frame lamp 28b Left frame lamp 28c Right frame lamp 29 Left drop prize opening 30 Right drop prize opening 31 Main board 33 Left prize opening 37 Dispensing control board 37a Signal branching means 39 Right prize opening 48 Full tank switch 50 Card unit 51 Prize ball lamp 52 Out of ball lamp 54 ROM
55 RAM
56 CPU
57 I / O port 60 Balance display board 60a Frequency display LED
60b LED for lending ball
60c Ball lending switch 60d Return switch 66 Interface board 67 Output circuit 68 Input circuit 91 Launch control board 94 Launch motor 97 Ball delivery device 101 Production control CPU
150 Capacitor 151 Photocoupler 187 Out of Ball Switch 292 Dispensing Motor 301 Dispensing Count Switch 371 Dispensing Control CPU
373A Input circuit 373B Output circuit 374 Error display LED
375 Error release switch

Claims (9)

It is possible for a player to play a predetermined game by launching a game medium into the game area, and according to a predetermined lending request, a function of paying out a prize game medium based on a predetermined payout condition being satisfied A game machine having a payout means having a function of paying out game media
A game control microcomputer for controlling the progress of the game and outputting a prize ball command signal for designating the number of payout of the prize game medium and instructing the payout of the prize game medium;
A game control board on which the game control microcomputer is mounted;
In accordance with a display control signal output from the game control microcomputer, a display control microcomputer that controls an effect device that performs a game effect;
A payout control microcomputer for controlling the payout means based on a prize ball command signal transmitted from the game control microcomputer;
A payout control board on which the payout control microcomputer is mounted;
Launching means for launching a game medium toward the game area;
Firing control means for controlling the firing operation of the firing means;
A launch control board on which the launch control means is mounted;
A signal that is output to the payout control board from a gaming device provided outside the gaming machine, and that is a loan request signal that is output in response to the loan request, and to start power supply to the gaming device. A connection board that relays a connection confirmation signal output in response, and
No capacitor is mounted on the relay board, the payout control board is provided with a photocoupler on the signal line of the connection confirmation signal, and further connected to the signal line on the light emission side of the photocoupler on the payout control board. Provided a capacitor,
The launch control means includes launch operation stop control means for stopping the launch operation of the launch means when the connection confirmation signal input to the payout control board via the photocoupler is turned off,
The game control microcomputer is:
Backup storage means for backup storing data for specifying a control state by the gaming control microcomputer for a predetermined period when power supply to the gaming machine is stopped;
When the power supply to the gaming machine is restored, the gaming state restoration means for restoring the control state by the gaming control microcomputer based on the data stored in the backup storage means;
A number-of-payout storage means for storing information included in the backup storage means and capable of specifying the number of premium game media to be paid out based on the establishment of the payout condition;
Prize ball command signal output means for outputting the prize ball command signal to the payout control microcomputer based on the number of payouts stored in the payout number storage means;
Payout memory number subtracting means for performing subtraction processing for subtracting the payout number specified by the prize ball command signal from the payout number stored in the payout number storage means,
The dispensing control microcomputer is:
A means for storing data for specifying a control state by the microcomputer for payout control, and a payout control storing means for not storing the data as a backup when power supply to the gaming machine is stopped;
A prize game medium payout control means for controlling the payout means to execute a payout process for paying out a prize game medium of a payout number specified by the prize ball command signal;
Lending game medium payout control means for controlling the payout means to execute a ball lending process for paying out the lending game medium based on the lending request;
Input confirmation signal output means for outputting an input confirmation signal to the game control microcomputer for a predetermined period based on the input of the prize ball command signal;
An in-operation signal output means for outputting an in-operation signal to the game control microcomputer during execution of the payout process by the prize game medium payout control means,
The input confirmation signal output means transmits the input confirmation signal to the game control microcomputer on the condition that the ball lending processing by the game medium payout control means is not executed,
The payout memory number subtraction means performs the subtraction process based on the game control microcomputer receiving the operating signal,
The game control microcomputer is:
Abnormality determination means for determining that an abnormal state has occurred when the input confirmation signal does not stop after the input confirmation signal is input and the payout by the payout means is not stopped when the input confirmation signal has not been stopped. When,
An abnormality notification control signal output means for outputting an abnormality notification control signal for notifying the display control microcomputer that the abnormal state has occurred when the abnormality determination means determines that an abnormal state has occurred; ,
After the input confirmation signal is input, the prize ball command signal is output by the prize ball command signal output means regardless of the number of prize game media stored in the payout number storage means until the in-operation signal stops. A gaming machine further comprising: a prize ball command signal output regulating means for regulating. The game control microcomputer outputs an initialization instruction signal for instructing initialization of the payout control microcomputer when the abnormality determination means determines that the abnormal state has occurred. Further comprising an instruction signal output means,
2. The gaming machine according to claim 1, wherein the payout control microcomputer further includes an initialization means for initializing the payout control microcomputer when the initialization instruction signal is input. The game control microcomputer outputs a game control connection confirmation signal to the payout control microcomputer indicating that the game control microcomputer is connected to the payout control microcomputer when power supply to the gaming machine is started. A control connection confirmation signal output means;
3. The payout control microcomputer further includes payout process prohibiting means for prohibiting execution of the payout process when the game control connection confirmation signal is not inputted. The gaming machine described. The payout control microcomputer outputs a payout control connection confirmation signal indicating that it is connected to the game control microcomputer to the game control microcomputer when power supply to the game machine is started. It further includes a connection confirmation signal output means,
The game control microcomputer further includes prize ball command signal output prohibiting means for prohibiting output of the prize ball command signal by the prize ball command signal output means when the payout control connection confirmation signal is not inputted. The gaming machine according to any one of claims 1 to 3, wherein:   5. The gaming machine according to claim 1, wherein the gaming control microcomputer stops outputting the prize ball command signal when the input confirmation signal is input. The prize ball command signal output means, as means for outputting the prize ball command signal, requests a payout number signal output means for outputting a payout number signal for designating the number of payouts of the game medium, and requests for taking in the payout number signal. An acquisition request signal for outputting, and an acquisition request signal output means for outputting,
The payout control microcomputer performs a process of taking in the payout number signal by inputting the take-in request signal,
The game control microcomputer stops the output of the prize ball command signal by stopping the output of the take-in request signal when the input confirmation signal is input. The gaming machine according to any one of claims 1 to 4.   When the payout control microcomputer does not stop the output of the prize ball command signal by the prize ball command signal output means after a predetermined period has elapsed after outputting the input confirmation signal by the input confirmation signal output means The game machine according to claim 5 or 6, further comprising prize ball command signal abnormality notifying means for executing control for notifying that an abnormal state has occurred. The game control microcomputer is:
A period measuring means for measuring a period during which the input confirmation signal output from the input confirmation signal output means is not input after the prize ball command signal is output;
When the period measured by the period measuring unit has passed a predetermined period, the data indicating the period measured by the period measuring unit is initialized and the data indicating the output state of the prize ball command signal is initialized. The game machine according to any one of claims 1 to 7, further comprising: a prize ball command signal re-output unit that re-outputs the prize ball command signal. The gaming machine detects whether or not a predetermined amount or more of game media to be supplied to the payout means is secured, and outputs a game medium out signal to the payout control microcomputer when the amount is less than the predetermined amount. When it is detected whether or not a predetermined amount or more of game media is stored in the storage portion for storing the game media outage detecting means and the game medium paid out by the payout means, And a storage state detection means for outputting a storage state detection signal to the payout control microcomputer.
The dispensing control microcomputer is:
An abnormality detection payout process prohibiting means for prohibiting execution of the payout process when the game medium out signal is input or when the storage state detection signal is input;
A payout stop state that outputs a payout stop state signal indicating that the payout process is stopped to the game control microcomputer when the game medium out signal is input or when the storage state detection signal is input A signal output means,
The game control microcomputer further includes a payout state determination means for determining that payout by the payout means is in a stopped state based on the input of the payout stop state signal.
The abnormality notification control signal output means is a stop state notification control for notifying the display control microcomputer that the stop state has occurred when the payout state determination means determines that the stop state has occurred. The gaming machine according to claim 1, which has a function of outputting a signal.

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