JP2006061368A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine preventing prize game media from being put out excessively. <P>SOLUTION: When receiving a receiving confirmation signal, a CPU 56 performing a game control executes a subtraction of subtracting the number of put-out prize balls stored in a buffer for the number of prize balls and, after the output of a putout command signal comprising the prize ball REQ signal and a signal of the number of putout balls are stopped by turning off the prize ball REQ signal and if the number of residuals is left in the stored number of putout balls after the subtraction, prohibits a next putout command signal till the output of a putout BUSY signal as a putout processing signal is stopped. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine represented by, for example, a pachinko gaming machine, a coin gaming machine, or a slot machine. More specifically, the present invention relates to a gaming machine that can be played using a game medium and that pays out a prize game medium as a prize based on the fact that a payout condition is established by the game.

  In this type of gaming machine, what is conventionally known is controlled by a game control microcomputer composed of a microcomputer or the like, for example, and a prize game medium such as a pachinko ball is paid out. A payout control microcomputer comprising a microcomputer or the like that performs control is provided, and the payout control microcomputer controls the payout means based on the fact that a predetermined payout condition such as a winning of a hit ball is established, and a prize game as a prize Some were configured to dispense media.

  In this type of conventional gaming machine, there is one in which the following control is performed by bidirectional communication between the game control microcomputer and the payout control microcomputer (Patent Document 1). The game control microcomputer side stores information that can specify the number of premium game media to be paid out based on the establishment of the payout conditions. Based on the stored number of payouts, a payout command signal for designating the number of payouts of a predetermined number of prize game media is output to the payout control microcomputer, and the payout control microcomputer outputs the payout command that has been output. A payout process is executed in which the payout means controls the payout means to pay out the prize game media specified by the signal.

Further, in this conventional gaming machine, when the payout command signal from the game control microcomputer is received by the payout control microcomputer, a reception confirmation signal for confirming the reception is received from the payout control microcomputer. Output to the control microcomputer. Then, the game control microcomputer performs a subtraction process for subtracting the number of payouts specified by the payout command signal based on the reception confirmation signal. Further, in this gaming machine, when power supply to the gaming machine is stopped due to a power failure or the like, data for specifying the control state by the gaming control microcomputer is backed up for a certain period, and then when the power supply is restored, Control to restore the control state by the game control microcomputer based on the data stored in the backup is performed. However, the payout control microcomputer is configured so that such backup storage is not performed from the viewpoint of preventing fraud.
JP 2004-65676 A (paragraph numbers 0168 to 0170, 0209 to 0211, FIGS. 31 and 42)

  However, the conventional gaming machine as described above has the following problems. When the game control microcomputer receives the reception confirmation signal, it performs a subtraction process for subtracting the stored number of payouts, but the output state of the payout command signal is maintained thereafter. Therefore, when the subtracting process is performed and the output state of the payout command signal is still maintained, that is, when the power supply to the gaming machine is stopped due to a power failure or the like in the middle of executing the payout control, the game control microcomputer The control state is backed up and stored on the side, and the control state is not backed up and stored on the payout control microcomputer side. As a result, when the power supply is restored, only the control state backed up and stored on the game control microcomputer side becomes valid, so that the payout process is performed based on the payout command signal whose output state is maintained after the subtraction process. Is executed again from the beginning, there is a risk that the prize game medium will be excessively paid out.

  Also, in such a configuration in which such control is performed, for example, illegal modification such as improperly installing a switch in the power supply line of the gaming machine, and repeatedly stopping the power supply and switching the supply, excessively paying out premium game media There was a high possibility of cheating such as

  The present invention has been devised in view of such circumstances, and an object thereof is to provide a gaming machine capable of preventing excessive payout of premium game media.

Specific examples of means for solving the problems and their effects

(1) A game is possible using a game medium (pachinko ball, coin), and a prize game medium (prize ball, prize ball, prize) is given as a prize based on the fact that a payout condition (batted ball winning) is established by the game. A gaming machine (pachinko gaming machine 1, coin gaming machine, slot machine)
A game control microcomputer (from the CPU 56) that controls the progress of the game and transmits a payout command signal (payout number signal, prize ball REQ signal) that designates the number of payouts of the prize game medium and instructs the payout of the prize game medium. A gaming control microcomputer)
A payout means (ball payout device 97) for receiving the payout command signal and paying out the prize game medium of the payout number specified by the received payout command signal;
A payout control microcomputer (a payout control microcomputer comprising a payout control CPU 371) for controlling the payout means;
The game control microcomputer and the payout control microcomputer perform two-way communication (FIG. 24),
The game control microcomputer is:
When the power supply to the gaming machine is stopped, backup storage means for back-up storing data for specifying the control state including the output state of the payout command signal by the game control microcomputer for a certain period (even when the power supply is stopped) Backup RAM 55) capable of holding the contents,
When the power supply to the gaming machine is restored, the control state including the output state of the payout command signal by the game control microcomputer is restored based on the data stored in the backup storage means (for example, a payout command) When the power supply is interrupted due to a power failure or the like during signal output, control of data or the like indicating the output state of the payout command signal backed up in the work area in the RAM 55 by the game state recovery processing in S81 to S84 Data will be used as control data when the game state is restored, and control state restoration is started based on this control data from the control state such as the signal output state before stopping power supply when the game state is restored) Means (S482, S483);
A payout number storage means (total winning ball number storage buffer in the RAM 55: S219) that stores information that is included in the backup storage means and that can specify the number of prize game media to be paid out based on the establishment of the payout condition;
A payout command signal output means for outputting the payout command signal to the payout control microcomputer based on the payout number stored in the payout number storage means (CPU 56 and output circuit 67 operating in accordance with S232);
Payout memory number subtracting means (CPU 56 operating in accordance with S265) for performing a subtraction process for subtracting the payout number specified by the payout command signal from the payout number stored in the payout number storage means;
The payout control microcomputer includes:
A means for storing data for specifying a control state by the payout control microcomputer, and a payout control storage means (RAM 371a) which does not back up the data when power supply to the gaming machine is stopped;
The prize game medium payout control means (payout control CPU 371 that operates according to the program of S546 and S756) that controls the payout means to execute a payout process for paying out the prize game media of the payout number specified by the payout command signal. When,
A means for outputting a signal to the game control microcomputer, and in response to receiving the payout command signal, a reception confirmation signal (rising edge of the payout BUSY signal) indicating that the payout command signal has been received; A payout processing signal indicating that the payout process is being executed after the reception confirmation signal is output (while the payout BUSY signal is in an ON state) is output by a change in the output state of a single signal (S547). Signal output means (a payout control CPU 371 operating in accordance with S531, S532, an output circuit 373b),
The payout memory number subtraction means includes reception subtraction means (S261 to S265) that performs the subtraction process (performs the subtraction process in S265) when the game control microcomputer receives the reception confirmation signal,
When the game control microcomputer receives the reception confirmation signal, after stopping the output of the payout command signal, the game control microcomputer has a remaining payout number stored in the payout number storage means after the subtraction process. Even so, the payout command signal prohibiting means for prohibiting the output of the next payout command signal until the output of the payout processing signal stops (S241, S242: unless the payout BUSY signal is confirmed to be off in S241). 30 is not executed, and the number-of-payout signal and the prize ball REQ signal are not output).

  According to such a configuration, when the game control microcomputer receives the reception confirmation signal, the game control microcomputer performs a subtraction process for subtracting the stored number of payouts, stops the output of the payout command signal, and then performs a subtraction process. Even when there is a remaining number in the number of payouts stored later, the output of the next payout command signal is prohibited until the output of the payout processing in progress signal stops. When the supply of power to the gaming machine is stopped due to a power failure or the like in the middle of executing the payout control, the game control microcomputer side backs up and stores data specifying the control state including the output state of the payout command signal, and the payout control microcomputer On the side, data specifying the control state is not backed up and stored. Therefore, after that, when the power supply is restored, only the control state that is backed up and stored on the game control microcomputer side is valid, but after the subtraction process, the output of the payout command signal is stopped along with the subtraction process. Since the output of the payout command signal is prohibited until the output of the payout processing signal stops, when the power supply to the gaming machine is stopped due to a power failure or the like during the execution of the payout control, the payout command signal is accompanied with the subtraction process. The state where the output of is stopped is stored as a backup. Thereby, when the power supply is restored, the payout process is not executed again from the beginning. Thereby, it is possible to prevent excessive payout of the prize game medium.

(2) The payout command signal output means, as means for outputting the payout command signal, payout number signal output means (S254) for outputting a payout number signal (payout number signal) for designating the payout number of the game medium; Reception request signal output means (S255) for outputting a reception request signal (prize ball REQ signal) for requesting reception of the payout number signal (FIG. 33),
The payout control microcomputer receives the payout number signal by outputting the reception request signal (S545, S546),
The game control microcomputer stops the output of the payout command signal by stopping the output of the reception request signal in a state where the payout number signal is output (S265a) (FIG. 33).

  According to such a configuration, when the reception request signal is output, the payout control microcomputer receives the payout number signal, and the game control microcomputer stops outputting the reception request signal while the payout number signal is output. As a result, the output of the payout command signal is stopped. Therefore, on the payout control microcomputer side, when checking whether or not the payout command signal is stopped, it is only necessary to check whether or not the reception request signal is output, and the payout number signal for designating the number of payouts of the game medium. Therefore, it is not necessary to confirm in detail what value the value of becomes, so that the processing load of the payout control microcomputer can be reduced.

(3) The payout control microcomputer is:
A payout response signal stop means (S554) for stopping the output of the payout processing signal when the execution of the payout process is completed;
When the output of the payout process signal is stopped by the payout response signal stop means (S554), and the output of the payout number signal by the payout number signal output means does not stop even after a predetermined period has elapsed. (S563Y) further includes payout number signal abnormality notifying means (S564, S759, error display LED 374) for executing control for notifying that an abnormal state has occurred.

  According to such a configuration, after the output of the payout processing signal in response to the payout command signal is stopped based on the end of execution of the payout processing, the output of the payout number signal in the payout command signal is a predetermined period. Since control for notifying that an abnormal state has occurred is executed when the vehicle does not stop even after elapse of time, it can be recognized that such an abnormal state has occurred, and there is an excess of premium game media. Dispensing can be prevented.

  (4) The payout control microcomputer outputs the receipt confirmation signal by the payout response signal output means (S547), and the payout command signal output by the payout number signal output means has passed a predetermined period. When not stopped (S551bY), it further includes payout command signal abnormality notifying means (S552, S759, error display LED 374) for executing control for notifying that an abnormal state has occurred.

  According to such a configuration, after outputting the reception confirmation signal in response to the payout command signal, when the output of the payout command signal does not stop even after a predetermined period of time, it is notified that an abnormal state has occurred. Therefore, it is possible to recognize that such an abnormal state has occurred, and to prevent the premium game medium from being excessively paid out.

(5) A game control connection confirmation signal (5) indicating that the game control microcomputer is connected to the payout control microcomputer when power is supplied to the game machine. A game control connection confirmation signal output means (S82, S12, S33) for outputting a power supply confirmation signal A) to the payout control microcomputer;
The payout control microcomputer prohibits the payout process by the prize game medium payout control means when it has not received the game control connection confirmation signal (returns directly from S544 in the main control communication normal process of FIG. 42). ) Further includes payout processing prohibition means (S544).

  According to such a configuration, when the payout control microcomputer has not received the game control connection confirmation signal, that is, when the game control microcomputer is not connected to the payout control microcomputer, on the game control microcomputer side, The payout amount subtraction process according to the reception of the reception confirmation signal cannot be performed. In such a case, since the payout process by the prize game medium payout control means is prohibited, it is possible to prevent an error from occurring in the stored information of the number of prize game media in the payout number storage means. Excessive payout of game media can be prevented.

  (6) When the output of the payout processing signal does not stop even after a predetermined period has elapsed (S277Y), the game control microcomputer executes control for notifying that an abnormal state has occurred. Medium signal abnormality notification means (S279, S280, S686, 711a, S759, LED 374 for error display, variable display device 9) is further included.

  According to such a configuration, when the game control microcomputer does not stop the output of the payout processing in progress signal even after a predetermined period of time, that is, an abnormal communication state between the game control microcomputer and the payout control microcomputer. In this case, the game control microcomputer side is in a state where the payout amount subtraction process according to the reception of the reception confirmation signal cannot be performed. In such a case, since control for notifying that such an abnormal state has occurred is executed, it is possible to recognize that the abnormal state has occurred, and to prevent the prize game medium from being excessively paid out. Can do.

(7) A payout control connection confirmation signal (7) indicating that the payout control microcomputer is connected to the game control microcomputer when power is supplied to the game machine. It further includes payout control connection confirmation signal output means (S711a, S760) for outputting a power supply confirmation signal B) to the game control microcomputer,
When the game control microcomputer has not received the payout control connection confirmation signal, the game control microcomputer prohibits the payout command signal output means from outputting the payout command signal (the process returns from S250 in the prize ball transmission process of FIG. 30). The payout control connection confirmation signal prohibiting means (S250) is further included (does not proceed to S254, S255).

  According to such a configuration, when the game control microcomputer has not received the payout control connection confirmation signal, that is, when the payout control microcomputer is not connected to the game control microcomputer, on the game control microcomputer side, The payout amount subtraction process according to the reception of the reception confirmation signal cannot be performed. In such a case, since the game control microcomputer side prohibits the output of the payout command signal by the payout command signal output means, the stored information on the number of prize game media in the payout number storage means does not cause an error. Accordingly, excessive payout of the prize game medium can be prevented.

  (8) The game control microcomputer is in a state in which the payout command signal is not output (a state in which the award ball waiting process 1 in FIG. 29 is being executed, which is a state before execution of the award ball transmission process in FIG. 30). When the reception confirmation signal is received (S241Y), the subtraction process by the payout memory number subtraction means is prohibited (returns from S241 to S242 in the award ball waiting process 1 in FIG. Further, subtraction processing prohibiting means (S241) is not included.

  According to such a configuration, when the game control microcomputer receives the reception confirmation signal in a state where the payout command signal is not output, that is, a communication abnormal state between the game control microcomputer and the payout control microcomputer. In this case, the game control microcomputer side is in a state where the payout amount subtraction process according to the reception of the reception confirmation signal cannot be performed. In such a case, since the subtraction process by the payout memory number subtraction means is prohibited on the game control microcomputer side, it is possible to prevent an error from occurring in the stored information on the number of prize game media in the payout number storage means. This makes it possible to prevent excessive payout of premium game media.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following embodiments, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to this, and may be other gaming machines such as a coin gaming machine and a slot machine. A game can be played using a medium, and any game machine can be applied as long as a payout game medium is paid out as a prize based on the fact that a payout condition is established by the game.

  First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as seen from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Below the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3, and a hitting operation handle (operation knob) 5 for firing game balls as game media. ing. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  In the vicinity of the center of the game area 7, a variable display device (hereinafter, variable display) including a plurality of variable display portions (hereinafter referred to as variable display portions) each displaying a symbol as identification information in a variable manner (hereinafter referred to as variable display). A device (referred to as a special symbol display device) 9 is provided. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, since the symbol display area and the start memory display area are provided separately, the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the start memory number may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9. However, a display (special symbol start memory display) for displaying the start memory number may be provided separately from the variable display device 9. Good.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area: special area) is detected by the V winning switch 22, and the winning ball from the opening / closing board 20 is counted. 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a left winning winning port 29, a right dropping winning port 30, a left winning port 33, and a right winning port 39 as a plurality of winning ports, and each of the game balls to the winning ports 29, 30, 33 is provided. Winnings are detected by a left winning winning port switch 29a, a right dropping winning port switch 30a, a left winning port switch 33a, and a right winning port switch 39a, respectively. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED 25 are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit when there is a remaining number of prize balls is provided in the vicinity of the left frame lamp 28b. An LED 52 is provided. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, FIG. 1 also shows a prepaid card unit (hereinafter referred to as a card unit) 50 that is installed adjacent to the pachinko gaming machine 1 and allows a ball lending by inserting a prepaid card.

  The card unit 50 includes a use indicator lamp 151 that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator 153 that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 50, a card A card insertion indicator lamp 154 indicating that a card is inserted into the unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader / writer mechanism provided on the back surface of the card insertion slot 155 A card unit lock 156 is provided for releasing the card unit 50 when checking the card.

  The game ball launched from the hit ball launching device 99 enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol starts variable display (variation) on the variable display device 9 if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When the game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. Change to an advantageous state. It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. 3 and FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the back side of the gaming machine.

  As shown in FIG. 3, on the back side of the gaming machine, game control with a variable display control unit 49 including an effect control board 80 on which an effect control means for controlling the variable display device 9 is mounted, a game control microcomputer and the like are mounted. A substrate (main substrate) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The production control means includes various decoration LEDs provided on the game board 6, the normal symbol start memory display 41, the decoration lamp 25, the top frame lamp 28a provided on the frame side, the left frame lamp 28b, and the right frame. The lamp 28c is turned on and sound generation from the speaker 27 is controlled.

  The effect control means is realized by one effect control microcomputer mounted on the effect control board 80, but various decoration LEDs, normal symbol start memory display 41, and decoration lamp 25 provided on the game board 6. The drive circuit for driving the top frame lamp 28a, the left frame lamp 28b and the right frame lamp 28c provided on the frame side is mounted on a lamp driver board electrically connected to the effect control board 80. Yes. The drive circuit for driving the speaker 27 is mounted on an audio output board that is electrically connected to the effect control board 80.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Although most of the power supply substrate 910 overlaps with the main substrate 31, there is an exposed portion that is exposed so as to be visible from the outside without overlapping the main substrate 31. In this exposed portion, power supply to each electrical component control board (main board 31, production control board 80, payout control board 37) of the gaming machine 1 and each electrical component provided in the gaming machine is executed or cut off. A power switch (not shown here and shown as a power switch 914 in FIG. 10 or the like) as a power supply permitting means for storing, a storage content holding means included in the main board 31 (for example, the contents when the power supply is stopped) A clear switch (not shown here and shown as a clear switch 921 in FIGS. 7, 11, etc.) is provided as an operation means for clearing backup data stored in the backup RAM). .

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. In addition, an information terminal board (information output board) 34 provided with terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rail 39, and as shown in FIG. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 is stopped. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion (storage tank 38). In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  A lot of game balls as prizes based on winning prizes (prize balls as prize game media) and ball lending requests are paid out, and the hitting ball supply tray 3 becomes full, and the game balls finally reach the contact port 45. When the game ball is later paid out, the game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. When the game ball is further paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device 97 is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device 99 is also stopped.

  As shown in FIG. 4, on the side of the ball payout device 97, a ball removal passage 191 is formed from the curve rod 186 to the discharge port 192 at the lower part of the gaming machine. A ball removal lever 193 is provided above the ball removal passage 191. When the ball removal lever 193 is operated by a game clerk or the like, a game ball passage from the guide rail 39 to the ball removal passage 191 is formed, and the storage tank 38 is provided. The game balls stored inside are discharged from the discharge port 192 to the outside of the gaming machine.

  FIG. 5 is a front view (FIG. 5 (A)) and a cross-sectional view (FIG. 5 (B)) showing the ball dispensing device 97 covered with the dispensing case 40A. As shown in FIG. 4, the ball payout device 97 is fixed to the lower part of the passage body 184 installed between the ball break switch 187 and the ball payout device 97. The passage body 184 includes ball passages 188a and 188b for flowing down two rows of game balls whose flow direction has been changed to the left and right directions by the curve rod 186. A ball break switch 187 is installed on the upstream side of the ball passages 188a and 188b. Actually, a ball break switch is installed in each of the ball passages 188a and 188b. The ball break switch 187 detects the presence or absence of a game ball in the ball passages 188a and 188b. When the ball break switch 187 stops detecting a game ball, the payout motor (not shown in FIG. 5) in the ball payout device 97 is used. )) Is stopped and the payout of the game ball is made immobile.

  The ball break switch 187 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball passages 188a and 188b.

  In the ball payout device 97, a payout motor (not shown) using a stepping motor rotates, for example, a cam, thereby paying out one winning ball or one game ball based on a ball lending request. Further, below the ball payout device 97, for example, a payout count switch 301 using a proximity switch is provided. Each time one game ball falls from the ball payout device 97, the payout count switch 301 is turned on. That is, the payout count switch 301 detects a game ball actually paid out from the ball payout device 97. Therefore, the payout control means can count the number of game balls actually paid out by the detection signal of the payout count switch 301.

  FIG. 6 is an exploded perspective view showing a configuration example of the ball dispensing device 97. In this example, a ball payout device 97 is formed inside three cases 140, 141, 142 as the payout case 40A. The upper portions of the cases 140 and 141 are provided with holes 170 and 171 communicating with the ball passages 188 a and 188 b below the ball break switch 187, and the game balls flow into the ball dispensing device 97 from the holes 170 and 171.

  The ball payout device 97 includes a payout motor (for example, a stepping motor) 289 as a drive source. The rotational force of the payout motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the payout motor 289 and further transmitted to the gear 291 that meshes with the gear 290. A cam 292 having a ball mounting portion is fitted to the central axis of the gear 291. The game balls that have flowed from the holes 170 and 171 are dropped one by one into the ball passage 293 below the cam 292 by the ball mounting portion of the cam 292.

  Further, the ball dispensing device 97 is provided with a dispensing motor position sensor 295 including a light emitting element (LED) and a light receiving element. The payout motor position sensor 295 is a sensor for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting.

  In this embodiment, the ball payout device 97 is configured to perform both prize ball payout and ball lending. In other words, this is a dual-use type ball payout device that pays out both premium game media and rental game media. Note that a ball payout device for paying out a prize ball and a ball payout device for lending a ball may be provided separately. When separately provided, the payout means is constituted by a ball payout device for paying out a prize ball and a ball payout device for lending a ball. Furthermore, for example, it may be configured to change the direction of rotation of the cam or sprocket so as to separate the winning ball payout and the ball lending. The present invention can be applied to any structure other than the structure).

  FIG. 7 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 7 also shows the payout control board 37 and the effect control board 80. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, a left dropping winning port switch 29a, and a right dropping winning port switch. 30a, a left prize opening switch 33a, a right prize opening switch 39a, and a switch circuit 58 for supplying signals from the clear switch 921 to the basic circuit 53, a solenoid 16 for opening and closing the variable winning ball apparatus 15, and a solenoid for opening and closing the opening / closing plate 20. 21 and a solenoid circuit 59 for driving a solenoid 21A for switching a route in the special winning opening in accordance with a command from the basic circuit 53 is mounted.

  The gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the left dropping winning port switch 29a, the right dropping winning port switch 30a, the left winning port switch 33a, the right winning port switch 39a, etc. What is called a sensor may be used. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. Each of the start opening switch 14a, the count switch 23, the left dropping winning opening switch 29a, the right dropping winning opening switch 30a, the left winning opening switch 33a, and the right winning opening switch 39a that performs winning detection is also a winning detection means. Note that the winning detection means may be configured to collectively detect the respective game balls that have won separately a plurality of winning openings. Further, even if a passing gate such as the gate switch 32a is used, if a prize ball is to be paid out, a game ball entering the passing gate becomes a win, and a switch ( For example, the gate switch 32a) serves as a winning detection means. Furthermore, in this embodiment, a game ball won in the V winning area is detected by the V winning switch 22 and also detected by the count switch 23, but may be detected only by the V winning switch 22. When a game ball won in the V prize area is detected only by the V prize switch 22, the number of game balls won in the big prize opening is the sum of the number detected by the V prize switch 22 and the number detected by the count switch 23. become.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as storage means (variation data storage means for storing fluctuation data) used as a work memory, a CPU 56 for performing control operations according to the program, and an I / O. Port part 57 is included. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built in, and the ROM 54 and the I / O port unit 57 may be externally attached or built in. Since CPU 56 executes control according to a program stored in ROM 54, what CPU 56 executes (or performs processing) hereinafter means that CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on substrates other than the main substrate 31. In this manner, the CPU 56 constitutes a game control microcomputer as game control means. When the ROM 54 and RAM 55 are not built in the CPU 56, the ROM 54, RAM 55, and basic circuit 53 including the CPU 56 constitute a game control microcomputer as game control means.

  A RAM 55 (may be a CPU built-in RAM) 55 is a backup RAM that is partially or entirely backed up by a backup power source created in the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 are stored for a predetermined period. In particular, it indicates at least the data that specifies the control state of game control, such as data corresponding to the game state, that is, the control state of the game control microcomputer, the data indicating the number of unpaid prize balls, and the output state of the output signal related to payout control. Data specifying the control state of the payout control such as data is stored in the backup RAM. The data specifying the control state is data necessary for restoring the control state of the game control before the occurrence of a power failure or the like based on the data when the power state is restored after a power failure or the like occurs. In addition, the data for specifying the control state of the payout control includes the output state of various output signals such as the payout command signal based on the data when recovered after a power failure or the like, and the control state of the payout control This data is necessary to restore the system before a power outage occurs.

  The hitting ball launching device 99 that hits and launches a game ball includes a launch motor 94 controlled by a circuit on the payout control board 37, and launches the game ball toward the game area 7 as the launch motor 94 rotates. A drive signal for driving the firing motor 94 is transmitted to the firing motor 94 via the touch sensor substrate 91. The touch sensor detects that the player is touching the operation knob (hit ball handle) 5, and a signal from the touch sensor is transmitted to the payout control board 37 via the touch sensor board 91. The circuit on the payout control board 37 stops the driving of the firing motor 94 when the signal from the touch sensor indicates an off state.

  In this embodiment, the effect control means mounted on the effect control board 80 controls the display of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board 6, and the frame side Display control of the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. The effect control means mounted on the effect control board 80 also performs display control of the variable display device 9 that variably displays the special symbol and the normal symbol display 10 that variably displays the normal symbol.

  FIG. 8 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 8, a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and includes at least a RAM 371a. Further, unlike the RAM 55 on the main board 31, the RAM 371a is not backed up. The payout control CPU 371, the RAM 371a, the ROM (not shown) storing the payout control program, the I / O port, and the like constitute a payout control microcomputer as payout control means. When the ROM and RAM 371a are not built in the CPU 371, a payout control microcomputer as payout control means is configured by a circuit including the ROM and RAM 371a.

  Detection signals from the full tank switch 48 and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. Further, detection signals from the ball break switch 187 and the payout motor position sensor 295 are input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout control CPU 371 of the payout control board 37 performs the ball payout process when the detection signal from the ball break switch 187 indicates a ball full state or when the detection signal from the full tank switch 48 indicates a full tank state. Stop. Further, when the detection signal from the full tank switch 48 indicates a full state, the ball firing from the hitting ball launching device 99 is stopped.

  When there is a win, the output circuit 67 of the main board 31 receives a prize ball REQ signal (prize ball request signal) and a number of prize balls to be paid out as a payout command signal (payout control signal). Is output. The payout number signal is composed of 4-bit data (binary 4-digit data) and is output by four signal lines. The payout number signal is input to the I / O port 372e via the input circuit 373A. When a prize ball REQ signal and a payout number signal are input via the I / O port 372e, the payout control CPU 371 controls to drive the ball payout device 97 to pay out the number of game balls indicated by the payout number signal. . From the main board 31 to the payout control board 37 is a signal indicating that the main board 31 is connected to the power supply, and the main board 31 (game control microcomputer) is connected to the payout control board 37 (payout control microcomputer). A power supply confirmation signal (connection confirmation signal) A, which is a signal indicating connection, is transmitted. The power confirmation signal A is output to the payout control board 37 via the output circuit 67. Further, a signal indicating that the payout control board 37 is connected to a power source is sent from the payout control board 37 to the main board 31, and the payout control board 37 (payout control microcomputer) is connected to the main board 31 (game control microcomputer). A power supply confirmation signal (connection confirmation signal) B, which is a signal indicating connection to a computer, is transmitted. The power confirmation signal B is output to the main board 31 through the output circuit 373b. The power confirmation signal A is output when the power of the pachinko gaming machine 1 is turned on and power is supplied to the main board 31, and then the power of the pachinko gaming machine 1 is turned off and the power to the main board 31 is transmitted. When the supply is cut off, the output is stopped. The power confirmation signal B is output when the power of the pachinko gaming machine 1 is turned on and power is supplied to the payout control board 37, and then the power of the pachinko gaming machine 1 is cut off and the payout control board 37 is turned off. When the power supply to is cut off, the output is stopped. The prize ball REQ signal and the payout number signal correspond to a payout command signal for designating the payout number.

  When the payout control microcomputer receives a payout command signal, it sends a command accepting signal to the main board 31. The command acceptance signal is transmitted to the main board 31 via the output port 372b of the payout control board 37 and the output circuit 373B. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port 57. Further, when the payout control microcomputer is executing a prize ball payout process, the payout control microcomputer receives a payout BUSY signal (award ball payout) indicating that the payout process is in progress via the output port 372b and the output circuit 373B. Medium signal). In this embodiment, when the payout BUSY signal is turned on, the command acceptance signal is transmitted.

  The payout control CPU 371 receives a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of lent balls via the output port 372b as a terminal board (frame external terminal board and board external terminal board). Output) 160. Although a driver circuit is installed outside the output port 372b, the description is omitted in FIG. In addition, door opening switches 161A and 161B are connected to the terminal board 160 (frame external terminal board).

  Further, the payout control CPU 371 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing lighting / extinguishing is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG. A drive signal from the payout control board 37 to the firing motor 94 is transmitted to the firing motor 94 via the output port 372 a and the touch sensor board 91.

  The card unit 50 is equipped with a card unit control microcomputer. In addition, the card unit 50 is provided with a usable display lamp 151, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  Each transmission path of connection signal (VL signal), unit operation signal (BRDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (PRDY signal) A coupler (an element that once converts an electrical signal into light and then converts it back into an electrical signal) is provided. That is, each of these signals is transmitted between the card unit 50 and the payout control board 37 via the photocoupler. By transmitting a signal through the photocoupler, it is possible to prevent an abnormal level signal from being transmitted when one of the card unit 50 and the payout control board 37 fails. Among these signals, the connection signal (VL signal) transmission path is a power line (photocoupler power supply for other signal transmission paths) as compared to other signal transmission paths having a simple signal line function. Therefore, it is necessary to stabilize the power supply, and a capacitor for stabilizing the power supply is provided in addition to the photocoupler.

  In this embodiment, a photocoupler is used for each transmission path of a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal (PRDY signal). It is provided (mounted) on the interface board 66. On the other hand, for the transmission path of the connection signal (VL signal), the above-described photocoupler and capacitor are provided on (mounted on) the dispensing control board 37 instead of on the interface board 66. Thereby, on the interface board 66, the photocoupler is provided, but the capacitor is not provided. Capacitors are often provided on regular boards or on illegal boards as illegal electronic components when various illegal acts are performed. On the other hand, in the case of the present embodiment, since no capacitor is provided on the interface board 66, an unauthorized electronic component is attached on the interface board 66, and the interface board 66 is replaced with an unauthorized board. When a fraudulent act such as doing is performed, it is possible to easily determine whether or not the fraudulent act has been performed by visually checking whether or not there is a capacitor on the substrate.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control CPU 371 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, a prize ball payout control is executed when a payout command signal is received from the game control microcomputer. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  The power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in the 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  FIG. 9 is a block diagram illustrating a circuit configuration example of the effect control board 80, the lamp driver board 35, and the audio output board 70. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a ROM (not shown), and the input driver 102 and the input port according to a strobe signal (effect control INT signal) from the main board 31. An effect control command is received via 103. Further, the production control CPU 101 performs display control of the variable display device 9 using the LCD via the output port 104 and the LCD drive circuit 106 based on the production control command, and controls the output port 104 and the lamp drive circuit 107. Display control of the normal symbol display 10 is performed.

  Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104 and the output driver 110. A bus (including an address bus, a data bus, and a control signal line such as a write / read signal) that is input / output to / from the effect control CPU 101 is extended to the lamp driver board 35 via the bus driver 105.

  In the lamp driver board 35, a bus that is input to and output from the effect control CPU 101 is connected to the output port 352 and the expansion port 353 via the bus receiver 351. A signal for driving each lamp output from the output port 352 is amplified by a lamp driver 354 and is supplied to each lamp 28a, 28b, 28c, 25 (top frame lamp 28a, left frame lamp 28b, right frame lamp 28, decorative lamp 25, etc. ). In addition, a signal for driving each LED output from the output port 352 is amplified by the LED driving circuit 355 and supplied to each LED 41 (normal symbol start memory display 41 or the like). A signal for driving the effect driving means 61 such as a movable member for effect is amplified by the drive circuit 356 and supplied to the effect driving means 61. However, in the case of this embodiment, the drive means 61 for production is not actually provided, and a drive circuit 356 is provided for the purpose of giving the lamp driver board 35 versatility as will be described later. ing.

  In this embodiment, the lamps / LEDs 28 a, 28 b, 28 c, 25, 41 and the effect driving means 61 provided in the gaming machine are provided by effect control means including the effect CPU 101 mounted on the effect control board 80. Be controlled. Further, data for controlling the variable display device 9, the normal symbol display 10, the lamp / LED and the like are stored in the ROM. The effect CPU 101 controls the variable display device 9, the normal symbol display 10, the lamp / LED, and the like based on the data stored in the ROM. Then, the lamp / LED and the driving means for presentation are driven via the output port 352 and each drive circuit mounted on the lamp driver board 35. Therefore, when changing the model, if the production control board 80 is replaced with a new model, the model change can be realized without replacing the lamp driver board 35.

  The effect control board 80, the lamp driver board 35, and the audio output board 70 are independent boards, but are installed in a single box on the back of the gaming machine, for example. In addition, the expansion port 353 is installed in consideration of the case where the number of lamps, LEDs, and the like is increased when changing the model, but may not be installed. The drive circuit 356 may not be provided in the case where there is no production drive means such as a production movable member. However, when changing the model, considering the case where a production movable member or the like is installed. In addition, it is preferable to provide a movable member for production.

  In the audio output board 70, the sound number data from the effect control board 80 is input to the voice synthesis IC 703 by a digital signal processor, for example, via the input driver 702. The voice synthesis IC 703 reads data corresponding to the sound number data from the voice data ROM 704, generates voice and sound effects corresponding to the read data, and outputs them to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27.

  The data corresponding to the sound number data stored in the sound data ROM 704 is a collection of data indicating the sound effect or sound output mode in a predetermined time period (for example, a special symbol fluctuation period) in time series. When the voice synthesis IC 703 receives the sound number data, it performs sound output control according to the corresponding data in the voice data ROM 704. The sound output control according to the corresponding data is continued until the next sound number data is input. When the next sound number data is input, the speech synthesis IC 703 performs sound output control according to the data in the sound data ROM 704 corresponding to the newly input sound number data.

  In this embodiment, the sound and sound output from the speaker 27 are controlled by the effect control means including the effect control CPU 101, but the effect control means outputs the sound number data to the sound output board 70. . In the audio output board 70, the audio data ROM 704 stores a large number of data for realizing sounds and sound effects that may appear as the game progresses, and these data are associated with the sound number data. . Therefore, the production control means can realize sound output control only by outputting the sound number data. Note that the sound number data is, for example, 1-byte data, and is transferred to the audio output board 70 via a serial signal line or a parallel signal line.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagrams of FIGS. FIG. 10 is a block diagram showing a DC voltage generating portion in the power supply substrate 910. As shown in FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), AC power (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply substrate 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911. The transformer 911 may be provided outside the external power supply board 910 instead of on the power supply board 910.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, and the effect control board 80), and generates a voltage used by each electric component control board and mechanism component in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 914. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 10), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 11, AC24V output from the transformer 911 is supplied to the connector 922A as it is. Further, VLP is supplied to the connector 922B via a fuse F01 as an overcurrent prevention means for preventing supply of overcurrent. A series body of an LED (LD01) and a resistor (R01) is connected between the connector 922B side of the fuse F01 and the ground (ground potential).

  VSL is supplied to the connector 922A via the fuse F02. A series body of an LED (LD02) and a resistor (R02) is connected between the connector 922A side of the fuse F02 and the ground. VSL is supplied to the connector 922B through the fuse F03. A series body of an LED (LD03) and a resistor (R03) is connected between the connector 922B side of the fuse F03 and the ground. Further, VSL is supplied to the connector 922C through the fuse F04. A series body of an LED (LD04) and a resistor (R04) is connected between the connector 922C side of the fuse F04 and the ground.

  VDD is supplied to the connector 922A through the fuse F05. A series body of an LED (LD05) and a resistor (R05) is connected between the connector 922A side of the fuse F05 and the ground. Further, VDD is supplied to the connector 922B via the fuse F06. A series body of an LED (LD06) and a resistor (R06) is connected between the connector 922B side of the fuse F06 and the ground. Further, VDD is supplied to the connector 922C through the fuse F07. A series body of an LED (LD07) and a resistor (R07) is connected between the connector 922C side of the fuse F07 and the ground.

  VCC is supplied to connector 922A through fuse F08. A series body of an LED (LD08) and a resistor (R08) is connected between the connector 922A side of the fuse F08 and the ground. In addition, Vcc is supplied to the connector 922B through the fuse F09. A series body of an LED (LD09) and a resistor (R09) is connected between the connector 922B side of the fuse F09 and the ground. Further, Vcc is supplied to the connector 922C through the fuse F10. A series body of an LED (LD10) and a resistor (R10) is connected between the connector 922C side of the fuse F10 and the ground.

  The cable connected to the connector 922A is connected to the payout control board 37. The cable connected to the connector 922B is connected to the effect control board 80. The cable connected to the connector 922C is connected to the main board 31. Therefore, VBB is also supplied to the connector 922C.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a clear switch signal at a low level (ON state) is output and transmitted to the main board 31 via the connector 922C. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided other than the power supply board 910 in the gaming machine.

  Further, the fuses F01 to F10 are not of a detachable (replaceable) type but of a type fixed to the power supply substrate 910. That is, it is installed on the board (in this example, the power board 910) so as not to be exchanged. When the fuses F01 to F10 are of a replaceable type, the fuse is replaced when a malfunction such as a short circuit failure occurs in the power supply board 910 or the electrical component control board, and the cause of the true malfunction is unknown. There is a risk that the gaming machine will be returned to the operating state. In that case, the defect is expected to recur soon. However, if the fuses F01 to F10 are of a non-replaceable type, when a problem occurs in the power supply board 910, the fuse F01 to F10 are guided to an action of searching for a true cause of the problem.

  When the power supply board 910 is provided with LEDs (LD01 to LD10) as shown in FIG. 11, unless a problem such as a short circuit failure occurs in the power supply board 910 and each electrical component control board, Each LED (LD01 to LD10) is in a lighting state. In other words, if each LED (LD01 to LD10) is in a lighting state, it can be seen that there is no problem such as a short circuit failure in the power supply board 910 and each electric component control board.

  FIG. 12 is a block diagram showing the CPU 56, the reset circuit, and the power supply monitoring circuit on the main board 31. As shown in FIG. As shown in FIG. 12, the power-off signal from the power supply monitoring circuit (power supply monitoring means) 920, that is, the detection signal from the power supply monitoring means is input to the CPU 56 via the inverting circuit 943 and the input port 572. Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 572.

  According to such a configuration, the central processing unit (CPU 56) of the game control microcomputer can be prevented from entering a multiple interrupt state. In other words, for example, when a detection signal from the power supply monitoring means is input to the non-maskable interrupt terminal of the central processing unit, the central processing unit that has already been interrupted is repeatedly turned on and off repeatedly, for example. In addition, a non-maskable interrupt signal is input to enter a multiple interrupt state, and the central processing unit enters a runaway state, but the detection signal from the power monitoring means is input to the input port and the detection signal is input to the input port. When the central processing unit determines that the power supply is stopped, it can prevent the central processing unit from entering the multiple interrupt state even if the power is turned on and off many times.

  As a result, it is possible to prevent the central processing unit from running away and being initialized, and it is possible to prevent the inconvenience that the specific gaming state (big hit state) is likely to be targeted by the player when the central processing unit is initialized. More specifically, when the central processing unit is initialized, the player starts to count up the random counter for hit / decision determination from the initial value (for example, “0”). The starting point of counting up from "0") can be grasped, and the starting winning signal is generated by starting and winning the hit ball in consideration of the time until the value corresponding to the big hit is counted up from there Thus, the count value associated with the instant start winning when the value corresponding to the big hit is counted up is extracted. However, according to the present invention, since the central processing unit can be prevented from being interrupted and initialization of the central processing unit can be avoided, such inconvenience can be prevented.

  Since the power supply monitoring circuit 920 is mounted on the main board 31, power supply monitoring means can be installed near the CPU 56 to which the power supply cut-off signal is input, and the game control microcomputer can reliably recognize the stoppage of power supply. Will be able to.

  The power monitoring circuit 920 includes a power monitoring IC 902. The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output because power supply is stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used.

  The predetermined value for the power monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while. In addition, since the power monitoring IC 902 is higher than the voltage for driving circuit elements such as the CPU 56 (+5 V in this example), the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop.

  When the voltage of the + 12V power supply decreases, the switch output starts to turn on. However, if the power supply voltage is monitored by monitoring the + 30V power supply voltage that drops earlier than + 12V, and the power supply is stopped, the power is output before the switch output turns on. It is possible to enter a supply recovery waiting state and not detect the switch output.

  The reset circuit 65 includes a reset IC 651. When the power is turned on, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to a high level when the predetermined time has elapsed. That is, the reset signal (system reset signal) is raised to a high level to make the CPU 56 operable. The reset signal is input to the reset terminal of the CPU 56 via the inverting circuits 942 and 941.

  In addition, the reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit 920, and the voltage value is a predetermined value (than the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal) When it is less than (low value), the output is set to low level. Therefore, the CPU 56 performs a predetermined power supply stop process in response to the power-off signal from the power supply monitoring circuit 920, and then the system is reset. That is, the operation is completely stopped. Accordingly, the reset circuit 65 corresponds to second power supply monitoring means for outputting the detection signal at a timing later than the timing at which the power supply monitoring means outputs the detection signal. In this example, the state in which the second power supply monitoring unit outputs the detection signal is a state in which the reset signal is set to a low level.

  The CPU 56 used in this embodiment includes a non-maskable interrupt terminal (NMI terminal) used to generate a non-maskable interrupt (NMI), and an interrupt (external interrupt; mask) from the outside of the CPU 56. An interrupt terminal (INT terminal) used to generate a possible interrupt). When the signal input to the NMI terminal falls to a low level, a non-maskable interrupt occurs. That is, the program counter of the CPU 56 is changed to the start address of the non-maskable interrupt process, and the CPU 56 enters a state of executing the instruction set at the start address of the non-maskable interrupt process.

  Further, when a signal input to the INT terminal falls to a low level, an external interrupt is generated. That is, the program counter of the CPU 56 is changed to the start address of the external interrupt process, and the CPU 56 enters a state of executing the instruction set at the start address of the external interrupt process.

  In this embodiment, non-maskable interrupts and external interrupts are not used. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors. Therefore, the input levels of the NMI terminal and the INT terminal are always high, and there is a possibility that the input level of the NMI terminal and the INT terminal falls due to noise or the like, and an interrupt is generated, as compared with the case where the terminal is open. To reduce.

  13 and 14 are explanatory diagrams showing an example of output port assignment in the game control microcomputer. As shown in FIG. 13, the output port 0 has a payout command signal (payout number signal, prize ball REQ signal) transmitted to the payout control board 37, a power supply confirmation signal A, and an effect control transmitted to the effect control board 80. This is an output port of an effect control INT signal (strobe signal) for a command. Further, 8-bit data of the effect control command transmitted to the effect control board 80 is output from the output port 1. The effect control INT signal is a signal for instructing the effect control means to take in the 8-bit data of the effect control command.

  Further, from the output port 2, a solenoid (large winning port door solenoid) 21 for opening and closing the opening / closing plate 2 of the large winning port, a solenoid (large winning port guide plate solenoid) 21A for switching the route in the large winning port, and a variable A drive signal is output to a solenoid (normal electric accessory solenoid) 16 for opening and closing the winning ball apparatus 15. Then, various information output signals from the output port 3 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 15 is an explanatory diagram showing an example of bit assignment of input ports in the game control microcomputer. As shown in FIG. 15, bits 0 to 7 of the input port 0 have a left drop winning opening switch 29a, a right drop winning opening switch 30a, a left winning opening switch 33a, a right winning opening switch 39a, and a start opening switch 14a, respectively. Detection signals of the count switch 23, the V winning switch 22, and the gate switch 32a are input. In addition, bits 0 to 3 of the input port 1 respectively include a power-off signal from the power supply monitoring circuit 920, a payout BUSY signal from the payout control board 37, a detection signal of the clear switch 921 from the power supply board 910, and a power supply confirmation signal. B is entered. The detection signal from each switch is logically inverted in the switch circuit 58.

  Next, the operation of the gaming machine will be described. FIG. 16 is a flowchart showing a main process executed by the game control microcomputer (peripheral circuits such as the CPU 56 and ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 executes a security check process that is a process for confirming whether or not the contents of the program are valid, and then step S1. Subsequent main processing is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set in an accessible state (step S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that made the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S15). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. Note that in the input port 1, the clear switch signal is in the high level. Further, for example, the game clerk can easily execute the initialization process by starting the power supply to the gaming machine (for example, turning on the power switch 914) while turning the clear switch 921 on. That is, the RAM can be cleared.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply stops, processing for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such a protection process has not been performed, the CPU 56 executes an initialization process.

  Whether there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop process. For example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state).

  If it is determined that there is a backup, the CPU 56 performs data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the processes of steps S10 to S15) executed when the power is turned on, not when the power supply is stopped. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control microcomputer and the control state of the electric component control means such as the display control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S81), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S82). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processes in steps S81 and S82, the saved contents of the work area that should not be initialized remain. The portion that should not be initialized is, for example, a portion in which data (such as a special symbol process flag) indicating a gaming state before stopping power supply or data indicating the number of unpaid prize balls is set. As a result, the data backed up in the work area in the RAM 55 is used as control data when the gaming state is restored. Based on this control data, control can be performed from the state before the power supply is stopped when the gaming state is restored. Be started.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S83), and power is supplied to the sub-boards (the payout control board 37 and the effect control board 80) according to the contents. Control is performed so that a control command indicating the recovery is transmitted (step S84). Then, the process proceeds to step S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S11). It should be noted that predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is without initializing the entire area of the RAM. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by unauthorized means. Therefore, it is difficult to aim at the timing at which the count value of the counter matches the jackpot determination value. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12). By the processing in steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball break An initial value is set to a flag for selectively performing processing according to the control state, such as a flag or a payout stop flag.

  In addition, the CPU 56 sets the initial address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and issues an initialization command for initializing the sub board according to the contents of the sub board. The process to transmit to is executed (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  In step S15, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated, for example, every 2 ms. That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the display random number update process (step S17) and the initial value random number update process (step S18) are repeatedly executed in the main process. The CPU 56 disables the interrupt when the display random number update process and the initial value random number update process are executed (step S16), and interrupts when the display random number update process and the initial value random number update process are finished. The permission state is set (step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. It is. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). In a game control process described later, when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set even when the display random number update process and the initial value random number update process are performed by the timer interrupt process described later. This is to avoid conflict with the processing in the timer interrupt processing. That is, if a timer interrupt is generated during the processing of steps S17 and S18 and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt disabled state is set during the processes of steps S17 and S18.

  When the timer interruption occurs, the CPU 56 executes the game control process of steps S20 to S33 shown in FIG. In the game control process, the CPU 56 first executes a power-off detection process for detecting whether or not a power-off signal has been output (whether the power-off signal has been turned on) (step S20). Next, through the switch circuit 58, switches such as the gate switch 32a, the start port switch 14a, the count switch 23 and the left drop winning port switch 29a, the right drop winning port switch 30a, the left winning port switch 33a, the right winning port switch 39a, etc. Are detected and their states are determined (switching process: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S22). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S23 and S24).

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the special symbol in a predetermined area of the RAM 55 and sending the effect control command (special symbol command control process: step S27). In addition, a process for setting the effect control command for the normal symbol in a predetermined area of the RAM 55 and sending the effect control command is performed (normal symbol command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes a winning ball process for setting the number of winning balls based on detection signals from the left dropping winning opening switch 29a, the right dropping winning opening switch 30a, the left winning opening switch 33a, and the right winning opening switch 39a ( Step S30). Specifically, a payout command signal such as a payout number signal indicating the number of prize balls is output to the payout control board 37 in response to winning detection based on the fact that each of the winning opening switches 29a, 30a, 33a, 39a is turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in accordance with a payout command signal such as a payout number signal indicating the number of winning balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start winning memory | storage number (step S31). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S32). A RAM area (output port buffer) corresponding to the output state of the output port is provided, and the CPU 56 outputs the contents of the RAM area to the output port (step S33: output processing). Note that the contents of the output port buffer are updated by the processes of steps S25 to S30 and S31. Thereafter, the interrupt permission state is set (step S34), and the process is terminated.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 2 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  18 and 19 are flowcharts illustrating an example of the power-off detection process in step S20. In the power-off detection process, the CPU 56 first checks whether or not a power-off signal is output (whether it is in an on state) (step S450). If it is in the on state, the power supply stop process after step S452 is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process for saving the game state is executed.

  In the power supply stop process, the CPU 56 stores the backup specified value (“55H” in this example) in the backup flag (step S452). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S453 to S461). That is, first, the clear data (00) is set in the checksum data area (step S453), and the checksum calculation start address is set in the pointer (step S454). Also, the number of checksum calculations is set (step S455).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S456). The calculation result is stored in the checksum data area (step S457), the pointer value is incremented by 1 (step S458), and the value of the checksum calculation count is decremented by 1 (step S459). Then, the processes in steps S456 to S459 are repeated until the value of the checksum calculation count becomes 0 (step S460).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S461). Then, the inverted data is stored in the checksum data area (step S462). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S482). When the power-off signal is turned off, the execution address at power-on (address in step S1) is set as a return address and a return command is executed (step S483).

  When the power supply is stopped by the above processing, the power supply stop processing in steps S452 to S481 is executed, and data indicating that the power supply stop processing is executed (specified value with backup and checksum) ) Is stored in the backup RAM, RAM access is disabled, the output port is cleared, and the timer interrupt for executing the game control process is disabled.

  If the power-off signal is turned off, the process returns to step S1. In this case, since the data indicating that the power supply stop process has been executed is set, the game state restoration process in steps S81 to S84 is executed, and the control data that has been backed up in the RAM 55 is restored to the game state. Based on this control data, control is executed from a control state such as a signal output state before stopping power supply when the gaming state is restored. Therefore, when the detection signal from the power supply monitoring unit is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The power supply confirmation signal A transmitted to the payout control board 37 is set to the off state by the process of clearing the output port. In the setting of the work area in steps S82 and S12, the contents of the output port buffer corresponding to the power supply confirmation signal A are set to values corresponding to the ON state of the power supply confirmation signal A. Then, when the output process of step S33 is executed, the contents of the output port buffer are output to the output port, so that the power supply confirmation signal A to the payout control board 37 is turned on. Therefore, the power supply confirmation signal A is output (turned on) when the main board 31 rises. Note that the power supply confirmation signal A is also output when the power supply is recovered from an instantaneous power interruption or the like.

  Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. A switch timer is used to measure the predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates an ON state. As shown in FIG. 20, the switch timer is provided by the number n of detection signals. In the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports.

  FIG. 21 is a flowchart showing a processing example of the switch processing in step S21 in the game control processing. In the switch process, the CPU 56 first inputs data input to the input port 0 (step S101). Next, “8” is set as the processing number (step S102), and the address of the switch timer for the left winning mouth switch 33a is set in the pointer (step S103). Then, a switch check processing subroutine is called (step S104).

  FIG. 22 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets port input data, in this case, input data from the input port 0, as a “comparison value” (step S121). Further, clear data (00) is set (step S122). Then, the switch timer pointed to by the pointer (switch timer address is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S124). Data of input port 0 is set as the comparison value. In this case, the detection signal of the left winning mouth switch 33a is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S125), that is, if the detection signal of the left prize opening switch 33a is on, the switch timer value is incremented by 1 (step S127). If the value after addition is not 0, the addition value is returned to the switch timer (steps S128 and S129). When the value after addition becomes 0, the addition value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased further.

  If the value of the carry flag is “0”, that is, if the detection signal of the left prize opening switch 33a is in the OFF state, clear data is set in the switch timer (step S126). That is, if the switch is off, the value of the switch timer returns to zero.

  Thereafter, the CPU 56 adds 1 to the pointer (switch timer address) (step S130) and subtracts 1 from the number of processes (step S131). If the number of processes is not 0, the process returns to step S122. Then, the processes of steps S122 to S132 are repeated.

  The processes in steps S122 to S132 are repeated for the number of processes, that is, eight times, and during that time, the detection signal of the switch input to the 8 bits of the input port 0 is sequentially checked to determine whether it is on or off. If it is ON, the value of the corresponding switch timer is incremented by one.

  In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

  Next, a payout control signal transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 23 is an explanatory diagram showing an example of the contents of a control signal output from the game control microcomputer to the payout control microcomputer and a control signal input to the game control microcomputer from the payout control microcomputer. In this embodiment, a plurality of types of control signals are exchanged between the main board 31 and the payout control board 37 in order to perform various controls relating to the payout control and the like. As shown in FIG. 23, the power supply confirmation signal A is output when the main board 31 rises, and is a signal for notifying the payout control board 37 that the main board 31 has risen (connection confirmation signal for the main board 31). ). Further, as described above, the power supply confirmation signal A is turned off when the power supply is detected, and is also used as a signal for notifying the payout control board 37 that the main board 31 has detected the power supply interruption. . The power supply confirmation signal B is output when the dispensing control board 37 rises, and is a signal for notifying the main board 31 that the dispensing control board 37 has risen (connection confirmation signal for the dispensing control board 37). The power confirmation signal B is also a signal for notifying that the main board 31 is turned off when the power is turned off and that the main board 31 is turned off.

  The prize ball REQ signal becomes a low level (output state = on state) at the time of a prize ball payout request, and becomes a high level (stop state = off state) at the end of the payout request (that is, a trigger signal for a prize ball payout request). ). The prize ball REQ signal is at a high level (stopped state) when the prize ball payout is forcibly stopped, and is also used as a forcible stop signal for instructing the prize ball payout to be forcibly stopped. The payout number signal is a signal output for designating the number (1 to 15) of game balls for which payout requests are made.

  The payout BUSY signal (the signal for paying out a winning ball) is a signal used by the main board 31 to confirm the operation state on the payout control board 37. Each control signal only needs to be configured so that the output state or the on state and the stop state or the off state can be distinguished, and the above logic may be reversed in polarity.

  24 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 24, the power confirmation signal A, the prize ball REQ signal, and the payout quantity signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. Further, the payout BUSY signal and the power supply confirmation signal B are output by the payout control CPU 371 via the output circuit 373 B and input to the CPU 56 via the input circuit 68. Each of the power supply confirmation signal A, the power supply confirmation signal B, the prize ball REQ signal, and the payout BUSY signal is 1-bit data, and is transmitted through one signal line. Since 1 to 15 payout number signals are designated, it is composed of 4-bit data and transmitted through four signal lines.

  FIG. 25 is a flowchart showing an example of the prize ball processing in step S30. In the prize ball process, the COU 56 executes a prize ball number addition process (step S201) and a prize ball control process (step S202).

  In the prize ball number adding process, a prize ball number table shown in FIG. 26 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “6”) is set at the start address of the winning ball number table, and then the switch timer for each switch of the winning opening that will pay out the winning ball by winning (see FIG. 20). Are sequentially set in pairs.

  FIG. 27 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (step S211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S212). Next, the upper address (8 bits) of the switch timer is set in the check pointer (step S213). The upper addresses of all switch timers are the same.

  Then, the value of the pointer is incremented by 1 (step S214), and the address of the switch timer is obtained based on the data set in the check pointer and the data of the address pointed to by the pointer (lower address of the switch timer). The switch timer value is loaded (step S215). The value loaded first is the value of the switch timer corresponding to the left prize opening switch 33a (see FIG. 26). Here, the pointer value is incremented by 1 (step S216).

  Next, the CPU 56 compares the value of the loaded switch timer with an ON determination value (for example, “2”) (step S217). If they match, the process proceeds to step S218. If they do not match, the process proceeds to step S222. Transition. The value of the switch timer is incremented by 1 when it is confirmed that the switch is turned on by the switch process in step S21. Since the switch process is started every 2 ms, the switch timer value becomes “2” if the switch is turned on continuously for 4 ms. That is, when the on determination value is “2”, if the switch is continuously turned on for 4 ms, the value of the switch timer matches the on determination value.

  In step S218, the data of the address pointed to by the pointer (in this case, the number of prize balls) is loaded, and the loaded value is set as the prize ball addition value. Further, the prize ball addition value is added to the contents of the total prize ball number storage buffer which is a 16-bit RAM area (step S219). The total winning ball number storage buffer is formed in the backup RAM. If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (steps S220 and 221).

  In step S221, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S214 (step S223).

  FIG. 28 is a flowchart showing the prize ball control process in step S201. In the prize ball control process, the CPU 56 executes any one of steps S231 to S234 according to the value of the prize ball process code.

  FIG. 29 is a flowchart showing the prize waiting process 1 (step S231) executed when the value of the prize ball process code is zero. In the award ball waiting process 1, the CPU 56 checks whether or not the payout BUSY signal is turned on (step S241). At this stage, since the payout BUSY signal should not be in the on state, if the payout BUSY signal is in the on state, an abnormal state code is output (step S242) and the process is terminated. The abnormal state code is an internal flag formed in the RAM 55. In the state where the payout command signal is not output because the prize ball transmission process shown in FIG. 30 to be described later is not executed, that is, in the state where the prize ball waiting process 1 is executed, the reception confirmation signal is obtained by S241Y. When the payout BUSY signal is received, it is a communication abnormal state between the game control microcomputer and the payout control microcomputer. At this time, the payout number subtraction process according to the reception of the reception confirmation signal cannot be performed. For this reason, in the award ball waiting process 1 in FIG. 29, the process directly returns from S241 and does not proceed to the award ball transmission process in FIG. 30 and the award ball waiting process 2 in FIG. It is forbidden.

  If the payout BUSY signal is off, the prize ball REQ signal is turned off and the payout number signal output is cleared to 0 (steps S243 and S244). The process of step S243 is a process for turning off the prize ball REQ signal after the execution of the prize ball waiting process 3 of step S234 is completed and the previous payout process is completed. Further, it is confirmed whether or not the prize ball timer is 0 (step S245). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (step S246), and the process is terminated. The prize ball timer is a timer for measuring the time required for prize ball processing. At this stage, if the value of the prize ball timer is not 0, the next prize ball after the previous payout process is completed. Waiting time until the REQ signal is turned on (this is a time for providing an interval between ON periods of a plurality of prize ball REQ signals when prize ball payout is continuously executed, and is set by S275. Means that it is not finished.

  If the value of the prize ball timer is 0, the CPU 56 confirms the contents of the total prize ball number storage buffer (step S247). If the value is 0, the process ends. If not, the value of the prize ball process code is set to 1 (step S248), and the process ends.

  FIG. 30 is a flowchart showing a prize ball transmission process (step S232) executed when the value of the prize ball process code is 1. In the prize ball transmission process, the CPU 56 first determines whether or not the connection confirmation signal B is in an on state (step S250). If it is not in the on state, the prize ball transmission process ends and the process returns. On the other hand, if it is in the ON state, it is confirmed whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S251). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S252). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S253).

  Thereafter, a payout number signal designating the number of payouts set in the prize ball number buffer is output (step S254), the prize ball REQ is turned on (step S255), and the value of the prize ball process code is set to 2. (Step S256), the process ends.

  In this embodiment, the maximum value of the prize ball command is “15”. Accordingly, a payout number signal designating a payout number of “15” at the maximum is transmitted to the payout control board 37. In the prize ball transmission process, when the game output control microcomputer does not receive the power supply confirmation signal B, that is, when the payout control microcomputer is not connected to the game control microcomputer, the CPU 56 side In this state, the payout number subtraction process according to reception of the payout BUSY signal as the reception confirmation signal cannot be performed. In such a case, since the process returns from S250 as it is and does not proceed to S254 and S255, the game control microcomputer side prohibits the output of the payout command signal.

  FIG. 31 is a flowchart showing the prize waiting process 2 (step S233) executed when the value of the prize ball process code is 2. In the award ball waiting process 2, the CPU 56 confirms whether or not the payout BUSY signal output (turned on) by the payout control microcomputer in response to the award ball REQ being turned on is turned on ( Step S261). When the on-state is not turned on, the BUSY start determination time value is set in the prize ball timer (step S262). The BUSY start determination time value is a value for the game control microcomputer to confirm that the payout BUSY signal has been output (turned on) if the payout BUSY signal is on for the time indicated by the value. .

  Therefore, the CPU 56 checks the value of the prize ball timer when the payout BUSY signal is turned on (step S263). If the value is not 0, the CPU 56 decrements the value of the prize ball timer by 1 (step S264), and performs processing. finish. When the value of the prize ball timer reaches 0, it is assumed that the payout BUSY signal is turned on, and the contents of the prize ball number buffer are changed from the contents of the total prize ball number storage buffer (the number of prize balls paid out to the payout control microcomputer). Is subtracted (step S265). Then, the prize ball REQ signal is turned off (S265a), and the BUSY end monitoring time value used for monitoring whether or not the on-state of the payout BUSY signal continues for an abnormally long time is set in the prize ball management timer. (S265b). Here, the BUSY end monitoring time value is a longer time than the standard time from when the payout BUSY signal is turned on until the payout operation of the prize ball is completed, and the payout BUSY signal. The value is determined in advance so that it can be determined that an abnormality has clearly occurred in the communication state. Therefore, when the time during which the on-state continues after the payout BUSY signal is turned on reaches the BUSY end monitoring time, it is determined that an abnormality has occurred in the communication state of the payout BUSY signal. Then, the value of the prize ball process code is set to 3 (step S266), and the process is terminated.

  FIG. 32 is a flowchart showing the award ball waiting process 3 (step S234) executed when the value of the award ball process code is 3. In the award ball waiting process 3, the CPU 56 checks whether or not the payout BUSY signal has been turned off (step S271). If not, the BUSY end determination time value is set in the prize ball timer (step S272). The BUSY end determination time value is a value for the game control microcomputer to confirm that the payout BUSY signal is no longer output (turned off) if the payout BUSY signal continues to be off for the time indicated by the value. is there. Then, it is determined whether or not the value of the prize ball management timer is 0 (step S277). If the value of the prize ball management timer is not 0, the value of the prize ball management timer is decreased by 1 (step S278), and the process is terminated. On the other hand, when the value of the prize ball management timer becomes 0, the BUSY end monitoring time has elapsed, so it is determined that the communication state of the payout BUSY signal is obviously abnormal, and the power supply confirmation signal A is turned off ( At the same time as step S279), an abnormality notification command that is an effect control command for instructing notification that a communication abnormality has occurred is set (step S280), and the process is terminated. When such an abnormality notification command is set, the abnormality notification command is transmitted to the effect control board 80 as an effect control command. Thereby, the CPU 101 for effect control of the effect control board 80 performs control to perform an abnormality notification effect such as an image display on the variable display device 9 and the generation of an abnormality notification sound from the speaker 27. Thereby, it becomes possible to easily grasp that such an abnormal state has occurred. The abnormality notification effect is not limited to image display and sound generation as described above, and a predetermined lamp may be controlled to emit light, and any one of display, sound generation, and light emission may be performed. One, any two combinations, or all combinations may be performed.

  When the payout BUSY signal is turned off, the CPU 56 confirms the value of the prize ball timer (step S273). If the value is not 0, the value of the prize ball timer is decreased by 1 (step S274), and the process ends. . When the value of the prize ball timer becomes 0, it is determined that the payout BUSY signal has been turned off, and the prize ball REQ waiting time is set in the prize ball timer (step S275). Then, the value of the prize ball process code is set to 0 (step S276), and the process is terminated. As described above, the award ball REQ waiting time is the waiting time until the next award ball REQ signal is turned on (when award ball payout is continuously performed, the on periods of a plurality of award ball REQ signals are Is a time for providing an interval).

  With the above processing, the game control microcomputer stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The total award ball number storage buffer corresponds to a prize game medium number storage means for storing stored contents for at least a predetermined period by a backup power source as a variable data storage means when power supply to the gaming machine is stopped. Further, the game control microcomputer transmits a payout command signal for designating a predetermined number of payout balls to the payout control microcomputer based on the number of prize balls stored in the total prize ball number storage buffer. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. Then, when a predetermined condition that the payout BUSY signal as the reception confirmation signal is turned on is satisfied, a subtraction process for subtracting the payout number specified by the payout command signal from the prize ball number stored in the total prize ball number storage buffer To do.

  In this embodiment, the predetermined condition for executing the subtraction process is when the reception confirmation signal is received from the payout control microcomputer, specifically when the payout BUSY signal is turned on. When the payout BUSY signal is turned on, the payout control microcomputer has not yet paid out the number of prize balls instructed by the payout command signal. If configured to perform subtraction processing of the total number of winning balls storage buffer when the winning ball payout is completed, an illegal act that restores the power supply after illegally stopping the power supply of the gaming machine during paying the winning ball As a result, a large number of prize balls are illegally paid out. For example, when 15 prize ball payouts are instructed by a payout command signal, when 10 prize ball payouts are made, if the power supply is restored after illegally stopping the power supply of the gaming machine, Since the contents of the total number of winning balls storage buffer are not subtracted at all, it is assumed that the ten winning balls are not paid out even though ten winning balls are actually paid out. Control will continue.

  However, in this embodiment, when the payout BUSY signal is turned on, that is, when the payout control microcomputer accepts the payout command signal and transmits the reception confirmation signal, the subtraction process of the total winning ball number storage buffer is executed. Therefore, the above fraud can be prevented.

  In this embodiment, as the prize game medium number storage means for storing the total number of premium game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of prize game media so as to be identifiable stores the number of prizes received in each prize area, or the number of prizes for each prize area (for example, the same number of prize balls) (for example, 14 winning holes corresponding to 6 winning balls, 10 left winning winning holes 29 corresponding to the number of 10 winning balls, right dropping winning opening 30, left winning opening 33, right winning opening 39, 15 winning balls (The number of winnings that have not been finished yet) may be stored.

  FIG. 33 is a timing chart showing an example of the output state of a payout control signal. Here, there are six switches for detecting a winning (for example, a left dropping winning opening switch 29a, a right dropping winning opening switch 30a, a left winning opening switch 33a, a right winning opening switch 39a, a start opening switch 14a, and a count switch 23). A case will be described where 15 winnings are detected after the winning is detected. As described above, when a winning is detected, the number of winning balls corresponding to the winning is added to the total winning ball number storage buffer in the winning ball number adding process.

  As shown in FIG. 33, when six winnings are detected, the CPU 56 determines that a prize ball is based on the fact that the content of the total prize ball number storage buffer is not 0 and the power confirmation signal B is on. By setting the REQ signal to the output state (ON state: low level) and setting the payout number signal indicating 6 to the output state (see steps S254 and S255), the payout command signal is set to the output state. That is, when the prize ball REQ signal and the number-of-payout signal are simultaneously output, the payout command signal is output. The payout control microcomputer receives the payout number signal by outputting the prize ball REQ signal.

  When the payout control CPU 371 receives the prize ball REQ signal, the payout control CPU 371 turns on the payout BUSY signal indicating that the prize ball is being paid out, and drives the payout motor 289 to display the six payout quantity signals. A prize ball payout process is executed. When the payout BUSY signal rises to the on state (changes from the off state to the on state), a reception confirmation signal indicating that the payout command signal has been received is output. In response to the payout BUSY signal being turned on, the CPU 56 subtracts the content of the prize ball number buffer (step S265) and sets the prize ball REQ signal to a stopped state (off state: high level) (step S265). S265a). By setting the prize ball REQ signal to the stop state, the payout command signal is stopped.

  When the payout BUSY signal continues to be in the on state, a payout process in-progress signal indicating that the payout BUSY signal is in the on state is executing a payout process (payout operation). When the payout process for six prize balls is completed, the payout control CPU 371 turns off the payout BUSY signal. When the payout BUSY signal falls (change from the on state to the off state), a payout completion signal indicating that the execution of the payout process (payout operation) has ended is output (turned on).

  When the CPU 56 confirms that six prize balls have been paid out based on the payout completion signal, the output of the payout number signal is stopped (see steps S271, S243, and S244). When the payout process based on the 6 winnings is completed, the CPU 56 sets the prize ball REQ signal to the output state based on the fact that the content of the total winning ball number storage buffer is not 0, and outputs a payout number signal indicating 15 games. Set to output state. In this manner, the output of the payout command signal is prohibited until the payout BUSY signal is turned off. That is, if it is not confirmed in step S241 in FIG. 29 that the BUSY signal is off, the prize ball transmission process is not executed, and the payout number signal and the prize ball REQ signal are not output, so that the payout BUSY signal is turned off. In this case, the output of the payout command signal is prohibited. In other words, the CPU 56 performs a subtraction process for subtracting the number of prize balls to be paid out according to the reception confirmation signal (S265) and stops outputting the payout command signal by stopping the output of the prize ball REQ signal (S265a). Thereafter, even when there is a remaining number of payouts stored after the subtraction process, the output of the next payout command signal is stopped until the output of the payout BUSY signal as the payout processing signal is stopped (S241N). Is prohibited.

  When the payout control CPU 371 receives the prize ball REQ signal, the payout control CPU 371 turns on a payout BUSY signal indicating that the prize ball is being paid out, and drives the payout motor 289 to indicate 15 payout quantity signals. A prize ball payout process is executed. When the payout process for 15 prize balls is completed, the payout control CPU 371 turns off the payout BUSY signal. Upon confirming that 15 prize balls have been paid out based on the payout completion signal, the CPU 56 stops the prize ball REQ signal and stops outputting the payout number signal.

  In this embodiment, as shown in FIG. 33, the payout process based on the 15 winnings generated later is waited until the payout process based on the 6 winnings is completed. That is, when a plurality of winnings occur continuously, the CPU 56 sends out a winning ball payout request based on the subsequent winning until the paying of the winning ball based on the previous winning is confirmed by the payout completion signal. wait. In other words, the payout command signal transmission means in the game control microcomputer has not paid out to the prize game medium number storage means (in this example, the total prize ball number storage buffer) after the subtraction processing by the prize game medium number storage number subtraction means. When the number of prize game media is stored, the next payout command signal is output after the payout processing of the prize game medium of the number of payouts designated by the payout command signal is completed.

  Next, the operation of the payout control microcomputer (peripheral circuits such as the payout control CPU 371 and ROM, RAM 371a, etc.) will be described. FIG. 34 is an explanatory diagram showing an example of output port assignment in the payout control microcomputer. As shown in FIG. 34, the output port 0 is an output port for outputting each phase signal supplied to the firing motor 94 by the stepping motor and each phase signal supplied to the dispensing motor 289 by the stepping motor. It is. Further, the output port 1 is an output for outputting a ball break LED 52, a prize ball LED 51, a payout BUSY signal, prize ball information output to the outside of the gaming machine, ball rental information, a gaming machine error signal, and a power supply confirmation signal B. Port.

  The output port 2 is an output port for outputting each segment of the error display LED 374 using a 7-segment LED. The output port 3 is an output port for outputting an EXS signal and a PRDY signal to the card unit 50.

  FIG. 35 is an explanatory diagram showing an example of bit assignment of input ports in the payout control microcomputer. As shown in FIG. 35, a 4-bit payout number signal is input to bits 0-3 of input port 0, and a power confirmation signal (power-off signal) from power supply monitoring circuit 920 is input to bits 4-7, respectively. A) A prize ball REQ signal from the main board 31, a detection signal from the ball break switch 187, and a detection signal from the payout motor position sensor 295 are input. In addition, bits 0 to 4 of the input port 1 respectively include a detection signal of the payout count switch 301, an operation signal from the error release switch 375, a signal from the single firing switch, a touch sensor signal from the touch sensor, and a full switch. 48 detection signals are input. The VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 5 to 7 of the input port 1, respectively.

  FIG. 36 is a timing chart for explaining the communication between the payout control microcomputer of the gaming machine and the card unit 50. The payout control microcomputer turns on the PRDY signal when power supply to the gaming machine is started and the payout operation is possible. When the power supply is started, the card unit 50 turns on the VL signal as a connection signal. When the card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit 50 outputs a BRDY signal to the payout control microcomputer. That is, the BRDY signal is turned on. When a predetermined delay time elapses from this point, the card unit 50 outputs a BRQ signal to the payout control microcomputer. That is, the BRQ signal is turned on.

  Then, when the payout control microcomputer turns on the EXS signal for the card unit 50 and detects the falling (off) of the BRQ signal from the card unit 50, the payout motor 289 is driven to set a predetermined number (for example, 25). Pay out the rental balls of the player to the player. When the payout is completed, the payout control microcomputer causes the EXS signal to the card unit 50 to fall. That is, the EXS signal is turned off.

  Next, the operation of the payout control microcomputer will be described. FIG. 37 is a flowchart showing main processing executed by the payout control microcomputer. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM 371a to an accessible state (step S706).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, a payout control process is executed.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, it is possible to use an interrupt process based on counting up the built-in CTC. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase.

  Next, the payout control CPU 371 executes normal initialization processing (steps S711 to S713). In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S711). In addition, initial values are set in the work area flags and counters of the RAM 371a (step S711a). Then, a CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically generated (step S712). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since the interruption is prohibited in step S701 of the initial setting process, the interruption is permitted before the initialization process is finished (step S713). Thereafter, the loop processing is started.

  As described above, in this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, a payout control process (steps S750 to S760 in FIG. 38) is executed in the timer interrupt process.

  In the payout control process, the payout control CPU 371 first performs an excitation pattern output process for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0) (step S750). In the firing motor control process in step S752, the excitation pattern is stored in the excitation pattern buffer that is the RAM area. In step S750, the payout control CPU 371 outputs the contents of the excitation pattern buffer to the lower 4 bits of the output port 0. The process to do is performed.

  Next, the payout control CPU 371 executes a switch process (step S751). The switch process is the same as the switch process in the game control microcomputer. If the state of the input port for inputting the detection signal of each switch is ON, the switch timer provided for each switch Add +1 to the value.

  Next, the payout control CPU 371 executes a firing motor control process (step S752). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer. When the firing motor 94 should be disabled, the patterns of the firing motors φ1 to φ4 that do not rotate the firing motor 94 are stored in the excitation pattern buffer. Also, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed. Then, a prepaid card unit control process for communicating with the card unit 50 is executed (step S754).

  Next, the payout control CPU 371 executes main control communication processing for communicating with the game control microcomputer of the main board 31 (step S755). Further, a payout control process is performed for paying out the lent balls in response to a ball lending request from the card unit 50, and for performing control for paying out the number of prize balls indicated by the payout number signal from the main board ( Step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S759). In the display control process, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball REQ signal is on. Further, when the prize ball REQ signal is turned off, control for turning off the prize ball LED 51 is performed.

  As in the case of the game control microcomputer, a RAM area (output port buffer) corresponding to the output state of the output port is provided, and the payout control CPU 371 outputs the contents of the output port buffer to the output port. (Step S760: output process). However, since the lower 4 bits (fire motors φ1 to φ4) of output port 0 are executed in step S750, the output of the lower 4 bits of output port 0 is not performed in the output process. The output port buffer is updated by a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), an information output process (step S758), and a display control process (step S759). The

  The power supply confirmation signal B transmitted to the main board 31 is turned off when the supply of power to the payout control board 37 is stopped. In the setting of the work area in step S711a described above, the content of the output port buffer corresponding to the power supply confirmation signal B is set to a value corresponding to the ON state of the power supply confirmation signal B. When the output process in step S760 is executed, the contents of the output port buffer are output to the output port, so that the power confirmation signal B to the main board 31 is turned on. Therefore, the power supply confirmation signal B is output (turned on) when the payout control board 37 rises. Note that the power supply confirmation signal B is also output when the power supply is recovered from an instantaneous power interruption or the like.

  FIG. 39 is a flowchart showing the firing motor control process in step S752. In the firing motor control process, the payout control CPU 371 determines that the VL signal from the card unit 50 is in the off state (not connected to the prepaid card), or the power confirmation signal A from the main board 31 is in the off state (main board). When not connected) or when the full switch 48 is on (bottom pan full), the process proceeds to step S518 (steps S511, S512, S513). If the prepaid card is not connected, the main board is not connected, and the lower pan is not full, the process proceeds to step S514. In step S514, the payout control CPU 371 checks whether or not the touch sensor signal is on. If it is in the on state, the process proceeds to step S515, and if it is not in the on state, the process proceeds to step S518.

  In step S515, the payout control CPU 371 increments the firing motor excitation pattern counter by one. Then, data corresponding to the value of the excitation pattern counter is read from the firing motor excitation pattern table stored in the ROM (step S516). Further, the read data is set in the firing motor excitation pattern buffer (step S517). As described above, the contents of the firing motor excitation pattern buffer are output to the output port in step S750. In the firing motor excitation pattern table, the excitation pattern data (shooting motors φ1 to φ4) for each step for rotating the firing motor 94 is sequentially set.

  In step S518, non-rotation data (excitation pattern for preventing the firing motor 94 from rotating) is set in the firing motor excitation pattern buffer.

  FIG. 40 is a flowchart showing the payout motor control process in step S753. In the payout motor control process, the payout control CPU 371 executes any one of steps S521 to S526 in accordance with the value of the payout motor control code.

  In the payout motor normal process (step S521) executed when the value of the payout motor control code is 0, the payout control CPU 371 sets the pointer at the head address of the table stored in the ROM. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 289 at the time of ball payout is sequentially set. Yes.

  In the payout motor start preparation process (step S522) executed when the value of the payout motor control code is 1, the payout control CPU 371 excites the bits 4 to 7 of the output port buffer corresponding to the output state of the output port 0. Processing such as setting the initial value of the pattern is performed.

  In the payout motor slow-up process (step S523) executed when the value of the payout motor control code is 2, the payout control CPU 371 starts the rotation of the payout motor 289 more smoothly than in the case of the constant speed process. The output port buffer bits 4 to 4 corresponding to the output state of the output port 0 are read out at a long interval and at a time interval that gradually approaches the time interval in the case of constant speed processing. Set to 7. At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the value of the pointer is incremented by one.

  In the payout motor constant speed process (step S524) executed when the value of the payout motor control code is 3, the payout control CPU 371 periodically reads the content of the payout motor excitation pattern table and outputs the output state of the output port 0. Are set in bits 4 to 7 of the output port buffer corresponding to.

  In the payout motor brake process (step S525) executed when the value of the payout motor control code is 4, the payout control CPU 371 has a longer interval than in the case of the constant speed process in order to stop the payout motor 289 smoothly. In addition, the content of the payout motor excitation pattern table is read at a time interval that gradually moves away from the time interval in the case of constant speed processing, and is stored in bits 4 to 7 of the output port buffer corresponding to the output state of the output port 0. Set.

  In the ball biting payout motor brake process (step S526) executed when the value of the payout motor control code is 5, the payout control CPU 371 smoothes the payout motor 289 in the case of rotation for releasing the ball biting. The payout motor excitation pattern is longer than the rotation of the payout motor 289 for releasing the ball biting, and gradually away from the time interval in the case of constant speed processing. The contents of the table are read and set in bits 4 to 7 of the output port buffer corresponding to the output state of output port 0.

  FIG. 41 is a flowchart showing the main control communication process of step S755. In the main control communication process, the payout control CPU 371 executes any one of steps S531 to S533 according to the value of the main control communication control code.

  FIG. 42 is a flowchart showing a main control communication normal process (step S531) executed when the value of the main control communication control code is 0. In the main control communication normal process, the payout control CPU 371 ends the process without executing the subsequent processes when the error bit is on (step S541). The error bit is a bit in an error flag that is set when it is detected that various errors have occurred. In step S541, if even one bit in the error flag is set, it is determined that the error bit is set. When the error bit is set as described above, it is notified that an error state as an abnormal state has occurred according to the type of the error bit, as will be described later.

  If the BRDY signal is on, the payout control CPU 371 ends the process without executing the subsequent processes (step S542). That the BRDY signal is on means that a ball lending request is generated from the card unit 50. That is, when a ball lending request is generated, communication with the game control microcomputer of the main board 31 does not proceed. Further, when the ball payout operation is being performed, that is, when a ball lending operation flag to be described later is set, the processing is terminated without executing the subsequent processing (step S543). Therefore, even when the ball payout operation is in progress, communication with the game control microcomputer of the main board 31 does not proceed. If the power supply confirmation signal A from the main board 31 is in the off state, the process is terminated without executing the subsequent processes (step S544).

  As described above, when the payout control microcomputer does not receive the power supply confirmation signal A, that is, when the game control microcomputer is not connected to the payout control microcomputer, the CPU 56 side issues a payout BUSY signal as a reception confirmation signal. In this state, the payout number cannot be subtracted according to the receipt of the number of payouts. In such a case, the payout process by the payout control CPU 371 is prohibited by returning from S544 as it is.

  When the conditions in steps S541 to S543 are not satisfied and the power supply confirmation signal A is in the on state, the payout control CPU 371 confirms whether or not the prize ball REQ signal is in the on state (step S545). If it is in the ON state, the number of prize balls indicated by the number-of-payout signal is set in an unpaid quantity counter as a means for counting and storing the number of prize balls out of the number of prize balls designated by the payout command signal. (Step S546), a process for turning on the payout BUSY signal is performed (step S547). Specifically, the bit corresponding to the payout BUSY signal in the output port buffer corresponding to the output state of the output port 1 is set to the on state.

  Next, a prize ball REQ signal monitoring time is set in the main control communication control timer (step S547a). The main control communication control timer is a timer used for monitoring the time related to communication with the game control microcomputer of the main board 31, but at this stage, the abnormal continuation of the on state of the prize ball REQ signal is monitored. The award ball REQ signal monitoring time is set. Here, the prize ball REQ signal monitoring time is based on the standard time from when the payout BUSY signal is turned on until the prize ball REQ signal is turned off, and is longer than the standard time. The value is determined in advance so that it can be clearly determined that an abnormality has occurred in the communication state of the ball REQ signal. Therefore, when the time when the prize ball REQ signal does not turn off after the payout BUSY signal is turned on reaches the prize ball REQ signal monitoring time, it is determined that an abnormality has occurred in the communication state of the prize ball REQ signal. Then, the value of the main control communication control code is set to 1 (step S548), and the process ends. The unpaid-off number counter is formed in a volatile (not backed up by power) RAM area.

  FIG. 43 is a flowchart showing main control communication processing (step S532) executed when the value of the main control communication control code is 1. In the main control communication process, the payout control CPU 371 checks whether or not the prize ball REQ signal is turned off (step S551). When it is turned off, the process proceeds to step S553. If not, the main control communication control timer is decremented by 1 (step S551a). If the value of the main control communication control timer is 0 (step S551b), it is determined that the prize ball REQ signal is not turned off even though the prize ball REQ signal needs to be turned off. Is set (step S552), and the process proceeds to step S553. As described above, when the time when the prize ball REQ signal is not turned off after the payout BUSY signal is turned off reaches the prize ball REQ signal monitoring time set in S547a, the prize ball REQ signal error bit is set. As a result, it is notified that an abnormality has occurred in the communication state of the prize ball REQ signal.

  Next, the payout control CPU 371 determines whether or not the prize ball operating flag is set (step S553). If it is not set, that is, if the prize ball action is not being executed, the payout BUSY signal is turned off. Is performed (step S554). Specifically, the bit corresponding to the payout BUSY signal in the output port buffer corresponding to the output state of the output port 1 is set to the off state. Also, the payout number signal OFF monitoring time is set in the main control communication control timer (step S555). At this stage, the main control communication control timer is set with a payout number signal off monitoring time for monitoring that the payout number signal is turned off. Here, the payout quantity signal off monitoring time is based on a standard time from when the payout BUSY signal is turned off to when the payout quantity signal is turned off, and is longer than the standard time. The value is determined in advance so that it can be determined that an abnormality has clearly occurred in the communication state of the signal. Accordingly, when the time during which the payout number signal is not turned off after the payout BUSY signal is turned off reaches the payout number signal off monitoring time, it is determined that an abnormality has occurred in the communication state of the payout number signal. Then, the value of the main control communication control code is set to 2 (step S556), and the process ends.

  FIG. 44 is a flowchart showing main control communication end processing (step S533) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 checks whether or not the payout number signal is turned off (step S561). If it becomes an OFF state, it will transfer to step S565. If it is not in the off state, the value of the main control communication control timer is decremented by 1 (step S562). If the value of the main control communication control timer is 0 (step S563), the payout number signal error bit is set in the error flag (step S564), assuming that the payout number signal has not been turned off (step S564). Transition. As described above, when the payout number signal OFF monitoring time reaches the payout number signal OFF monitoring time after the payout BUSY signal is turned off, the payout number signal error bit is set, thereby It is notified that an abnormality has occurred in the communication state. In step S565, the value of the main control communication control code is set to 0 (step S565), and the process ends.

  FIG. 45 is a flowchart showing the payout control process in step S756. In the payout control process, when the payout control CPU 371 confirms that the detection signal of the payout count switch 301 is turned on, the payout control CPU 371 decreases the value of the unpaid-out number counter by 1. Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  FIG. 46 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (step S621). On the other hand, if the BRDY signal is not in the on state, processing for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal that is a ball lending request signal is on, a ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid number counter (step S625), and “25” is set in the unpaid number counter in the payout motor rotation count buffer (step S626).

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S634), the value of the payout control code is set to 1 (step S635), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S631). If 0, the process ends. The unpaid-out number counter has a non-zero value (the number indicated by the number-of-paid-out signal) when a prize ball REQ signal is received from the game control microcomputer of the main board 31 in step S546 in the main control communication normal process. It is set. Accordingly, when the value of the unpaid-out number counter is not 0, a prize ball operating flag is set (step S632), and the value of the unpaid-out number counter is set in the payout motor rotation number buffer (step S633). Then, control goes to a step S634.

  FIG. 47 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and whether the payout operation is completed by checking the flag in step S641. You can check whether or not.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  FIG. 48 is a flowchart showing a payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first decrements the value of the payout control timer by 1 (step S651). Then, the value of the payout control timer is confirmed. If the value is not 0, that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the value of the unpaid-out number counter is confirmed (step S653). If the payout operation is normally executed, all the game balls paid out by the payout motor 289 pass through the payout count switch 301 before the payout control timer times out, and the unpaid number counter of the payout count counter is processed by the processes of steps S601 and S602. The value is 0. When the value of the unpaid-out number counter indicates a positive value, it means that the number of game balls actually paid out is less than the planned payout number (insufficient payout). In addition, when the value of the unpaid-out number counter indicates a negative value, it means that the number of game balls actually paid out is larger than the planned payout number (excess payout).

  The payout control CPU 371 changes the internal state indicating that the payout process is being performed to a state where the payout process is not being performed when the value of the unpaid-out number counter is not a positive value (when the payout is not insufficient). Specifically, when the ball lending operation is being executed, that is, when the ball lending operation flag is set, the ball lending operation flag is reset (steps S654 and S655). Further, when the winning ball motion is being executed, that is, when the winning ball motion flag is set, the winning ball motion flag is reset (steps S654 and S656). Thereafter, the re-payout operation counter is cleared (step S667), the value of the payout control code is set to 0 (step S658), and the process ends. If the payout operation is normally executed, the process of step S657 is unnecessary, but after the corrected payout process described later is executed, the process of step S657 is required. Further, in this embodiment, it is considered that the payout process is normally completed even when there is an excessive payout. However, when there is an excessive payout, it may be notified that an error has occurred.

  When it is confirmed in step S653 that the value of the unpaid number counter is a positive value, the payout control CPU 371 performs control for the corrected payout process in steps S661 to S666. Here, a maximum of two re-payout operations are performed until the number of game balls to be paid out is paid out. An error bit is set when the number of game balls to be paid out is not paid out even after two re-payout operations are performed.

  In step S661, the payout control CPU 371 checks whether or not the value of the re-payout operation counter is 2. If not 2, the value of the unpaid number counter is set in the payout motor rotation number buffer (step S662), and the value (“1”) corresponding to the payout motor start preparation process is set in the payout motor control code ( Step S663). Further, the value of the re-payout operation counter is incremented by 1 (step S664), the value of the payout control code is set to 1 (step S665), and the process is terminated. The processing in steps S662, S663, and S665 is the same as the processing in steps S633 to S635 in the payout start waiting process, although the values set in the payout motor rotation frequency buffer are different.

  In step S661, when it is confirmed that the value of the re-payout operation counter is 2, the payout control CPU 371 sets a payout count switch non-passing error bit (payout case error bit) in the error flag ( Step S666), the process is terminated.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control microcomputer is based on the detection signal from the payout count switch 301 serving as the payout detection means, in the volatile storage means (in this example, the unpaid number counter). ), When it is detected that a prize game medium less than the number of payouts stored is detected, a predetermined amount (two in this example) is limited to a predetermined amount (in this example, two times). The game medium is paid out.

  FIG. 49 is a timing chart for explaining the ball biting detection process executed in the payout motor control process (step S753). In the payout motor constant speed process (step S524) in the payout motor control process, the payout control CPU 371 monitors the detection signal of the payout motor position sensor 295. The detection signal of the dispensing motor position sensor 295 is turned on twice, for example, every time the cam 292 makes one rotation. In order for the detection signal to be output twice each time the cam 292 makes one rotation, the cam 292 has two locations in the portion that receives light from the light emitting portion in the payout motor position sensor 295 (symmetric with respect to the axis). (Position) is provided with a reflector. The output of the light receiving unit in the dispensing motor position sensor 295 is used as a detection signal.

  Therefore, even if the payout control CPU 371 gives an excitation pattern having a step number of 1/2 rotation or more to the payout motor 289, the detection signal of the payout motor position sensor 295 does not turn on. Actually, the payout motor 289 does not rotate due to a foreign matter such as dust adhering to the cam 292 and clogging the game ball (ball biting has occurred), and as a result, the cam 292 rotates. It can be determined that they have not.

  In this embodiment, the payout motor 289 rotates once when receiving an excitation pattern for 16 steps. For example, as shown in FIG. 49, the payout control CPU 371 checks the detection signal of the payout motor position sensor 295 every time the payout motor 371 gives an excitation pattern for 8 steps to the payout motor 289. Thus, it is determined whether or not the payout motor 289 is rotating. Then, if the same state is detected five times continuously (the detection signal of the dispensing motor position sensor 295 is turned off five times continuously or turned on five times continuously), it is determined that ball engagement has occurred. A ball biting release process is executed.

  As shown in FIG. 50, the payout control CPU 371 repeats a process of rotating the payout motor 289 at a high speed and a process of rotating at a low speed a predetermined number of times (for example, 9 times) as shown in FIG. Each time an excitation pattern for 8 steps is given to the payout motor 289, the detection signal of the payout motor position sensor 295 is checked to determine whether or not the payout motor 289 is rotating. If it is determined by the detection signal that the rotation of the payout motor 289 has been restored, the ball biting release process is terminated, and the normal ball payout process returns.

  If there is no change in the detection signal of the payout motor position sensor 295 even if the high speed rotation process and the low speed rotation process are executed a predetermined number of times, a ball biting error bit (payout case error bit) in the error flag Set. When the payout case error bit is set, the payout control CPU 371 does not drive the payout motor 289.

Thus, the payout control microcomputer includes a drive state monitoring means for monitoring the operating state of the payout means, and a drive stop means for stopping the drive of the payout means when the drive state monitoring means detects a malfunction of the payout means. including.
From here, error processing will be described. FIG. 51 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 51, when the power supply confirmation signal A from the main board 31 is turned off (for example, when the signal line is disconnected and when the communication state of the payout BUSY signal shown in FIG. 32 is abnormal). The payout control CPU 371 performs control to display “1” on the error display LED 374 as a main board non-connection error. When the disconnection of the payout count switch 301 or a ball clogging occurs in the payout count switch 301, control is performed to display “2” on the error display LED 374 as the payout switch abnormality detection error 1. The disconnection of the payout count switch 301 or the occurrence of ball clogging in the payout count switch 301 is determined by the detection signal of the payout count switch 301 not being turned off.

  When the detection signal of the payout count switch 301 is turned on although the game ball is not paying out, a control is performed to display “3” on the error display LED 374 as the payout switch abnormality detection error 2. . When the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, a control for displaying “4” on the error display LED 374 as a payout case error To do. If the prize ball REQ signal is turned on at an incorrect timing, control is performed to display “5” on the error display LED 374 as a prize ball REQ signal error.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit unconnected error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S754). When the payout number signal is turned on at an incorrect timing, control is performed to display “0” on the error display LED 374 as a payout number signal error.

  Among the above errors, after a main control disconnection error, a payout switch abnormality detection error 2, a payout case error, a prize ball REQ signal error, or a payout number signal error occurs, the error release switch 375 is operated to cancel the error. When the operation signal is output from the switch 375 (when the switch 375 is turned on), the payout control microcomputer returns to the state before the error occurred.

  52 and 53 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 checks the error flag, and the set bits are the main control unconnected error, the payout switch abnormality detection error 2, the payout case error, the winning ball REQ signal error, and the payout number. It is confirmed whether or not only a signal error occurs (only one of the three bits, or only two of the three bits, or only these three bits) (step S671). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S672). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S673). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S674). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S678. If the timer before error recovery is set, the value of the timer before error recovery is decremented by -1 (step S675). If the value of the timer before error recovery becomes 0 (step S676), the main control among the error flags is set. Bits of unconnected error, payout switch abnormality detection error 2, payout case error, prize ball REQ signal error and payout number signal error are reset (step S677).

  As described above, since the error state (which is in the payout prohibited state as shown in step S621 in FIG. 46) is released based on the operation of the error release switch 375, the payout prohibited state is immediately released and the payout is made. Processing can be activated.

  In step S678, the payout control CPU 371 checks the detection signal of the full switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S679). If the detection signal of the full tank switch 48 is OFF, the full tank error bit is reset (step S680).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S681). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S682). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S683). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port buffer is set to a value corresponding to the lighting state in the display control process of step S759.

  Further, the payout control CPU 371 checks the state of the power supply confirmation signal A from the main board 31 (step S685). If the power supply confirmation signal A is not output (if it is in the off state), the main board unconnected error A bit is set (step S686).

  The payout control CPU 371 checks the value of the switch timer corresponding to the payout count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “240 ”) (Step S688), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S689). If the value of the switch timer corresponding to the payout count switch 301 is equal to or shorter than the switch-on maximum time, the payout switch abnormality detection error 1 bit is reset (step S690). Note that the value of each switch timer is incremented by 1 if the state of the input port to which the detection signal of each switch is input is switched on in the switch processing of step S751, and cleared by 0 if it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout count switch 301 has exceeded the maximum switch-on time means that the payout count switch 301 has been turned on beyond the maximum switch-on time. It is determined that the game ball is clogged at the disconnection of the count switch 301 or at the portion of the payout count switch 301.

  Also, the payout control CPU 371 resets both the ball lending operation flag and the winning ball operation flag when the value of the switch timer corresponding to the payout count switch 301 becomes a switch-on determination value (for example, “2”). If it is in the state, it is determined that the game ball has passed through the payout count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (step S693). If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S694).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S695). If the VL signal is not input (if it is in the off state), the prepaid card unit not yet in the error flag is displayed. A connection error bit is set (step S696). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S697).

  In the display control process in step S759, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374. In this embodiment, the game control microcomputer mounted on the main board 31 and the payout control microcomputer mounted on the payout control board 37 perform two-way communication with respect to prize ball payout, but a communication error is displayed as an error. This can be notified by the LED 374 for use. In addition, as a communication error, a main board non-connection error due to the power supply confirmation signal A from the main board 31 being turned off, and a prize ball REQ signal error in which the prize ball REQ signal is turned on at an incorrect timing (see steps S551 to S552). In addition, there is a prize ball number signal error (see steps S561 to S564) in which the prize ball number signal is turned on at an improper timing, but when a communication error such as a main board non-connection error occurs, the firing motor 94 is disabled. Be activated. That is, the game ball cannot be launched into the game area 7. Therefore, the game does not proceed despite the occurrence of a communication error such as a main board unconnected error.

  Further, among the communication errors, the main board non-connection error, the prize ball REQ signal error, and the prize ball number signal error excluding an abnormality in the communication state of the payout BUSY signal are detected on the payout control microcomputer side. Even if the microcomputer and the payout control microcomputer perform two-way communication with respect to prize ball payout, a communication error can be detected without increasing the burden on the game control microcomputer.

  In this embodiment, the error of the main board unconnected error is resolved on condition that the error cancel switch 375 is operated (see steps S685 and S687), but automatically when the power confirmation signal A is turned on. The problem may be resolved.

  Further, in this embodiment, a communication error is notified in distinction from a communication error with the card unit 50 (prepaid card unit non-connection error and prepaid card unit communication error) and other errors (see FIG. 51). . Therefore, a communication error between the game control microcomputer and the payout control microcomputer is easily identified.

  Next, in this embodiment, the control operation when power supply to the pachinko gaming machine 1 is stopped due to a power failure or the like in the middle of execution of the winning ball payout operation by the payout motor 289 will be described in comparison with the conventional example. To do. Referring to FIG. 33, for example, assuming that the power supply is stopped in the middle of the payout operation for six or fifteen, as shown in FIG. When the subtraction process for subtracting the number of prize balls to be paid out is performed in response to the rising of the payout BUSY signal (S265), the output of the prize ball REQ signal is stopped (S265a) to stop the payout command signal. Done. For this reason, since the payout command signal is already stopped when the payout operation of the prize ball by the payout motor 289 is executed, the payout command signal is already stopped when the power supply is stopped.

  As described above, when the power supply to the pachinko gaming machine 1 is stopped due to a power failure or the like, data specifying the control state including the output state of the payout command signal is backed up and stored on the main board 31 side. On the substrate 37 side, data specifying the control state is not backed up and stored. For this reason, when the power supply is restored after the power supply is stopped as described above, only the control state backup-stored on the main board 31 side is effective. When the prize ball REQ signal stops, the data stored in backup for the payout command signal specifies the stop state of the payout command signal that the payout number signal is in the output state and the prize ball REQ signal is in the stop state. It becomes data to do. As shown in S545 to S548 in FIG. 42, the payout control CPU 371 does not advance the payout control unless the award ball REQ signal is output. Therefore, the payout command that the award ball REQ signal is in a stopped state as described above. Even when the control state is restored based on the backup data specifying the signal stop state, the payout operation is not executed again from the beginning. That is, when the power supply to the pachinko gaming machine 1 is stopped due to a power failure or the like in the middle of execution of the winning ball payout operation, it is possible to prevent excessive payout of winning balls based on the backup data.

  When the payout control in the conventional pachinko gaming machine is executed with respect to the present embodiment as described above, the pachinko gaming machine 1 is caused by a power failure or the like in the middle of executing the winning ball payout operation as described below. When the power supply to is stopped, excessive payout of prize balls based on the backup data cannot be prevented. FIG. 55 is a timing chart showing an example of an output state of a payout control signal in a conventional pachinko gaming machine.

  FIG. 55 shows an output state example of a payout control signal in the same control situation as FIG. In the conventional case, in the game control microcomputer, the power supply confirmation signal is only a signal transmitted from the game control microcomputer to the payout control microcomputer. In the conventional case, as in the embodiment, when a payout BUSY signal reception confirmation signal is received, a subtraction process for subtracting the stored payout number is performed.

  However, in the conventional case, the output state (ON state) of the prize ball REQ signal is maintained until the payout operation is completed and the payout BUSY signal is turned off. That is, the output state (ON state) of the payout command signal is maintained until the payout operation is completed and the payout BUSY signal is turned off. Therefore, when the subtracting process is performed and the output state of the payout command signal is still maintained, that is, when the power supply to the gaming machine is stopped due to a power failure or the like in the middle of executing the payout control, the payout is performed after the subtracting process. A state where the output state of the command signal is maintained is backed up and stored on the game control microcomputer side. As a result, when the power supply is restored, the payout process is executed again from the beginning based on the payout command signal whose output state is maintained after the subtraction process, so that the prize game medium is excessively paid out. Compared to such a conventional example, in the case of the present embodiment, as shown in FIG. 33, when the subtraction process is performed in response to the rising of the payout BUSY signal which is the reception confirmation signal, the prize ball REQ Since the control for stopping the payout command signal is performed by stopping the output of the signal, the payout operation is performed when the power supply to the pachinko gaming machine 1 is stopped due to a power failure or the like during the execution of the payout operation of the prize ball. It is not executed again from the beginning, and excessive payout of prize balls based on backup data can be prevented.

  FIG. 54 is a block diagram showing an example of test signal output from the payout control board 37. 54 also shows a test terminal board 200 and a test apparatus 210. As shown in FIG. 54, in the payout control board 37, the detection signal from the payout count switch 301 and the payout BUSY signal output to the main board 31 are branched, and the branched signals are logical product circuits ( AND circuit) 376. Accordingly, the AND circuit 376 can output a prize ball count signal indicating that a prize ball has been paid out when the payout count switch 301 detects the payout of a game ball during the output of the payout BUSY signal.

  In the payout control board 37, the prize ball count signal is output to a connector 377 provided on the payout control board 37. The connector 377 also outputs a test signal other than the prize ball count signal. The connector 377 is mounted only on the gaming machine used for the test. That is, a gaming machine that is not used for the test has a test signal output path such as a wiring pattern or a through hole, but the connector 377 is not mounted. Therefore, it is not necessary to provide the connector 377 for all the payout control boards 37, and the cost spent for testing the gaming machine is reduced. Further, since it is not necessary to attach the connectors to all the payout control boards 37 by soldering or the like, the work efficiency for testing the gaming machine is improved. Further, since a wiring pattern and a through hole for outputting a test signal are provided in all the gaming machines, a connector 377 is attached to connect the test terminal board 200 when performing an inspection after being installed in a game shop. It's easy to do. Therefore, in this embodiment, the connector 377 may not be provided. In other words, any means such as a wiring pattern for externally outputting the winning ball count signal from the AND circuit 376 may be provided, and the connector 377 may or may not be provided. Further, a prize ball count signal may be output from the main board 31 to the outside. That is, an AND circuit 376 is provided toward the main board 31, and a detection signal from the payout count switch 301 is input to one input terminal of the AND circuit 376 and a payout BUSY signal is input to the other input terminal of the AND circuit 376. An output signal (prize ball count signal) from the AND circuit 376 is externally output via the wiring pattern of the main board 31.

  The test terminal board 200 includes a connector 202 for inputting a test signal from a connector 377 mounted on the dispensing control board 37, a test signal output circuit 203, and a connector 204 for connecting to the test apparatus 210. ing. The test signal output circuit 203 includes an IC, a buffer circuit, and the like for selecting a test terminal used for signal output from a plurality of test terminals provided in the connector 204.

  The test apparatus 210 collects various test signals. At the time of the test, for example, a personal computer or the like is connected to the test apparatus 210. Therefore, data based on various test signals input to the test apparatus 210 is collected by a personal computer, and information for use in a test such as the number of awarded balls is displayed on a display unit of the personal computer. Data calculations can be performed.

  The ball payout device 97 is configured to perform both a winning ball payout and a lending ball payout, and a payout count switch 301 detects both a game ball due to a prize ball payout and a game ball due to a lending ball payout. As shown in 54, by installing an AND circuit 376 that allows the detection signal of the payout count switch 301 to pass when the payout BUSY signal output during the winning ball operation is in an on state, the payout control CPU 371 It is possible to create a prize ball count signal as a test signal without being involved.

  Next, main effects obtained by the embodiment described above will be described.

  (1) As shown in S241 of FIG. 29, S265, S265a of FIG. 31, and FIG. 33, the CPU 56 receives the award to the ON state of the payout BUSY signal as a reception confirmation signal (S261Y). A subtraction process is performed to subtract the prize ball payout number specified by the payout number signal included in the payout command signal from the number of prize balls stored in the ball number storage buffer (S265), and the output of the prize ball REQ signal is stopped. After the output of the payout command signal is stopped (S265a), even if there is a remaining payout number stored after the subtraction process, the output of the payout BUSY signal as the payout processing signal is output. Is stopped until the next payout command signal is stopped (S241N). When the power supply to the gaming machine is stopped due to a power failure or the like during the execution of the payout control, as described above, data specifying the control state including the output state of the payout command signal is backed up and stored on the main board 31 side. On the payout control board 37 side, data specifying the control state is not backed up and stored. Therefore, after that, when the power supply is restored, only the control state backed up and stored on the main board 31 side is effective. In addition, after the payout number subtraction process, after the award ball REQ signal is stopped due to the payout number subtraction process, the output of the payout command signal is stopped, and then it is confirmed that the BUSY signal is OFF in S241 of FIG. Otherwise, the prize ball transmission process is not executed, and the payout number signal and the prize ball REQ signal are not output, thereby prohibiting the output of the payout command signal until the payout BUSY signal is turned off. For this reason, when the supply of power to the gaming machine is stopped due to a power failure or the like in the middle of the execution of the payout control, the state in which the output of the payout command signal is stopped in accordance with the subtraction process is backed up and stored. Thus, when the power supply is restored, the payout control CPU 371 does not execute the payout process again from the beginning. Thereby, excessive payout of prize balls can be prevented.

  On the other hand, it is conceivable to back up and store data specifying the control state on both the main board 31 side and the payout control board 37 side. As compared with the configuration to be performed, there arises a problem that a circuit for supplying backup power, a program for performing processing for backing up data, and a storage area (storage capacity) of a memory (RAM) must be increased. If the data for specifying the control state is backed up and stored on both the main board 31 side and the payout control board 37 side in this way, the manufacturing cost of the gaming machine increases and the storage area of the memory (RAM) is compressed. Various inconveniences occur. In addition, in the pachinko machine and the slot machine, the size of the storage area (storage capacity) of the memory (RAM) is limited in order to easily detect that the control program has been illegally rewritten. Under the circumstances, it is practically impossible to increase the storage area (storage capacity) of the memory (RAM). Therefore, in this embodiment, a configuration in which the control state is backed up and stored only on the main board 31 side has been considered.

  (2) As shown in FIG. 33, when the prize ball REQ signal is output, the payout number signal is received by the payout control microcomputer, and the game control microcomputer outputs the payout number signal. The output of the payout command signal is stopped by stopping the output. Therefore, when the payout control microcomputer confirms whether or not the payout command signal is stopped, the presence or absence of the output of the prize ball REQ signal can be determined without checking the state of all the bits of the payout command signal. Since it is only necessary to confirm, it is not necessary to confirm in detail until the value of the number-of-payout signal is, so that the processing load on the payout control CPU 371 can be reduced.

  (3) As shown in FIG. 38, FIG. 43, and FIG. 44, after the output of the payout BUSY signal in response to the payout command signal is stopped based on the completion of the payout process (S554), the payout in the payout command signal When the output of the number signal does not stop even after a predetermined period has elapsed (S563Y), control for notifying the error display LED 374 that an abnormal state has occurred is executed (S564, S759). The game hall staff can recognize that such an abnormal state has occurred, and can prevent excessive payout of prize balls.

  (4) As shown in FIGS. 38, 42 and 43, after outputting a payout BUSY signal (ON state) as a reception confirmation signal in response to the payout command signal (S547), When the output of the prize ball REQ signal does not stop even after a predetermined period has passed (S551bY), control for notifying that an abnormal state has occurred is executed (S552, S759). Can recognize that such an abnormal state has occurred, and can prevent excessive payout of prize balls.

  (5) When the payout control microcomputer does not receive the power supply confirmation signal A, that is, when the game control microcomputer is not connected to the payout control microcomputer, the CPU 56 side displays the payout BUSY signal as the reception confirmation signal. The payout amount subtraction process according to reception cannot be performed. In such a case, since the payout process by the payout control CPU 371 is prohibited by returning as it is from S544 in the main control communication process of FIG. 42, there is an error in the storage information of the number of winning balls in the total winning ball number storage buffer. It can be prevented from occurring, thereby preventing excessive payout of prize balls.

  (6) As shown in FIG. 32, when the output of the payout BUSY signal as a payout processing signal in response to the payout command signal does not stop even after a predetermined period has passed (S277Y), that is, the game control micro When the communication between the computer and the payout control microcomputer is in an abnormal state, the CPU 56 is in a state in which the payout number subtraction process cannot be performed in response to reception of the payout BUSY signal as the reception confirmation signal. In such a case, as shown in FIGS. 32, 37, and 53, control is performed to indicate that such an abnormal state has occurred in each of the error display LED 374 and the variable display device 9. (S 279, S 280, S 686, 711 a, S 759), it is possible for the attendant at the game hall to recognize that the abnormal state has occurred, and to prevent excessive payout of prize balls.

  (7) When the CPU 56 has not received the power supply confirmation signal B, that is, when the payout control microcomputer is not connected to the game control microcomputer, the payout control CPU 371 receives the payout BUSY signal as the reception confirmation signal. The payout amount subtraction process according to reception cannot be performed. In such a case, the prize ball transmission process of FIG. 30 returns from S250 as it is and does not proceed to S254 and S255, so the payout control microcomputer side prohibits the output of the payout command signal and stores the total number of winning balls. It is possible to prevent an error from occurring in the stored information on the number of prize balls in the buffer, thereby preventing excessive prize balls from being paid out.

  (8) As shown in FIGS. 29 to 31, the CPU 56 outputs a payout BUSY signal as a reception confirmation signal in S241Y in a state in which the prize ball transmission process, which is a state in which no payout command signal is output, is not executed. When it is received, that is, when the communication between the game control microcomputer and the payout control microcomputer is abnormal, the payout number subtraction process according to the reception of the reception confirmation signal cannot be performed. In such a case, the process returns from S241 to S242 in the award ball waiting process 1 in FIG. 29, and does not proceed to the award ball transmission process in FIG. 30 and the award ball waiting process 2 in FIG. Since the subtracting process is prohibited, it is possible to prevent an error from occurring in the stored information of the number of winning balls in the total winning ball number storage buffer, thereby preventing excessive payout of the winning balls.

  Next, modifications and feature points of the embodiment described above are listed below.

  (1) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout means (for example, a ball payout device 97). A payout control board 37 on which a payout control CPU 371 and the like are mounted, and the game control means pays out the number of prize game media based on establishment of a predetermined payout condition (for example, winning of a game ball in a winning area) The command signal is transmitted to the payout control means, and the payout control means causes the payout means to pay out the commanded number of prize game media and pays out the commanded number of prize game media based on the receipt of the payout command signal. A game machine that transmits a payout completion signal to the game control means when the game ends. According to such a configuration, the game control means can recognize that the payout of the premium game medium has ended. In addition, the next payout command signal can be transmitted after receiving the payout completion signal, and the payout management of the number of prize game media is ensured.

  (2) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, a CPU 56) for controlling the progress of the game is mounted and a payout game medium (for example, a ball payout device 97). A payout control board 37 on which a payout control CPU 371 and the like are mounted, and a launching means (for example, a ball hitting device 99 including a launching motor 94) for launching a game medium toward the game area. Communication abnormality detection means for detecting an abnormality in communication of signals relating to the payout of game media between the means and the payout control means (for example, a part for detecting the power supply confirmation signal A being turned off in the payout control means or a prize ball REQ at an improper timing) A portion for detecting that the signal is turned off or on), and when the communication abnormality detecting means detects an abnormality, control for stopping the operation of the emitting means is performed. (Step S512, portions for performing the S518 in example payout control means) and a game machine including stop means. According to such a configuration, the operation of the launching unit can be stopped when a situation in which the game medium cannot be paid out occurs.

  (3) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout means (for example, a ball payout device 97). A payout control board 37 on which a payout control CPU 371 and the like are mounted, and a launching means (for example, a ball hitting device 99 including a launching motor 94) for launching a game medium toward the game area. A game controllable state detection unit (for example, a part for executing step S512 in the payout control unit) for detecting that the unit is in a controllable state (for example, the power confirmation signal A is turned on), and a game control unit When the game controllable state detecting means detects that the control means is in a controllable state, the firing control means (for example, the payout control means) that makes the firing means operable Gaming machine including a portion) and to perform a definitive step S515～S517. According to such a configuration, the game control means disables the launching means only by turning off the information for the payout control means indicating that the controllable state has been entered when it is desired to disable the firing means. be able to.

  (4) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout means (for example, a ball payout device 97). A payout control board 37 equipped with a payout control CPU 371 and the like, and the game control means stores the total number of prize game media to be paid out based on the establishment of the payout condition so that the total number of prize game media can be specified ( For example, a payout command signal for designating a predetermined number of prize game media to be paid out to the payout control means based on the number of prize game media stored in the prize game number storage buffer and the prize game medium number storage means. For example, a payout command signal transmission means (for example, a part of the game control means for executing the award ball transmission process of step S232), Command acceptance signal transmission means for transmitting a command acceptance signal (for example, turn-out of the payout BUSY signal) indicating that the outgoing command signal has been received to the game control means (for example, a part for executing the main control communication normal processing of step S531 in the payout control means) ), And the game control means further subtracts the payout number specified by the payout command signal from the number of prize game media stored in the prize game medium number storage means when receiving the command acceptance signal A game machine including a prize game medium number storage number subtraction means (for example, a portion of steps S261, S263, S264, and S265 in the game control means) for executing. According to such a configuration, it is possible to prevent a large number of prize balls from being illegally discharged by an illegal act of restoring the power supply after illegally stopping the power supply of the gaming machine during the prize ball payout. it can.

  (5) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout game medium (for example, a ball payout device 97). A payout control board 37 equipped with a payout control CPU 371 and the like, and payout detection means (for example, payout count switch 301) for detecting payout of premium game media and payout of rental game media by the payout means. A payout processing signal output means (for example, step S531, in the payout control means) that outputs a prize game medium payout processing signal (for example, a payout BUSY signal) to the game control means indicating that the prize game medium is being paid out. A portion for executing a main control communication normal process and a main control communication in-process in S532) A prize game medium payout signal (for example, a prize ball count signal) for making it possible to specify the number of prize game medium payouts on condition that a detection signal is input from the payout detection means during the output of the payout processing signal. And a signal output path (for example, a wiring pattern for outputting the output of the AND circuit 376 to the outside) for outputting a prize game medium payout signal to the outside of the gaming machine. A gaming machine provided. According to such a configuration, even when the payout detecting means detects both payout of premium game media and payout of rented game media, it is possible to easily generate a premium game media payout signal without intervention of software. it can.

  (6) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout game medium (for example, a ball payout device 97). When the supply of power to the payout control board 37 on which the payout control CPU 371 and the like are mounted and the gaming machine is stopped, at least the gaming state stored in the fluctuation data storage means (for example, RAM) is stored for at least a predetermined period. Fluctuation data storage means (for example, a backup RAM), and the game control means stores the total number of prize game media to be paid out based on the establishment of the payout condition, and also supplies power to the gaming machine. Including a prize game medium number storage means for storing the stored contents for at least a predetermined period of time by the variable data storage means when stopped, and the payout control means A volatile storage means (for example, a RAM area) is formed with a rental request from a gaming device (for example, the card unit 50) communicatively connected to the gaming machine and a payout number of premium game media designated by the game control means. In the prize game medium payout control means (for example, in the payout control means), the payout process is executed so that the payout means controls the payout means to pay out the prize game media stored in the volatile storage means. A gaming machine including a part for executing the payout control process in step S756. According to such a configuration, it is possible to prevent the player from being disadvantaged due to a power failure or the like by performing the power backup only in the game control means.

  (7) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout means (for example, a ball payout device 97). A payout control board 37 equipped with a payout control CPU 371 and the like, and a game control means for storing the total number of the prize game media to be paid out based on the establishment of the payout condition so as to be identifiable. A payout command signal that designates a payout number of a predetermined number (for example, a maximum of 15) of prize game media to the payout control means based on the number of prize game media stored in the prize game medium number storage means Including a command signal transmitting means, wherein the payout control means stores the payout number of the prize game medium designated by the payout command signal from the game control means (for example, formed in a RAM area). A prize game medium payout control means (for example, a payout control means step) executes a payout process for controlling the payout means to pay out premium game media of the number of payouts stored in the volatile storage means. A gaming machine including a part for executing the payout control process of S756. That is, the payout control means stores only the number of game media to be paid out in one prize ball payout. According to such a configuration, the storage capacity for storing the number of prize game media to be paid out can be reduced as a whole gaming machine.

  (8) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout game medium (for example, a ball payout device 97). The payout control board 37 on which the payout control CPU 371 and the like are mounted and the state of a predetermined power source used in the gaming machine are monitored, and a detection signal ( For example, when the power supply to the gaming machine is stopped, the gaming state stored in at least the fluctuation data storage unit (for example, RAM) is output when the power supply to the gaming machine is stopped. Fluctuation data storage means (for example, backup RAM) for storing at least a predetermined period, and a detection signal from the power supply monitoring means is an input port of the game control means The input and the game control means periodically confirms the input state of the input port by the power supply confirmation process arranged at a predetermined location in the control process (for example, the power interruption detection process in step S20), and the power monitoring means is applied to the input port. Power supply stop time processing means for executing power supply stop time processing, which is processing for storing information necessary for restoring the control state in the fluctuation data storage means in response to the detection signal from (For example, the part which performs step S452-S481 in a game control means). According to such a configuration, an act of illegally aiming for a big hit can be effectively prevented.

  (9) Constructed as in (8), and further, the game control means stops the power supply for saving the game state from the state of controlling the progress of the game in response to the input of the detection signal from the power supply monitoring means In addition to shifting to a state in which the time process is executed, when the detection signal is turned off after executing the process at the time of stopping power supply, the process returns to a state in which the progress of the game is controlled (for example, the processes in steps S482 and S483). Configured gaming machine. According to such a configuration, even if a power interruption occurs, the control of the progress of the game can be continued, and a disadvantage can be prevented from being given to the player.

  (10) A gaming machine configured as described in (8) or (9), and further having power supply monitoring means mounted on a main board. According to such a configuration, the game control means can quickly recognize the stop of power supply.

  (11) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout means (for example, a ball payout device 97). A payout control board 37 on which a payout control CPU 371 and the like are mounted, and the payout control means detects error relating to payout of game media (for example, steps S551, S563, S653, S661 of the payout control means, S691 and S692 are executed) and an error release signal (for example, an operation signal corresponding to the operation) is monitored from an error release switch means (for example, error release switch 375), and an error is detected after the error detection means detects an error. An error canceling means for canceling the error state when an input is detected in the cancel signal (for example, the payout control means Gaming machine including a portion) and executing the step S671～S677. According to such a configuration, the error is canceled when the payout control means recognizes the error release signal, so that the stored contents of the payout control means can be prevented from being cleared, and as a result It is possible to prevent the player from being disadvantaged by the switch operation.

  (12) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout means (for example, a ball payout device 97). A payout control board 37 equipped with a payout control CPU 371 and the like, and a launching means (for example, a ball hitting device 99 including a launching motor 94) for launching a game medium toward the game area. A gaming machine that performs drive control. According to such a configuration, it is possible to reduce the cost related to the game medium launch control.

  (13) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout means (for example, a ball payout device 97). A payout control board 37 on which a payout control CPU 371 and the like are mounted, and the payout control means executes drive state monitoring means for monitoring the operating state of the payout means (for example, the payout motor constant speed process in step S524 in the payout control means) 49, in particular, the part that executes the ball biting determination process illustrated in FIG. 49), and when the drive state monitoring means detects a malfunction (for example, ball biting) of the payout means, the drive of the payout means is stopped. A game machine including drive stop means (for example, a part for executing the ball-carrying-out payout motor brake process in step S526 in the payout control means). According to such a configuration, it is possible to prevent the payout means from being driven even though the game medium cannot be paid out by the payout means.

  (14) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56 or the like) for controlling the progress of the game is mounted and a payout game medium is paid out. A payout control board 37 equipped with a payout control CPU 371 and the like, and a payout detecting means (for example, a payout count switch 301) for detecting a game medium paid out from the payout means and outputting a payout detection signal. However, when it is detected on the basis of the payout detection signal from the payout detecting means that payout of a prize game medium that is less than the payout number has been made (for example, the process of step S653), a predetermined number of times (for example, 2), the payout means pays out the insufficient prize game media (for example, processing in steps S661 to S666). We made a game machine. According to such a configuration, it is possible to automatically recover a recoverable error regarding payout control and continue the game.

  (15) A payout control means (for example, a ball payout device 97) for controlling a main board 31 on which a game control means (for example, CPU 56) for controlling the progress of the game is mounted and a payout game medium (for example, a ball payout device 97). A payout control board 37 on which a payout control CPU 371 and the like are mounted, and an effect control board 80 on which effect control means (for example, the effect control CPU 101 and the like) that controls electric parts for effects provided in the gaming machine are mounted A game machine in which the production control means is configured to control a plurality of types of production electrical parts (for example, the variable display device 9, the speaker 27, and the lamp / LED). According to such a configuration, the cost of the gaming machine can be reduced as compared with the case where a plurality of effect control means for controlling each effect means is provided.

  (16) A payout control means (for example, a ball payout device 97) for controlling the main board 31 on which game control means (for example, the CPU 56) for controlling the progress of the game is mounted and a payout game medium (for example, a ball payout device 97). A payout control board 37 on which a payout control CPU 371 and the like are mounted, and the payout control means converts the value specified by the information recorded on the recording medium into a game use value that can be used for a game in a gaming machine. And a recording medium processing apparatus (for example, card unit 50) that performs processing for the purpose, and has a function of causing the payout means to pay out a rented game medium based on the game use value, and a payout control means and a recording medium processing apparatus. Are communicated via a relay board (for example, the interface board 66) different from the payout control board provided with the payout control means. Gaming machine. According to such a configuration, it is possible to prevent an abnormality occurring in the recording medium processing apparatus from being transmitted to the payout control board.

  (17) A payout control means (for example, a ball payout device 97) for controlling the main board 31 on which a game control means (for example, the CPU 56 or the like) for controlling the progress of the game is mounted and a payout game medium is paid out. A payout control board 37 equipped with a payout control CPU 371, etc., and the payout means has a function of paying out rental game media based on the loan request, and detects and rents the prize game media paid out from the payout means A gaming machine configured such that medium detection is performed by the same payout detection means. According to such a configuration, the number of parts is reduced and the cost of the gaming machine is reduced.

  In addition, even if the above configurations (1) to (17) are arbitrarily combined, a gaming machine that exhibits the effects based on the respective configurations can be configured.

  The game control means subtracts the number of unpaid prize game media in relation to transmission of the payout command signal (specifically, the payout BUSY signal is turned on in response to the transmission of the payout command signal) (step S261 in FIG. 31). , S263, S265), it is possible to minimize the disadvantage given to the player even if an unexpected power supply stoppage occurs due to a power failure or the like, and to effectively prevent fraud. In other words, the total award ball number storage buffer in which the number of unpaid prize game media is set is formed in the backup RAM in the game control means, so even if the power supply to the gaming machine is stopped, a predetermined period (backup power supply The content is saved within the duration), and when the power supply is restored, the game control means can restart the prize ball processing based on the saved contents of the total number of prize balls stored. That is, if the content of the stored total number of winning balls is not 0, a payout command signal can be output to the payout control means.

  For example, if the subtraction process for the number of unpaid prize game media is executed based on the receipt of the payout completion signal, the payout control means starts the payout based on the payout command signal and then sends a payout completion signal before sending a payout completion signal. The number of unpaid prize game media that have not been subtracted if an action is made to restore the power supply after the power supply is stopped or the game control means is illegally reset once. The prize ball payout is executed twice based on the above. However, if the subtraction process for the number of unpaid prize game media is executed based on the reception of the payout completion signal, the prize ball payout is not executed twice even if such an illegal act is performed.

  Further, in the above embodiment, the output of the payout count switch 301 is input only to the payout control board 37. Therefore, compared with the case where the output of the payout count switch 301 is supplied to both the main board 31 and the payout control board 37, the circuit configuration is simplified and the cost can be reduced.

  In the above embodiment, the payout control means is configured to output a control signal (payout BUSY signal) indicating that the payout process based on the prize ball REQ signal is being executed to the game control means. Therefore, the game control means can recognize that the payout process is being executed.

  Further, since the payout control means outputs a payout completion signal as a control signal indicating that the payout processing of the number of prize balls indicated by the payout number signal has been completed to the game control means, specifically, payout Since the BUSY signal is in the OFF state, the game control means can recognize that the payout process of the payout control means has ended.

  In addition, the game control means can output a control signal (power confirmation signal A) as a supply stop detection signal indicating that a power interruption has occurred in response to an input of a power interruption signal from the power monitoring circuit 920. The payout control means can recognize that the power cut has occurred. Specifically, when the power supply confirmation signal A is turned off, the supply stop detection signal is output.

  Also, the game control means is configured to output a control signal (power supply confirmation signal A) indicating that power supply to the gaming machine has started to the payout control means at the start of power supply. The payout control means can recognize that the power supply has started and the control operation of the game control means has started.

  In the above embodiment, the RAM provided on the payout control board 37 is not backed up by power, but a part or all of the RAM may be backed up by power as in the case of the main board 31.

  In the above embodiment, the payout request is made by the prize ball REQ signal and the payout number is specified by the payout number signal. However, the payout request and the payout number may be specified by the payout number signal. Good. In this case, the payout control means may determine that the payout request is made at the same time when the payout number signal is output. According to such a configuration, it is not necessary to use the prize ball REQ signal.

  In the above-described embodiment, the payout BUSY signal is output during the payout process of the winning ball. However, the payout BUSY signal may be output also during the payout process of the rental ball. If comprised in that way, it can recognize that the game control means is in a ball lending process. Therefore, the game control means can determine that an error has occurred when it is recognized that the ball lending process has been continuously executed for a predetermined period or longer based on the ON state of the payout BUSY signal.

  In the above embodiment, the payout control means determines that the prize ball payout has ended when it detects that the payout motor 289 has rotated by the planned payout number. However, the number of times detected by the payout motor position sensor is the expected payout number. If it reaches, it may be determined that the prize ball payout has ended. That is, the payout control means is configured to determine whether or not the payout is completed by detecting the operation amount of the payout means (in this example, the rotation amount of the payout motor 289 or the number of detections by the payout motor position sensor). May be.

  Further, in the above embodiment, the payout control unit checks whether or not the payout is completed based on the detection signal of the payout count switch 301, but the payout is completed based on the output signal of the payout motor position sensor. It may be confirmed whether or not.

  Also, the payout control means detects the operation amount of the drive means (for example, payout motor 289, cam, etc.) of the payout means and determines whether or not an abnormality related to payout (payout unit error) has occurred based on the detection. It may be configured to. With such a configuration, it is possible to reliably detect an abnormality relating to payout.

  In the above embodiment, the ball payout device 97 has a configuration capable of executing both ball lending and prize ball payout. However, even if the mechanism that lends the ball and the mechanism that pays out the prize ball are independent, The invention can be applied.

  In the above-described embodiment, the payout is prohibited when the ball is out of the ball or the lower pan is full. However, when it is not preferable to perform another payout or when the payout cannot be performed. You may set it in a payout prohibition state. For example, the payout prohibition state may be set also when the glass door frame 2 is in an open state and a detection signal is output from the door opening switches 161A and 161B.

  In each of the above-described embodiments, the recording medium used in the recording medium processing apparatus (card unit 50) is a magnetic card (prepaid card). However, the recording medium is not limited to a magnetic card, and is a non-contact type or a contact type. An IC card may be used. In addition, when the recording medium processing apparatus is configured to be able to identify the recording information based on the identification code, the recording medium can at least read the information such as the identification code that can identify the recording information. It may be something that can be recorded on. Further, the recording medium may be a medium on which a predetermined information recording symbol such as a barcode is printed so as to be readable. The shape of the recording medium is not limited to a card shape, and may be any shape such as a disk shape, a spherical shape, or a chip shape.

  The pachinko gaming machine of each of the above embodiments mainly gives a player a predetermined game value when a stop symbol of a special symbol variably displayed on the variable display unit 9 based on a start winning is a combination of a predetermined symbol It was a first type pachinko gaming machine that can be used, but if there is a winning in a predetermined area of an electric game that is released based on a start winning prize, a second type pachinko game that can give a predetermined gaming value to a player A third type of pachinko game where a predetermined right is generated or continued when there is a prize for a predetermined electric game that is released when the stop symbol of the pattern that is variably displayed based on the start winning prize becomes a combination of the predetermined pattern The present invention can be applied even to a machine.

  Further, the present invention is not limited to pachinko gaming machines in which the game medium is a game ball, and the slot machine or the like can be applied to the case where an electrical component for paying out the game medium is provided.

  Further, in the above-described embodiment, it has been described that the payout BUSY signal is lowered from the on state to the off state when the execution of the payout process (payout operation) for the number of payouts that has been commanded is completed. Therefore, such a fall of the payout BUSY signal indicates that the payout process executed after the output of the reception confirmation signal (the fall of the payout BUSY signal) output from the payout response signal output means is completed. The payout process end signal shown is included in a signal output by the payout response signal output means according to a change in the output state of a single signal.

  Also, the above-mentioned payout number signal abnormality notifying means (S564, S759, error display LED 374), payout command signal abnormality notifying means (S552, S759, error display LED 374), and payout processing signal abnormality notifying means (S279, Each of S280, S686, 711a, S759, the error display LED 374, and the variable display device 9) executes control for notifying that an abnormal state has occurred, but this control directly reports the abnormal state. However, the control may be control necessary for notifying the abnormal state, although it is not control for directly notifying the abnormal state.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is the rear view which looked at the mechanism board to which various members were attached from the game machine back side. It is the front view and sectional drawing which show a ball dispensing apparatus. It is a disassembled perspective view which shows a ball dispensing apparatus. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. FIG. 4 is a block diagram illustrating a configuration example of an effect control board, a lamp driver board, and an audio output board. It is a block diagram which shows the structural example of a power supply board. It is a block diagram which shows the structural example of a power supply board. It is a block diagram which shows CPU, a reset circuit, and a power supply monitoring circuit in a main board | substrate. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a power-off detection process. It is a flowchart which shows a power-off detection process. It is explanatory drawing which shows the example of formation of the switch timer in RAM. It is a flowchart which shows an example of a switch process. It is a flowchart which shows an example of a switch check process. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a flowchart which shows a prize ball process. It is explanatory drawing which shows the structural example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball waiting processing 1. It is a flowchart which shows a prize ball transmission process. It is a flowchart which shows the winning ball waiting process 2. FIG. It is a flowchart which shows prize ball waiting processing 3. It is a timing chart which shows the example of the output state of a control signal. It is explanatory drawing which shows the bit allocation example of the output port in the payout control microcomputer. It is explanatory drawing which shows the bit allocation example of the input port in the payout control microcomputer. It is a timing diagram for demonstrating communication between a prepaid card unit and a game machine. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a discharge motor control process. It is a flowchart which shows a payout motor control process. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control communication normal process. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a timing diagram for explaining a ball biting detection process. It is a timing diagram for demonstrating a ball biting cancellation | release process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a block diagram which shows an example of the output of a test signal. It is a timing diagram which shows the example of the output state of the signal for payout control in the conventional pachinko game machine.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Pachinko machine, 31 Game control board (main board), 97 ball payout device, 37 payout control board, 55 RAM, 56 CPU, 67 output circuit, 374 LED for error display, 9 Variable display device.

Claims (8)

A gaming machine that is capable of playing using a game medium and paying out a prize game medium as a prize based on the fact that a payout condition is established by the game,
A game control microcomputer for controlling the progress of the game and transmitting a payout command signal for specifying the payout number of the prize game medium and instructing the payout of the prize game medium;
A payout means for receiving the payout command signal and paying out the prize game medium of the payout number specified by the received payout command signal;
A payout control microcomputer for controlling the payout means,
The game control microcomputer and the payout control microcomputer perform two-way communication,
The game control microcomputer is:
Backup storage means for backing up and storing data for specifying a control state including an output state of the payout command signal by the game control microcomputer when power supply to the gaming machine is stopped;
Control state recovery means for recovering a control state including an output state of the payout command signal by the game control microcomputer based on data stored in the backup storage means when power supply to the gaming machine is recovered When,
A payout number storage means for storing information included in the backup storage means and capable of specifying the number of premium game media to be paid out based on establishment of the payout condition;
A payout command signal output means for outputting the payout command signal to the payout control microcomputer based on the payout number stored in the payout number storage means;
A payout memory number subtracting means for performing a subtraction process for subtracting the payout number specified by the payout command signal from the payout number stored in the payout number storage means;
The payout control microcomputer includes:
A means for storing data for specifying a control state by the payout control microcomputer, and a payout control storing means for storing the data in a backup when power supply to the gaming machine is stopped;
A prize game medium payout control means for controlling the payout means to execute a payout process for paying out a prize game medium of the number of payouts specified by the payout command signal;
A means for outputting a signal to the game control microcomputer, and in response to receiving the payout command signal, a reception confirmation signal indicating that the payout command signal has been received, and after outputting the reception confirmation signal A payout response signal output means for outputting a payout process in progress signal indicating that the payout process is being executed according to a change in the output state of a single signal;
The payout memory number subtraction means includes a subtraction means at the time of reception that performs the subtraction process when the game control microcomputer receives the reception confirmation signal,
When the game control microcomputer receives the reception confirmation signal, after stopping the output of the payout command signal, the game control microcomputer has a remaining payout number stored in the payout number storage means after the subtraction process. Even so, the gaming machine further includes payout command signal prohibiting means for prohibiting the output of the next payout command signal until the output of the payout processing signal stops. The payout command signal output means, as means for outputting the payout command signal, a payout number signal output means for outputting a payout number signal for designating the number of payouts of the game medium, and reception for requesting reception of the payout number signal. Receiving request signal output means for outputting a request signal,
The payout control microcomputer receives the payout number signal by outputting the reception request signal,
2. The gaming machine according to claim 1, wherein the game control microcomputer stops outputting the payout command signal by stopping outputting the reception request signal in a state where the payout number signal is output. . The payout control microcomputer includes:
A payout response signal stop means for stopping the output of the payout processing signal when the execution of the payout process is completed;
After the output of the payout processing signal is stopped by the payout response signal stop unit, an abnormality occurs when the output of the payout number signal by the payout number signal output unit does not stop even after a predetermined period has elapsed. The gaming machine according to claim 2, further comprising payout number signal abnormality notifying means for executing control for notifying that a state has occurred. When the payout control microcomputer outputs the reception confirmation signal by the payout response signal output means, the output of the payout command signal by the payout number signal output means does not stop even after a predetermined period of time has passed. 4. A gaming machine according to claim 1, further comprising payout command signal abnormality notifying means for executing control for notifying that a state has occurred. The game control microcomputer receives a game control connection confirmation signal indicating that the game control microcomputer is connected to the payout control microcomputer when power is supplied to the gaming machine. It further includes a game control connection confirmation signal output means for outputting to the microcomputer,
The payout control microcomputer further includes payout processing prohibiting means for prohibiting the payout processing by the prize game medium payout control means when the game control connection confirmation signal is not received. The gaming machine according to any one of 1 to 4. The game control microcomputer has a payout processing signal abnormality notifying means for executing control for notifying that an abnormal state has occurred when the output of the payout processing signal does not stop even after a predetermined period of time has elapsed. The game machine according to claim 1, further comprising: The payout control microcomputer receives a payout control connection confirmation signal indicating that the payout control microcomputer is connected to the game control microcomputer when power is supplied to the gaming machine. It further includes payout control connection confirmation signal output means for outputting to the microcomputer,
The game control microcomputer further includes payout control connection confirmation signal prohibiting means for prohibiting output of the payout command signal by the payout command signal output means when the payout control connection confirmation signal is not received. A gaming machine according to any one of claims 1 to 6. The game control microcomputer further includes subtraction processing prohibiting means for prohibiting the subtraction processing by the payout memory number subtracting means when the reception confirmation signal is received in a state where the payout command signal is not output. The gaming machine according to any one of claims 1 to 7, characterized in that it is a feature.

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