JP2006140682A - Carrier phase synchronizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently improve deterioration in BER characteristic caused by phase noise in a multi-valued QAM environment by effectively using frequency resources. <P>SOLUTION: A carrier phase synchronizing circuit includes a 1st APC circuit which inputs a quadrature demodulated received signal and outputs a 1st received signal with its carrier phase error estimated and compensated and a 1st phase error signal indicating phase synchronism precision, a 2nd APC circuit which has different carrier phase compensation characteristics from the 1st APC circuit, inputs a quadrature demodulated received signal, and outputs a 2nd received signal with its carrier phase error estimated and compensated and a 2nd phase error signal indicating phase synchronism precision, a comparing circuit which inputs the 1st and the 2nd phase error signals and makes a large-small comparison between them, and a selecting circuit which selects and outputs a received signal having higher phase synchronism precision between the 1st and the 2nd received signals with the carrier phase errors compensated according to the result of the comparison between the phase error signals by the comparing circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a carrier phase synchronization circuit that reduces deterioration of a bit error rate (BER) characteristic caused by a carrier synchronization error in a receiver in an amplitude phase modulation system or a phase modulation system.

  In digital communication, a QAM (Quadrature Amplitude Modulation) system that expresses information using two orthogonal amplitude modulation signals can efficiently transfer data with a limited bandwidth. In the QAM system, the number of bits per symbol can be increased by superimposing and transmitting information not only on the phase direction but also on the amplitude level of the in-phase / quadrature components, and CATV and FWA, which require high-speed communication. (Fixed Wireless Access) and other fields.

  In the QAM system, a signal that is synchronized in frequency and phase with a local oscillator on the transmitter side is reproduced on the receiver side, and demodulation using synchronous detection is performed to obtain a baseband in-phase / quadrature signal. At this time, if the phase synchronization of the transmission and reception local signals (hereinafter referred to as “carrier phase synchronization”) is insufficient, the arrangement of the demodulated signals is obtained by rotating from a predetermined position. For example, when a phase rotation of 15 degrees occurs in 16QAM, the signal points are arranged as shown in FIG. If such a phase rotation occurs when there is a phase error, the distance (identification margin) from the received signal to the threshold value decreases, and the BER characteristics deteriorate.

  The deterioration of the BER characteristic due to the carrier phase synchronization error becomes remarkable as the modulation multi-level number increases. Specifically, in 16QAM shown in FIG. 4 and 64QAM shown in FIG. 5, when the phase of the outermost signal point and the signal point adjacent thereto are compared, the phase difference between signal points 401 and 402 is 26.6 degrees in 16QAM. On the other hand, in 64QAM, the phase difference between signal points 501 and 502 decreases to 9.5 degrees. For this reason, it is necessary to perform carrier phase synchronization with higher accuracy as the degree of multi-level amplitude increases.

By the way, as a factor that degrades the accuracy of carrier phase synchronization, there is fluctuation of local oscillation frequency (phase noise) in a transceiver. The received signal r (t) on which the phase noise φ (t) is superimposed is obtained by using the in-phase / quadrature component modulation signals i (t) and q (i), the angular frequency ω, the time t, and the white noise n (t). , R (t) = i (t) cos (ωt + φ (t)) − q (t) sin (ωt + φ (t)) + n (t) (1)
Given by. For example, a received signal of 64QAM has a form in which the original signal point spreads in the phase direction due to the influence of phase noise as shown in FIG. Usually, the band of the phase noise φ (t) is about several tens to several hundreds of kHz, and an influence appears as a gradual phase change in high-speed communication with a symbol rate of several MHz or more.

  Application of an automatic phase control (APC) circuit is effective for carrier phase synchronization of a received signal including phase noise. The APC circuit realizes carrier phase error compensation by sequentially calculating and correcting the phase difference from the received signal after phase compensation and the signal point after symbol determination. However, although the APC circuit can stably and highly accurately compensate for the carrier phase that varies gently with respect to the symbol rate, the accuracy of the carrier phase compensation of the APC circuit decreases as the phase variation increases. Therefore, depending on the frequency band of the phase noise, there is a problem that sufficient phase synchronization cannot be realized only by the APC circuit.

  On the other hand, a method of reducing phase noise by using it together with an APC circuit has been proposed (Non-Patent Document 1). Conventionally, as shown in FIG. 9, the threshold value 901 of the signal point is represented by a straight line on the in-phase / orthogonal plane so that the symbol determination error characteristic with respect to thermal noise is the best. The proposed approach replaces the signal point threshold 901 with a curve 902 that is determined to be best from both thermal and phase noise aspects. Here, the line representing the threshold becomes wider so as to increase the identification margin in the phase direction as the amplitude increases. Thereby, it is possible to optimize the symbol determination under the environment of thermal noise and phase noise by changing only the receiver side, and the BER characteristics can be improved.

As another compensation method for phase noise, a system including a transmitter 200 and a receiver 210 shown in FIG. 10 has been proposed (Non-Patent Document 2). 10, the transmitter 200 includes a local oscillator 201, an intermediate frequency band signal input terminal 202, a mixer 203, a bandpass filter 204, an amplifier 205, and an antenna 206. The receiver 210 includes an antenna 211, an amplifier 212, a band-pass filter 213, a mixer 214, and an output terminal 215 for intermediate frequency band signals. The transmitter 200 transmits the local signal a on the transmission side simultaneously with the modulated signal b, and the receiver 210 performs down-conversion by square-detecting the received signal without using a local oscillator. As a result, demodulation using a reference signal including exactly the same phase noise as that included in the local signal becomes possible, and the phase noise can be completely canceled.
Takuya Kurakake et al., QAM Symbol Judgment Method to Reduce the Effect of Phase Noise, 2003 IEICE Communication Society Conference, B-8-8, 2003 Yozo Shoji et al., Proposal of millimeter-wave self-heterodyne communication system, IEICE technical report, RCS2000-30, 2000

  In the method of Non-Patent Document 1, the optimum threshold value changes due to a change in the relative value of the white noise level and the phase noise level. Therefore, it has been difficult to make an optimal design. In addition, by distorting the threshold value in order to enhance the characteristics against phase noise, there is a problem that the BER characteristics against thermal noise deteriorates and a large improvement effect cannot be obtained.

  In the method of Non-Patent Document 2, since the phase noise information of the local oscillator on the transmission side is directly transmitted, a frequency band for transmitting the local signal (a in FIG. 10) is required separately. Therefore, it has been difficult to apply to a region where frequency resources are limited.

  An object of the present invention is to provide a carrier phase synchronization circuit that can efficiently improve the deterioration of BER characteristics caused by phase noise in a multilevel QAM environment by effectively using frequency resources.

  According to a first aspect of the present invention, a first received signal obtained by inputting a quadrature demodulated received signal and estimating / compensating a carrier phase error, and a first APC circuit that outputs a first phase error signal representing phase synchronization accuracy are provided. The carrier phase compensation characteristic is different from that of the first APC circuit, the orthogonally demodulated received signal is input, and the second received signal obtained by estimating and compensating the carrier phase error and the second phase error signal indicating the phase synchronization accuracy are output. The second APC circuit, the comparison circuit for inputting the first phase error signal and the second phase error signal and comparing the magnitudes thereof, and the carrier phase according to the comparison result of each phase error signal in the comparison circuit A selection circuit configured to select and output a received signal having a higher phase synchronization accuracy out of the first received signal and the second received signal in which the error is compensated;

  The first invention is characterized in that two APC circuits having a low correlation of carrier phase compensation characteristics are used, and an APC circuit output having a higher phase synchronization accuracy is selected at any time. In an APC circuit that performs carrier phase compensation that is independent of each other, even if one of the synchronization states deteriorates and the BER characteristic deteriorates, the other may be normally synchronized. For this reason, the APC circuit with higher phase synchronization accuracy can be selected, bit errors due to the carrier phase can be avoided, and the BER characteristics can be improved.

  According to a second aspect of the present invention, a digital signal to which redundant bits for error correction are added is received on the transmission side, a reception signal obtained by orthogonal demodulation is input, and a first reception signal in which carrier phase error is estimated and compensated is output. A first APC circuit having a carrier phase compensation characteristic different from that of the first APC circuit, receiving a quadrature demodulated received signal, and outputting a second received signal in which a carrier phase error is estimated and compensated; The first symbol determination circuit that performs symbol determination of the first reception signal, the second symbol determination circuit that performs symbol determination of the second reception signal, and the reception signal that has been subjected to symbol determination by the first symbol determination circuit A first error correction circuit that outputs a first error correction enable / disable signal indicating whether or not the number of errors in the received signal is within a correctable range, and a second symbol determination circuit A second error correction circuit that performs error correction on the received signal determined as a symbol and outputs a second error correction enable / disable signal indicating whether or not the number of errors in the received signal is within a correctable range; 1 error correction enable / disable signal and 2nd error correction enable / disable signal are input, and when either one indicates error correction enable, a selection signal for selecting a reception signal error-corrected by the error correction circuit is output, When both indicate that error correction is possible or when both indicate error correction failure, a determination circuit that outputs a selection signal for selecting a reception signal that has been error-corrected by the first error correction circuit, and a determination circuit that outputs the selection signal A selection circuit that selects and outputs the received signal that has been error-corrected by the first error correction circuit or the second error correction circuit in accordance with the selection signal.

  The second invention is characterized in that an error correction circuit is used as means for representing the phase synchronization accuracy of the APC circuit in the first invention. The error correction circuit has a function of correcting an error that has occurred and a function of detecting an error that cannot be corrected. Thus, the error correction availability signal output from the error correction circuit can be used as an index representing the phase synchronization state in the APC circuit. In the present invention, this is used to select the APC circuit with higher phase synchronization accuracy.

  In the first and second inventions, the first APC circuit has a carrier phase compensation characteristic having a high tracking characteristic with respect to phase fluctuation, and the second APC circuit is a carrier having a low tracking characteristic with respect to phase fluctuation. The configuration has phase compensation characteristics.

  The APC circuit can set the phase error band that can be compensated by the tracking parameter. An APC circuit with a large follow-up parameter is strong against phase changes with fast fluctuations, and an APC circuit with a small follow-up parameter is strong against phase changes with slow fluctuations. By utilizing this, the correlation between the carrier phase compensation characteristics of the two APC circuits can be reduced.

  The present invention can reduce bit errors caused by phase noise by using two APC circuits having a small correlation of carrier phase compensation characteristics and selecting an APC circuit with higher phase synchronization accuracy. This makes it possible to use an inexpensive oscillator that does not necessarily have good phase noise characteristics, and can reduce the cost of the digital communication system.

(First embodiment)
FIG. 1 shows a first embodiment of the carrier phase synchronization circuit of the present invention. In the figure, a received signal whose carrier frequency offset is compensated is input to two APC circuits 101 and 102 having different carrier phase compensation characteristics. The APC circuits 101 and 102 output a reception signal compensated for the carrier phase error and a phase error signal representing the phase synchronization accuracy. The comparison circuit 107 receives the phase error signals output from the APC circuits 101 and 102, respectively, and compares the magnitudes thereof. The selection circuit 108 receives the reception signal compensated for the carrier phase error output from the APC circuits 101 and 102, and receives the signal having the higher phase synchronization accuracy according to the comparison result of each phase error signal in the comparison circuit 107. Select to output.

  The APC circuits 101 and 102 estimate and compensate for the phase fluctuation caused by the carrier phase and the residual carrier frequency offset, and the phase fluctuation caused by the phase noise. Here, assuming the application of the LMS (Least Mean Square) algorithm, the operation of the APC circuit in that case will be described with reference to FIG. In this embodiment, 64QAM is applied.

  The received signal 701 input to the APC circuit is compensated for the phase by the phase estimation value 702 at that time, and becomes a received signal 703. The phase-compensated received signal 703 is determined to be the closest 64QAM signal 704, and a phase error 705 from the received signal 703 is calculated using this signal as a reference signal. This is multiplied by the step size parameter indicating the tracking characteristic, and the estimated value of the phase is updated. Phase compensation is realized by sequentially repeating this operation. However, since the APC circuit does not operate correctly before the symbol synchronization is correctly established after the symbol synchronization is established, a known signal is used instead of the reference signal 704 after the symbol determination in the initial pull-in stage. Further, the step size parameters of the APC circuits 101 and 102 are different from each other, and the carrier phase compensation characteristics are independent from each other.

  Through the above procedure, the APC circuits 101 and 102 each output a reception signal compensated for the carrier phase error, and also output a phase error signal that is the difference between the phase-compensated reception signal 703 and the reference signal 704. The comparison circuit 107 compares the phase error signals output from the APC circuits 101 and 102, respectively, and outputs a selection signal for selecting a signal indicating the one with higher phase synchronization accuracy. The selection circuit 108 selects and outputs the reception signal with higher phase synchronization accuracy among the reception signals output from the APC circuits 101 and 102 according to the selection signal output from the comparison circuit 107. Thereby, an APC circuit with high carrier phase synchronization accuracy can be selected at any time, and BER characteristics can be improved.

(Second Embodiment)
FIG. 2 shows a second embodiment of the carrier phase synchronization circuit of the present invention. In the figure, the received signal whose carrier frequency offset is compensated is input to two APC circuits 101 and 102 having different carrier phase compensation characteristics. The APC circuits 101 and 102 output the received signal compensated for the carrier phase error, and the symbol determination circuits 103 and 104 determine the closest symbol among the signal points in 64QAM. The received signals subjected to symbol determination are input to error correction circuits 105 and 106, respectively. The error correction circuits 105 and 106 perform error correction of the received signal determined as a symbol and output an error correction enable / disable signal indicating whether or not error correction is possible. The decision circuit 109 receives and compares the error correction availability signals output from the error correction circuits 105 and 106, respectively. The selection circuit 108 receives the reception signals output from the error correction circuits 105 and 106, selects the reception signal with higher phase synchronization accuracy according to the determination result of each error correction enable / disable signal in the determination circuit 109. Output.

  In this embodiment, a Reed-Solomon code is used as the error correction code. The 64QAM signal encoded in the Reed-Solomon code on the transmission side is compensated for the carrier frequency offset after being received, and is input to the APC circuits 101 and 102. The APC circuits 101 and 102 estimate and compensate for the phase fluctuation caused by the carrier phase and the residual carrier frequency offset, and the phase fluctuation caused by the phase noise. Here, as in the first embodiment, an LMS algorithm with a different step size parameter is applied, and a received signal after phase compensation is output.

The received signals subjected to symbol determination by the symbol determination circuits 103 and 104 are error-corrected by error correction circuits 105 and 106. At this time, the error correction circuits 105 and 106 output an error correction enable / disable signal indicating whether or not the number of errors included in the received signal is within a correctable range. The error correction availability signal is “1” when there is no error in the symbol-determined received signal or when all errors can be corrected, and “0” otherwise. Whether or not error correction is correctly performed is determined by calculating a syndrome that is a vector representing an error pattern. If the received signal is Y and the check matrix is H, the syndrome S is
S = YH ^t (2)
Is calculated by Note that the subscript t represents transposition of the matrix. When equation (2) is applied to the received signal after error correction, if there is no error in the received signal after error correction, the syndrome is 0 vector, so it is determined whether the error has been corrected or not. Can do.

  The determination circuit 109 compares the accuracy of carrier phase compensation based on the determination result of the error correction availability signal output from the error correction circuits 105 and 106. Here, an operation when the APC circuit 101 is a master and the APC circuit 102 is a slave will be described. First, an error correction enable / disable signal output from the error correction circuit 105 is determined, and if there is no error in the received signal output from the APC circuit 101, or if error correction is possible, the error correction circuit 105 A signal for selecting a reception signal to be output is output. On the other hand, when an error that cannot be corrected has occurred in the APC circuit 101, an error correction enable / disable signal output from the error correction circuit 106 is determined. At this time, if there is no error in the reception signal output from the APC circuit 102 or if error correction is possible, a signal for selecting the reception signal output from the error correction circuit 106 is output. In addition, when an error that cannot be corrected in both has occurred, a signal for selecting a reception signal output from the error correction circuit 105 corresponding to the master APC 101 is output. The selection circuit 108 selects and outputs one of the reception signals output from the error correction circuits 105 and 106 according to the selection signal output from the determination circuit 109.

  By performing such a selection process, the BER characteristic equivalent to the case where the APC circuit 101 is used alone can be obtained at worst. If bit errors of APC circuits 101 and 102 occur independently, it is possible to select a received signal with higher phase synchronization accuracy, so that the BER characteristics can be improved.

FIG. 8 shows BER characteristics when the carrier phase synchronization circuit of the present invention is applied to 64QAM. Here, a VLMS (Variable-gain Least Mean Squares) algorithm is applied to the APC circuits 101 and 102, and the step size parameters are 0.15 and 0.05, respectively. For comparison, the BER characteristics when the APC circuits 101 and 102 are used alone are also shown. According to this, in the high CNR region where error correction is effective, the characteristics of selecting the received signal with the higher phase synchronization accuracy as in the present embodiment is improved as compared with the case where a single APC circuit is used. I understand that. For example, paying attention to the point where the BER is 10 ⁻³ , it is possible to achieve the same effect as when the CNR is improved by 0.5 dB.

The figure which shows 1st Embodiment of the carrier phase synchronizing circuit of this invention. The figure which shows 2nd Embodiment of the carrier phase synchronizing circuit of this invention. The figure which shows the state which produced the phase error of 15 degree | times in the signal point arrangement | positioning of 16QAM. The figure which shows the signal point arrangement | positioning of 16QAM. The figure which shows the signal point arrangement | positioning of 64QAM. The figure which shows typically signal point arrangement | positioning of 64QAM containing phase noise. The figure which shows typically the structure of the carrier phase compensation by a LMS algorithm. The figure which shows the BER characteristic at the time of applying the carrier phase synchronizing circuit of this invention to 64QAM. The figure which shows the threshold value of 64QAM in a conventional method. The figure which shows the structural example of the transmitter / receiver in the conventional method.

Explanation of symbols

101, 102 Automatic phase control (APC) circuit 103, 104 Symbol determination circuit 105, 106 Error correction circuit 107 Comparison circuit 108 Selection circuit 109 Determination circuit 200 Transmitter 201 Local oscillator 202 Intermediate frequency band signal input terminal 203, 214 Mixer 204, 213 Band pass filter 205, 212 Amplifier 206, 211 Antenna 210 Receiver 215 Intermediate frequency band signal output terminal 401, 402 16QAM signal point 501, 502 64QAM signal point 701 Received signal before phase compensation in APC circuit 702 Estimated value of carrier phase by LMS algorithm 703 Received signal compensated for carrier phase by LMS algorithm 704 Symbol determined signal point 705 Residual carrier phase

Claims (3)

In a carrier phase synchronization circuit that compensates for a carrier phase error in a quadrature demodulated received signal, the first received signal is input, and the first received signal that is estimated and compensated for the carrier phase error, and a first phase error that represents the phase synchronization accuracy A first automatic phase control circuit for outputting a signal;
The carrier phase compensation characteristic is different from that of the first automatic phase control circuit, the received signal is input, and the second received signal obtained by estimating and compensating the carrier phase error and the second phase error signal indicating the phase synchronization accuracy are output. A second automatic phase control circuit,
A comparison circuit that inputs the first phase error signal and the second phase error signal and compares the magnitudes thereof;
According to the comparison result of each phase error signal in the comparison circuit, the received signal having the higher phase synchronization accuracy is selected from the first received signal and the second received signal compensated for the carrier phase error. A carrier phase synchronization circuit comprising: a selection circuit for outputting. In the carrier phase synchronization circuit that receives a digital signal with redundant bits for error correction on the transmission side and compensates for the carrier phase error of the orthogonally demodulated reception signal,
A first automatic phase control circuit that inputs the received signal and outputs a first received signal in which a carrier phase error is estimated and compensated;
A second automatic phase control circuit that has a carrier phase compensation characteristic different from that of the first automatic phase control circuit, inputs the received signal, and outputs a second received signal in which a carrier phase error is estimated and compensated;
A first symbol determination circuit that performs symbol determination of the first received signal;
A second symbol determination circuit for performing symbol determination of the second received signal;
A first error correction enable / disable signal indicating whether or not the number of errors in the received signal is within a correctable range is output while performing error correction on the received signal determined by the first symbol determining circuit. 1 error correction circuit;
A second error correction enable / disable signal indicating whether or not the number of errors in the received signal is within a correctable range is output while performing error correction on the received signal determined by the second symbol determining circuit. Two error correction circuits;
The first error correction enable / disable signal and the second error correction enable / disable signal are input, and when either one indicates error correction enable, a selection signal for selecting a received signal error-corrected by the error correction circuit is provided. A determination circuit that outputs a selection signal for selecting a reception signal that has been error-corrected by the first error correction circuit when both output indicate error correction possible or both indicate error correction failure;
A selection circuit that selects and outputs a reception signal that has been error-corrected by the first error correction circuit or the second error correction circuit in accordance with a selection signal output from the determination circuit. Carrier phase synchronization circuit. In the carrier phase synchronization circuit according to claim 1 or 2,
The first automatic phase control circuit is configured to have a carrier phase compensation characteristic with a high follow-up characteristic with respect to phase fluctuations,
The carrier phase synchronization circuit, wherein the second automatic phase control circuit has a carrier phase compensation characteristic having a low follow-up characteristic with respect to phase fluctuation.

Images