JP2006140337A

JP2006140337A - Mos semiconductor device and its manufacturing method

Info

Publication number: JP2006140337A
Application number: JP2004329108A
Authority: JP
Inventors: Osamu Sasaki; 修佐々木
Original assignee: Fuji Electric Device Technology Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2004-11-12
Filing date: 2004-11-12
Publication date: 2006-06-01

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS semiconductor device which can deal with a process of making the diameter of a wafer large and with a process of making a design rule fine, and which is isolated from a semiconductor substrate. <P>SOLUTION: The MOS semiconductor device comprises a first conductive epitaxial layer 3 selectively deposited and formed on a first conductive semiconductor substrate 1, a second conductive embedded diffusion layer 2 selectively formed between the semiconductor substrate 1 and the first conductive epitaxial layer 3, a second conductive well layer 4 diffused and formed so as to reach the embedded diffusion layer 2 from the surface of the epitaxial layer 3, a first conductive well layer 5 diffused and formed in the second conductive well layer 4, a second conductive source layer 6 and a second conductive drain layer 7 diffused and formed in the first conductive well layer 5, and a gate electrode 9 formed between the source layer 6 and the drain layer 7 via a gate insulating film 8. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はＭＯＳ半導体装置に関し、詳しくは、半導体基板から電気的に分離されたＭＯＳ半導体装置およびその製造方法に関する。 The present invention relates to a MOS semiconductor device, and more particularly to a MOS semiconductor device electrically isolated from a semiconductor substrate and a method for manufacturing the same.

図２の断面図に示すように、Ｐ型半導体基板１１を用いた場合はＰ型ＭＯＳトランジスタはＮ型ウェル層１４の中にＰ型ソース層およびドレイン層１７とゲート電極１８を形成し、Ｎ型ＭＯＳトランジスタはＰ型半導体基板１１にＮ型ソース層およびドレイン層１６とゲート電極１９を形成している。そのために、Ｐ型半導体基板の場合は、Ｐ型半導体基板の電位とＮ型ＭＯＳトランジスタのサブストレート電位が同電位となるため、Ｎ型ＭＯＳトランジスタのサブストレート電位を高い電位で使用する回路構成が不可能である。
そこで、図３に示したようなＮ型ウェル層２４の中にＰ型ウェル層２５を形成するトリプルウェル構造にすることで、Ｎ型ＭＯＳトランジスタのサブストレート電位を高い電位で使用する回路構成が可能であるが、寄生ＰＮＰトランジスタ（Ｐ型ウェル層２５−Ｎ型ウェル層２４−Ｐ型半導体基板２１）構造となるため、Ｐ型ウェル層２５−Ｐ型半導体基板２１の分離耐圧はベースとなるＮ型ウェル層２４の不純物総量に大きく依存し、不純物総量が少ないと分離耐圧が低いという問題がある。Ｎ型ウェル層２４を高不純物総量でかつ深い構造とすれば、高い分離耐圧が得られるが、いずれも微細なパターンプロセスが要求されるＭＯＳ半導体装置を含む半導体集積回路装置では困難である。 As shown in the cross-sectional view of FIG. 2, when a P-type semiconductor substrate 11 is used, a P-type MOS transistor forms a P-type source layer and drain layer 17 and a gate electrode 18 in an N-type well layer 14. In the MOS transistor, an N-type source / drain layer 16 and a gate electrode 19 are formed on a P-type semiconductor substrate 11. Therefore, in the case of a P-type semiconductor substrate, since the potential of the P-type semiconductor substrate and the substrate potential of the N-type MOS transistor are the same potential, there is a circuit configuration that uses the substrate potential of the N-type MOS transistor at a high potential. Impossible.
Therefore, by adopting a triple well structure in which the P-type well layer 25 is formed in the N-type well layer 24 as shown in FIG. 3, a circuit configuration that uses the substrate potential of the N-type MOS transistor at a high potential is obtained. Although possible, since the structure is a parasitic PNP transistor (P-type well layer 25-N-type well layer 24-P-type semiconductor substrate 21), the isolation breakdown voltage of the P-type well layer 25-P-type semiconductor substrate 21 is the base. This greatly depends on the total amount of impurities in the N-type well layer 24. If the total amount of impurities is small, the isolation breakdown voltage is low. If the N-type well layer 24 has a high total impurity amount and a deep structure, a high isolation breakdown voltage can be obtained, but both are difficult in a semiconductor integrated circuit device including a MOS semiconductor device that requires a fine pattern process.

前記トリプルウェル構造を有するＭＯＳトランジスタにおける寄生ＰＮＰトランジスタによる問題を解決するために、従来技術では図４に示したように、Ｐ型半導体基板３１にＮ型埋込拡散層３２を形成し、その上にＰ型エピタキシャル層３３を形成する。このようなウェハを使用し、Ｎ型分離拡散層３９をエピタキシャル層３３表面より拡散して、Ｐ型エピタキシャル層３３をＰ型半導体基板３１より分離し、その中にＮ型ＭＯＳトランジスタを形成することで、Ｎ型埋込拡散層３２およびＮ型分離拡散層３９の不純物濃度を高く形成できるため、寄生トランジスタのベースの不純物濃度を高くして分離耐圧を高くしていた。
また、従来技術の異なる方法として図５に示したように、Ｐ型半導体基板４１にＮ型エピタキシャル層４３を形成する。このようなウェハを使用し、Ｐ型分離拡散層４９をＮ型エピタキシャル層４３表面より拡散して、Ｎ型エピタキシャル層４３をＰ型半導体基板４１より分離し、その中にＮ型ＭＯＳトランジスタを形成することで、寄生ＰＮＰトランジスタのベースの実行距離を広くして分離耐圧を高くしていた。 In order to solve the problem caused by the parasitic PNP transistor in the MOS transistor having the triple well structure, the N-type buried diffusion layer 32 is formed in the P-type semiconductor substrate 31 as shown in FIG. A P-type epitaxial layer 33 is formed. Using such a wafer, the N type isolation diffusion layer 39 is diffused from the surface of the epitaxial layer 33, the P type epitaxial layer 33 is separated from the P type semiconductor substrate 31, and an N type MOS transistor is formed therein. Thus, since the impurity concentration of the N-type buried diffusion layer 32 and the N-type isolation diffusion layer 39 can be formed high, the impurity concentration at the base of the parasitic transistor is increased to increase the isolation breakdown voltage.
Further, as shown in FIG. 5 as a method different from the prior art, an N-type epitaxial layer 43 is formed on a P-type semiconductor substrate 41. Using such a wafer, the P-type isolation diffusion layer 49 is diffused from the surface of the N-type epitaxial layer 43 to separate the N-type epitaxial layer 43 from the P-type semiconductor substrate 41, and an N-type MOS transistor is formed therein. As a result, the execution distance of the base of the parasitic PNP transistor is increased to increase the isolation breakdown voltage.

さらに、前記図３のトリプルウェルＭＯＳトランジスタにおける寄生ＰＮＰトランジスタによる問題を解決するために、図６に示すように、Ｎ型ウェル層領域５８内にＰ型ウェル層領域５２が形成され、Ｐ型ウェル層領域５２にＭＯＳＦＥＴが形成されたトリプルウェルＮＭＯＳトランジスタにおいて、Ｎドレイン領域５５側にＮドレイン領域よりも不純物濃度が低いＮ型不純物拡散領域５９を設け、それによって基板電流を抑制する。Ｐ型ウェル層領域５２の不純物濃度を高くして寄生バイポーラトランジスタの電流利得を下げる。さらに電流利得を下げるために、パンチスルーストッパー層を設ける。Ｎ型不純物拡散領域５９の不純物濃度を、基板１上に集積される微細集積ＣＭＯＳデバイスのＮ−ＬＤＤ領域６１と同じ濃度とし、それらを一度のイオン注入工程で形成する製造方法が知られている（特許文献１−要約）。
特開２００２−２２２８６９号公報 Further, in order to solve the problem caused by the parasitic PNP transistor in the triple well MOS transistor of FIG. 3, a P type well layer region 52 is formed in the N type well layer region 58 as shown in FIG. In the triple well NMOS transistor in which the MOSFET is formed in the layer region 52, an N-type impurity diffusion region 59 having an impurity concentration lower than that of the N drain region is provided on the N drain region 55 side, thereby suppressing the substrate current. The impurity concentration of the P-type well layer region 52 is increased to reduce the current gain of the parasitic bipolar transistor. In order to further reduce the current gain, a punch-through stopper layer is provided. A manufacturing method is known in which the impurity concentration of the N-type impurity diffusion region 59 is set to the same concentration as that of the N-LDD region 61 of the micro-integrated CMOS device integrated on the substrate 1, and these are formed in a single ion implantation step. (Patent Document 1-Abstract).
JP 2002-222869 A

しかしながら、前述のいずれの従来構造でも、ＭＯＳトランジスタを半導体基板から分離するために高濃度の深い拡散層を形成することが必要なため、ウェハの大口径化における面内の不純物濃度の均一性や面方向への拡散の拡がりのため、デザインルールの微細化プロセスに対応することが困難であった。
本発明は、そのような問題点に鑑みてなされたものであり、その目的とするところは、ウェハの大口径化やデザインルールの微細化プロセスに対応できる、半導体基板から分離させたＭＯＳ半導体装置を提供することである。 However, in any of the above-described conventional structures, it is necessary to form a deep diffusion layer having a high concentration in order to separate the MOS transistor from the semiconductor substrate. Due to the spread of diffusion in the surface direction, it was difficult to cope with the finer process of design rules.
The present invention has been made in view of such problems, and an object of the present invention is to provide a MOS semiconductor device separated from a semiconductor substrate, which can cope with an increase in wafer diameter and a miniaturization process of a design rule. Is to provide.

特許請求の範囲の請求項１記載の発明によれば、前記目的は、第一導電型の半導体基板上に堆積形成される第一導電型エピタキシャル層と、前記半導体基板と前記第一導電型エピタキシャル層との間に選択的に形成される第二導電型埋込拡散層と、前記エピタキシャル層表面から前記埋込拡散層に達するように拡散形成される第二導電型ウェル層と、該第二導電型ウェル層内に拡散形成される第一導電型ウェル層と、該第一導電型ウェル層内に形成される第二導電型ソース層および第二導電型ドレイン層と、前記ソース層とドレイン層との間にゲート絶縁膜を介して形成されるゲート電極を備えるＭＯＳ半導体装置とすることにより、達成される。
特許請求の範囲の請求項２記載の発明によれば、前記第一導電型ウェル層の深さを第二導電型埋込拡散層に接触されない深さとする請求項１記載のＭＯＳ半導体装置とすることが好ましい。 According to the first aspect of the present invention, the object is to form a first conductive type epitaxial layer deposited on a first conductive type semiconductor substrate, the semiconductor substrate and the first conductive type epitaxial layer. A second conductivity type buried diffusion layer selectively formed between the second conductivity type and the second conductivity type well layer diffused to reach the buried diffusion layer from the surface of the epitaxial layer; A first conductivity type well layer formed by diffusion in the conductivity type well layer; a second conductivity type source layer and a second conductivity type drain layer formed in the first conductivity type well layer; and the source layer and the drain. This is achieved by forming a MOS semiconductor device having a gate electrode formed between the layers via a gate insulating film.
According to the second aspect of the present invention, the MOS semiconductor device according to claim 1, wherein the depth of the first conductive type well layer is a depth that does not contact the second conductive type buried diffusion layer. It is preferable.

特許請求の範囲の請求項３記載の発明によれば、埋込拡散層の面方向のパターン面積より第二導電型ウェル層の面方向のパターン面積が小さい請求項１または２記載のＭＯＳ半導体装置とすることが望ましい。
特許請求の範囲の請求項４記載の発明によれば、第一導電型の半導体基板表面層に第二導電型の不純物を導入し、第一導電型エピタキシャル層を堆積形成した後、前記不純物を拡散して埋込拡散層を形成した半導体基板に、前記埋込拡散層に対応する位置の前記エピタキシャル層表面から前記埋込拡散層に達するように第二導電型ウェル層を拡散形成し、該第二導電型ウェル層内に第一導電型ウェル層を形成し、第一導電型ウェル層内に、それぞれ第二導電型ソース層と第二導電型ドレイン層を形成し、前記ソース層とドレイン層との間にゲート絶縁膜を介して形成されるゲート電極を形成するＭＯＳ半導体装置の製造方法とすることができる。 3. The MOS semiconductor device according to claim 1, wherein the pattern area in the surface direction of the second conductivity type well layer is smaller than the pattern area in the surface direction of the buried diffusion layer. Is desirable.
According to the invention of claim 4, the second conductivity type impurity is introduced into the surface layer of the first conductivity type semiconductor substrate, the first conductivity type epitaxial layer is deposited, and then the impurity is A second conductivity type well layer is formed by diffusing in a semiconductor substrate which has been diffused to form a buried diffusion layer so as to reach the buried diffusion layer from the surface of the epitaxial layer at a position corresponding to the buried diffusion layer; Forming a first conductivity type well layer in the second conductivity type well layer; forming a second conductivity type source layer and a second conductivity type drain layer in the first conductivity type well layer; A method of manufacturing a MOS semiconductor device in which a gate electrode formed between the layers via a gate insulating film can be formed.

前述の本発明によれば、深くて高濃度ウェル層を形成するための不純物拡散処理が不要となるため、ウェハの大口径化やデザインルールの微細化プロセスに対応した、半導体基板から分離させたＭＯＳ半導体装置を提供することができる。 According to the above-described present invention, since the impurity diffusion process for forming a deep and high-concentration well layer is not required, the wafer is separated from the semiconductor substrate corresponding to the process of increasing the diameter of the wafer and miniaturizing the design rule. A MOS semiconductor device can be provided.

図１は本発明にかかるＭＯＳ半導体装置の断面図である。本発明の要旨を超えない限り、本発明は以下説明する実施例の記載に限定されるものではない。 FIG. 1 is a cross-sectional view of a MOS semiconductor device according to the present invention. As long as the gist of the present invention is not exceeded, the present invention is not limited to the description of the examples described below.

図１によれば、Ｐ型半導体基板を用いた場合、高濃度の厚いＰ型半導体基板１に選択的にＮ型埋込拡散層２を形成するための不純物を導入する。その後に不純物濃度１×１０^１５ｃｍ^−３で、厚さ５μｍのＰ型エピタキシャル層３を堆積形成する。熱処理により、不純物濃度１×１０^１６ｃｍ^−３〜１×１０^１７ｃｍ^−３のＮ型埋込拡散層２を形成する。このウェハを使用して、Ｎ型埋込拡散層２の上部に対応するＰ型エピタキシャル層３表面より、不純物濃度が１×１０^１６ｃｍ^−３〜１×１０^１７ｃｍ^−３のＮ型ウェル層４を約５μｍの深さに拡散する。このときにＮ型埋込拡散層２とＮ型ウェル層４は製造プロセス終了後に電気的に同電位となって接触するように、Ｐ型エピタキシャル層３との厚さをあらかじめ調整することが重要である。次にＮ型ウェル層４の中に不純物濃度１×１０^１５ｃｍ^−３〜１×１０^１６ｃｍ^−３のＰ型ウェル層５を３μｍの深さに形成し、さらにこのＰ型ウェル層５の中にＮ型ソース層６およびＮ型ドレイン層７と、前記Ｎ型ソース層６とドレイン層７の間に形成されるゲート絶縁膜８を介してゲート電極９を形成すると、分離耐圧４０ＶのＮ型ＭＯＳトランジスタが完成する。Ｐ型ウェル層５は耐圧低下を防ぐために、Ｎ型埋込拡散層２と接触しない深さで形成する。 According to FIG. 1, when a P-type semiconductor substrate is used, an impurity for selectively forming an N-type buried diffusion layer 2 is introduced into a high-concentration thick P-type semiconductor substrate 1. Thereafter, a P-type epitaxial layer 3 having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ and a thickness of 5 μm is deposited. The N-type buried diffusion layer 2 having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ is formed by heat treatment. Using this wafer, an N-type well layer having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ from the surface of the P-type epitaxial layer 3 corresponding to the upper portion of the N-type buried diffusion layer 2 4 is diffused to a depth of about 5 μm. At this time, it is important to adjust the thickness with the P-type epitaxial layer 3 in advance so that the N-type buried diffusion layer 2 and the N-type well layer 4 come into contact with each other at the same electric potential after the end of the manufacturing process. It is. Next, a P-type well layer 5 having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ is formed in the N-type well layer 4 to a depth of 3 μm. When the gate electrode 9 is formed through the N-type source layer 6 and the N-type drain layer 7 and the gate insulating film 8 formed between the N-type source layer 6 and the drain layer 7, an N with an isolation breakdown voltage of 40V is formed. A type MOS transistor is completed. The P-type well layer 5 is formed with a depth not in contact with the N-type buried diffusion layer 2 in order to prevent a decrease in breakdown voltage.

前記Ｎ型ＭＯＳトランジスタでは、ＮＭＯＳ構造のサブストレート電位をＰ型半導体基板電位と分離するためのＮ型ウェル層の底部にＮ型ウェル層より高濃度のＮ型埋込拡散層２が接触して同電位にされているため、前述の図３のＮ型ＭＯＳトランジスタで問題であった寄生ＰＮＰトランジスタのベース幅が大きく、その不純物濃度が高くなるので、容易に分離耐圧を高くすることができる。図３に示すＮ型ＭＯＳトランジスタの場合、この実施例と同じ分離耐圧を得るためには、不純物濃度１×１０^１５ｃｍ^−３のＰ型基板２１に深さ１０μｍ、不純物濃度１×１０^１６ｃｍ^−３〜１×１０^１７ｃｍ^−３のＮ型ウェル層２４を形成し、深さ５μｍ、不純物濃度１×１０^１５ｃｍ^−３〜１×１０^１６ｃｍ^−３のＰ型ウェル層２５を形成する必要がある。この実施例は、前述の図３に示すＮ型ＭＯＳトランジスタでは困難であった深くて高不純物濃度のＮ型ウェル層２４を形成するための高温長時間の拡散処理が不要になるので、ウェハの大口径化やデザインルールの微細化プロセスに適用させることが容易になる。 In the N-type MOS transistor, the N-type buried diffusion layer 2 having a higher concentration than the N-type well layer is in contact with the bottom of the N-type well layer for separating the substrate potential of the NMOS structure from the P-type semiconductor substrate potential. Since they are at the same potential, the base width of the parasitic PNP transistor, which has been a problem in the above-described N-type MOS transistor of FIG. 3, is large and its impurity concentration is high, so that the isolation breakdown voltage can be easily increased. In the case of the N-type MOS transistor shown in FIG. 3, in order to obtain the same isolation withstand voltage as in this embodiment, a P-type substrate 21 having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ has a depth of 10 μm and an impurity concentration of 1 × 10 ¹⁶ cm. ⁻³ to 1 × 10 ¹⁷ cm ^{−3 of} an N-type well layer 24 is formed, and a P-type well layer 25 having a depth of 5 μm and an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ is formed. There is a need. This embodiment eliminates the need for high-temperature and long-time diffusion processing for forming the deep and high impurity concentration N-type well layer 24, which was difficult with the N-type MOS transistor shown in FIG. It can be easily applied to a large diameter process and a fine design rule process.

また、Ｎ型埋込拡散層２の面積がＰ型ウェル層５の面積より小さくなると、前記寄生ＰＮＰトランジスタの影響が次第に大きくなるので、寄生ＰＮＰトランジスタの影響を少なくするためには、Ｎ型埋込拡散層２の面積をＰ型ウェル層５の面積より大きくすることが望ましい。 If the area of the N-type buried diffusion layer 2 is smaller than the area of the P-type well layer 5, the influence of the parasitic PNP transistor gradually increases. Therefore, in order to reduce the influence of the parasitic PNP transistor, the N-type buried diffusion layer 2 is reduced. It is desirable to make the area of the buried diffusion layer 2 larger than the area of the P-type well layer 5.

本発明の実施例にかかるＮＭＯＳトランジスタの断面図、Sectional drawing of the NMOS transistor concerning the Example of this invention, 従来のＮＭＯＳトランジスタとＰＭＯＳトランジスタの断面図、Cross-sectional view of a conventional NMOS transistor and PMOS transistor, 従来の分離タイプのＮＭＯＳトランジスタの断面図、Sectional view of a conventional isolation type NMOS transistor, 従来の改良型の分離タイプのＮＭＯＳトランジスタの断面図、Sectional view of a conventional improved isolation type NMOS transistor, 従来の改良型の分離タイプの異なるＮＭＯＳトランジスタの断面図、A cross-sectional view of a conventional NMOS transistor with a different isolation type, 従来のトリプルウェルを有するＮＭＯＳトランジスタの断面図。Sectional drawing of the NMOS transistor which has the conventional triple well.

Explanation of symbols

１、１１、２１、３１、４１第一導電型半導体基板
２、３２第二導電型形埋め込み層
３、３３、４３第一導電型形エピタキシャル層
４、１４、２４第二導電型ウェル層
５、２５、４５第一導電型ウェル層
６ソース層
７、１７、２６、３６、４６ドレイン層
８ゲート絶縁膜
９、１８、１９、２８、３８、４８ゲート電極
３９、４９分離層
５２Ｐ型ウェル層領域
５８Ｎ型ウェル層領域
５５Ｎドレイン領域
５９Ｎ型低不純物領域
６１Ｎ−ＬＤＤ領域。
1, 11, 21, 31, 41 First conductivity type semiconductor substrate
2, 32 Second conductivity type buried layer 3, 33, 43 First conductivity type epitaxial layer 4, 14, 24 Second conductivity type well layer 5, 25, 45 First conductivity type well layer 6 Source layer
7, 17, 26, 36, 46 Drain layer 8 Gate insulating film
9, 18, 19, 28, 38, 48 Gate electrode 39, 49 Separation layer 52 P-type well layer region 58 N-type well layer region 55 N drain region 59 N-type low impurity region 61 N-LDD region.

Claims

A first conductivity type epitaxial layer deposited on a first conductivity type semiconductor substrate and a second conductivity type buried diffusion layer selectively formed between the semiconductor substrate and the first conductivity type epitaxial layer A second conductivity type well layer that is diffused and formed so as to reach the buried diffusion layer from the surface of the epitaxial layer, a first conductivity type well layer that is diffused and formed in the second conductivity type well layer, A second conductivity type source layer and a second conductivity type drain layer formed in the first conductivity type well layer; and a gate electrode formed through a gate insulating film between the source layer and the drain layer. MOS semiconductor device characterized by the above.

2. The MOS semiconductor device according to claim 1, wherein the depth of the first conductivity type well layer is set to a depth not contacting the second conductivity type buried diffusion layer.

3. The MOS semiconductor device according to claim 1, wherein a pattern area in the surface direction of the second conductivity type well layer is smaller than a pattern area in the surface direction of the buried diffusion layer.

After introducing a second conductivity type impurity into the surface layer of the first conductivity type semiconductor substrate, depositing and forming the first conductivity type epitaxial layer, the semiconductor substrate having the buried diffusion layer formed by diffusing the impurity, A second conductivity type well layer is formed by diffusion so as to reach the buried diffusion layer from the surface of the epitaxial layer at a position corresponding to the buried diffusion layer, and the first conductivity type well layer is formed in the second conductivity type well layer. Forming a second conductive type source layer and a second conductive type drain layer in the first conductive type well layer, respectively, and forming a gate between the source layer and the drain layer via a gate insulating film; A method of manufacturing a MOS semiconductor device, comprising forming an electrode.