JP2006140293A - Semiconductor microfabricated structure and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a microfabricated structure which has a reduced crystalline defect level and has superior semiconductor characteristics. <P>SOLUTION: The method of manufacturing the microfabricated structure formed of a single crystal semiconductor comprises a process (a) wherein first catalyst fine particles 130 containing a first dopant element to be grown as a first conductivity type for the single crystal semiconductor are formed on a support body 101; and a process (b) wherein a material gas containing an element constituting the single crystal semiconductor is introduced near the surface of the support body, the material gas is decomposed by the first catalyst fine particles, and then a single crystal semiconductor containing the first dopant element is so grown as to form a first microfabricated object 111. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a fine semiconductor structure used in a semiconductor device such as a field effect transistor and a method for manufacturing the same.

  Large-scale integrated circuits are composed of many semiconductor transistors, and so far, by miniaturizing the transistors, the operating speed of large-scale integrated circuits has been improved and the power consumption has been reduced. Has been achieved.

  In the future, it is predicted that the characteristics of large scale integrated circuits can be continuously improved by miniaturization of transistors. However, in the near future, the lithography and etching technologies used to manufacture transistors will reach the limits of microfabrication. As long as lithography and etching technologies are used, it is difficult to improve the characteristics of large-scale integrated circuits due to the limitations of microfabrication. There are also predictions. From these backgrounds, a technique for performing microfabrication of a semiconductor without using lithography is attracting attention.

  As one of the methods for forming a semiconductor microstructure without using lithography, semiconductor nanowire technology has attracted attention. For example, Non-Patent Document 1 discloses a transistor using semiconductor nanowire technology. This conventional semiconductor nanowire technology will be described with reference to FIGS.

  First, as shown in FIG. 5A, fine particles 202 serving as a catalyst are formed on the surface of the substrate 201. Although the surface of the substrate 201 is often a silicon oxide film or a single crystal silicon surface, the same crystal growth occurs below without being limited to the material. In Non-Patent Document 1, Au is used as the material of the fine particles 202. In addition to Au, examples using Fe, Ni, Ti, Pd, etc. have been reported. The diameter of the fine particles 202 is usually about 5 nm to 50 nm.

As shown in FIG. 5B, a semiconductor source gas 203 is injected onto the surface of the substrate 201 on which the fine particles 202 are formed. SiH ₄ is usually used for growing Si nanowires, and hydrides such as GeH ₄ are usually used for growing Ge nanowires. By injecting the semiconductor source gas 203, the microparticles 202 become catalysts and the semiconductor source gas 203 is decomposed only on the microparticles 202. As a result, as shown in FIG. 5C, columnar semiconductor nanowires 204 made of a single crystal grow.

  In the region where the fine particles 202 are not formed on the surface of the substrate 201, the semiconductor source gas 203 is not decomposed. For this reason, the semiconductor nanowire 204 is locally formed only in the portion where the fine particles 202 are formed. The diameter of the semiconductor nanowire 204 is approximately the same as the diameter of the fine particles 202. That is, a fine structure of about 5 nm to 50 nm can be formed without patterning.

In Non-Patent Document 1, a semiconductor nanowire 204 formed by this method is used as a channel of a field effect transistor. Thus, it can be said that the semiconductor nanowire technology is a useful technology capable of self-forming a nanometer-level fine structure without using lithography.
Applied Physics Letters vol.83 (2003) p2432-2434.

  The conventional semiconductor nanowire technology has the advantage that a fine structure can be formed without using lithography, but has the following two problems.

  The first problem is to form a crystal defect level by incorporating a minute amount of metal atoms constituting the fine particles into the semiconductor nanowire. Au, Fe, Ni, Ti, Pd, and the like used as the fine particles are heavy metal atoms, and function as crystal defect levels for trapping carriers by being taken into the semiconductor. As a result, the carrier mobility of the semiconductor nanowire is reduced, the lifetime of the carrier is shortened, and the device characteristics are deteriorated.

The second problem relates to the complexity of the process in manufacturing a complementary MOS transistor (CMOS transistor) using semiconductor nanowires as a channel. In order to form a CMOS transistor, it is necessary to grow a p-channel transistor and an n-channel transistor, that is, a p-type nanowire and an n-type nanowire. For example, as shown in FIG. 6A, a source / drain electrode 302 and a source / drain electrode 303 used for a p-channel transistor and an n-channel transistor are formed on the surface of a substrate 301, respectively. Next, as shown in FIG. 6B, fine particles 304 are formed on the source / drain electrode 302 and the source / drain electrode 303. As shown in FIG. 6C, a mask 305 is formed in a region including the source / drain electrodes 303 and the n-channel transistor. The formation method of the mask 305 is a generally known fine processing technique such as lithography or etching. Specifically, after an oxide film is formed on the entire surface of the substrate 301, a resist film is formed on a portion where the oxide film is desired to be left, and the oxide film is etched using the resist film as a mask. In this manner, the source / drain electrode 302 is exposed, while an oxide film mask 305 is formed as shown on the right side of FIG. Thereafter, the p-channel nanowire 306 is grown by the fine particles 304 on the source / drain electrode 302. When the p-channel nanowire 306 is grown, a gas 308 containing a p-type dopant is supplied simultaneously with the semiconductor source gas 307. SiH ₄ or GeH ₄ can be used for the semiconductor source gas 307, and B ₂ H ₆ or the like can be used for the gas 308 containing the p-type dopant.

After removing the mask 305, a mask 309 is formed in the region where the p-channel transistor including the source / drain electrode 302 is to be formed by the same method as in FIG. A nanowire 310 is grown. When the n-channel nanowire 310 is grown, a gas 311 containing an n-type dopant such as PH ₃ is supplied simultaneously with the semiconductor source gas 307. Thereafter, the mask 309 is removed, and a gate oxide film, gate electrode formation, wiring, and the like are formed, and a CMOS transistor is formed.

  Thus, in order to fabricate a CMOS transistor using semiconductor nanowires according to the prior art, it is necessary to grow the p-channel wire and the n-channel wire in two steps. In particular, since the p-channel wire and the n-channel wire have a size that is difficult to produce by conventional microfabrication techniques such as lithography and etching, the p-channel wire and the n-channel wire are separately grown twice. The use of conventional microfabrication techniques such as lithography and etching is considered to increase the difficulty and complexity of manufacturing CMOS transistors.

  An object of the present invention is to solve at least one of the problems of the prior art as described above, and to provide a method for manufacturing a microstructure having a small number of crystal defect levels and excellent semiconductor characteristics.

  The method for manufacturing a microstructure according to the present invention is a method for manufacturing a microstructure made of a single crystal semiconductor, and includes only a first dopant element serving as a dopant of the first conductivity type with respect to the single crystal semiconductor on a support. A step (a) of forming first catalyst fine particles comprising or containing the first dopant element, and introducing a source gas containing an element constituting the single crystal semiconductor in the vicinity of the surface of the support, And (b) growing the single crystal semiconductor containing the first dopant element so as to decompose the source gas with the catalyst fine particles and form the first microstructure.

  In a preferred embodiment, the first catalyst fine particle does not serve as a dopant of the first conductivity type, but further includes a first catalytic metal element that functions as a catalyst for promoting decomposition of the raw material gas in the step (b). Including.

  In a preferred embodiment, the first catalyst fine particles contain more of the first dopant element than the catalytic metal element in an atomic ratio.

  In a preferred embodiment, the first catalyst fine particles include only the first dopant element.

  In a preferred embodiment, the manufacturing method of the microstructure according to the present invention includes a second dopant which becomes a second conductivity type dopant with respect to the single crystal semiconductor on the support surface before the step (b). The method further includes a step (c) of forming second catalyst fine particles made of only an element or containing the second dopant element, and in the step (b), a source gas containing an element constituting the single crystal semiconductor is added. The single crystal semiconductor containing the second dopant element is introduced into the vicinity of the support surface and decomposed with the second catalyst fine particles to form the second microstructure so as to form the second microstructure. The single crystal semiconductor containing one dopant element is grown at the same time.

  In a preferred embodiment, the second catalyst fine particles further include a catalytic metal element that does not serve as a dopant of the second conductivity type but functions as a catalyst that promotes decomposition of the raw material gas in the step (b).

  In a preferred embodiment, the second catalyst fine particles contain more of the second dopant element than the catalyst metal element in an atomic ratio.

  In a preferred embodiment, the second catalyst fine particle contains only the first dopant element.

  In a preferred embodiment, the element constituting the single crystal semiconductor is a group IV element, and the first dopant element is a group III or group V element.

  In a preferred embodiment, the element constituting the single crystal semiconductor is a group IV element, and the first and second dopant elements are a group III element and a group V element, respectively.

  In a preferred embodiment, the group III element is Al, Ga, or In.

  In a preferred embodiment, the group V element is P, As, Sb or Bi.

  In a preferred embodiment, the group IV element is Si or Ge.

  In a preferred embodiment, the elements constituting the single crystal semiconductor are a group III element and a group V element.

  In a preferred embodiment, the elements constituting the single crystal semiconductor are a group II element and a group VI element.

  In a preferred embodiment, the first catalytic metal element or the second catalytic metal element is at least one selected from Au, Fe, Ni, Ti, and Pd.

  In a preferred embodiment, the first microstructure has a column shape.

  In a preferred embodiment, the maximum length of the cross section perpendicular to the direction in which the column extends in the first microstructure is 100 μm or less.

  In a preferred embodiment, the step (a) includes a step of forming a thin film containing the first dopant element on the support, and a fine particle shape containing the first dopant element by heat-treating the thin film. Forming the first catalyst fine particles.

  The method of manufacturing a field effect transistor according to the present invention includes the steps of forming a first source / drain electrode and a second source / drain electrode on a support, and a first source / drain electrode on the first source / drain electrode. A mask is formed, and the first source / drain electrode is made of only the first dopant element which becomes a dopant of the first conductivity type with respect to the single crystal semiconductor, or the first dopant element contains the first dopant element. Forming the catalyst fine particles, removing the first mask on the second source / drain electrode, forming a second mask on the first source / drain electrode, and On the two source / drain electrodes, the second catalyst fine particles are formed only of the second dopant element which is a dopant of the second conductivity type with respect to the single crystal semiconductor or contains the second dopant element. A step of removing the second mask on the first source / drain electrode, a source gas containing an element constituting the single crystal semiconductor is introduced in the vicinity of the surface of the support, and the first The raw material gas is decomposed by the catalyst fine particles and the second catalyst fine particles, and a single crystal semiconductor containing the first dopant element is grown to form the first microstructure, and at the same time, the second dopant element is A step of growing a single crystal semiconductor including the second microstructure, and a step of forming a gate oxide film so as to cover the first microstructure and the second microstructure; Forming a gate electrode on the gate oxide film.

  The semiconductor microstructure of the present invention is formed on a support and is made of a single crystal semiconductor having a first conductivity type, and comes into contact with the microstructure to become the first conductivity type. And first catalyst fine particles containing only the first dopant element or the first dopant element.

  In a preferred embodiment, the micro semiconductor structure is formed on a support and is made of a single crystal semiconductor having a second conductivity type. The micro semiconductor structure is in contact with the micro structure, and the second conductivity type. And a second catalyst fine particle containing only the second dopant element or the second dopant element.

  In a preferred embodiment, the first microstructure has a column shape.

  In a preferred embodiment, each of the first and second microstructures has a column shape.

  In a preferred embodiment, the columnar shape has a maximum length of a cross section perpendicular to the longitudinal direction of 100 μm or less.

  The field-effect transistor of the present invention is formed between a support, a first source / drain electrode and a second source / drain electrode formed on the support, and the first source / drain electrode. A first microstructure made of a single crystal semiconductor having a first conductivity type; and the first microstructure contacting the first microstructure and at least one of the first source / drain electrodes. A single crystal semiconductor having a second conductivity type formed between a first catalyst fine particle made of only the first dopant element having the conductivity type or containing the first dopant element, and the second source / drain electrode And a second dopant element of the second conductivity type that is in contact with the second microstructure and is in contact with at least one of the second source / drain electrodes. A second catalyst fine particle comprising or comprising the second dopant element; a gate oxide film covering the first microstructure and the second microstructure; and a gate oxide film on the gate oxide film. And a formed gate electrode.

  According to the present invention, the content of heavy atoms in the grown single crystal semiconductor can be reduced, and generation of crystal defect levels in the semiconductor can be suppressed. For this reason, the microstructure which has the outstanding semiconductor characteristic can be obtained. In addition, since a microstructure formed of a p-type semiconductor and a microstructure formed of an n-type semiconductor can be formed at the same time, the manufacturing process of a semiconductor device including a p-type semiconductor such as a CMOS transistor and an n-type semiconductor is greatly simplified. Can be realized.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(Embodiment 1)
With reference to FIGS. 1A to 1C, FIG. 2 and FIG. 3, a manufacturing method of a microstructure made of a single crystal semiconductor according to the present invention will be described.

  First, as shown in FIG. 1A, catalyst fine particles 130 are formed on a support 101 such as a substrate. The support 101 can be made of various materials as long as it is not deformed at the heat treatment temperature used in the following manufacturing process. Specifically, a glass substrate, a Si substrate, a substrate on which a silicon oxide film is formed, or the like can be used. The surface of the support 101 need not have crystallinity. The support 101 may be an electrode provided on the surface of the substrate.

  As shown in FIG. 3, the catalyst fine particles 130 serve as a p-type or n-type dopant for the single crystal semiconductor to be grown, and only the dopant element 131 that functions as a catalyst for decomposing the source gas when the single crystal semiconductor is grown. (FIG. 3A) and a case where a catalytic metal element 132 that does not become a dopant is included together with the dopant element 131 (FIG. 3B).

  When forming a group IV single crystal semiconductor, a p-type single crystal semiconductor can be formed by using a group III element as a dopant element. Specifically, Al, Ga, In, or the like can be used for the dopant element. An n-type single crystal semiconductor can be formed by using a group V element as a dopant element. Specifically, P, As, Bi, or the like can be used as a dopant element.

  The single crystal semiconductor to be grown may be a compound semiconductor. Specifically, a single crystal of a III-V group compound semiconductor such as GaAs, GaP, GaAsP, InP, InAs, or InAsP or a II-VI group compound semiconductor such as ZnS, ZnSe, CdS, or CdSe may be grown. In this case, whether a dopant element is a p-type dopant or an n-type dopant with respect to a compound semiconductor is not uniquely determined depending on the group of the element. It changes depending on whether you enter.

  As the catalytic metal element, Au, Fe, Ni, Ti, Pd, or the like can be used. These metals do not become p-type or n-type dopants because they form deep impurity levels in single crystal semiconductors and serve as carrier traps. However, it is excellent in promoting the decomposition of the source gas and forms a eutectic state with the elements constituting the semiconductor, thereby promoting the growth of the semiconductor.

  In the catalyst fine particles 130, the dopant element and the catalyst metal element preferably form an alloy. The content ratio of the dopant element and the catalytic metal element depends on the concentration of the dopant element to be introduced into the semiconductor and the catalytic ability to decompose the dopant element source gas. In order to increase the impurity concentration of the semiconductor to be formed, it is preferable that the catalyst fine particles 130 contain a large amount of dopant elements. When the capability of decomposing the source gas of the dopant element is high, the catalytic metal element may not be included in the catalyst fine particles 130. In this case, it is possible to form a single crystal semiconductor having excellent characteristics without containing any catalytic metal element that forms a deep impurity level.

  Even in the case where the dopant element is included in the catalytic metal element, the concentration of the catalytic metal element contained in the catalyst fine particles 130 is lower than that in the conventional method of manufacturing nanowires. For this reason, the concentration of the catalytic metal element in the growing single crystal semiconductor is also reduced, and the semiconductor characteristics are improved.

  The size of the catalyst fine particles 130 is approximately equal to the diameter of the semiconductor to be grown. For this reason, the diameter of the catalyst fine particles 130 can be selected so that a semiconductor having a desired diameter can be obtained. However, if the diameter of the catalyst fine particle 130 becomes too large, it becomes difficult to grow a single crystal semiconductor. Preferably, the catalyst fine particle 130 has a diameter of 100 nm or less, and more preferably in the range of 5 nm to 50 nm.

  A known method for forming fine particles can be used to form the catalyst fine particles 130. For example, as shown in FIG. 1B, a thin film 130 containing a dopant element and a catalytic metal element is formed on the surface of the support 101 using a known thin film forming apparatus such as a sputtering method or a vapor deposition method. Thereafter, when the thin film 130 ′ is heat-treated, the thin film 130 ′ self-aggregates, and a plurality of particulate catalyst fine particles 130 are formed on the support 101 as shown in FIG. The diameter d1 of the catalyst fine particles 130 and the distance L1 between the adjacent catalyst fine particles 130 depend on the thickness of the thin film 130 'and the heat treatment conditions, and d1 and L1 can be changed by adjusting them. As described above, the diameter d1 of the catalyst fine particles 130 is preferably 100 nm or less. For example, by forming a thin film 130 ′ having a thickness of about 5 nm containing only In as a dopant element on the support 1 and performing a heat treatment at a temperature of about 200 ° C. for about 10 minutes, In particles having a diameter of about 20 nm are generated. To do. The In particles can be used as the catalyst fine particles 130.

  In addition, the catalyst fine particles 130 can also be formed by applying or spraying a solution containing a dopant element and a catalyst metal element on the surface of the support 101. If necessary, after forming the thin film 103 ′, patterning may be performed to form the catalyst fine particles 130 only in a predetermined region on the support 101.

  Next, as shown in FIG. 2A, the support 101 on which the catalyst fine particles 130 are formed is introduced into a chamber capable of heating the support 101 such as a CVD apparatus and capable of adjusting the pressure. . A source gas 108 containing an element constituting the semiconductor is introduced into the chamber and kept at a predetermined pressure. As a result, the surface of the support 101 on which the catalyst fine particles 130 are formed is in contact with the source gas atmosphere at a predetermined pressure. The support 101 is heated at a temperature lower than the temperature at which the source gas 108 decomposes.

As the source gas, a hydride of an element constituting a semiconductor can be preferably used. For example, SiH ₄ , Si ₂ H ₆ , GeH _4, etc. can be used to grow a group IV semiconductor. In this embodiment, GeH ₄ is used as the source gas 108, and the support 101 is heated to about 200 ° C. while maintaining the chamber at a pressure of 0.1 Torr. In the case of growing a compound semiconductor, a metal compound can be preferably used.

  As shown in FIG. 2B, the introduced source gas 108 is selectively decomposed only in the vicinity of the catalyst fine particles 130. The elements constituting the semiconductor are precipitated by the decomposition, and the precipitated elements are aggregated to grow a single crystal semiconductor. Thereby, a microstructure 111 made of a single crystal semiconductor is formed. Although the growth mechanism of the single crystal semiconductor has not yet been fully clarified, it is considered that the deposited elements first constitute an alloy with the catalyst fine particles 130. This alloy is often a liquid. As the element precipitates, the concentration of the element constituting the semiconductor in the alloy increases and reaches a saturated state, and then the elements constituting the semiconductor aggregate to form a single crystal semiconductor.

  For this reason, it is considered that crystal growth occurs at the boundary between the catalyst fine particles 130 and the microstructure 111 made of the grown single crystal semiconductor. As the single crystal semiconductor grows, the catalyst fine particles 130 are separated from the support 101 and come into contact with the microstructure 111 on the support 101. The other end of the microstructure 111 that is not in contact with the support 101 is brought into contact so that the catalyst fine particles 130 are held. Thereby, as shown in FIG. 2C, the single crystal semiconductor grows and the microstructure 111 is formed. At this time, the single crystal semiconductor is crystallized so as not to contain impurities, but contains a small amount of a dopant element and a catalytic metal element constituting the catalyst fine particles 130. By adding this dopant element, the microstructure 111 has a p-type or n-type conductivity. Further, the catalytic metal element and the microstructure 111 are also included.

  FIGS. 3A and 3B are diagrams schematically showing a microstructure 111 made of a single crystal semiconductor grown in this manner. As described above, the microstructure 111 preferably has a maximum length d2 of a cross section perpendicular to the growth direction of 100 nm or less, and more preferably 5 to 50 nm. As shown in FIGS. 3A and 3B, the microstructure 111 is supported by the support 101, and the catalyst fine particles 130 are in contact with the tips thereof. As described above, since the catalyst fine particles 130 melt and become spherical during semiconductor growth, the growing microstructure 111 has a cylindrical shape. However, the cross section of the microstructure 111 may have a shape other than a circle.

  As shown in FIG. 3B, the dopant element 131 and the catalyst metal element 132 constituting the catalyst fine particle 130 are also included in the microstructure 111 for the reason described above. However, the catalytic metal element 132 taken in from the catalyst fine particles 130 is almost the same as the amount of the catalytic metal element 132 mixed by the conventional method even when combined with the dopant element 131, and the concentration of the catalytic metal element 132 in the microstructure 111. Has been reduced compared to the prior art. For this reason, the impurity level which becomes a trap of carriers is reduced and the semiconductor characteristics are improved. As shown in FIG. 3A, when the catalytic metal element 132 is not included in the catalyst fine particles 130, the microstructure 111 does not include the catalytic metal element 132 at all, and the impurity level that becomes a carrier trap is It becomes very small and the semiconductor characteristics are further improved. Further, the microstructure 111 made of a p-type or n-type semiconductor can be formed without adding a dopant element to the source gas. The concentration of the dopant element 131 in the catalyst fine particle 130 is higher than the concentration of the dopant element 131 in the microstructure 111.

  Note that the length L2 of the microstructure 111 in the crystal growth direction can be adjusted by the time for growing the crystal. If crystal growth is performed for a sufficiently long time, the microstructure 111 having a length L2 of several μm can be formed. When the microstructure 111 has a diameter of 100 μm or less and the crystal growth direction coincides with the longitudinal direction, the microstructure 111 has an outer shape generally called “nanowire”. However, the length L2 may be made smaller than the diameter d2 of the microstructure 111 by shortening the crystal growth time. The microstructure 111 having such a shape is also useful depending on the type and application of the semiconductor device formed by the microstructure 111.

  Further, in FIGS. 2B and 2C, the microstructure 111 is grown substantially vertically upward from the support 101, but the growth direction of the single crystal semiconductor is lateral to the surface of the support 101. (Horizontal) or diagonal. The growth conditions of the single crystal semiconductor may be optimized so that the growth in a certain direction preferentially occurs, or the single crystal semiconductor may be grown in a random direction.

(Embodiment 2)
Next, an example in which a p-type microstructure and an n-type microstructure are formed on the same support using the manufacturing method of the present invention will be described. In particular, a method for manufacturing a CMOS transistor including a field effect transistor having a p-type channel and a field effect transistor having an n-type channel will be described below.

  First, as shown in FIG. 4A, the source / drain electrode 102 and the source / drain electrode 103 are formed on the surface of the support 101. Here, a glass substrate is used as the support 101. However, as described above, a Si substrate coated with a silicon oxide film or the like may be used. The source / drain electrode 102 and the source / drain electrode 103 are used for a p-channel transistor and an n-channel transistor, respectively. The distance between the source / drain electrodes 102 is set to 100 nm, for example. Although close in FIG. 4A, the source / drain electrode 102 and the source / drain electrode 103 are not connected to each other so that the semiconductor does not grow between the source / drain electrode 102 and the source / drain electrode 103. Are preferably separated sufficiently. The source / drain electrode 102 and the source / drain electrode 103 can be formed by depositing a Ni film on the support 101 and then patterning it using photolithography and dry etching.

  Next, as shown in FIG. 4B, a mask 104 is formed with a photoresist or the like in the n-channel transistor region including the source / drain electrode 103, and then on the source / drain electrode 102 and the mask 104. A solution containing the first catalyst fine particles 105 is applied or sprayed to form the first catalyst fine particles 105 on the source / drain electrodes 102. In the present embodiment, the first catalyst fine particle 105 contains only In as the first dopant element. As the first dopant element, in addition to In, other group III elements such as Al and Ga may be used.

  After the mask 104 is removed, as shown in FIG. 4C, a mask 106 is formed using a photoresist or the like in the p-channel transistor region including the source / drain electrodes 102. Thereafter, second catalyst fine particles 107 are formed on the source / drain electrodes 103 by the same method as in FIG. In the present embodiment, the second catalyst fine particle 107 contains only Sb as the second dopant element. As the second dopant element, in addition to Sb, other group V elements such as P, As, and Bi may be used.

  In the present embodiment, the first catalyst fine particles 105 and the second catalyst clutter 107 contain only the first dopant element and the second dopant element, but do not function as a dopant such as Au described above, but the source gas A catalyst element containing a dopant element in a catalytic metal element exhibiting an excellent catalytic action for decomposing and promoting single crystal growth may be used.

After removing the mask 106, the surface of the support 101 on which the first catalyst fine particles 105 and the second catalyst fine particles 107 are formed is filled with a GeH ₄ atmosphere that is a group IV semiconductor source gas 108. At this time, the support 101 is heated to about 200 ° C. The pressure of the source gas 108 is set to about 0.1 Torr. As a result, as shown in FIG. 4D, the raw material gas 108 is decomposed in the vicinity of the first catalyst fine particles 105 and the second catalyst fine particles 107, and the first catalyst fine particles 105 and the second catalyst fine particles are used as catalysts. A single crystal Ge semiconductor grows. Then, a first microstructure 109 and a second microstructure 110 made of a single crystal Ge semiconductor are formed. When SiH ₄ or Si ₂ H ₆ is used as the source gas 108, a single crystal Si semiconductor grows.

  When the first microstructure 109 is formed, the first dopant element constituting the first catalyst fine particles 105 is naturally taken into the single crystal Ge semiconductor. Therefore, the single crystal Ge semiconductor of the first microstructure 109 is p-type. Further, when the second microstructure 110 is formed, the second dopant element constituting the second catalyst fine particle 107 is naturally taken into the single crystal Ge semiconductor. For this reason, the single crystal Ge semiconductor of the second microstructure 110 is n-type. The formation of the first microstructure 109 made of the p-type single crystal Ge semiconductor and the second microstructure 110 made of the n-type single crystal Ge semiconductor are substantially simultaneous, and a single source gas 108 is introduced. Thus, a p-type semiconductor and an n-type semiconductor are formed simultaneously.

  Note that when the first microstructure 109 and the second microstructure 110 are formed, the growth direction of the single crystal semiconductor is generally random, and between the source / drain electrodes 102 and between the source / drain electrodes 103. The semiconductor does not necessarily grow only in the middle. However, it is possible to control so that the growth in the horizontal direction is preferentially generated with respect to the surface of the support 101 by devising the growth conditions, for example, by applying an electric field when growing the semiconductor. . Further, there is no problem unless a semiconductor is grown and electrically connected between the source / drain electrode 102 and the source / drain electrode 103. Even when a semiconductor grown between the source / drain electrode 102 and the source / drain electrode 103 exists, an unnecessary semiconductor may be cut after crystal growth using a laser beam or the like.

  As shown in FIG. 4D, a CMOS transistor can be manufactured by using the first microstructure 109 and the second microstructure 110 bridged between the source / drain electrodes 102 and 103 as a channel. it can. Here, the structure in which the fine structure is connected between the catalyst fine particles is shown, but one end of the fine structure may be directly joined to the source / drain electrode as shown in FIG.

As shown in FIG. 4E, a gate oxide film 112 is formed so as to cover the side surfaces of the columnar first microstructure 109 and the second microstructure 110. As the gate oxide film, for example, a TiO ₂ film formed by sputtering is used. Thereafter, a gate oxide film 112 is formed by forming a conductive thin film and performing patterning. Thereby, the p-type channel transistor 121 and the n-type channel transistor 122 are formed, and the CMOS transistor including the p-type channel transistor 121 and the n-type channel transistor 122 is completed.

  In this embodiment, as a method for forming catalyst fine particles, a solution containing catalyst fine particles is applied or sprayed to form catalyst fine particles on the source / drain electrodes. However, a thin film of catalyst fine particles having a thickness of about 5 nm (for example, an In thin film or After the Sb thin film or the like is deposited on the source / drain electrodes, the fine particles of the catalyst fine particles may be formed on the source / drain electrodes by performing a heat treatment. In that case, the particle diameter of the catalyst fine particles is about 20 nm. As the first dopant element, in addition to In, other group III elements such as Al and Ga may be used. In addition to Sb, other V group elements such as P, As, and Bi may be used as the second dopant element.

  According to the CMOS transistor of the present invention, the first microstructure 109 and the second microstructure 110, which are semiconductor regions of the p-type channel transistor 121 and the n-type channel transistor 122, are manufactured using conventional techniques. Unlike semiconductor nanowires, it does not contain heavy metals such as Au. Therefore, formation of crystal defect levels is suppressed, and the mobility of the transistor can be improved. In addition, since the p-type semiconductor nanowire 109 and the n-type semiconductor nanowire 110 can be formed at the same time, the process can be greatly simplified as compared with the case of manufacturing a CMOS using the conventional technique.

  In addition, although embodiments of manufacturing a CMOS transistor have been described so far, according to the present invention, a semiconductor microstructure in which formation of crystal defect levels is suppressed may be another semiconductor element such as a light emitting element or a light receiving element, It can be suitably used for junction type transistors other than the field effect type.

  The semiconductor microstructure according to the manufacturing method of the present invention can be suitably used for a light emitting element, a light receiving element, a switching element, and an integrated circuit in which these are combined, having a minute size on the order of nanoscale. In particular, it is suitably used for a semiconductor device having a p-type and n-type semiconductor region and having a nanoscale-like minute size.

(A) is a perspective view which shows the process in the middle in the manufacturing method of the microstructure by this invention, Comprising: The support body in which the catalyst fine particle was formed is shown. (B) And (c) is a manufacturing process diagram for forming catalyst fine particles. The manufacturing process figure of the microstructure by this invention. The schematic diagram of the microstructure manufactured by the manufacturing method of the microstructure by this invention. The manufacturing process figure of the CMOS transistor by this invention. The manufacturing process figure of the conventional semiconductor nanowire. The manufacturing process figure of the CMOS transistor by the manufacturing method of the conventional semiconductor nanowire. The enlarged view of the CMOS transistor electrode part of this invention.

Explanation of symbols

101 Support 102, 103, 302, 303 Source / Drain Electrode 104, 106, 305, 309 Mask 105 First Catalyst Fine Particle 107 Second Catalyst Fine Particle 108, 203, 307, Source Gas 109 First Microstructure 110 Second microstructure 130 Catalyst fine particle 204 Semiconductor nanowire 201, 301 Substrate 202, 304 Fine particle 306 p-type semiconductor nanowire 308 p-type dopant gas 310 n-type semiconductor nanowire 311 n-type dopant gas

Claims (26)

A manufacturing method of a microstructure formed of a single crystal semiconductor,
A step (a) of forming first catalyst fine particles comprising only the first dopant element serving as the dopant of the first conductivity type with respect to the single crystal semiconductor on the support, or including the first dopant element;
A source gas containing an element constituting the single crystal semiconductor is introduced near the support surface, the source gas is decomposed by the first catalyst fine particles, and the first microstructure is formed. A step (b) of growing a single crystal semiconductor containing a dopant element of
For producing a microstructure including   2. The first catalyst fine particle further includes a first catalytic metal element that does not serve as a dopant of the first conductivity type but functions as a catalyst for promoting decomposition of the raw material gas in the step (b). Manufacturing method of the micro structure.   3. The method for manufacturing a microstructure according to claim 2, wherein the first catalyst fine particles contain more of the first dopant element than the catalyst metal element in an atomic ratio.   The method for manufacturing a microstructure according to claim 1, wherein the first catalyst fine particles include only the first dopant element. Before the step (b), the second surface consisting of only the second dopant element which becomes a dopant of the second conductivity type with respect to the single crystal semiconductor on the surface of the support or contains the second dopant element Further comprising a step (c) of forming catalyst fine particles,
In the step (b), a source gas containing an element constituting the single crystal semiconductor is introduced in the vicinity of the surface of the support, and the source gas is decomposed by the second catalyst fine particles, whereby a second microstructure is formed. 5. The method for manufacturing a microstructure according to claim 1, wherein a single crystal semiconductor containing the second dopant element is grown simultaneously with the single crystal semiconductor containing the first dopant element so as to form a body. .   6. The microstructure according to claim 5, wherein the second catalyst fine particle does not serve as a dopant of the second conductivity type, but further includes a catalytic metal element that functions as a catalyst that promotes decomposition of the raw material gas in the step (b). Body manufacturing method.   The method for producing a microstructure according to claim 6, wherein the second catalyst fine particles contain more of the second dopant element than the catalyst metal element in an atomic ratio.   The method for manufacturing a microstructure according to claim 5, wherein the second catalyst fine particles include only the first dopant element.   The method for manufacturing a microstructure according to any one of claims 1 to 8, wherein the element constituting the single crystal semiconductor is a group IV element, and the first dopant element is a group III or group V element.   9. The microstructure according to claim 5, wherein the element constituting the single crystal semiconductor is a group IV element, and the first and second dopant elements are a group III element and a group V element, respectively. Method.   The method for manufacturing a microstructure according to claim 10, wherein the group III element is Al, Ga, or In.   The method for manufacturing a microstructure according to claim 10, wherein the group V element is P, As, Sb, or Bi.   The method for manufacturing a microstructure according to claim 10, wherein the group IV element is Si or Ge.   The method for manufacturing a microstructure according to any one of claims 1 to 8, wherein the elements constituting the single crystal semiconductor are a group III element and a group V element.   The method for manufacturing a microstructure according to any one of claims 1 to 9, wherein the elements constituting the single crystal semiconductor are a group II element and a group VI element.   The method for manufacturing a microstructure according to claim 3 or 5, wherein the first catalytic metal element or the second catalytic metal element is at least one selected from Au, Fe, Ni, Ti, and Pd.   The method for manufacturing a microstructure according to claim 1, wherein the first microstructure has a column shape.   The method for manufacturing a microstructure according to claim 17, wherein the maximum length of a cross section perpendicular to the direction in which the pillar extends in the first microstructure is 100 μm or less. The step (a) includes forming a thin film containing the first dopant element on the support;
Forming the first catalyst fine particles in the form of fine particles containing the first dopant element by heat-treating the thin film;
The manufacturing method of the microstructure of Claim 1 containing this. Forming a first source / drain electrode and a second source / drain electrode on a support;
A first mask is formed on the second source / drain electrode, and only the first dopant element which becomes a first conductivity type dopant for the single crystal semiconductor is formed on the first source / drain electrode. Forming first catalyst fine particles comprising or comprising the first dopant element;
Removing the first mask on the second source / drain electrode;
A second mask is formed on the first source / drain electrode, and only a second dopant element which becomes a dopant of the second conductivity type with respect to the single crystal semiconductor is formed on the second source / drain electrode. Forming second catalyst fine particles comprising or comprising the second dopant element;
Removing the second mask on the first source / drain electrodes;
A source gas containing an element constituting the single crystal semiconductor is introduced in the vicinity of the support surface, the source gas is decomposed by the first catalyst fine particles and the second catalyst fine particles, and the first dopant element is Growing a single crystal semiconductor containing the first microstructure to simultaneously grow a single crystal semiconductor containing the second dopant element to form a second microstructure;
Forming a gate oxide film so as to cover the first microstructure and the second microstructure;
Forming a gate electrode on the gate oxide film;
For producing a field effect transistor including A first microstructure formed on a support and made of a single crystal semiconductor having a first conductivity type;
A first catalyst fine particle containing only the first dopant element or the first dopant element in contact with the microstructure and having the first conductivity type;
A semiconductor microstructure comprising: A second microstructure formed on a support and made of a single crystal semiconductor having a second conductivity type;
A second catalyst fine particle containing a second dopant element in contact with the microstructure and having the second conductivity type;
The semiconductor microstructure according to claim 21, further comprising:   The semiconductor microstructure according to claim 21, wherein the first microstructure has a column shape.   The semiconductor microstructure according to claim 22, wherein each of the first and second microstructures has a column shape.   25. The semiconductor microstructure according to claim 24, wherein the columnar shape has a maximum length of a cross section perpendicular to the longitudinal direction of 100 μm or less. A support;
A first source / drain electrode and a second source / drain electrode formed on the support;
A first microstructure made of a single crystal semiconductor having a first conductivity type formed between the first source / drain electrodes;
The first dopant element which is in contact with the first microstructure and which is in contact with at least one of the first source / drain electrodes and which has the first conductivity type, or the first dopant element Containing first catalyst particulates;
A second microstructure formed of a single crystal semiconductor having a second conductivity type formed between the second source / drain electrodes;
The second dopant element which is in contact with the second microstructure and which is in contact with at least one of the second source / drain electrodes and which has the second conductivity type, or is made of the second dopant element. Containing second catalyst particulates;
A gate oxide film covering the first microstructure and the second microstructure;
A gate electrode formed on the gate oxide film;
Field effect type transistor consisting of