JP2006135749A - Synchronizing signal generating device and video signal processor provided with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronizing signal generating device capable of eliminating a noise pulse superimposed upon an external synchronizing signal by electromagnetic disturbance. <P>SOLUTION: A mask signal generating means 16 outputs a mask signal to be 'L' in a period (called signal change period, for example, for each clock ahead and behind falling of internal synchronizing signal) when falling of an external synchronizing signal is predicted with the internal synchronizing signal and the external synchronizing signal locked and outputs a mask signal to be 'H' in the other periods, and a mask means 17 ORs the external synchronizing signal with the mask signal and eliminates signal change by a noise pulse outside the signal change period of the external synchronizing signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a synchronization signal generator, and more particularly, to a synchronization signal generator that generates a signal synchronized with an externally input signal.

As shown in FIG. 6, the conventional sync signal generator includes an internal sync signal generating means 50 that generates an internal sync signal from a clock signal, and a level representing the phase difference between the input external sync signal and the internal sync signal. A phase difference signal generating means 51 for generating a phase difference signal and an oscillator 52 for generating a clock signal having a frequency corresponding to the phase difference signal are provided and synchronized with an external synchronization signal obtained from a video signal input from the outside. Some generate an internal synchronization signal (see, for example, Patent Document 1).
JP 55-95467 A

  However, in the conventional synchronization signal generator, when a noise pulse due to electromagnetic disturbance is superimposed on the external synchronization signal, the phase difference signal generation means 51 determines that the noise pulse is a change in the external synchronization signal and causes an erroneous phase difference. There is a problem that the signal is generated and the internal synchronization signal is disturbed.

  The present invention has been made to solve the conventional problems, and an object of the present invention is to provide a synchronization signal generator capable of removing a noise pulse superimposed on an external synchronization signal due to electromagnetic disturbance.

  The synchronization signal generating device of the present invention includes an internal synchronization signal generating means for generating an internal synchronization signal from a clock signal, and a phase difference for generating a phase difference signal representing a phase difference between the input external synchronization signal and the internal synchronization signal. A signal generation unit; an oscillator that generates the clock signal having a frequency corresponding to the phase difference signal; a mask signal generation unit that generates a mask signal indicating a signal change period including a signal change of the internal synchronization signal; and the mask And a masking means for removing a signal change outside the signal change period of the external synchronization signal based on a signal and outputting a masked external synchronization signal.

  With this configuration, the signal change outside the signal change period in which the signal change of the external synchronization signal is expected is eliminated. Therefore, the disturbance of the internal synchronization signal due to the influence of electromagnetic disturbance can be suppressed.

  Here, a lock determination for outputting a lock signal indicating whether or not the lock is made depending on whether or not the phase difference between the internal synchronization signal and the external synchronization signal is smaller than a preset value smaller than the signal change period. And, based on the lock signal, the masked external synchronization signal is input to the phase difference signal generation means when locked, and the external synchronization signal is generated as the phase difference signal when not locked. Selecting means for inputting to the means.

  With this configuration, the masked external synchronization signal is used only in a locked state where the mask works properly, and the internal synchronization signal generation processing can be performed efficiently.

  The masking external synchronization signal is provided with a latch means for outputting the external synchronization signal latched by limiting the signal change within the signal change period to one time.

  With this configuration, the signal change outside the signal change period is removed, the signal change within the signal change period is limited to one time, and the disturbance of the internal synchronization signal due to the influence of the electromagnetic disturbance can be suppressed.

  And a latch means for outputting the external synchronization signal latched by limiting the signal change of the masked external synchronization signal within the signal change period to one time, and the selection means is in a locked state. The latched external synchronization signal is input to the phase difference signal generation means, and the external synchronization signal is input to the phase difference signal generation means in an unlocked state.

  With this configuration, the external synchronization signal latched only in the locked state where the mask works properly is used, and the internal synchronization signal generation processing can be performed efficiently.

  Further, the latch means includes latch release signal generation means for stopping removal of signal change by a latch release signal and generating the latch release signal, and the latch release signal generation means includes the internal synchronization signal or the internal signal. A signal obtained by logically inverting the signal is used as the latch release signal.

  With this configuration, the configuration of the latch release signal generation unit can be simplified.

  The video signal processing apparatus according to the present invention includes any one of the above-described synchronization signal generators, and converts the external synchronization signal and the internal synchronization signal generated by the synchronization signal generator into a horizontal synchronization signal of a video signal. It has the structure.

  With this configuration, it is possible to suppress disturbance of the internal synchronization signal due to the influence of electromagnetic disturbance.

  According to the present invention, since the signal change outside the signal change period of the external synchronization signal is removed by the mask means, the disturbance of the internal synchronization signal due to the influence of electromagnetic disturbance can be suppressed.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a synchronization signal generator according to a first embodiment of the present invention. The synchronization signal generator of this embodiment is provided in a video signal processing device that processes a video signal so as to process a video signal obtained by being captured by a camera and output an image to a monitor device inside the vehicle. The video signal processing apparatus is mounted on a vehicle.

  In the following description, when a signal state is indicated, a high level state is simply described as “'H”, a low level state is simply described as “' L”, and a high impedance state is described. Simply described as “'Z'”. Further, a signal changing from 'L' to 'H' is described as "rise" or "rise", and a signal changing from 'H' to 'L' is described as "falling" or "falling". .

  In FIG. 1, a synchronization signal generator 1 according to the present embodiment includes an external synchronization signal input means 11 for inputting an external synchronization signal, an internal synchronization signal generation means 12 for generating an internal synchronization signal from a clock signal, and an external synchronization signal. Phase difference signal generating means 13 for generating a phase difference signal representing a phase difference between the internal synchronization signal and the internal synchronization signal, an oscillator 14 for generating a clock signal having a frequency corresponding to the phase difference signal, an internal synchronization signal and an external signal from the phase difference signal Lock determination means 15 for determining whether the synchronization signal is locked, mask signal generation means 16 for outputting a mask signal in a state where the internal synchronization signal and the external synchronization signal are locked, and external synchronization by the mask signal A mask unit 17 for masking a signal, and a selection unit 18 for selecting an external synchronization signal to be input to the phase difference signal generation unit 13 in accordance with the determination result of the lock determination unit 15. It is provided.

  In the present embodiment, the external synchronization signal is a horizontal synchronization signal of the video signal input to the video signal processing device, and the internal synchronization signal is a horizontal synchronization signal of the video signal used on the output side of the video signal processing device. It is.

  The external synchronization signal input means 11 receives a horizontal synchronization signal separated by an external synchronization signal separation means (not shown) that separates the horizontal synchronization signal from the decoded video signal output from the camera device.

  The internal synchronization signal generating means 12 has a counter (not shown) for counting the number of clocks of the clock signal, and sets the internal synchronization signal to a low level when the count by the counter reaches a predetermined value, and a certain time has elapsed. After that, go to the high level state. The low level and high level periods of the internal synchronization signal generated by the internal synchronization signal generation means 12 are determined so as to have substantially the same cycle as the external synchronization signal.

  The phase difference signal generation means 13 compares the falling time of the internal synchronization signal with the falling time of the external synchronization signal, calculates the phase difference, and outputs the phase difference signal.

  The oscillator 14 generates a clock signal having a frequency corresponding to the phase difference signal. For example, a voltage controlled crystal oscillator can be used.

  The lock determination unit 15 receives the phase difference signal generated by the phase difference signal generation unit 13, and whether or not the phase difference between the internal synchronization signal and the external synchronization signal is smaller than a predetermined phase difference (for example, 1 clock), That is, it is determined whether or not the internal synchronization signal and the external synchronization signal are locked. If the phase difference between the internal synchronization signal and the external synchronization signal is smaller than a predetermined phase difference, it is determined that the lock is established.

  The mask signal generation means 16 is a period during which the external synchronization signal is expected to fall in a state where the internal synchronization signal and the external synchronization signal are locked (referred to as a signal change period, for example, before and after the fall time of the internal synchronization signal). A mask signal that is 'L' for each one clock) and 'H' at other times is output.

  The mask means 17 takes the logical sum of the external synchronization signal and the mask signal, and masks the external synchronization signal.

  The selection unit 18 selects an external synchronization signal to be input to the phase difference signal generation unit 13 according to the determination result of the lock determination unit 15. If locked, the signal masked by the mask means 17 is selected, and if not locked, the signal input to the external synchronization signal input means 11 is selected. Immediately after operating the synchronization signal generator 1, since the internal synchronization signal and the external synchronization signal are not locked, the masking of the external synchronization signal by the mask means 17 is inappropriate. The masking operation is started after the external synchronization signal is locked once.

  The operation of the synchronization signal generator 1 configured as described above will be described with reference to FIGS.

  FIG. 2 is a schematic timing diagram showing one cycle of the external synchronization signal and the internal synchronization signal. FIG. 3 is an enlarged view of a circle in FIG. 2 for explaining the operation of the synchronization signal generator 1. FIG.

  In FIG. 3, s1 is an output clock of the oscillator 14. s2 is an external synchronization signal that falls at time T1, and it is assumed that noise due to electromagnetic disturbance is superimposed at time T3 and time T4. s3 is an internal synchronization signal, which is synchronized with the clock s1 and falls at time T2.

  s4 is an erroneous phase difference signal that becomes an output when the external synchronization signal s2 and the internal synchronization signal s3 are input to the phase difference signal generation means 13. The erroneous phase difference signal s4 starts with high impedance 'Z', but the noise of the external synchronization signal s2 at time T3 and time T4 is determined as a signal change, and the order of the external synchronization signal s2 and the internal synchronization signal s3 is determined. The result does not reflect the phase difference correctly.

  s5 is a mask signal, and one clock before and after the rising edge of the internal synchronization signal s3 becomes 'L', and other times are 'H'. The mask signal s5 can be generated using the counter value used by the internal synchronization signal generating means 12 for generating the internal synchronization signal s3.

  s6 is a masked synchronization signal obtained by the logical sum of the external synchronization signal s2 and the mask signal s5, and falls at the fall time T1 of the external synchronization signal s2, and rises at the time when the mask signal s5 rises.

  In s6, the noise seen in the external synchronization signal s2 is removed. Although the masked external synchronization signal s6 is different in signal rising position from the external synchronization signal s2 before masking, the phase difference signal generating means 13 uses only the signal falling time for the phase difference determination, and the signal rising edge Since the time is not used for the phase difference determination, there is basically no influence on the phase difference determination.

  In the case where the 'L' period of the masked external synchronization signal s6 is short, it is possible to extend the 'L' period later, and this does not affect the determination of the phase difference.

  s7 is a correct phase difference signal that is output when the masked external synchronization signal s6 and internal synchronization signal s3 are input to the phase difference signal generation means 13. The correct phase difference signal s7 is a result of correctly reflecting the phase difference between the external synchronization signal s2 and the internal synchronization signal s3.

  In the above description, the period (signal change period) in which the mask signal s5 is 'L' is set to be one clock before and after the falling time of the internal synchronization signal s3. It can be implemented in any period including the fall time.

  Further, the signal polarity is fixed, but the present invention can be implemented with any signal polarity.

  As described above, in this embodiment, the mask signal generation means 16 generates the mask signal s5 for removing the signal change outside the signal change period of the external synchronization signal, and the external synchronization signal s6 masked by the mask signal s5 Since the phase difference is determined based on the internal synchronization signal s3, disturbance of the internal synchronization signal due to the influence of electromagnetic disturbance can be suppressed.

(Second Embodiment)
Next, FIG. 4 is a diagram showing a synchronization signal generator according to the second embodiment of the present invention. Since the present embodiment is configured in substantially the same manner as the first embodiment described above, the same reference numerals are given to the same configurations, and only the characteristic portions will be described.

  The synchronizing signal generator 2 of the present embodiment outputs “H” in the initial state, sets the output to “L” at the falling time of the external synchronizing signal masked by the masking means 17, and outputs the output by the latch release signal. Latch means 21 for returning to “H” and latch release signal generation means 22 for generating a latch release signal are provided, and the signal change within the period (signal change period) when the mask signal s5 is “L” is suppressed to one time. It is characterized by that.

  The latch means 21 outputs “H” in the initial state, the external synchronization signal masked by the mask means 17 is set as the first input, the output is set to “L” at the falling time of the first input, and the second The output is returned to “H” when the latch release signal which is the input of the signal becomes valid. That is, after the first input falls once and the output becomes “L”, the output is “L” until the latch release signal which is the second input becomes valid regardless of the operation of the first input. Will remain.

  The operation of the synchronization signal generator 2 configured as described above will be described with reference to FIG.

  FIG. 5 is a timing diagram for explaining the operation of the synchronization signal generator 2.

  In FIG. 5, s1 is an output clock of the oscillator 14. s2 is an external synchronization signal, which falls at time T1, and it is assumed that noise due to electromagnetic disturbance is superimposed at time T7 and time T8. s3 is an internal synchronization signal, which is synchronized with the clock s1 and falls at time T2.

  s5 is a mask signal, and one clock before and after the rising edge of the internal synchronization signal s3 becomes 'L', and other times are 'H'. The mask signal s5 can be generated using the counter value used by the internal synchronization signal generating means 12 for generating the internal synchronization signal s3.

  s6 is a masked synchronization signal obtained by the logical sum of the external synchronization signal s2 and the mask signal s5, but the noise pulse superimposed on the external synchronization signal s2 is masked because the mask signal s5 is in the “L” period. It is not removed by the mask of means 17.

  s8 is an erroneous phase difference signal that becomes an output when the masked external synchronization signal s6 and internal synchronization signal s3 are input to the phase difference signal generation means 13. Since the noise pulse is not removed in the masked external synchronization signal s6, it becomes 'H' due to the influence of the noise pulse at time T7, and becomes 'Z' at the falling edge of the internal synchronization signal s3 at time T2, and at time T8. It becomes “H” again due to the influence of the noise pulse. This state is recognized by the phase difference signal generation means 13 as a phase difference of about one cycle between the internal synchronization signal and the external synchronization signal.

  s9 is a latch release signal generated by the latch release signal generation unit 22 and input to the latch unit 21. The initial state is 'H', and 'L' at time T9 set after the rising time of the mask signal s5. 'Become.

  The latch release signal s9 may be generated by using the internal synchronization signal s3 to generate a signal that falls at the rising edge of the internal synchronization signal s3 and release the latch at the rising edge of the internal synchronization signal s3. Even if the signal obtained by logically inverting the internal synchronization signal s3 is used as the latch release signal s9, the latch release can be performed at the rising edge of the internal synchronization signal s3, and the configuration of the latch release signal generation means 22 can be simplified.

  s10 is an external synchronization signal latched by the latch means 21. The initial state is 'H', and becomes 'L' at time T7 due to the influence of the noise pulse of the masked external synchronization signal s6. Thereafter, it becomes 'H' at the falling edge of the latch release signal s9 at time T9.

  s11 is a corrected phase difference signal, which is an output when the latched external synchronization signal s10 and internal synchronization signal s3 are input to the phase difference signal generation means 13. The corrected phase difference signal s11 becomes “H” at the time T7 due to the influence of the noise pulse, and there is a deviation from the original falling time T1 of the external synchronization signal s2. However, the influence on the oscillator 14 is slight and erroneous. The internal synchronization signal is not disturbed unlike when the phase difference signal s8 is applied to the oscillator 14.

  Although the description has been made with the signal polarity fixed, the present invention can be implemented with any signal polarity.

  As described above, in the present embodiment, the mask signal generation means 16 generates the mask signal s5 for removing the signal change outside the signal change period of the external synchronization signal, and the external synchronization signal s6 masked by the mask signal s5 is generated. The signal change within the signal change period is suppressed to once by the latch means 21, and the phase difference is determined by the latched external synchronization signal s10 and the internal synchronization signal s3. Therefore, the internal synchronization due to the influence of electromagnetic disturbance is detected. Signal disturbance can be suppressed.

  As described above, the synchronization signal generating device according to the present invention has an effect that the disturbance of the internal synchronization signal due to the influence of electromagnetic disturbance can be suppressed, and the period is the same as the horizontal synchronization signal of the video signal processing device. Since it is long, it is useful for generating a synchronization signal of a signal that is easily affected by an electromagnetic disturbance, and is useful as a synchronization signal generator used in an environment with a lot of electromagnetic disturbance such as a vehicle.

The block diagram of the synchronous signal generator in the 1st Embodiment of this invention Schematic timing diagram showing one cycle of an external synchronization signal and an internal synchronization signal of the synchronization signal generator in the first embodiment of the present invention Timing diagram for explaining the operation of the synchronization signal generator in the first embodiment of the present invention The block diagram of the synchronous generator in the 2nd Embodiment of this invention Timing diagram for explaining the operation of the synchronization signal generator in the first embodiment of the present invention Block diagram of a conventional sync signal generator

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Synchronization signal generator 11 External synchronization signal input means 12 Internal synchronization signal generation means 13 Phase difference signal generation means 14 Oscillator 15 Lock determination means 16 Mask signal generation means 17 Mask means 18 Selection means 2 Synchronization signal generation apparatus 21 Latch means 22 Latch Release signal generation means 50 Internal synchronization signal generation means 51 Phase difference signal generation means 52 Oscillator

Claims (6)

An internal synchronization signal generating means for generating an internal synchronization signal from a clock signal; a phase difference signal generating means for generating a phase difference signal representing a phase difference between the input external synchronization signal and the internal synchronization signal; and the phase difference signal An oscillator that generates the clock signal having a frequency corresponding to the internal synchronization signal, a mask signal generation unit that generates a mask signal indicating a signal change period including a signal change of the internal synchronization signal, and the external synchronization signal based on the mask signal. And a masking means for outputting a masked external synchronization signal by removing a signal change outside the signal change period. Lock determination means for outputting a lock signal indicating whether or not locking is performed depending on whether or not a phase difference between the internal synchronization signal and the external synchronization signal is smaller than a preset value smaller than the signal change period; Based on the lock signal, the masked external synchronization signal is input to the phase difference signal generation means in the locked state, and the external synchronization signal is input to the phase difference signal generation means in the unlocked state. The synchronization signal generator according to claim 1, further comprising a selection unit that performs the selection. 2. The synchronization signal according to claim 1, further comprising latch means for outputting an external synchronization signal latched by limiting a signal change within the signal change period of the masked external synchronization signal to one time. Generator. Latch means for outputting the external synchronization signal latched by limiting the signal change within the signal change period of the masked external synchronization signal to one time, and the selection means latches in the locked state. 3. The synchronization signal generation according to claim 2, wherein the external synchronization signal is input to the phase difference signal generation unit, and the external synchronization signal is input to the phase difference signal generation unit in an unlocked state. apparatus. The latch means includes a latch release signal generation means for stopping signal change removal by a latch release signal and generating the latch release signal, and the latch release signal generation means is configured to logically output the internal synchronization signal or the internal signal. 5. The synchronization signal generator according to claim 3, wherein the inverted signal is used as the latch release signal. A synchronization signal generator according to any one of claims 1 to 5, comprising the external synchronization signal and the internal synchronization signal generated by the synchronization signal generator as a horizontal synchronization signal of a video signal. A characteristic video signal processing apparatus.

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