JP2006135342A - Process for manufacturing nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a stable and high-reliability nonvolatile semiconductor memory. <P>SOLUTION: Trenches 13a and 13b are formed in a p-type silicon semiconductor substrate 15, and impurity diffusion layers 12a and 12b are formed on the bottom face of the trenches 13a and 13b. A first insulating film 16a composed of a silicon oxide film, a charge-capturing film 16b composed of a silicon nitride film, and a second insulating film 16c composed of a silicon oxide film are then sequentially formed on the p-type silicon semiconductor substrate 15 thus forming a gate insulating film 16 of three layer structure. A gate electrode 11 is formed on the gate insulating film 16. A protrusion 14 formed by the trenches 13a and 13b serves as the channel region of a nonvolatile semiconductor memory 10. Since effective channel length is ensured, even if the element is microfabricated, a high reliability stabilized nonvolatile semiconductor memory 10 can be realized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory, and more particularly to a method for manufacturing a nonvolatile semiconductor memory in which information is stored by capturing electrons in a gate insulating film formed between a semiconductor substrate and a gate electrode.

  There has been proposed a nonvolatile semiconductor memory in which electrons are locally captured in an insulating film having a charge trapping level and information is written / read out (see, for example, Patent Document 1). In recent years, there has been proposed a nonvolatile semiconductor memory in which 2 bits of information is stored per memory cell by applying this.

23A and 23B are diagrams showing a configuration example of a conventional nonvolatile semiconductor memory, in which FIG. 23A is a schematic sectional view in each operation state of a write operation, and FIG. 23B is a read operation.
The nonvolatile semiconductor memory 200 has a pair of impurity diffusion layers 202 and 203 formed in the surface region of the p-type silicon semiconductor substrate 201. The impurity diffusion layers 202 and 203 function as a source / drain in the nonvolatile semiconductor memory 200. A gate insulating film 204 is formed on the p-type silicon semiconductor substrate 201, and a gate electrode 205 is formed on the gate insulating film 204.

  The gate insulating film 204 has a three-layer structure in which a first insulating film 204a made of a silicon oxide film, a charge trapping film 204b made of a silicon nitride film, and a second insulating film 204c made of a silicon oxide film are sequentially stacked. .

  In writing / reading of information in the nonvolatile semiconductor memory 200, electrons are locally captured in a charge trapping region formed in the charge trapping film 204b near the impurity diffusion layers 202 and 203 under an appropriate applied voltage. Is done by. In FIG. 23, two charge trapping regions, a left bit region 206 and a right bit region 207, are shown as the charge trapping region. The non-volatile semiconductor memory 200 can write / read information of 1 bit in each of the left bit area 206 and the right bit area 207 for a total of 2 bits.

  In such a nonvolatile semiconductor memory 200, when information is written in the left bit region 206, for example, voltages of 5V and 0V are applied to the impurity diffusion layers 202 and 203, respectively, and a voltage of about 8V is applied to the gate electrode 205. Apply. As a result, as shown in FIG. 23A, the inversion layer 208a is formed between the impurity diffusion layers 202 and 203, and channel hot electrons generated in the vicinity of the impurity diffusion layer 202 jump over the first insulating film 204a to the left. Captured in the bit region 206.

  On the other hand, when information is read from the left bit region 206, a voltage in the direction opposite to that at the time of writing information is applied to the impurity diffusion layers 202 and 203. For example, voltages of 0V and 2V are applied to the impurity diffusion layers 202 and 203, respectively, and a voltage of about 5V is applied to the gate electrode 205.

  Here, when electrons are trapped in the left bit region 206, as shown in FIG. 23B, the inversion layer 208b is blocked by the influence of the trapped electrons, and current flows between the impurity diffusion layers 202 and 203. Not flowing.

  Further, when information is read from the left bit region 206 when no electrons are captured in the left bit region 206, the presence or absence of the trapped electrons in the right bit region 207 opposite to this does not affect the reading operation. Has been. This is because if the electrons are captured in the write bit region 207, the inversion layer 208b disappears in the vicinity of the impurity diffusion layer 203, but the range is narrow with respect to the channel length, and the influence on the current can be ignored. This is because it is so small. If electrons are not captured in the write bit region 207, the inversion layer 208b is not lost, and a current corresponding to the applied voltage flows between the impurity diffusion layers 202 and 203.

The same applies to the case where the electron holding states in the left bit area 206 and the right bit area 207 are reversed.
By the way, in recent years, further miniaturization, higher performance, and high reliability are required for various semiconductor elements including such a nonvolatile semiconductor memory.
JP-A-11-67937

  However, when the channel length is shortened by miniaturization of the semiconductor element, the ratio of the length of the charge trapping region to the channel length is increased. For this reason, when reading information from one bit area, there is a problem that the influence of the presence or absence of trapped electrons in the other bit area opposite to this cannot be ignored.

  24A and 24B are diagrams showing a configuration example of a miniaturized nonvolatile semiconductor memory, where FIG. 24A shows a state in which the inversion layer has partially disappeared, and FIG. 24B shows a state in which the position of the bit region has shifted. Each is shown.

  In the nonvolatile semiconductor memory 300, the distance between the left bit region 302 and the right bit region 303 formed in the charge trapping film 301 is reduced due to the channel length being shortened.

  In such a nonvolatile semiconductor memory 300, for example, a case is considered where information is read from the left bit region 302 when electrons are not captured in the left bit region 302 and electrons are captured in the right bit region 303. .

  In this case, as shown in FIG. 24A, the inversion layer 304 in the channel region disappears in the vicinity of the write bit region 303 due to the negative electric field generated by the trapped electrons. As the channel length becomes shorter, the ratio of the disappearance range of the inversion layer 304 to the channel length becomes larger than in the prior art. For this reason, when the left bit region 302 is read, the current flowing between the impurity diffusion layers 305 and 306 is greatly reduced, which may cause a problem that an accurate read operation cannot be performed.

  In the conventional structure, the charge trapping film 301 is formed corresponding to the entire channel region. For this reason, when the drain voltage or gate voltage at the time of writing varies, the write bit region 303 that has captured electrons may shift to the left bit region 302 side as shown in FIG. As a result, there arises a problem that the effective channel length is shortened. This problem becomes more prominent as the channel length becomes shorter and the distance between the bit regions, which are charge trapping regions, becomes shorter. As a result, for the same reason as described in FIG. This makes it impossible to perform a proper read operation.

  With respect to such a problem, it can be considered that the effect of the disappearance can be avoided by pinching off the inversion layer 304 at the time of reading the left bit region 302 in front of the opposed right bit region 303. However, in this case, a high voltage must be applied between the source / drain or the gate electrode. As a result, channel hot electrons are generated, and when this is captured by the charge trapping film 301, there may be a problem that erroneous writing is performed at the time of reading.

  A method of reducing the number of electrons trapped in the charge trapping region to narrow the range of the charge trapping region itself can be considered, but in this case, data retention reliability is lowered. Further, in this case, the negative electric field formed by the trapped electrons is reduced. For example, a state is assumed in which there are captured electrons in the left bit region 302 and no captured electrons in the right bit region 303. In such a state, if the number of trapped electrons is small, the inversion layer 304 in the vicinity of the left bit region 302 may not be sufficiently lost during the read operation of the left bit region 302, causing a problem that current flows.

  The present invention has been made in view of these points, and an object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory capable of performing a stable and reliable operation against miniaturization. .

  In the present invention, in order to solve the above problem, in a method for manufacturing a nonvolatile semiconductor memory having a charge trapping region for trapping electrons in a gate insulating film formed between a semiconductor substrate and a gate electrode, A groove is formed in the semiconductor substrate, a second conductivity type impurity diffusion layer is formed on a bottom surface of the formed groove, and a charge trapping region is formed on the semiconductor substrate on which the impurity diffusion layer is formed. A non-volatile semiconductor memory manufacturing method is provided, wherein a gate insulating film including a charge trapping film is formed.

  According to this method, for example, in the formation of the nonvolatile semiconductor memory 10 shown in FIG. 2, the grooves 13a and 13b are formed in the p-type silicon semiconductor substrate 15, and the n-type impurity diffusion layer 12a is formed on the bottom surface of the grooves 13a and 13b. , 12b. Then, the gate electrode 11 is formed on the p-type silicon semiconductor substrate 15 via the gate insulating film 16. Thereby, the non-volatile semiconductor memory 10 having the convex portion 14 formed by the grooves 13a and 13b as a channel region is formed.

  In the present invention, a gate insulating film in which a charge trapping region is formed on a side wall portion of the convex portion is formed on a semiconductor substrate having the convex portion. As a result, even if the nonvolatile semiconductor memory is miniaturized, an effective channel length is ensured, so that it is easy to miniaturize and a highly reliable nonvolatile semiconductor memory can be obtained.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the first embodiment will be described.
1 is a plan view of the nonvolatile semiconductor memory according to the first embodiment, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG.

As shown in FIG. 1, the nonvolatile semiconductor memory 10 includes a gate electrode 11 and impurity diffusion layers 12a and 12b that function as source / drains, which are orthogonal to each other.
As shown in FIG. 2, the non-volatile semiconductor memory 10 has a p-type silicon semiconductor substrate 15 on which a convex portion 14 sandwiched between two grooves 13a and 13b is formed. Impurity diffusion layers 12a and 12b are formed on the bottom surfaces of the grooves 13a and 13b, respectively. A gate insulating film 16 is formed on the p-type silicon semiconductor substrate 15. The gate insulating film 16 has a three-layer structure in which a first insulating film 16a made of a silicon oxide film, a charge trapping film 16b made of a silicon nitride film, and a second insulating film 16c made of a silicon oxide film are sequentially stacked. Yes. A gate electrode 11 is formed on the gate insulating film 16. In the nonvolatile semiconductor memory 10, the convex portion 14 of the p-type silicon semiconductor substrate 15 becomes the channel region.

  In the non-volatile semiconductor memory 10, the gate electrode 11 is formed on the gate insulating film 16 of the memory cell formed continuously in the horizontal direction in FIG. 1 in the AA cross section shown in FIG. 2. On the other hand, in the BB cross section shown in FIG. 3, the gate electrodes 11 of the memory cells continuous in the vertical direction in FIG. 1 are formed electrically independently.

  In this nonvolatile semiconductor memory 10, a charge trapping region (bit region) that captures electrons when writing information on the side wall (including the side wall and the vicinity of the side wall) of the convex portion 14 of the charge trapping film 16 b by applying a predetermined voltage. ) Is formed. The nonvolatile semiconductor memory 10 has two bit regions as the charge trapping region, that is, the left bit region 17a on the impurity diffusion layer 12a side and the write bit region 17b on the impurity diffusion layer 12b side shown in FIG. In the nonvolatile semiconductor memory 10, writing / reading of information of 1 bit, 2 bits in total, is performed in the left bit region 17a and the right bit region 17b.

FIG. 4 is a diagram showing a circuit configuration example of the nonvolatile semiconductor memory.
The circuit of the nonvolatile semiconductor memory includes a memory cell array, a row decoder, a column decoder, a sense amplifier, a reference current generation circuit (not shown), an input / output circuit, a control circuit, and the like.

  The memory cell array is composed of a plurality of memory cells M00, M01,..., And each memory cell M00, M01,... Has two bit areas, a left bit area and a right bit area.

  The gate electrode and the source / drain of each of the memory cells M00, M01,... Are connected to the word lines WL0, WL1,. For example, the gate electrode of the memory cell M00 is connected to the word line WL0, and the source / drain is connected to the bit lines BL0 and BL1.

  In the nonvolatile semiconductor memory 10 shown in FIGS. 1 to 3, a predetermined voltage is applied to the gate electrode 11 and the impurity diffusion layers 12a and 12b serving as the source / drain from the word line and the bit line. Done.

  FIGS. 5A and 5B are diagrams for explaining the operation of the nonvolatile semiconductor memory according to the first embodiment. FIG. 5A is a diagram for explaining a write operation, FIG. 5B is a diagram for explaining a read operation, and FIG. 5A and 5B show a state in which electrons are captured in the write bit region 17b.

  First, a case where information is written to the write bit area 17b will be described. In this case, for example, the voltage of the impurity diffusion layer 12a serving as the source is set to 0V, and the voltage of the impurity diffusion layer 12b serving as the drain is set to about 5V to generate a potential difference between the source and drain. Then, a high voltage of about 10 V is applied to the gate electrode 11. As a result, as shown in FIG. 5A, the inversion layer 18a is formed between the impurity diffusion layers 12a and 12b. Then, channel hot electrons generated in the vicinity of the impurity diffusion layer 12b jump over the first insulating film 16a and are captured in the write bit region 17b.

  When reading information from the write bit region 17b, a voltage in the direction opposite to that in writing is applied between the source and drain. That is, for example, the voltage of the impurity diffusion layer 12 a serving as the drain is set to 2 V, the voltage of the impurity diffusion layer 12 b serving as the source is set to about 0 V, and a voltage of about 5 V is applied to the gate electrode 11. Thereby, the inversion layer 18b is formed between the impurity diffusion layers 12a and 12b.

  Here, as shown in FIG. 5B, when electrons are trapped in the write bit region 17b, the inversion layer 18b is not formed in the vicinity of the write bit region 17b due to the negative electric field of the electrons. As a result, no current flows between the source / drain. On the other hand, when electrons are not captured in the write bit region 17b, an inversion layer 18b is also formed near the write bit region 17b (not shown), and a current flows between the source / drain. Thus, the nonvolatile semiconductor memory 10 can store 1-bit information corresponding to the presence or absence of trapped electrons in the charge trapping region.

  Information can be written / read to / from the left bit area 17a in the same manner as in the right bit area 17b. In this case, the direction of the voltage applied when writing / reading information to / from the write bit region 17b is reversed.

  When erasing information once written in the charge trapping region, a negative high voltage of, for example, about −10 V is applied to the gate electrode 11, and a positive high voltage of about 10 V is applied to the p-type silicon semiconductor substrate 15. Apply. As a result, as shown in FIG. 5C, electrons captured in the write bit region 17b are extracted into the p-type silicon semiconductor substrate 15 by FN tunneling. At this time, the source / drain is open or 0V. The same applies when erasing the information in the left bit area 17a.

  Further, as another method for erasing information, there is a method in which a negative high voltage of, for example, about -10 V is applied to the gate electrode 11 and a positive voltage of, for example, about 5 V is applied to the impurity diffusion layer 12b. . In this method, a depletion layer is formed in the vicinity of the impurity diffusion layer 12b as a result of voltage application, and the charge trapping region is neutralized by injecting hot holes generated here into the write bit region 17b. At this time, the impurity diffusion layer 12a is open or 0V.

  When erasing information in the left bit region 17a by this method, similarly, a negative high voltage of, for example, about -10V is applied to the gate electrode 11, and a positive voltage of, for example, about 5V is applied to the impurity diffusion layer 12a. Apply. The generated hot holes are injected into the left bit region 17a to neutralize them.

  Further, when it is desired to simultaneously erase the information in the left bit region 17a and the right bit region 17b, a negative high voltage may be applied to the gate electrode 11 and a positive voltage may be applied to both the impurity diffusion layers 12a and 12b.

  As described above, in the nonvolatile semiconductor memory 10 in which the gate electrode 11 is formed on the p-type silicon semiconductor substrate 15 via the gate insulating film 16, the channel region is formed in a convex shape. Then, a charge trapping region is formed in the gate insulating film 16 on the side wall of the convex portion 14 of the p-type silicon semiconductor substrate 15. Thereby, an effective channel length can be ensured even for miniaturization of elements. Therefore, it is possible to obtain a highly reliable nonvolatile semiconductor memory in which element miniaturization is easy.

Next, a method for manufacturing the nonvolatile semiconductor memory 10 having the above configuration will be described.
6 and 7 are explanatory views of the method for manufacturing the nonvolatile semiconductor memory according to the first embodiment. FIG. 6A is a first ion implantation step, and FIG. 6B is a convex portion forming step. 6C shows the second ion implantation step, FIG. 7A shows the impurity diffusion layer forming step, FIG. 7B shows the gate insulating film forming step, and FIG. 7C shows the polycide layer forming step. It is a schematic sectional drawing in a process.

First, a predetermined well is formed on the p-type silicon semiconductor substrate 15, and further element isolation in the peripheral circuit region is performed (not shown).
Next, as shown in FIG. 6A, boron (B) ions, which are p-type impurities, are ion-implanted into the entire surface of the p-type silicon semiconductor substrate 15 by a known ion implantation method. This ion implantation is performed under conditions of an acceleration energy of about 30 keV to 90 keV and a dose amount of about 5 × 10 ¹¹ ions / cm ² to 5 × 10 ¹² ions / cm ² .

  Next, as shown in FIG. 6B, a photoresist 19 is formed on the p-type silicon semiconductor substrate 15 by known photolithography. Subsequently, a part of the p-type silicon semiconductor substrate 15 is selectively removed by etching using the photoresist 19 as a mask to form grooves 13a and 13b. Thereby, the convex part 14 is formed in the p-type silicon semiconductor substrate 15.

  Here, the grooves 13a and 13b are, for example, about 0.3 μm wide and about 0.15 μm deep. However, these widths and depths are merely examples, and can be arbitrarily set in consideration of the applied voltage range of the nonvolatile semiconductor memory to be formed, required data retention characteristics, and the like.

Next, as shown in FIG. 6C, boron ions are implanted with the p-type silicon semiconductor substrate 15 inclined by a known ion implantation method using the photoresist 19 as a mask. This ion implantation is performed under conditions of an acceleration energy of about 30 keV to 90 keV and a dose amount of about 5 × 10 ¹¹ ions / cm ² to 5 × 10 ¹² ions / cm ² .

Next, as shown in FIG. 7A, using the photoresist 19 as a mask, arsenic (As), which is an n-type impurity, is accelerated at an energy of about 50 keV and a dose amount of 1 × 10 ¹⁵ ions / cm ² to 5 × 10 5. Ions are implanted under conditions of about ¹⁵ ions / cm ² . Thereby, impurity diffusion layers 12a and 12b functioning as the source / drain and bit line of the memory cell are formed.

  Next, as shown in FIG. 7B, the photoresist 19 is removed, and a silicon oxide film is formed to a thickness of about 10 nm on the exposed p-type silicon semiconductor substrate 15 by a known thermal oxidation method. A first insulating film 16a is formed.

Next, a silicon nitride film is formed to a thickness of about 10 nm on the first insulating film 16a by a known CVD (Chemical Vapor Deposition) method to form a charge trapping film 16b.
Thereafter, according to a known thermal oxidation method, a heat treatment is performed in an oxygen atmosphere at a temperature of about 900 ° C. to 950 ° C. for a time of about 30 minutes to 60 minutes to oxidize the upper portion of the charge trapping film 16b by about 10 nm. An insulating film 16c is formed.

Thereby, the gate insulating film 16 having a three-layer structure in which the first insulating film 16a, the charge trapping film 16b, and the second insulating film 16c are sequentially stacked is formed.
Next, as shown in FIG. 7C, a polycide layer 11a is formed on the entire surface by a known CVD method. The polycide layer 11a is formed by forming a polycrystalline silicon film containing about 2 × 10 ²⁰ atoms / cm ³ to 6 × 10 ²⁰ atoms / cm ^{3 of} phosphorus (P) with a thickness of about 300 nm and a tungsten silicide film with a thickness of 200 nm. Perform by forming to a certain extent.

  Next, the polycide layer 11a is processed by a known photolithography and etching method to form the gate electrode 11 shown in FIGS. Thereafter, impurity activation heat treatment is performed by a known thermal diffusion method to diffuse and activate the impurity diffusion layers 12a and 12b.

Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.
In the above description, the boron ion ion implantation shown in FIGS. 6A and 6C is performed to adjust the impurity concentration in the convex portion 14 which becomes the channel region. Therefore, these steps can be performed as necessary, and the order thereof is not limited thereto. For example, the ion implantation process shown in FIG. 6A can be performed after the formation of the gate insulating film 16 shown in FIG.

Next, as modifications of the first embodiment, second to fifth embodiments will be described with reference to the drawings.
First, a second embodiment will be described.

  FIGS. 8A and 8B are explanatory views of the method for manufacturing the nonvolatile semiconductor memory according to the second embodiment, wherein FIG. 8A is an impurity diffusion layer forming step, FIG. 8B is a gate insulating film forming step, and FIG. 8C is a polycide layer. It is a schematic sectional drawing in each process of a formation process. In FIG. 8, the same components as those shown in FIGS. 6 and 7 are denoted by the same reference numerals.

First, a predetermined well is formed on the p-type silicon semiconductor substrate 15, and further element isolation in the peripheral circuit region is performed (not shown).
Next, as shown in FIG. 8A, a silicon oxide film is formed to a thickness of about 15 nm on the p-type silicon semiconductor substrate 15 by a known thermal oxidation method, and the upper surface insulating film 21 is used as a third insulating film. Form.

  Subsequent to the formation of the upper surface insulating film 21 is substantially the same as that of the first embodiment. That is, first, a photoresist 19 is formed on the p-type silicon semiconductor substrate 15 by known photolithography. Subsequently, the upper surface insulating film 21 and a part of the p-type silicon semiconductor substrate 15 are selectively removed by an etching method using the photoresist 19 as a mask to form the grooves 13a and 13b and the protrusions 14.

Thereafter, using the photoresist 19 as a mask, arsenic is ion-implanted under conditions of an acceleration energy of about 50 keV and a dose of about 1 × 10 ¹⁵ ions / cm ² to 5 × 10 ¹⁵ ions / cm ² , and the impurity diffusion layers 12a and 12b. Form.

  Next, as shown in FIG. 8B, the photoresist 19 is removed, and a silicon oxide film is formed to a thickness of about 10 nm on the exposed p-type silicon semiconductor substrate 15 by a known thermal oxidation method. A first insulating film 16a is formed.

Next, a silicon nitride film is formed to a thickness of about 10 nm on the first insulating film 16a by a known CVD method to form a charge trapping film 16b.
Thereafter, according to a known thermal oxidation method, a heat treatment is performed in an oxygen atmosphere at a temperature of about 900 ° C. to 950 ° C. for a time of about 30 minutes to 60 minutes to oxidize the upper portion of the charge trapping film 16b by about 10 nm. An insulating film 16c is formed.

  Thereby, the upper surface portion of the convex portion 14 has a three-layer structure of the upper surface insulating film 21, the charge trapping film 16b, and the second insulating film 16c. On the other hand, as for the portions other than the upper surface portion of the convex portion 14 (side wall portions of the convex portion 14 and upper surface portions of the impurity diffusion layers 12a and 12b), as in the first embodiment, the first insulating film 16a, the charge trapping film 16b and the first The two-insulating film 16c has a three-layer structure.

  In the subsequent steps, as in the first embodiment, as shown in FIG. 8C, a polycide layer 11a is formed by forming a polycrystalline silicon film and a tungsten silicide film on the entire surface by CVD. After the polycide layer 11a is processed, the impurity diffusion layers 12a and 12b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed in this way, the film thickness of the upper surface insulating film 21 on the upper surface portion of the convex portion 14 is formed thicker than the film thickness of the first insulating film 16a on the side wall portion of the convex portion 14. it can. This prevents electrons from being trapped by the charge trapping film 16b beyond the upper surface insulating film 21 in the channel region in the convex portion 14, and the electrons are selected with respect to the charge trapping film 16b on the side wall portion of the convex portion 14. Will be captured. Therefore, the position of the charge trapping region formed in the charge trapping film 16b can be more accurately controlled, and the charge trapping region can be surely positioned on the side wall of the convex portion 14, so that it is stable and reliable. Thus, a nonvolatile semiconductor memory that performs high operation can be obtained.

  Next, a third embodiment will be described. However, in the third embodiment, the steps shown in FIGS. 6A to 6C and FIG. 7A in the first embodiment are similarly performed. The subsequent steps will be described below.

  FIG. 9 and FIG. 10 are explanatory diagrams of the method of manufacturing the nonvolatile semiconductor memory according to the third embodiment. FIG. 9A shows the first insulating film and charge trapping film forming step, and FIG. 9C shows the first oxide film removal process, FIG. 9D shows the charge trap film removal process, FIG. 10A shows the second oxide film removal process, and FIG. 10B. FIG. 10C is a schematic sectional view in each step of the polycide layer forming step. 9 and 10, the same components as those shown in FIGS. 6 and 7 are denoted by the same reference numerals.

  First, after removing the photoresist 19 shown in FIG. 7A, a silicon oxide film is formed on the exposed p-type silicon semiconductor substrate 15 by a known thermal oxidation method as shown in FIG. 9A. The first insulating film 16a is formed to a thickness of about 10 nm. Next, a silicon nitride film is formed to a thickness of about 10 nm on the first insulating film 16a by a known CVD method to form a charge trapping film 16b.

Next, as shown in FIG. 9B, an oxide film 31 having a thickness of about 500 nm is formed on the entire surface by a known CVD method.
Next, as shown in FIG. 9C, the oxide film 31 is removed by a known CMP (Chemical Mechanical Polishing) method using the silicon nitride film of the charge trapping film 16b as a stopper until the silicon nitride film is exposed. .

Next, as shown in FIG. 9D, the charge trapping film 16b exposed on the surface is removed by a known etching method using a phosphoric acid solution.
Next, as shown in FIG. 10A, the oxide film 31 inside the grooves 13a and 13b is removed by a known etching method using a hydrogen fluoride solution.

  Next, as shown in FIG. 10B, a silicon oxide film having a thickness of about 20 nm is formed on the exposed p-type silicon semiconductor substrate 15 by a known thermal oxidation method, and the upper surface is formed as a fourth insulating film on the convex portion 14. A partial insulating film 32 is formed. At this time, the upper portion of the remaining charge trapping film 16b is also partially oxidized to form a second insulating film 16c made of a silicon oxide film having a thickness of about 2 nm to 5 nm. Accordingly, the upper surface insulating film 32 is formed on the upper surface portion of the convex portion 14, and the portion other than the upper surface portion of the convex portion 14 has a three-layer structure of the first insulating film 16a, the charge trapping film 16b, and the second insulating film 16c. Become.

  In the subsequent steps, as in the first embodiment, as shown in FIG. 10C, after the polycide layer 11a is formed and processed, the impurity diffusion layers 12a and 12b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed in this way, the charge trapping film 16b is not formed on the upper surface portion of the convex portion 14, so that electrons in the channel region are selectively captured by the charge trapping film 16b on the side wall portion of the convex portion 14. . As described above, since the position control of the charge trapping region can be performed more accurately, a non-volatile semiconductor memory that performs a stable and highly reliable operation can be obtained.

Furthermore, the threshold value can be set by forming the upper surface insulating film 32 with an appropriate film thickness.
Next, a fourth embodiment will be described. However, in the fourth embodiment, the steps shown in FIGS. 6A to 6C and FIG. 7B in the first embodiment are similarly performed. The subsequent steps will be described below.

  FIGS. 11A and 11B are explanatory views of the method for manufacturing the nonvolatile semiconductor memory according to the fourth embodiment, in which FIG. 11A is a gate insulating film removing step, FIG. (C) is a schematic sectional drawing in each process of a polycide layer formation process. In FIG. 11, the same components as those shown in FIGS. 6 and 7 are denoted by the same reference numerals.

  First, as shown in FIG. 11A, the entire surface of the gate insulating film 16 shown in FIG. 7B is etched using a known etching method until the p-type silicon semiconductor substrate 15 is exposed. Thereby, only the side wall portion of the convex portion 14 has a three-layer structure of the first insulating film 16a, the charge trapping film 16b, and the second insulating film 16c.

  Next, as shown in FIG. 11B, a silicon oxide film having a thickness of about 20 nm is formed on the exposed p-type silicon semiconductor substrate 15 using a known thermal oxidation method. As a result, the upper surface insulating film 41 is formed on the upper surface of the convex portion 14, and the bottom surface insulating films 42 a and 42 b are formed on the bottom surfaces of the grooves 13 a and 13 b as fourth insulating films.

  In the subsequent steps, as in the first embodiment, as shown in FIG. 11C, after the polycide layer 11a is formed and processed, the impurity diffusion layers 12a and 12b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed as described above, the charge trapping film 16b is formed on the side wall of the convex portion 14. At the same time, bottom surface insulating films 42a and 42b having a lower capacitance than those of the three-layer structure are formed on the upper surface portions of the impurity diffusion layers 12a and 12b. Therefore, the parasitic capacitance between the gate electrode 11 shown in FIGS. 1 to 3 formed from the polycide layer 11a and the impurity diffusion layers 12a and 12b serving as the source / drain is reduced. Thereby, a high-speed and stable nonvolatile semiconductor memory can be obtained.

In addition, since the charge trapping film 16b is not formed on the upper surface of the convex portion 14, electrons are selectively captured by the charge trapping film 16b on the side wall of the convex portion 14, and accurate position control of the trapping region is possible.
Next, a fifth embodiment will be described. However, in the fifth embodiment, the processes up to the step shown in FIG. 8B in the second embodiment are similarly performed. The subsequent steps will be described below.

  12A and 12B are explanatory diagrams of a method for manufacturing the nonvolatile semiconductor memory according to the fifth embodiment, in which FIG. 12A is a gate insulating film removing step, FIG. (C) is a schematic sectional drawing in each process of a polycide layer formation process. In FIG. 12, the same components as those shown in FIG. 8 are denoted by the same reference numerals.

  First, after the step of forming the gate insulating film in FIG. 8B, as shown in FIG. 12A, the entire surface is etched using a known etching method until the p-type silicon semiconductor substrate 15 is exposed. Thereby, only the side wall portion of the convex portion 14 has a three-layer structure of the first insulating film 16a, the charge trapping film 16b, and the second insulating film 16c. At this time, the upper surface portion insulating film 21 formed as the third insulating film remains on the upper surface portion of the convex portion 14 with a film thickness of about 5 nm.

  Next, as shown in FIG. 12B, a silicon oxide film having a thickness of about 20 nm is formed on the exposed p-type silicon semiconductor substrate 15 using a known thermal oxidation method. At this time, the upper surface insulating film 21 is also slightly oxidized. Thereby, an upper surface insulating film 51 is newly formed on the upper surface of the convex portion 14 as a fourth insulating film. Also, bottom surface insulating films 52a and 52b are formed as fourth insulating films on the bottom surface of the grooves 13a and 13b.

  In the subsequent steps, as in the second embodiment, as shown in FIG. 12C, after the polycide layer 11a is formed and processed, the impurity diffusion layers 12a and 12b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed as described above, the gate insulating film, the upper surface insulating film 51, and the bottom surface insulating films 52a and 52b on the side wall of the convex portion 14 are independently formed. Therefore, the threshold value can be set by forming the upper surface insulating film 51 with an appropriate film thickness.

  In addition, bottom surface insulating films 52a and 52b having a lower capacity than that of the three-layer structure can be formed on the upper surfaces of the impurity diffusion layers 12a and 12b. Therefore, the parasitic capacitance between the gate electrode and the source / drain is reduced, and a high-speed and stable nonvolatile semiconductor memory can be obtained.

Furthermore, since the charge trapping film 16b is formed only on the side wall of the convex portion 14, the position control of the charge trapping region can be performed more accurately.
As described above, as described in the second to fifth embodiments, the channel region of the nonvolatile semiconductor memory is convex, and the charge trapping region is formed in the gate insulating film 16 on the side wall of the convex portion 14. As a result, an effective channel length can be ensured even for element miniaturization, and a highly reliable nonvolatile semiconductor memory that can be easily miniaturized can be obtained.

  In the above description, the case where the channel region of the nonvolatile semiconductor memory is convex has been described, but the channel region may be concave. Next, a structure and a manufacturing method of a nonvolatile semiconductor memory having a concave channel region will be described as a sixth embodiment.

FIG. 13 is a diagram illustrating a configuration example of the nonvolatile semiconductor memory according to the sixth embodiment.
The nonvolatile semiconductor memory 60 includes a p-type silicon semiconductor substrate 65 having a recess in which a groove 63 is formed. Impurity diffusion layers 62a and 62b are formed in the two convex portions 64a and 64b forming the concave portions, respectively.

  A gate insulating film 66 is formed on the p-type silicon semiconductor substrate 65. The gate insulating film 66 has a three-layer structure in which a first insulating film 66a made of a silicon oxide film, a charge trapping film 66b made of a silicon nitride film, and a second insulating film 66c made of a silicon oxide film are sequentially stacked. Yes. A gate electrode 61 is formed on the gate insulating film 66. The recess formed in the p-type silicon semiconductor substrate 65 becomes a channel region of the nonvolatile semiconductor memory 60.

  In such a nonvolatile semiconductor memory 60, charge trapping regions are formed on the side walls of the convex portions 64a and 64b in the charge trapping film 66b of the gate insulating film 66 by applying a predetermined voltage. FIG. 13 shows two charge trapping regions, a left bit region 67a on the convex portion 64a side and a right bit region 67b on the convex portion 64b side, as charge trapping regions of the nonvolatile semiconductor memory 60. The nonvolatile semiconductor memory 60 is capable of writing / reading information of 2 bits in total with 1 bit for each of the left bit area 67a and the right bit area 67b.

  14A and 14B are diagrams for explaining the operation of the nonvolatile semiconductor memory according to the sixth embodiment. FIG. 14A shows a write operation, FIG. 14B shows a read operation, and FIG. 14C shows an erase operation. 14A and 14B show a state in which electrons are captured in the write bit region 67b.

  First, when writing information in the write bit region 67b, the voltage of the impurity diffusion layer 62a serving as the source is set to 0V, and a positive voltage is applied to the impurity diffusion layer 62b serving as the drain, thereby generating a potential difference between the source / drain. Let Then, a positive high voltage is applied to the gate electrode 61. As a result, as shown in FIG. 14A, an inversion layer 68a is formed between the impurity diffusion layers 62a and 62b. Then, channel hot electrons generated in the vicinity of the impurity diffusion layer 62b jump over the first insulating film 66a and are captured in the write bit region 67b.

  When reading information from the write bit region 67b, a voltage in the direction opposite to that in writing is applied between the source and drain. Thereby, the inversion layer 68b is formed between the impurity diffusion layers 62a and 62b.

  Here, as shown in FIG. 14B, when electrons are trapped in the write bit region 67b, the inversion layer 68b is not formed in the vicinity of the write bit region 67b, and no current flows between the source and drain. Does not flow. On the other hand, when electrons are not captured in the write bit region 67b, an inversion layer 68b is also formed near the write bit region 67b (not shown), and a current flows between the source / drain.

Information can be written / read to / from the left bit area 67a by applying a voltage in the opposite direction to that in the right bit area 67b.
When erasing the written information, a negative high voltage is applied to the gate electrode 61 and a positive high voltage is applied to the p-type silicon semiconductor substrate 65. As a result, as shown in FIG. 14C, the electrons captured in the write bit region 67 b are extracted into the p-type silicon semiconductor substrate 65. At this time, the source / drain is open or 0V. The same applies when erasing the information in the left bit area 67a.

  Furthermore, as another method for erasing information, there is a method in which a negative high voltage is applied to the gate electrode 61 and a positive voltage is applied to the impurity diffusion layer 62b. At this time, the impurity diffusion layer 62a is open or 0V. When erasing information in the left bit region 67a by this method, similarly, a negative high voltage is applied to the gate electrode 61, and a positive voltage is applied to the impurity diffusion layer 62a.

  When erasing the left bit region 67a and the right bit region 67b simultaneously, a negative high voltage is applied to the gate electrode 61 and a positive voltage is applied to both the impurity diffusion layers 62a and 62b.

  15 and 16 are explanatory views of a method for manufacturing the nonvolatile semiconductor memory according to the sixth embodiment, in which FIG. 15A is an impurity diffusion layer forming step, FIG. 15B is a convex portion forming step, FIG. 15C is a schematic cross-sectional view in each step of the ion implantation step, FIG. 16A is a gate insulating film formation step, and FIG. 16B is a polycide layer formation step.

First, a predetermined well is formed on the p-type silicon semiconductor substrate 65, and further element isolation in the peripheral circuit region is performed (not shown).
Next, as shown in FIG. 15A, arsenic is implanted into the entire surface of the p-type silicon semiconductor substrate 65 by a known ion implantation method. This ion implantation is performed under conditions of an acceleration energy of about 50 keV and a dose of about 1 × 10 ¹⁵ ions / cm ² to 5 × 10 ¹⁵ ions / cm ² . As a result, the impurity diffusion layer 62 for forming the source / drain and bit line of the memory cell is formed.

  Next, as shown in FIG. 15B, a photoresist 69 is formed on the p-type silicon semiconductor substrate 65 by known photolithography. Subsequently, a groove 63 is formed by selectively removing a part of the p-type silicon semiconductor substrate 65 by an etching method using the photoresist 69 as a mask. Thereby, the convex portions 64 a and 64 b and the impurity diffusion layers 62 a and 62 b are formed in the p-type silicon semiconductor substrate 65.

  Here, the groove 63 has, for example, a width of about 0.3 μm and a depth of about 0.15 μm. The width and depth are merely examples, and can be arbitrarily set according to the use of the nonvolatile semiconductor memory to be formed.

Next, as shown in FIG. 15C, boron ions are implanted in a state where the p-type silicon semiconductor substrate 65 is inclined by a known ion implantation method using the photoresist 69 as a mask. This ion implantation is performed under conditions of an acceleration energy of about 30 keV to 90 keV and a dose amount of about 5 × 10 ¹¹ ions / cm ² to 5 × 10 ¹² ions / cm ² .

  Next, as shown in FIG. 16A, the photoresist 69 is removed, and a silicon oxide film is formed to a thickness of about 10 nm on the exposed p-type silicon semiconductor substrate 65 by a known thermal oxidation method. A first insulating film 66a is formed.

Next, a silicon nitride film is formed to a thickness of about 10 nm on the first insulating film 66a by a known CVD method to form a charge trapping film 66b.
Thereafter, in accordance with a known thermal oxidation method, a heat treatment is performed in an oxygen atmosphere at a temperature of about 900 ° C. to 950 ° C. for a time of about 30 minutes to 60 minutes, and the upper portion of the charge trapping film 66b is oxidized by a thickness of about 10 nm. A second insulating film 66c made of an oxide film is formed. As a result, a gate insulating film 66 having a three-layer structure including the first insulating film 66a, the charge trapping film 66b, and the second insulating film 66c is formed.

Next, as shown in FIG. 16B, a polycide layer 61a is formed on the entire surface by a known CVD method. The polycide layer 61a is formed by forming a polycrystalline silicon film containing about 2 × 10 ²⁰ atoms / cm ³ to about 6 × 10 ²⁰ atoms / cm ^{3 of} phosphorus and a thickness of about 300 nm and a tungsten silicide film of about 200 nm. Do it.

  Next, the polycide layer 61a is processed by a known photolithography method and etching method to form the gate electrode 61 shown in FIG. Thereafter, an impurity activation heat treatment is performed by a known thermal diffusion method to diffuse and activate the impurity diffusion layers 62a and 62b.

Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.
In the above description, the boron ion ion implantation shown in FIG. 15C is performed for adjusting the impurity concentration in the convex portions 64a and 64b. Therefore, this process can be performed as needed, and the order is not limited to this. For example, in the step shown in FIG. 16A, before forming the gate insulating film 66, boron ions can be implanted with the p-type silicon semiconductor substrate 65 tilted.

  As described above, the channel region of the nonvolatile semiconductor memory 60 is concave, and the charge trapping region is formed in the gate insulating film 16 on the side walls of the convex portions 64a and 64b. As a result, an effective channel length can be ensured even for element miniaturization, and a highly reliable nonvolatile semiconductor memory that can be easily miniaturized can be obtained.

Next, as modifications of the sixth embodiment, seventh to eleventh embodiments will be described with reference to the drawings.
First, a seventh embodiment will be described.

  FIGS. 17A and 17B are explanatory views of a method of manufacturing the nonvolatile semiconductor memory according to the seventh embodiment, where FIG. 17A is an impurity diffusion layer and upper surface insulating film forming step, FIG. ) Is a schematic cross-sectional view in each step of the gate insulating film forming step and (d) is a polycide layer forming step. In FIG. 17, the same components as those shown in FIGS. 15 and 16 are denoted by the same reference numerals.

First, a predetermined well is formed on the p-type silicon semiconductor substrate 65, and further, element isolation in the peripheral circuit region is performed (both not shown).
Next, as shown in FIG. 17A, arsenic is implanted into the entire surface of the p-type silicon semiconductor substrate 65 by a known ion implantation method to form an impurity diffusion layer 62. As ion implantation conditions at this time, the acceleration energy is about 50 keV and the dose is in the range of about 1 × 10 ¹⁵ ions / cm ² to about 5 × 10 ¹⁵ ions / cm ² .

Next, a silicon oxide film is formed to a thickness of about 15 nm on the p-type silicon semiconductor substrate 65 by a known thermal oxidation method, and an upper surface insulating film 71 is formed as a third insulating film.
Next, as shown in FIG. 17B, a photoresist 69 is formed on the p-type silicon semiconductor substrate 65 by known photolithography. Subsequently, the upper surface insulating film 71 and a part of the p-type silicon semiconductor substrate 65 are selectively removed by an etching method using the photoresist 69 as a mask to form a groove 63. Thereby, the protrusions 64a and 64b, the upper surface insulating films 71a and 71b, and the impurity diffusion layers 62a and 62b are formed on the p-type silicon semiconductor substrate 65.

  Next, as shown in FIG. 17C, the photoresist 69 is removed, and a silicon oxide film is formed to a thickness of about 10 nm on the exposed p-type silicon semiconductor substrate 65 by a known thermal oxidation method. A first insulating film 66a is formed.

Next, a silicon nitride film is formed to a thickness of about 10 nm on the first insulating film 66a by a known CVD method to form a charge trapping film 66b.
Thereafter, in accordance with a known thermal oxidation method, a heat treatment is performed in an oxygen atmosphere at a temperature of about 900 ° C. to 950 ° C. for a time of about 30 minutes to 60 minutes to oxidize the upper portion of the silicon nitride film by about 10 nm. An insulating film 66c is formed.

  Thus, the upper surfaces of the convex portions 64a and 64b have a three-layer structure in which the charge trapping film 66b and the second insulating film 66c are stacked on the upper surface insulating films 71a and 71b. On the other hand, as for the portions other than the upper surface portions of the convex portions 64 and 64b (the side walls of the convex portion 14 and the upper surface portions of the impurity diffusion layers 12a and 12b), as in the sixth embodiment, the first insulating film 66a and the charge trapping film 66b. And it becomes a three-layer structure of the second insulating film 66c.

  In the subsequent steps, as in the sixth embodiment, as shown in FIG. 17D, after the polycide layer 61a is formed and processed, the impurity diffusion layers 62a and 62b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed in this way, the upper surface insulating films 71a and 71b can be formed thicker than the film thickness of the first insulating film 66a in the channel region. Therefore, the parasitic capacitance between the gate electrode and the source / drain is reduced, and a high-speed and stable nonvolatile semiconductor memory can be obtained.

  Next, an eighth embodiment will be described. However, in the eighth embodiment, the processes up to the step shown in FIG. 15B in the sixth embodiment are similarly performed. The subsequent steps will be described below.

  FIG. 18 and FIG. 19 are explanatory diagrams of the method for manufacturing the nonvolatile semiconductor memory according to the eighth embodiment. FIG. 18A is a process for forming a first insulating film and a charge trapping film, and FIG. FIG. 18C shows a first oxide film removal process, FIG. 18D shows a charge trap film removal process, FIG. 19A shows a second oxide film removal process, and FIG. FIG. 19C is a schematic cross-sectional view in each step of the polycide layer forming step. In FIGS. 18 and 19, the same components as those shown in FIGS. 15 and 16 are denoted by the same reference numerals.

  First, after removing the photoresist 69 shown in FIG. 15B, a silicon oxide film is formed on the exposed p-type silicon semiconductor substrate 65 by a known thermal oxidation method as shown in FIG. A first insulating film 66a is formed to a thickness of about 10 nm. Next, a silicon nitride film is formed to a thickness of about 10 nm on the first insulating film 66a by a known CVD method to form a charge trapping film 66b.

Next, as shown in FIG. 18B, an oxide film 81 is formed to a thickness of about 700 nm on the entire surface by a known CVD method.
Next, as shown in FIG. 18C, the oxide film 81 is removed by a known CMP method using the silicon nitride film of the charge trapping film 66b as a stopper until the charge trapping film 66b is exposed.

Next, as shown in FIG. 18D, the exposed charge trapping film 66b is removed by a known etching method using a phosphoric acid solution.
Next, as shown in FIG. 19A, the oxide film 81 inside the trench 63 is removed by a known etching method using a hydrogen fluoride solution.

  Next, as shown in FIG. 19B, a silicon oxide film having a thickness of about 15 nm is formed on the exposed p-type silicon semiconductor substrate 65 by a known thermal oxidation method, and a fourth insulating film is formed on the protrusions 64a and 64b. The upper surface insulating films 82a and 82b are formed as follows. At this time, the remaining upper portion of the charge trapping film 66b is also partially oxidized to form a second insulating film 66c having a thickness of about 5 nm.

  Thereby, upper surface insulating films 82a and 82b are formed on the upper surface portions of the convex portions 64a and 64b, and the portions other than the upper surface portions of the convex portions 64a and 64b are the first insulating film as in the sixth embodiment. 66a, a charge trapping film 66b, and a second insulating film 66c.

  In the subsequent steps, as in the sixth embodiment, as shown in FIG. 19C, after the polycide layer 61a is formed and processed, the impurity diffusion layers 62a and 62b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed in this way, since the upper surface insulating films 82a and 82b are silicon oxide films, the parasitic capacitance between the gate electrode and the source / drain is reduced, and the high-speed and stable nonvolatile semiconductor is provided. Memory can be obtained.

  Next, a ninth embodiment will be described. However, in the ninth embodiment, the steps shown in FIGS. 15A to 15C and FIG. 16A in the sixth embodiment are similarly performed. The subsequent steps will be described below.

  FIGS. 20A and 20B are explanatory diagrams of the method for manufacturing the nonvolatile semiconductor memory according to the ninth embodiment, in which FIG. 20A is a gate insulating film removing step, FIG. 20B is a top surface insulating film and bottom surface insulating film forming step, (C) is a schematic sectional drawing in each process of a polycide layer formation process. In FIG. 20, the same components as those shown in FIGS. 15 and 16 are denoted by the same reference numerals.

  First, as shown in FIG. 20A, the gate insulating film 66 shown in FIG. 16A is entirely etched using a known etching method until the p-type silicon semiconductor substrate 65 is exposed. Thus, the side walls of the convex portions 64a and 64b have a three-layer structure of the first insulating film 66a, the charge trapping film 66b, and the second insulating film 66c.

  Next, as shown in FIG. 20B, a silicon oxide film having a thickness of about 20 nm is formed on the exposed p-type silicon semiconductor substrate 65 using a known thermal oxidation method. As a result, the upper surface insulating films 91a and 91b are formed on the upper surfaces of the convex portions 64a and 64b, and the bottom surface insulating film 92 is formed on the bottom surface of the groove 63 as a fourth insulating film.

  In the subsequent steps, as in the sixth embodiment, as shown in FIG. 20C, after the polycide layer 61a is formed and processed, the impurity diffusion layers 62a and 62b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory thus formed, the charge trapping film 66b is formed only on the side walls of the convex portions 64a and 64b. Therefore, the position control of the charge trapping region can be performed more accurately.

  Further, since the bottom surface insulating film 92 is formed of a silicon oxide film, the parasitic capacitance between the gate electrode and the source / drain is reduced, and a high-speed and stable nonvolatile semiconductor memory can be obtained.

  Next, a tenth embodiment will be described. However, in the tenth embodiment, the processes up to the step shown in FIG. 17C in the seventh embodiment are similarly performed. The subsequent steps will be described below.

  FIGS. 21A and 21B are explanatory diagrams of a method for manufacturing the nonvolatile semiconductor memory according to the tenth embodiment, in which FIG. 21A is a gate insulating film removing step, FIG. 21B is a top surface insulating film and bottom surface insulating film forming step, (C) is a schematic sectional drawing in each process of a polycide layer formation process. In FIG. 21, the same components as those shown in FIG. 17 are denoted by the same reference numerals.

  First, after the gate insulating film formation step of FIG. 17C, as shown in FIG. 21A, the entire surface is etched using a known etching method until the p-type silicon semiconductor substrate 65 is exposed. Thus, the side walls of the convex portions 64a and 64b have a three-layer structure of the first insulating film 66a, the charge trapping film 66b, and the second insulating film 66c. At this time, the upper surface insulating films 71a and 71b formed as the third insulating film remain on the upper surfaces of the convex portions 64a and 64b by about 5 nm.

  Next, as shown in FIG. 21B, a silicon oxide film having a thickness of about 20 nm is formed on the exposed p-type silicon semiconductor substrate 65 by using a known thermal oxidation method. At this time, the upper surface insulating films 71a and 71b are also slightly oxidized. As a result, new upper surface insulating films 101a and 101b are formed as the fourth insulating film on the upper surfaces of the convex portions 64a and 64b. Further, the bottom surface insulating film 102 is formed on the bottom surface of the groove 63 as a fourth insulating film.

  In the subsequent steps, as in the seventh embodiment, as shown in FIG. 21C, after the polycide layer 61a is formed and processed, the impurity diffusion layers 62a and 62b are activated. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed as described above, the gate insulating film, the top surface insulating films 101a and 101b, and the bottom surface insulating film 102 on the side walls of the protrusions 64a and 64b are independently formed. Therefore, the threshold value can be set by forming the upper surface insulating films 1011 and 101b with appropriate thicknesses.

  Further, a bottom surface insulating film 102 made of a silicon oxide film having a lower capacity than that of the three-layer structure is formed on the upper surface portions of the impurity diffusion layers 62a and 62b. Therefore, the parasitic capacitance between the gate electrode and the source / drain is reduced, and a high-speed and stable nonvolatile semiconductor memory can be obtained.

Furthermore, since the charge trapping film 66b can be formed only on the side walls of the convex portions 64a and 64b, the position control of the charge trapping region can be performed more accurately.
Next, an eleventh embodiment will be described. However, in the eleventh embodiment, the processes up to the step shown in FIG. 15A in the sixth embodiment are similarly performed. The subsequent steps will be described below.

  FIGS. 22A and 22B are explanatory views of the method of manufacturing the nonvolatile semiconductor memory according to the eleventh embodiment, in which FIG. 22A is a groove forming step, FIG. 22B is a gate insulating film forming step, and FIG. It is a schematic sectional drawing in each process of. In FIG. 22, the same components as those shown in FIG. 15 are denoted by the same reference numerals.

  First, after the formation of the impurity diffusion layer 62 shown in FIG. 15A, the p-type silicon semiconductor substrate 65 is moved inward by a known photolithography method and etching method as shown in FIG. 22A. Thus, a trapezoidal groove 113 having a narrow width is formed.

For example, the groove 113 may be formed by performing anisotropic dry etching after processing the photoresist into a trapezoidal shape in a photolithography process.
The subsequent steps are the same as in the sixth embodiment. First, as shown in FIG. 22B, the gate insulating film having a three-layer structure including the first insulating film 66a, the charge trapping film 66b, and the second insulating film 66c. 66 is formed. Next, as shown in FIG. 22C, a polycide layer 61a is formed by forming a polycrystalline silicon film and a tungsten silicide film on the entire surface by CVD. Then, after the polycide layer 61a is processed, activation heat treatment is performed to form impurity diffusion layers 62a and 62b. Finally, opening of contact holes (not shown), formation of metal wirings, and the like are performed.

  In the nonvolatile semiconductor memory formed in this way, since the inclination of the sidewall of the groove 113 can be arbitrarily set, the processing margin of the gate electrode formed from the polycide layer 61a is widened, and the yield is high and the reliability is high. A nonvolatile semiconductor memory can be manufactured.

  Further, when the side wall of the groove is made vertical, an etching residue may be generated on the side wall portion in the etching of the polycide layer. However, such a problem can be avoided by inclining the side wall like the groove 113.

  As described above in the seventh to eleventh embodiments, the channel region of the nonvolatile semiconductor memory is made concave, and the charge trapping region is formed in the gate insulating film 16 on the side wall of the convex portion 14. Channel length is ensured. Therefore, it is possible to obtain a highly reliable nonvolatile semiconductor memory in which element miniaturization is easy.

  Further, since the impurity diffusion layers 62a and 62b are formed on the two convex portions 64a and 64b forming the concave portions, the lateral expansion of the implanted impurities in the activation heat treatment is prevented. Thereby, the impurity diffusion layers 62a and 62b can be formed with high accuracy, and the reliability of the nonvolatile semiconductor memory can be improved.

  In the above description, the silicon nitride film is formed as the charge trapping films 16b and 66b. However, this may be made of other materials capable of capturing electrons. In addition to the above three-layer structure, the gate insulating films 16 and 66 have a structure capable of capturing electrons, such as a two-layer structure of a silicon oxide film and a silicon nitride film, or a one-layer structure of only a silicon nitride film. It can be set as the structure containing.

(Supplementary Note 1) In a nonvolatile semiconductor memory having a charge trapping region for trapping electrons in a gate insulating film formed between a semiconductor substrate and a gate electrode,
A non-volatile semiconductor memory comprising a gate insulating film formed on a semiconductor substrate having a projecting portion and having a charge trapping region formed on a side wall portion of the projecting portion.

(Supplementary note 2) The nonvolatile semiconductor memory according to supplementary note 1, wherein the gate insulating film includes a silicon nitride film.
(Additional remark 3) The non-volatile semiconductor memory of Additional remark 1 characterized by having the impurity diffusion layer used as a source or a drain in the bottom face part of the groove | channel which forms the said convex part of the said semiconductor substrate.

(Supplementary note 4) The nonvolatile semiconductor memory according to supplementary note 1, wherein an impurity diffusion layer serving as a source or a drain is provided on the convex portion of the semiconductor substrate.
(Supplementary Note 5) The film thickness of the gate insulating film on the upper surface portion of the convex portion and / or the film thickness of the gate insulating film on the bottom surface portion of the groove forming the convex portion is the thickness of the side wall portion of the convex portion. The nonvolatile semiconductor memory according to appendix 1, wherein the nonvolatile semiconductor memory is formed thicker than the gate insulating film.

  (Supplementary Note 6) The charge trapping density in the gate insulating film on the side wall portion of the convex portion is equal to the charge trapping density of the gate insulating film on the upper surface portion of the convex portion and / or the bottom surface of the groove forming the convex portion. The nonvolatile semiconductor memory according to appendix 1, wherein the charge trapping density of the gate insulating film is higher than that of the gate insulating film.

(Supplementary Note 7) In a method for manufacturing a nonvolatile semiconductor memory having a charge trapping region for trapping electrons in a gate insulating film formed between a semiconductor substrate and a gate electrode,
Forming a groove in the semiconductor substrate of the first conductivity type;
Forming a second conductivity type impurity diffusion layer on the bottom surface of the formed groove;
A method for manufacturing a nonvolatile semiconductor memory, comprising: forming a gate insulating film including a charge trapping film in which a charge trapping region is formed on the semiconductor substrate on which the impurity diffusion layer is formed.

  (Supplementary note 8) The nonvolatile semiconductor memory according to supplementary note 7, wherein when the groove is formed in the semiconductor substrate, the groove is formed after a third insulating film is formed on the semiconductor substrate. Production method.

(Supplementary Note 9) When forming the gate insulating film including the charge trapping film in which the charge trapping region is formed on the semiconductor substrate on which the impurity diffusion layer is formed,
Forming a first insulating film on the semiconductor substrate on which the impurity diffusion layer is formed;
Forming the charge trapping film on the formed first insulating film;
After removing the first insulating film and the charge trapping film formed on the upper surface portion of the convex portion formed by the groove of the semiconductor substrate,
The method for manufacturing a nonvolatile semiconductor memory according to appendix 7, wherein a fourth insulating film is formed on an upper surface portion of the convex portion.

(Supplementary Note 10) After forming the gate insulating film including the charge trapping film in which the charge trapping region is formed on the semiconductor substrate on which the impurity diffusion layer is formed,
Removing the gate insulating film on the bottom surface of the groove and the gate insulating film on the top surface of the convex portion formed by the groove;
8. The method for manufacturing a nonvolatile semiconductor memory according to appendix 7, wherein a fourth insulating film is formed on the semiconductor substrate from which the gate insulating film has been removed.

(Appendix 11) After forming the gate insulating film including the charge trapping film in which the charge trapping region is formed on the semiconductor substrate on which the impurity diffusion layer is formed,
Removing the gate insulating film on the bottom of the trench;
9. The method of manufacturing a nonvolatile semiconductor memory according to appendix 8, wherein a fourth insulating film is formed on the semiconductor substrate from which the gate insulating film has been removed.

(Additional remark 12) In the manufacturing method of the non-volatile semiconductor memory which has an electric charge capture | acquisition area | region which captures an electron in the gate insulating film formed between the semiconductor substrate and the gate electrode,
Forming a second conductivity type impurity diffusion layer on the first conductivity type semiconductor substrate;
Forming a groove in the semiconductor substrate on which the impurity diffusion layer is formed;
A method for manufacturing a nonvolatile semiconductor memory, comprising: forming a gate insulating film including a charge trapping film in which a charge trapping region is formed on the semiconductor substrate in which the trench is formed.

  (Additional remark 13) When forming the said groove | channel on the said semiconductor substrate, after forming a 3rd insulating film on the said semiconductor substrate in which the said impurity diffusion layer was formed, the said groove | channel is formed, It is characterized by the above-mentioned. 12. A method for producing a nonvolatile semiconductor memory according to 12.

(Supplementary Note 14) When forming the gate insulating film including the charge trapping film in which the charge trapping region is formed on the semiconductor substrate in which the trench is formed,
Forming a first insulating film on the semiconductor substrate in which the groove is formed;
Forming the charge trapping film on the formed first insulating film;
After removing the first insulating film and the charge trapping film formed on the upper surface portion of the convex portion formed by the groove,
14. The method for manufacturing a nonvolatile semiconductor memory according to appendix 12, wherein a fourth insulating film is formed on an upper surface portion of the convex portion.

(Supplementary Note 15) After forming the gate insulating film including the charge trapping film in which the charge trapping region is formed on the semiconductor substrate in which the trench is formed,
Removing the gate insulating film on the bottom surface of the groove and the gate insulating film on the top surface of the convex portion formed by the groove;
14. The method for manufacturing a nonvolatile semiconductor memory according to appendix 12, wherein a fourth insulating film is formed on the semiconductor substrate from which the gate insulating film has been removed.

(Supplementary Note 16) After forming the gate insulating film including the charge trapping film in which the charge trapping region is formed on the semiconductor substrate in which the trench is formed,
Removing the gate insulating film on the bottom of the trench;
14. The method of manufacturing a nonvolatile semiconductor memory according to appendix 13, wherein a fourth insulating film is formed on the semiconductor substrate from which the gate insulating film has been removed.

  (Additional remark 17) When forming the said groove | channel in the said semiconductor substrate in which the said impurity diffusion layer was formed, the said groove | channel is formed so that a width | variety may become narrow toward the said semiconductor substrate inside. The manufacturing method of the non-volatile semiconductor memory of description.

1 is a plan view of a nonvolatile semiconductor memory according to a first embodiment. It is AA sectional drawing of FIG. It is BB sectional drawing of FIG. It is a figure which shows the circuit structural example of a non-volatile semiconductor memory. FIG. 4 is an operation explanatory diagram of the nonvolatile semiconductor memory according to the first embodiment, where (a) illustrates a write operation, (b) illustrates a read operation, and (c) illustrates an erase operation. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 1st Embodiment, (a) is a 1st ion implantation process, (b) is a convex part formation process, (c) is 2nd ion implantation. It is a schematic sectional drawing in each process of a process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 1st Embodiment, (a) is an impurity diffusion layer formation process, (b) is a gate insulating film formation process, (c) is a polycide layer formation process. It is a schematic sectional drawing in each process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 2nd Embodiment, (a) is an impurity diffusion layer formation process, (b) is a gate insulating film formation process, (c) is a polycide layer formation process. It is a schematic sectional drawing in each process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 3rd Embodiment, (a) is a 1st insulating film and charge trap film formation process, (b) is an oxide film formation process, (c) is the 1st. FIG. 1D is a schematic cross-sectional view in each step of the charge trapping film removing step. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 3rd Embodiment, (a) is a 2nd oxide film removal process, (b) is a gate insulating film formation process, (c) is polycide layer formation. It is a schematic sectional drawing in each process of a process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 4th Embodiment, (a) is a gate insulating film removal process, (b) is an upper surface part insulating film and bottom surface part insulating film formation process, (c). These are schematic sectional drawing in each process of a polycide layer formation process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 5th Embodiment, (a) is a gate insulating film removal process, (b) is an upper surface part insulating film and bottom surface part insulating film formation process, (c). These are schematic sectional drawing in each process of a polycide layer formation process. It is a figure which shows the structural example of the non-volatile semiconductor memory of 6th Embodiment. FIG. 10 is a diagram illustrating an operation of a nonvolatile semiconductor memory according to a sixth embodiment, where (a) illustrates a write operation, (b) illustrates a read operation, and (c) illustrates an erase operation. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 6th Embodiment, (a) is an impurity diffusion layer formation process, (b) is a convex part formation process, (c) is each process of an ion implantation process. FIG. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 6th Embodiment, (a) is a gate insulating film formation process, (b) is a schematic sectional drawing in each process of a polycide layer formation process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 7th Embodiment, (a) is an impurity diffusion layer and an upper surface part insulating film formation process, (b) is a convex part formation process, (c) is a gate. (D) is a schematic sectional view in each step of the polycide layer forming step. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 8th Embodiment, (a) is a 1st insulating film and charge trap film formation process, (b) is an oxide film formation process, (c) is the 1st. FIG. 1D is a schematic cross-sectional view in each step of the charge trapping film removal step. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 8th Embodiment, (a) is a 2nd oxide film removal process, (b) is a gate insulating film formation process, (c) is polycide layer formation. It is a schematic sectional drawing in each process of a process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 9th Embodiment, (a) is a gate insulating film removal process, (b) is an upper surface part insulating film and bottom surface part insulating film formation process, (c). These are schematic sectional drawing in each process of a polycide layer formation process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 10th Embodiment, (a) is a gate insulating film removal process, (b) is an upper surface part insulating film and bottom surface part insulating film formation process, (c). These are schematic sectional drawing in each process of a polycide layer formation process. It is explanatory drawing of the manufacturing method of the non-volatile semiconductor memory of 11th Embodiment, (a) is a groove | channel formation process, (b) is a gate insulating film formation process, (c) is each process of a polycide layer formation process FIG. It is a figure which shows the structural example of the conventional non-volatile semiconductor memory, (a) is write-in operation | movement, (b) is a schematic sectional drawing in each operation state of read-out operation | movement. FIGS. 2A and 2B are diagrams illustrating a configuration example of a miniaturized nonvolatile semiconductor memory, in which FIG. 1A illustrates a state in which an inversion layer is partially lost, and FIG. Yes.

Explanation of symbols

10, 60 Nonvolatile semiconductor memory 11, 61 Gate electrode 11a, 61a Polycide layer 12a, 12b, 62, 62a, 62b Impurity diffusion layer 13a, 13b, 63, 113 Groove 14, 64a, 64b Protrusion 15, 65 p-type silicon Semiconductor substrate 16, 66 Gate insulating film 16a, 66a First insulating film 16b, 66b Charge trapping film 16c, 66c Second insulating film 17a, 67a Left bit region 17b, 67b Right bit region 18a, 18b, 68a, 68b Inversion layer 19 , 69 photoresist 21, 32, 41, 51, 71, 71a, 71b, 82a, 82b, 91a, 91b, 101a, 101b upper surface insulating film 31, 81 oxide film 42a, 42b, 52a, 52b, 92, 102 bottom surface Insulation film

Claims (3)

In a method for manufacturing a nonvolatile semiconductor memory having a charge trapping region in a gate insulating film formed between a semiconductor substrate and a gate electrode,
Forming a groove in the semiconductor substrate of the first conductivity type;
Forming a second conductivity type impurity diffusion layer on the bottom surface of the formed groove;
A method for manufacturing a nonvolatile semiconductor memory, comprising: forming a gate insulating film including a charge trapping film in which a charge trapping region is formed on the semiconductor substrate on which the impurity diffusion layer is formed.   2. The method of manufacturing a nonvolatile semiconductor memory according to claim 1, wherein when forming the groove in the semiconductor substrate, the groove is formed after forming a third insulating film on the semiconductor substrate. After forming the gate insulating film including the charge trapping film in which the charge trapping region is formed on the semiconductor substrate on which the impurity diffusion layer is formed,
Removing the gate insulating film on the bottom surface of the groove and the gate insulating film on the top surface of the convex portion formed by the groove;
2. The method of manufacturing a nonvolatile semiconductor memory according to claim 1, wherein a fourth insulating film is formed on the semiconductor substrate from which the gate insulating film has been removed.

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