JP2006135216A - Method for packaging semiconductor chip - Google Patents

Method for packaging semiconductor chip Download PDF

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JP2006135216A
JP2006135216A JP2004324754A JP2004324754A JP2006135216A JP 2006135216 A JP2006135216 A JP 2006135216A JP 2004324754 A JP2004324754 A JP 2004324754A JP 2004324754 A JP2004324754 A JP 2004324754A JP 2006135216 A JP2006135216 A JP 2006135216A
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connection
substrate
terminal
semiconductor chip
wiring
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JP4371041B2 (en
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Hirofumi Kurosawa
弘文 黒沢
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a packaging method of a semiconductor chip for preventing short-circuiting caused by the contact of adjacent wires and hence reducing the pitch between terminals when forming wiring for connecting the connection terminal of the semiconductor chip to the substrate-side terminal of a substrate by using a droplet discharge method, and packaging the semiconductor chip onto the substrate. <P>SOLUTION: In the packaging method of the semiconductor chip, the semiconductor chip 2 in which the connection terminal 3 is arranged is packaged onto the substrate 1 on which the substrate-side terminal 4 is arranged, and the connection wiring is formed by the droplet discharge method. The semiconductor chip 2 is packaged onto the substrate 1, and first connection wiring 7, which connects one or a plurality of connection terminals 3 to the corresponding substrate-side terminal 4, is formed. The first wiring 7 is covered for forming a first insulating layer 8, and second connection wiring 9, which connects one of connection terminals 3 in which no first connection wiring 7 is formed or the plurality of connection terminals 3 to the substrate-side terminal 4 corresponding to the connection terminals, is formed. The second connection wiring 9 is formed for forming a second insulating layer 10, and the entire connection wiring is formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体チップの実装方法に関する。   The present invention relates to a semiconductor chip mounting method.

半導体チップを基板上に実装する技術として、ワイヤボンディングを用いて半導体チップと基板とを電気的に配線接続する方法が知られている。
しかしながら、ワイヤーボンディングを用いる場合、実装する半導体チップには加熱及び加圧処理が必要となる。また、半導体素子が形成されている素子領域は圧力に弱いので、ワイヤー接続時に圧力の加わる半導体チップの接続端子を前記素子領域の外側に配置する必要がある。
そこで、半導体チップの接続端子と基板の基板側端子とを接続する配線を形成する時に加圧工程が不要な技術として、導電材料を液滴吐出法で吐出することで配線を形成する技術が知られている（例えば、特許文献１参照）。
特開２０００−２１６３３０号公報 As a technique for mounting a semiconductor chip on a substrate, a method of electrically connecting the semiconductor chip and the substrate by wire bonding is known.
However, when wire bonding is used, the semiconductor chip to be mounted needs to be heated and pressurized. In addition, since the element region where the semiconductor element is formed is vulnerable to pressure, it is necessary to dispose the connection terminal of the semiconductor chip to which pressure is applied during wire connection outside the element region.
Therefore, as a technique that does not require a pressurizing step when forming a wiring for connecting a connection terminal of a semiconductor chip and a substrate side terminal of a substrate, a technique for forming a wiring by discharging a conductive material by a droplet discharge method is known. (For example, refer to Patent Document 1).
JP 2000-216330 A

ところで、近年、電子部品の小型化、高密度実装化に伴って、例えば半導体チップの接続端子及び基板の基板側端子の端子間ピッチを小さくすることで、半導体チップを実装してなる半導体デバイスを小型化することが望まれている。しかしながら、端子間ピッチを小さくした半導体チップを基板上に実装し、前記接続端子と基板側端子とを接続する配線（接続配線）を液滴吐出法で形成した場合、前記端子間ピッチが接続配線の幅に近づくに連れ、隣り合う配線間が接触してショートしてしまうおそれが生じる。
したがって、特に液滴吐出法で配線を形成する場合、端子間ピッチの狭ピッチ化を十分に進められないのが現状である。 By the way, with recent miniaturization and high-density mounting of electronic components, for example, a semiconductor device in which a semiconductor chip is mounted by reducing a pitch between terminals of a connection terminal of a semiconductor chip and a terminal on a substrate side of a substrate. Miniaturization is desired. However, when a semiconductor chip with a small inter-terminal pitch is mounted on a substrate and a wiring (connection wiring) for connecting the connection terminal and the substrate-side terminal is formed by a droplet discharge method, the inter-terminal pitch is the connection wiring. As the width becomes closer, the adjacent wirings may come into contact with each other and short-circuit.
Therefore, the current situation is that the inter-terminal pitch cannot be sufficiently narrowed particularly when the wiring is formed by the droplet discharge method.

本発明は前記事情に鑑みてなされたもので、液滴吐出法を用いて前記半導体チップの接続端子と前記基板の基板側端子とを接続する配線を形成し、基板上に半導体チップを実装する際に、隣り合う配線の接触によるショートを防止し、これによって端子間の狭ピッチ化を可能にした、半導体チップの実装方法を提供することを目的とする。   The present invention has been made in view of the above circumstances. A wiring for connecting the connection terminal of the semiconductor chip and the substrate-side terminal of the substrate is formed using a droplet discharge method, and the semiconductor chip is mounted on the substrate. At the same time, an object is to provide a semiconductor chip mounting method which prevents a short circuit due to contact between adjacent wirings, thereby enabling a narrow pitch between terminals.

上記課題を解決するため、本発明の半導体チップの実装方法は、複数の基板側端子が配列された基板上に、複数の接続端子が配列された半導体チップを、該各接続端子の配列方向が前記各基板側端子の配列方向と同じ方向となるように実装し、液滴吐出法で導電材料を吐出することによって接続配線を形成する半導体チップの実装方法において、前記半導体チップを基板上に実装した後、一あるいは複数の前記接続端子と該接続端子に対応する前記基板側端子とを接続する第１の接続配線を形成する工程と、前記第１の接続配線を覆って第１の絶縁層を形成する工程と、前記第１の接続配線が形成されていない前記接続端子の一あるいは複数の前記接続端子と該接続端子に対応する前記基板側端子とを接続する第２の接続配線を形成する工程と、前記第２の接続配線を覆って第２の絶縁層を形成する工程とを、全ての前記接続端子について対応する基板側端子に接続する接続配線が形成されるまで、繰り返すことを特徴とする。   In order to solve the above problems, a semiconductor chip mounting method according to the present invention includes a semiconductor chip on which a plurality of connection terminals are arranged on a substrate on which a plurality of board-side terminals are arranged. In the mounting method of a semiconductor chip, wherein the semiconductor chip is mounted on the substrate in such a manner that the connection wiring is formed by discharging the conductive material by a droplet discharge method. Then, a step of forming a first connection wiring for connecting one or a plurality of the connection terminals and the substrate-side terminal corresponding to the connection terminal, and a first insulating layer covering the first connection wiring And forming a second connection wiring for connecting one or a plurality of the connection terminals where the first connection wiring is not formed and the substrate side terminal corresponding to the connection terminal Process The step of covering the second connection wiring and forming the second insulating layer is repeated until connection wirings connected to the corresponding substrate side terminals are formed for all the connection terminals. .

本発明の半導体チップの実装方法によれば、第１の接続配線が、例えば一あるいは隣り合わない複数の接続端子とこれに対応する基板側端子とを接続する場合に、接続配線の配線幅がこれら端子における端子間ピッチに近づいた際に、第１の接続配線を形成するための導電材料が濡れ拡がった場合でも第１の接続配線同士が接触することはない。よって、第１の接続配線同士の接触による対応しない接続端子及び基板側端子の端子間でのショートを防止することができる。
また、第２の接続配線を前記第１の接続配線が形成されていない接続端子のうち、例えば一あるいは隣り合わない複数の接続端子とこれに対応する基板側端子とを接続する場合に、前記第１の接続配線と同様に、第２の接続配線同士が接触することはない。よって、第２の接続配線同士の接触による対応しない端子間でのショートを防止することができる。
さらに、前記第２の接続配線を形成する導電材料が第１の接続配線側に多少濡れ拡がった場合に、前記第１の接続配線が第１の絶縁層によって覆われているので、第１の接続配線と第２の接続配線とが導通することはない。よって、隣り合う第１の接続配線及び第２の接続配線からなる接続配線が接触した場合のショートを防止し、対応する接続端子と基板側端子とを確実に接続することができる。このような工程によって、すべての接続配線を形成することができる。
よって、前記接続端子及び基板側端子の端子間ピッチが狭く隣り合う接続配線が接触してしまうような場合でも、本発明を採用すれば接続配線間を接触させることなく半導体チップを基板上に実装することができる。
したがって、実装する半導体チップ及び基板の端子間ピッチの狭ピッチ化を可能とすることができる。 According to the semiconductor chip mounting method of the present invention, when the first connection wiring connects, for example, one or a plurality of connection terminals that are not adjacent to each other and the corresponding substrate side terminal, the wiring width of the connection wiring is reduced. Even when the conductive material for forming the first connection wiring wets and spreads when approaching the inter-terminal pitch in these terminals, the first connection wirings do not contact each other. Therefore, it is possible to prevent a short circuit between the connection terminal and the terminal of the board side terminal that do not correspond due to contact between the first connection wirings.
Further, among the connection terminals in which the first connection wiring is not formed with the second connection wiring, for example, when connecting one or a plurality of connection terminals that are not adjacent to each other and the corresponding substrate side terminal, Similar to the first connection wiring, the second connection wirings do not contact each other. Therefore, it is possible to prevent a short circuit between terminals that do not correspond due to contact between the second connection wirings.
Further, when the conductive material forming the second connection wiring spreads slightly to the first connection wiring side, the first connection wiring is covered with the first insulating layer. The connection wiring and the second connection wiring do not conduct. Therefore, it is possible to prevent a short circuit when a connection wiring composed of the adjacent first connection wiring and the second connection wiring comes into contact, and to reliably connect the corresponding connection terminal and the board side terminal. Through such a process, all connection wirings can be formed.
Therefore, even if the connection pitch between the connection terminals and the board-side terminal is narrow and adjacent connection wirings come into contact, if the present invention is adopted, the semiconductor chip can be mounted on the substrate without contacting the connection wirings. can do.
Therefore, it is possible to reduce the pitch between the terminals of the semiconductor chip to be mounted and the substrate.

また、前記半導体チップの実装方法においては、前記半導体チップの接続端子が千鳥状に複数列配列されてなるとともに、前記基板の基板側端子が前記接続端子の配列と対応した千鳥状に複数列配列されてなり、前記半導体チップを基板上に実装する際に、前記接続端子が前記基板の基板側端子に対して線対称となるように該半導体チップを前記基板上に配し、前記接続配線の形成を、前記接続端子からなる複数の列と前記基板側端子からなる複数の列との間において、まず、内側の各列間で行い、その後、順次それぞれの外側の列間で行うようにしてもよい。   In the semiconductor chip mounting method, the connection terminals of the semiconductor chips are arranged in a plurality of rows in a staggered manner, and the substrate-side terminals of the substrate are arranged in a plurality of rows in a staggered manner corresponding to the arrangement of the connection terminals. When the semiconductor chip is mounted on the substrate, the semiconductor chip is arranged on the substrate so that the connection terminal is line-symmetric with respect to the substrate-side terminal of the substrate, and the connection wiring The formation is performed between each of the inner rows between the plurality of rows of the connection terminals and the plurality of rows of the board-side terminals, and then sequentially performed between the outer rows. Also good.

このようにすれば、接続端子及び基板側端子を千鳥状に複数列配列することで、半導体チップ及び基板の端子が狭ピッチとなる。また、線対称となるように配された接続端子からなる複数の列と基板側端子からなる複数の列との内側の各列間に、前述したように接続配線を形成することで、例えば隣り合う接続配線をショートさせることなく形成できる。また、外側の列間に接続配線を形成する場合に、内側の列間に形成した接続配線は絶縁層で覆われているので、先に形成された内側の列間の接続配線上に外側の列間の接続配線を積層した場合でも、これら接続配線が直接接触することが無いため導通することもない。よって、順次外側の列間まで接続配線を形成することで、対応する接続端子及び基板側端子の間を接続し、半導体チップを基板上に実装することができる。
したがって、端子の狭ピッチ化を図ることで前記接続配線の形成領域を小さくし、例えば基板上に半導体チップを実装した半導体デバイス自体を小型化することができる。 If it does in this way, the terminal of a semiconductor chip and a board | substrate will become a narrow pitch by arranging a connecting terminal and a board | substrate side terminal in multiple rows | rows in zigzag form. In addition, by forming the connection wiring as described above between the plurality of columns composed of the connection terminals arranged in line symmetry and the plurality of columns composed of the substrate-side terminals, for example, adjacent lines are formed. Matching connection wiring can be formed without short-circuiting. In addition, when the connection wiring is formed between the outer columns, the connection wiring formed between the inner columns is covered with an insulating layer, so that the outer wiring is formed on the connection wiring between the inner columns formed earlier. Even when the connection wirings between the columns are stacked, the connection wirings are not in direct contact with each other, so that they do not conduct. Therefore, by sequentially forming connection wirings to the outer rows, the corresponding connection terminals and substrate side terminals can be connected, and the semiconductor chip can be mounted on the substrate.
Therefore, by narrowing the pitch of the terminals, the area for forming the connection wiring can be reduced, and for example, the semiconductor device itself in which the semiconductor chip is mounted on the substrate can be downsized.

また、前記半導体チップの実装方法においては、前記絶縁層を形成する工程では、液滴吐出法を用いて前記絶縁層を形成することが好ましい。
このようにすれば、接続配線形成する工程と同様に液滴吐出法を用いることで、絶縁層の形成工程を簡略化することができ、半導体チップが実装された半導体デバイスの生産性を向上することができる。 In the semiconductor chip mounting method, it is preferable that the insulating layer is formed by a droplet discharge method in the step of forming the insulating layer.
In this way, the step of forming the insulating layer can be simplified by using the droplet discharge method similarly to the step of forming the connection wiring, and the productivity of the semiconductor device on which the semiconductor chip is mounted is improved. be able to.

また、前記半導体チップの実装方法においては、前記半導体チップは、半導体素子が形成された素子領域上に前記接続端子を配列していることが好ましい。   In the semiconductor chip mounting method, it is preferable that the semiconductor chip has the connection terminals arranged on an element region where a semiconductor element is formed.

このようにすれば、液滴吐出法によって接続配線を形成するので、例えばワイヤーボンディングによって実装する際の接続端子への加圧が不要となり、半導体チップの素子領域に圧力がかかることを防止するようになる。よって、半導体チップの外力によるダメージを防止することができる。   In this way, since the connection wiring is formed by the droplet discharge method, it is unnecessary to apply pressure to the connection terminal when mounting by, for example, wire bonding, so that pressure is not applied to the element region of the semiconductor chip. become. Therefore, damage due to the external force of the semiconductor chip can be prevented.

また、前記半導体チップの実装方法においては、前記半導体チップを前記基板上に実装した後、該半導体チップの側方部であって、前記接続端子と前記基板側端子との間に、該半導体チップの上面と基板の上面とを連続させる傾斜面を形成する工程を有し、前記接続配線及び前記絶縁膜の形成に際しては、その一部を前記傾斜面上に形成することが好ましい。   Further, in the semiconductor chip mounting method, after the semiconductor chip is mounted on the substrate, the semiconductor chip is a side portion of the semiconductor chip and between the connection terminal and the substrate side terminal. It is preferable to form an inclined surface that makes the upper surface of the substrate and the upper surface of the substrate continuous, and when forming the connection wiring and the insulating film, a part thereof is preferably formed on the inclined surface.

このようにすれば、前記傾斜面上に接続配線が形成されることで、前記接続配線が半導体チップと基板と間に生じる段差によって急激に曲げられることによる断線を防止するようになる。   In this way, the connection wiring is formed on the inclined surface, thereby preventing disconnection due to the connection wiring being suddenly bent by a step formed between the semiconductor chip and the substrate.

以下、本発明の半導体チップの実装方法を詳しく説明する。
まず、本発明に用いる基板と、この基板上に実装する半導体チップの構造について説明する。図１（ａ），（ｂ）は、基板上に半導体チップを実装した状態を示した図であり、図１中符号１は基板、２は半導体チップである。
矩形状の半導体チップ２の上面には、その上面の一辺に沿って、複数の接続端子３が配列されている。前記基板１の半導体チップ２を実装する面上には、この半導体チップ２の接続端子３に接続するための複数の基板側端子４が形成されている。
前記半導体チップ２の側方部には、該半導体チップ２を囲んで絶縁性樹脂からなる傾斜部５（傾斜面）が形成されている。この傾斜部５は、半導体チップ２の上面に設けられた前記接続端子３と基板１上に設けられた基板側端子４との段差を無くすことで、後述する接続配線が曲げられることで断線することを防止するようにしている。また、前記基板側端子４は、一部が前記傾斜部５によって覆われている。なお、前記基板側端子４は、前記接続端子３と同様のパッド状の形状でもよく、後述する実施形態においては前記基板側端子４と前記接続端子３とは同一の形状となっている。また、接続端子３が半導体チップ１の上面の、四辺の外周縁部に沿って形成されていてもよい。このとき、前記傾斜部５は、半導体チップ９の四方の側方部に形成するのが好ましい。 Hereinafter, the semiconductor chip mounting method of the present invention will be described in detail.
First, the structure of a substrate used in the present invention and a semiconductor chip mounted on the substrate will be described. 1A and 1B are views showing a state in which a semiconductor chip is mounted on a substrate. In FIG. 1, reference numeral 1 denotes a substrate, and 2 denotes a semiconductor chip.
On the upper surface of the rectangular semiconductor chip 2, a plurality of connection terminals 3 are arranged along one side of the upper surface. On the surface of the substrate 1 on which the semiconductor chip 2 is mounted, a plurality of substrate side terminals 4 for connecting to the connection terminals 3 of the semiconductor chip 2 are formed.
An inclined portion 5 (inclined surface) made of an insulating resin is formed on a side portion of the semiconductor chip 2 so as to surround the semiconductor chip 2. The inclined portion 5 is disconnected by bending a connection wiring, which will be described later, by eliminating a step between the connection terminal 3 provided on the upper surface of the semiconductor chip 2 and the substrate side terminal 4 provided on the substrate 1. I try to prevent that. The substrate side terminal 4 is partially covered with the inclined portion 5. The board-side terminal 4 may have a pad shape similar to that of the connection terminal 3. In the embodiment described later, the board-side terminal 4 and the connection terminal 3 have the same shape. Further, the connection terminals 3 may be formed along the outer peripheral edges of the four sides on the upper surface of the semiconductor chip 1. At this time, the inclined portion 5 is preferably formed on four side portions of the semiconductor chip 9.

次に、基板１上に半導体チップ２を実装する方法について説明する。
まず、図１（ａ）に示したように、前記接続端子３が設けられている半導体チップ２の上面を上にした状態（フェースアップ）で、例えばシリコンなどからなる基板１上に半導体チップ２を実装する。なお、前記基板１は、ガラスエポキシ基板やフレキシブル基板（ポリイミド、ＰＥＴ、ＰＥＮ）等であってもよい。このとき、前記接続端子３の配列方向と前記基板側端子４の配列方向とが同じ方向になるようにしている。また、端子の配列方向と直交する方向に、前記接続端子３とこれら接続端子３にそれぞれ対応する基板側端子４とを整列させるようにして実装する。なお、前記半導体チップ２は、前記基板１上にアライメントした状態で、例えば接着剤（図示せず）を用いて貼着するようにしている。また、半導体チップを貼着した際の前記接続端子３に対する基板側端子４の位置ズレは小さいものとし、角度方向の位置ズレはほとんどないことからここでは考慮しない。
前記半導体チップ２を前記基板１上に実装した後、図１（ｂ）に示したように、半導体チップ２の側方部であって、前記接続端子３と前記基板側端子４との間に、半導体チップ２の上面と基板の上面とを連続させる傾斜部５を形成する。
この傾斜部５の形成方法としては、例えば、絶縁性樹脂を基板１上に塗布した後、リソグラフィ法等を用いた公知のパターニング法で形成することができる。 Next, a method for mounting the semiconductor chip 2 on the substrate 1 will be described.
First, as shown in FIG. 1A, the semiconductor chip 2 is placed on a substrate 1 made of, for example, silicon, with the upper surface of the semiconductor chip 2 provided with the connection terminals 3 facing up (face up). Is implemented. The substrate 1 may be a glass epoxy substrate, a flexible substrate (polyimide, PET, PEN) or the like. At this time, the arrangement direction of the connection terminals 3 and the arrangement direction of the board side terminals 4 are set to be the same direction. Further, the connection terminals 3 and the board-side terminals 4 respectively corresponding to the connection terminals 3 are mounted in a direction orthogonal to the terminal arrangement direction. The semiconductor chip 2 is attached to the substrate 1 in an aligned state using, for example, an adhesive (not shown). Further, the positional deviation of the substrate-side terminal 4 with respect to the connection terminal 3 when the semiconductor chip is attached is assumed to be small, and since there is almost no positional deviation in the angular direction, it is not considered here.
After the semiconductor chip 2 is mounted on the substrate 1, as shown in FIG. 1 (b), it is a side portion of the semiconductor chip 2 between the connection terminal 3 and the substrate side terminal 4. Then, the inclined portion 5 is formed to connect the upper surface of the semiconductor chip 2 and the upper surface of the substrate.
As a method of forming the inclined portion 5, for example, after applying an insulating resin on the substrate 1, it can be formed by a known patterning method using a lithography method or the like.

液滴吐出装置（図示せず）のステージ上に半導体チップ２が実装された基板を保持した後、導電材料を吐出して接続配線を形成する。吐出する導電材料としては、例えば銀微粒子がトルエン中に分散した銀微粒子分散液（真空冶金社製、商品名「パーフェクトシルバー」）にキシレンを添加してこれを希釈した液体材料を用いた。また、前記接続配線の電気抵抗は滴下する導電材料の量（例えば、重ね塗り回数）等によって任意に設定することができる。   After holding the substrate on which the semiconductor chip 2 is mounted on the stage of a droplet discharge device (not shown), a conductive material is discharged to form connection wiring. As the conductive material to be discharged, for example, a liquid material obtained by adding xylene to a silver fine particle dispersion (trade name “Perfect Silver”, manufactured by Vacuum Metallurgical Co., Ltd.) in which silver fine particles are dispersed in toluene and diluting it is used. Further, the electrical resistance of the connection wiring can be arbitrarily set according to the amount of conductive material to be dropped (for example, the number of times of overcoating).

なお、接続配線を形成する前の下地処理を行うようにしてもよい。この下地処理の方法としては、例えばエポキシ系材料を有機溶媒に溶解させたエポキシ系のインクを、液滴吐出装置で均一に塗布するといった方法を採用することができる。この膜厚については厳密に管理する必要はない。
また、前記接続配線は、前記接続端子３及び基板側端子４の端子間ピッチより細くなっている。 In addition, you may make it perform the base treatment before forming connection wiring. As a method for the base treatment, for example, a method in which an epoxy ink in which an epoxy material is dissolved in an organic solvent is uniformly applied by a droplet discharge device can be employed. It is not necessary to strictly manage this film thickness.
The connection wiring is thinner than the pitch between the connection terminals 3 and the board-side terminals 4.

前述したように、半導体チップ２を基板１上に実装した後、一あるいは複数の接続端子３とこれに対応する基板側端子４とを接続する第１の接続配線を形成する。
本発明における第１の実施形態では、図２（ａ）に示すように半導体チップ２の接続端子３の配列のうち、図２（ａ）中Ａ側からＢ側に向かって順に奇数番毎に配置された接続端子３０に対して導電材料を吐出して、後述するように奇数端子配線（第１の接続配線）７を形成する。よって、図２（ａ）中Ａ側を１番目に配置された接続端子３及び基板側端子４とする。このとき、１番目の接続端子３に対して３番目と５番目の接続端子３とが、奇数番毎に配列された接続端子３となる。なお、本実施形態においては、接続端子３及び基板側端子４が五個の場合について説明するが、前記接続端子３及び基板側端子４が五個以上の場合について同様に適応できるのはもちろんである。 As described above, after the semiconductor chip 2 is mounted on the substrate 1, the first connection wiring for connecting one or a plurality of connection terminals 3 and the corresponding substrate-side terminals 4 is formed.
In the first embodiment of the present invention, as shown in FIG. 2A, in the arrangement of the connection terminals 3 of the semiconductor chip 2, every odd number in order from the A side to the B side in FIG. A conductive material is discharged to the arranged connection terminals 30 to form odd terminal wirings (first connection wirings) 7 as will be described later. Therefore, the A side in FIG. 2A is the connection terminal 3 and the board side terminal 4 arranged first. At this time, the third and fifth connection terminals 3 with respect to the first connection terminal 3 become the connection terminals 3 arranged in odd numbers. In the present embodiment, the case where the number of the connection terminals 3 and the board-side terminals 4 is five will be described. Of course, the case where the number of the connection terminals 3 and the board-side terminals 4 is five or more can be similarly applied. is there.

まず、液滴吐出装置のステージを移動することで、図２（ａ）中、２点鎖線で示した液滴吐出ヘッド１１を前記基板側端子４に向けて相対的に移動させ対応するノズルから導電材料を吐出して、前述した奇数番毎に配置された接続端子３とこれに対応する基板側端子４とを接続する奇数端子配線７を形成する。よって、１番目、３番目、５番目に配置された接続端子３及び基板側端子４を接続する奇数端子配線７を同時に形成する。
このとき、前記奇数端子配線７の一部は前述した傾斜部５上に形成されることで、半導体チップ２と基板１との間に生じる段差によって、この奇数端子配線７が急激に曲げられることによる断線を防止できる。このとき、吐出された導電性材料は、金属で形成された接続端子３及び基板側端子４上ではここに保持されやすく、端子の外側にまでは濡れ広がりにくい。
なお、本実施形態においては、前記奇数端子配線７及び後述する偶数端子配線を同時に形成するが、例えば液滴吐出ヘッド１１のノズルピッチが前記接続端子３の端子間ピッチと一致せず、液滴吐出ヘッド１１を相対的に移動することでノズル位置を調整する必要がある場合には、複数回に分けて形成するようにしてもよい。
その後、本実施形態においては、前記奇数端子配線７を２００℃、２時間の条件で焼成させる。 First, by moving the stage of the droplet discharge device, the droplet discharge head 11 indicated by a two-dot chain line in FIG. 2A is moved relatively toward the substrate-side terminal 4 from the corresponding nozzle. The conductive material is discharged to form the odd terminal wiring 7 for connecting the connection terminals 3 arranged for every odd number and the substrate side terminals 4 corresponding thereto. Therefore, the odd-numbered terminal wirings 7 that connect the first, third, and fifth-arranged connection terminals 3 and the board-side terminals 4 are simultaneously formed.
At this time, a part of the odd-numbered terminal wiring 7 is formed on the inclined portion 5 described above, so that the odd-numbered terminal wiring 7 is abruptly bent due to a step generated between the semiconductor chip 2 and the substrate 1. Disconnection due to can be prevented. At this time, the discharged conductive material is easily held here on the connection terminal 3 and the substrate-side terminal 4 made of metal, and hardly spreads to the outside of the terminal.
In the present embodiment, the odd-numbered terminal wiring 7 and the even-numbered terminal wiring described later are formed at the same time. For example, the nozzle pitch of the droplet discharge head 11 does not coincide with the inter-terminal pitch of the connection terminals 3, and the droplets When it is necessary to adjust the nozzle position by relatively moving the ejection head 11, it may be formed in a plurality of times.
Thereafter, in the present embodiment, the odd terminal wiring 7 is fired at 200 ° C. for 2 hours.

このとき、１番目の接続端子３に隣り合う２番目の接続端子３には、接続配線が形成されていない。よって、前記接続端子３の端子間ピッチが狭く、接続配線の幅がこの端子間ピッチに近い場合でも、１番目の接続端子３の奇数端子配線７と３番目の接続端子３の奇数端子配線７とが仮に濡れ拡がった場合においても接触することはない。
また、３番目の接続端子３及び５番目の接続端子３に形成された奇数端子配線７も同様に、接触することはない。
したがって、奇数端子配線７同士が接触することはなく、対応しない接続端子３及び基板側端子４の端子間でのショートを防止できる。 At this time, no connection wiring is formed on the second connection terminal 3 adjacent to the first connection terminal 3. Therefore, even when the pitch between the terminals of the connection terminal 3 is narrow and the width of the connection wiring is close to the pitch between the terminals, the odd-numbered terminal wiring 7 of the first connection terminal 3 and the odd-numbered terminal wiring 7 of the third connection terminal 3. Even if and spreads wet, they do not come into contact.
Similarly, the odd-numbered terminal wirings 7 formed on the third connection terminal 3 and the fifth connection terminal 3 do not contact each other.
Therefore, the odd terminal wirings 7 do not come into contact with each other, and a short circuit between the non-corresponding connection terminal 3 and the board side terminal 4 can be prevented.

次に、図２（ｂ）に示すように、前述した下地処理で用いたエポキシ系のインクを液滴吐出ヘッド１１から吐出することで前記奇数端子配線７を覆うようにして、奇数端子絶縁層（第１の絶縁層）８を形成する。なお、液滴吐出法で前記奇数端子絶縁層を形成することで、奇数端子絶縁層８の形成工程を簡略化でき半導体チップが実装された半導体デバイスの生産性を向上することができる。
その後、奇数端子絶縁層８を焼成するために、本実施形態においては、１８０℃の温度で１５分の焼成を行った。なお、奇数端子配線７を形成する際の焼成条件を用いることで、前記奇数端子配線７と奇数端子絶縁層８との焼成工程を同時に行うようにしてよい。また、前記絶縁層８の絶縁性を確保するためにその厚みを厚くしたい場合には、前記液滴吐出ヘッド１１から複数回インクを吐出することで前記絶縁層８の厚みを増すようにしてもよい。例えば、８回の吐出で絶縁層８を形成する場合は、インクを２回吐出した後、１８０℃で５分程度焼成し、残り６回の吐出を行って最終焼成を行うことで前記絶縁層８を形成できる。 Next, as shown in FIG. 2B, the odd-numbered terminal insulating layer is formed so as to cover the odd-numbered terminal wiring 7 by discharging the epoxy-based ink used in the above-described base treatment from the droplet discharge head 11. (First insulating layer) 8 is formed. By forming the odd terminal insulating layer by a droplet discharge method, the process of forming the odd terminal insulating layer 8 can be simplified, and the productivity of a semiconductor device on which a semiconductor chip is mounted can be improved.
Thereafter, in order to fire the odd terminal insulating layer 8, in this embodiment, baking was performed at a temperature of 180 ° C. for 15 minutes. Note that the firing process of the odd-numbered terminal wiring 7 and the odd-numbered terminal insulating layer 8 may be performed simultaneously by using the firing conditions for forming the odd-numbered terminal wiring 7. Further, when it is desired to increase the thickness of the insulating layer 8 in order to ensure insulation, the thickness of the insulating layer 8 may be increased by discharging ink from the droplet discharge head 11 a plurality of times. Good. For example, when the insulating layer 8 is formed by eight ejections, the ink is ejected twice, and then fired at 180 ° C. for about 5 minutes, and the remaining six ejections are performed and final firing is performed. 8 can be formed.

次に、図２（ｃ）に示すように、前記奇数端子配線７が形成されていない接続端子３のうち、一あるいは複数の接続端子３上の液滴吐出ヘッド１１のノズルから導電材料を吐出して、後述するようにしてこの接続配線３とこれに対応する基板側端子４とを接続する第２の接続配線を形成する。
なお、前述した工程では奇数番毎の接続端子３及び基板側端子４を接続する奇数端子配線７を形成したので、偶数番毎に配置された接続端子３には前記奇数端子配線７が形成されていない。
そこで、図２（ｃ）中Ａ側からＢ側に向かって偶数番に配置された接続端子３に対してのみ導電材料を吐出して、偶数端子配線（第２の接続配線）９を形成する。このとき、前述したように１番目に配置された接続端子３に対しては、２番目、４番目の接続端子３が偶数番目に配置された接続端子３となる。 Next, as shown in FIG. 2C, the conductive material is discharged from the nozzles of the droplet discharge heads 11 on one or a plurality of connection terminals 3 among the connection terminals 3 where the odd terminal wirings 7 are not formed. Then, as will be described later, a second connection wiring for connecting the connection wiring 3 and the corresponding substrate side terminal 4 is formed.
In the above-described process, since the odd-numbered terminal wirings 7 for connecting the odd-numbered connection terminals 3 and the board-side terminals 4 are formed, the odd-numbered terminal wirings 7 are formed in the connection terminals 3 arranged for each even-numbered number. Not.
Therefore, the conductive material is discharged only to the connection terminals 3 arranged in an even number from the A side to the B side in FIG. 2C to form the even terminal wiring (second connection wiring) 9. . At this time, as described above, with respect to the connection terminal 3 arranged first, the second and fourth connection terminals 3 become the connection terminals 3 arranged evenly.

まず始めに、まず、液滴吐出装置のステージを移動することで、図２（ｃ）中、２点鎖線で示した液滴吐出ヘッド１１を前記基板側端子４に向けて相対的に移動し対応するノズルから導電材料を吐出して、前述した偶数番毎に配置された接続端子３とこれに対応する基板側端子４とを接続する偶数端子配線９を形成する。よって、２番目、４番目に配置された接続端子３及び基板側端子４を接続する偶数端子配線９が形成される。
その後、前記奇数端子配線７と同様に、２００℃の温度で２時間、前記偶数端子配線９を焼成する。なお、この偶数端子配線９の一部を前記奇数端子配線７と同様に前記傾斜部５上に形成することで、半導体チップ２と基板１と間に生じる段差によって急激に曲げられることによる断線を防止できる。 First, by moving the stage of the droplet discharge device, the droplet discharge head 11 indicated by a two-dot chain line in FIG. 2C is relatively moved toward the substrate side terminal 4. The conductive material is discharged from the corresponding nozzle to form the even-numbered terminal wiring 9 that connects the connection terminal 3 arranged for each even-numbered number and the substrate-side terminal 4 corresponding thereto. Therefore, the even-numbered terminal wiring 9 that connects the second and fourth-arranged connection terminals 3 and the board-side terminals 4 is formed.
Thereafter, similarly to the odd terminal wiring 7, the even terminal wiring 9 is baked at a temperature of 200 ° C. for 2 hours. In addition, by forming a part of the even terminal wiring 9 on the inclined portion 5 similarly to the odd terminal wiring 7, disconnection due to abrupt bending due to a step generated between the semiconductor chip 2 and the substrate 1 is prevented. Can be prevented.

このとき、２番目の接続端子３の偶数端子配線９に隣り合う１番目又は３番目の接続端子３には前述した奇数端子配線７が形成されている。よって、前記接続端子３の端子間ピッチが狭く、接続配線の幅がこの端子間ピッチに近い場合でも、２番目の接続端子３における偶数端子配線９が１番目及び３番目の接続端子３の奇数端子配線７に接触するおそれがある。
しかしながら、これら奇数端子配線７は奇数端子絶縁層８で覆われているので、２番目の接続端子３の偶数端子配線９がに濡れ拡がって１番目又は３番目の奇数端子配線７と接触しても、前記偶数端子配線９と奇数端子配線７とが導通することはない。また、４番目の接続端子３の接続端子３に形成された偶数端子配線９についても同様である。
したがって、偶数端子配線９及び奇数端子配線７とが接触することによるショートを防止し、対応する前記接続端子３及び基板側端子４を確実に接続できる。
なお、前記奇数端子配線７と同様に、すべての偶数端子配線９を同時に形成することで接続配線の製造工程を簡略化してもよい。 At this time, the odd terminal wiring 7 described above is formed in the first or third connection terminal 3 adjacent to the even terminal wiring 9 of the second connection terminal 3. Therefore, even when the inter-terminal pitch of the connection terminals 3 is narrow and the width of the connection wiring is close to this inter-terminal pitch, the even-numbered terminal wiring 9 in the second connection terminal 3 is an odd number of the first and third connection terminals 3. There is a risk of contact with the terminal wiring 7.
However, since these odd terminal wirings 7 are covered with the odd terminal insulating layer 8, the even terminal wiring 9 of the second connection terminal 3 spreads into contact with the first or third odd terminal wiring 7. However, the even terminal wiring 9 and the odd terminal wiring 7 do not conduct. The same applies to the even-numbered terminal wiring 9 formed on the connection terminal 3 of the fourth connection terminal 3.
Therefore, a short circuit due to contact between the even-numbered terminal wiring 9 and the odd-numbered terminal wiring 7 can be prevented, and the corresponding connection terminal 3 and board-side terminal 4 can be reliably connected.
Note that, similarly to the odd-numbered terminal wiring 7, the manufacturing process of the connection wiring may be simplified by forming all the even-numbered terminal wirings 9 simultaneously.

最後に、図２（ｄ）に示すように、前記奇数端子絶縁層８と同様にエポキシ系のインクを液滴吐出ヘッド１１から吐出することで前記偶数端子配線９を覆うようにして、偶数端子絶縁層（第２の絶縁層）１０を形成する。その後、前記偶数端子絶縁層１０を焼成するために、１８０℃の温度で１５分の焼成工程を設けた。なお、前記偶数端子配線９を形成する際の焼成条件を用いることで、前記偶数端子配線９と前記偶数端子絶縁層１０との焼成工程を同時に行うようにしてよい。また、前述した奇数端子絶縁層８と同様に複数回の吐出によって、絶縁性の高い偶数端子絶縁層１０を形成するようにしてもよい。   Finally, as shown in FIG. 2D, the even-numbered terminals 9 are covered so as to cover the even-numbered terminal wires 9 by ejecting the epoxy-based ink from the droplet ejection head 11 in the same manner as the odd-numbered terminal insulating layers 8. An insulating layer (second insulating layer) 10 is formed. Thereafter, in order to fire the even terminal insulating layer 10, a baking process of 15 minutes at a temperature of 180 ° C. was provided. Note that the firing process of the even-numbered terminal wiring 9 and the even-numbered terminal insulating layer 10 may be performed simultaneously by using the firing conditions for forming the even-numbered terminal wiring 9. Further, the even-numbered terminal insulating layer 10 having high insulating properties may be formed by discharging a plurality of times as in the case of the odd-numbered terminal insulating layer 8 described above.

本発明の半導体チップ２の実装方法によれば、奇数端子配線７が、奇数番毎に配列した隣り合わない複数の接続端子３とこれに対応する基板側端子４とを接続しているので、奇数端子配線７同士が接触することはない。よって、奇数端子配線７同士の接触による対応しない接続端子３及び基板側端子４の端子間でのショートを防止できる。
また、偶数端子配線９が、偶数番毎に配列した隣り合わない複数の接続端子３とこれに対応する基板側端子４とを接続しているので、前記奇数端子配線７と同様に、偶数端子配線９同士が接触することはなく偶数端子配線９同士の接触によるショートを防止できる。
また、偶数端子配線９を形成する際に導電材料が奇数端子配線７側に多少濡れ拡がっても、前記奇数端子配線７を覆う奇数端子絶縁層８により奇数端子配線７と偶数端子配線９とが導通することはない。よって、隣り合う奇数端子配線７及び偶数端子配線９からなる接続配線が接触した場合のショートを防止し、対応する接続端子３と基板側端子４とを接続できる。
したがって、前記接続端子３及び基板側端子４の端子間ピッチが小さく隣り合う接続配線が接触してしまうおそれがある場合に、本発明を採用すれば液滴吐出法によって隣り合う接続端子をショートさせることなく、半導体チップ２を基板１上に実装できる。よって、実装する半導体チップ２及び基板１の端子間ピッチの狭ピッチ化が可能となる。 According to the mounting method of the semiconductor chip 2 of the present invention, the odd terminal wiring 7 connects the plurality of non-adjacent connection terminals 3 arranged for each odd number and the substrate side terminal 4 corresponding thereto, The odd terminal wirings 7 do not contact each other. Therefore, it is possible to prevent a short circuit between the connection terminal 3 and the board-side terminal 4 that do not correspond to each other due to contact between the odd-numbered terminal wires 7.
In addition, since the even terminal wiring 9 connects the plurality of non-adjacent connection terminals 3 arranged for each even number and the board side terminal 4 corresponding thereto, the even terminal similarly to the odd terminal wiring 7. The wires 9 are not in contact with each other, and a short circuit due to the contact between the even-numbered terminal wires 9 can be prevented.
Even when the conductive material spreads slightly toward the odd terminal wiring 7 when the even terminal wiring 9 is formed, the odd terminal wiring 7 and the even terminal wiring 9 are separated by the odd terminal insulating layer 8 covering the odd terminal wiring 7. There is no conduction. Therefore, it is possible to prevent a short circuit when the connection wiring composed of the adjacent odd-numbered terminal wiring 7 and even-numbered terminal wiring 9 comes into contact, and connect the corresponding connection terminal 3 and the board-side terminal 4.
Therefore, when the pitch between the terminals of the connection terminal 3 and the board side terminal 4 is small and there is a possibility that adjacent connection wirings may come into contact, if the present invention is adopted, the adjacent connection terminals are short-circuited by the droplet discharge method. The semiconductor chip 2 can be mounted on the substrate 1 without any problem. Therefore, the pitch between the terminals of the semiconductor chip 2 and the substrate 1 to be mounted can be narrowed.

なお、本実施形態においては、前述した実装方法に限定されることなく種々の変更が可能である。例えば、前記第１の配線７及び第２の配線９を奇数番毎及び偶数番毎に順番に形成したが、一つの接続端子３毎に接続配線を形成したり、隣り合っていない接続端子３であれば接続配線３を形成する順番などは種々に変更してもよい。
また、奇数端子配線７及び偶数端子配線９をすべて形成した後、これら接続配線を覆う奇数端子絶縁層８及び偶数端子絶縁層１０を形成したが、前記接続配線を一つ形成する毎に前記絶縁膜で覆うようにしてもよい。 In the present embodiment, various modifications are possible without being limited to the mounting method described above. For example, although the first wiring 7 and the second wiring 9 are formed in order for every odd number and every even number, a connection wiring is formed for each connection terminal 3 or connection terminals 3 that are not adjacent to each other. If so, the order of forming the connection wiring 3 may be variously changed.
In addition, after all of the odd terminal wiring 7 and the even terminal wiring 9 are formed, the odd terminal insulating layer 8 and the even terminal insulating layer 10 covering these connection wirings are formed. You may make it cover with a film | membrane.

(第２の実施形態)
次に、本発明の第２の実施形態について説明する。なお、本実施形態で用いる半導体チップ２及び基板３との構造は前記第１の実施形態と同様のものとする。
本実施形態では半導体チップ２を基板１上に実装した後、隣り合わない（例えば、２個又は３個毎に配列された）複数の接続端子３とこの接続端子３に対応する基板側端子４とを接続する第１の接続配線を形成する。第１の接続配線を形成する工程としては、前記第１の実施形態同様に液滴吐出法によって、第１の接続配線を形成し、この第１の接続配線を第１の絶縁層で覆うようにする。このとき、第１の接続配線同士が接触することは無く、第１の接続配線間でショートが生じることがない。なお、前記第１の接続配線を複数づつ形成したが、一つだけ形成するようにしてもよい。また、隣り合わない接続端子３とこれに対応する基板側端子４とを接続していれば、前記第１の接続配線を形成する単位（数量、又は位置）は自由である。 (Second Embodiment)
Next, a second embodiment of the present invention will be described. The structures of the semiconductor chip 2 and the substrate 3 used in this embodiment are the same as those in the first embodiment.
In the present embodiment, after the semiconductor chip 2 is mounted on the substrate 1, a plurality of connection terminals 3 that are not adjacent to each other (for example, arranged every two or three) and substrate-side terminals 4 corresponding to the connection terminals 3. First connection wirings are connected to each other. As a step of forming the first connection wiring, the first connection wiring is formed by the droplet discharge method as in the first embodiment, and the first connection wiring is covered with the first insulating layer. To. At this time, the first connection wires do not come into contact with each other, and a short circuit does not occur between the first connection wires. Although a plurality of the first connection wirings are formed, only one may be formed. In addition, if the connection terminals 3 that are not adjacent to each other and the board-side terminals 4 corresponding to the connection terminals 3 are connected, the unit (quantity or position) for forming the first connection wiring is arbitrary.

次に、前記第１の接続配線が形成されていない接続端子３のうち、隣り合わない複数（例えば、２個又は３個毎に配列された）の接続端子３とこの接続端子３に対応する基板側端子４とを接続する第２の接続配線を形成し、第２の接続配線を覆って第２の絶縁層を形成する。なお、前記第２の接続配線は、一つづつ形成してもよい。また、隣り合わない接続端子３とこれに対応する基板側端子４とを接続していれば、前記第２の接続配線を形成する単位（数量、又は位置）は自由である。   Next, among the connection terminals 3 in which the first connection wiring is not formed, a plurality of connection terminals 3 that are not adjacent to each other (for example, arranged every two or three) correspond to the connection terminals 3. A second connection wiring for connecting to the substrate side terminal 4 is formed, and a second insulating layer is formed to cover the second connection wiring. The second connection wirings may be formed one by one. Further, if the connection terminals 3 that are not adjacent to each other and the board-side terminals 4 corresponding to the connection terminals 3 are connected, the unit (quantity or position) for forming the second connection wiring is arbitrary.

本実施形態では、前記第２の絶縁層を形成した後、前記第１及び第２の接続配線が形成されていない接続端子３が残っている場合に、その接続端子３のうち一あるいは複数の接続端子３とこの接続端子３に対応する基板側端子４とを接続する接続配線を形成する工程と、この接続配線を覆う絶縁層を形成する工程とを、すべての接続端子３について対応する基板側端子４に接続する接続配線を形成されるまで繰り返すようにしている。
このとき、第１の接続配線が形成されていない接続端子３から形成した第２の接続配線同士が接触することは無く、接続配線の接触によるショートを防止できる。また、第１の接続配線と第２の接続配線とが第１の絶縁膜及び第２の絶縁膜で覆われているので、接続配線を構成する導電材料が多少濡れ拡がっても、接続配線と第１の接続配線及び第２の接続配線とが導通することがない。
全ての接続端子３について、対応する基板側端子４に接続する接続配線が形成されるまで前述した処理を繰り返すので、すべての接続配線の接触によるショートを防止して半導体チップ２を基板１上に確実に実装することができる。 In the present embodiment, after the second insulating layer is formed, when one or more of the connection terminals 3 remain without the first and second connection wirings being formed, A step of forming a connection wiring for connecting the connection terminal 3 and the substrate-side terminal 4 corresponding to the connection terminal 3 and a step of forming an insulating layer covering the connection wiring are provided for all the connection terminals 3. The connection wiring connected to the side terminal 4 is repeated until it is formed.
At this time, the second connection wires formed from the connection terminals 3 in which the first connection wires are not formed do not contact each other, and a short circuit due to the contact of the connection wires can be prevented. In addition, since the first connection wiring and the second connection wiring are covered with the first insulating film and the second insulating film, even if the conductive material constituting the connection wiring slightly wets and spreads, There is no conduction between the first connection wiring and the second connection wiring.
The above-described process is repeated for all the connection terminals 3 until connection wirings connected to the corresponding substrate side terminals 4 are formed. Therefore, a short circuit due to contact of all the connection wirings is prevented, and the semiconductor chip 2 is placed on the substrate 1. It can be reliably implemented.

（第３の実施形態）
次に、本発明の第３の実施形態について説明する。
図３は、第３の実施形態に用いる半導体チップ２の接続端子３と基板１の基板側端子４との構造を模式的に示した要部拡大図である。なお、本実施形態における基板１及び半導体チップ２の構造は、前記第１の実施形態での接続端子３及び基板側端子４の配置とこれら端子間ピッチが異なる以外は同じであって、接続配線を形成するための導電材料及び接続配線の配線幅などは同じものとする。 (Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 3 is an enlarged view of an essential part schematically showing the structure of the connection terminal 3 of the semiconductor chip 2 and the substrate side terminal 4 of the substrate 1 used in the third embodiment. The structures of the substrate 1 and the semiconductor chip 2 in this embodiment are the same as the arrangement of the connection terminals 3 and the substrate-side terminals 4 in the first embodiment except that the pitch between these terminals is different. The conductive material for forming the wiring and the wiring width of the connection wiring are the same.

まず始めに、本実施形態の基板１及び半導体チップ２の構造について説明する。図３に示すように、前記半導体チップ２の接続端子３の配列は半導体チップ２の上面の外周部に沿うように配置されている。さらに、前記接続端子３の配列は千鳥状に複数列配列されたものとなっている。また、前記基板１の基板側端子４は、前記接続端子３の配列と対応した千鳥状に複数列配列されていて、前記接続端子３と基板側端子４とは線対称の関係となるように後述するように実装されている。このとき、向かい合う接続端子３及び基板側端子４において、内側の各列間を第１列とし、外側（図３中矢印方向）の列に向かって第２列とし、以下、順次第３列、第４列…とする。   First, the structures of the substrate 1 and the semiconductor chip 2 of this embodiment will be described. As shown in FIG. 3, the arrangement of the connection terminals 3 of the semiconductor chip 2 is arranged along the outer peripheral portion of the upper surface of the semiconductor chip 2. Further, the connection terminals 3 are arranged in a plurality of rows in a staggered manner. The substrate-side terminals 4 of the substrate 1 are arranged in a plurality of rows in a staggered manner corresponding to the arrangement of the connection terminals 3, and the connection terminals 3 and the substrate-side terminals 4 are in a line-symmetric relationship. It is implemented as described later. At this time, in the connection terminal 3 and the board-side terminal 4 facing each other, the inner row is the first row, the second row is directed to the outer row (in the direction of the arrow in FIG. 3), and the third row, The fourth column is assumed.

本発明における千鳥状の配置とは、図３に示した第１列目の接続端子３ａと第２列目の接続端子３ｂとの端子間ピッチ（端子の中心間距離）Ｐがこの接続端子３ａ，３ｂの幅ｗよりも大きくなるように配置されている。よって、前記接続端子３を千鳥状に配置しない場合に比べて端子間ピッチＰを狭くすることができる。また、基板側端子４は前述したように前記接続端子３に対応して、線対称となるように配置されているので、同様に第１列目の基板側端子４と第２列目の基板側端子４との端子間ピッチＰは狭くなっている。なお、前述したように接続配線の配線幅も同様にｗとする。
したがって、本実施形態においては、このように接続端子３及び基板側端子４を千鳥状に配置することで、接続配線の配線幅ｗよりこれら端子間ピッチＰを狭くすることができ、半導体チップ２の狭ピッチ化が図られている。 The staggered arrangement in the present invention means that the inter-terminal pitch (distance between the centers of terminals) P between the connection terminals 3a in the first row and the connection terminals 3b in the second row shown in FIG. 3 is the connection terminals 3a. , 3b is arranged to be larger than the width w. Therefore, the inter-terminal pitch P can be made narrower than in the case where the connection terminals 3 are not arranged in a staggered manner. Further, since the board side terminals 4 are arranged so as to be line-symmetrically corresponding to the connection terminals 3 as described above, the board side terminals 4 in the first row and the board in the second row are similarly arranged. The inter-terminal pitch P with the side terminal 4 is narrow. As described above, the wiring width of the connection wiring is also set to w.
Therefore, in this embodiment, by arranging the connection terminals 3 and the substrate side terminals 4 in a staggered manner in this way, the pitch P between these terminals can be made narrower than the wiring width w of the connection wiring, and the semiconductor chip 2 Narrow pitch is achieved.

また、前記半導体チップ２の側方部には、該半導体チップ２を囲んで絶縁性樹脂からなる傾斜部５（傾斜面）が形成されている。この傾斜部５は、半導体チップ２の上面に設けられた前記接続端子３と基板１上に設けられた基板側端子４との段差を無くすことで、後述する接続配線の曲げによる断線を防止するようにしている。なお、接続端子３が半導体チップ１の上面の、四辺の外周縁部に沿って形成されていてもよい。このとき、前記傾斜部５は、半導体チップ９の四方の側方部に形成するのが好ましい。   Further, an inclined portion 5 (inclined surface) made of an insulating resin is formed on a side portion of the semiconductor chip 2 so as to surround the semiconductor chip 2. The inclined portion 5 prevents disconnection due to bending of the connection wiring, which will be described later, by eliminating a step between the connection terminal 3 provided on the upper surface of the semiconductor chip 2 and the substrate-side terminal 4 provided on the substrate 1. I am doing so. Note that the connection terminals 3 may be formed along the outer periphery of the four sides on the upper surface of the semiconductor chip 1. At this time, the inclined portion 5 is preferably formed on four side portions of the semiconductor chip 9.

次に、基板１上に半導体チップ２を実装する方法について説明する。
まず、図３に示したように、前記接続端子３が設けられている半導体チップ２の上面を上にした状態（フェースアップ、具体的には図１に示した状態）でシリコンなどからなる基板１上に半導体チップ２を実装する。このとき、前述した千鳥状に配列された接続端子３が前記基板１の千鳥状に配置された基板側端子４に対して線対称となるようにして、前記半導体チップ１を前記基板１上に実装する。なお、前記半導体チップ２は、前記基板１上にアライメントした状態で、例えば接着剤（図示せず）を用いて貼着するようにしている。なお、半導体チップを貼着した際の前記接続端子３に対する基板側端子４の位置ズレは小さいものとし、角度方向の位置ズレはほとんどないことからここでは考慮しない。
前記半導体チップ２を前記基板１上に実装した後、前記第１の実施形態と同様に、半導体チップ２の上面と基板の上面とを連続させる傾斜部５を形成する。 Next, a method for mounting the semiconductor chip 2 on the substrate 1 will be described.
First, as shown in FIG. 3, a substrate made of silicon or the like with the upper surface of the semiconductor chip 2 provided with the connection terminals 3 facing upward (face-up, specifically, the state shown in FIG. 1). A semiconductor chip 2 is mounted on 1. At this time, the semiconductor chips 1 are placed on the substrate 1 such that the connection terminals 3 arranged in a staggered manner are axisymmetric with respect to the substrate-side terminals 4 arranged in a staggered manner on the substrate 1. Implement. The semiconductor chip 2 is attached to the substrate 1 in an aligned state using, for example, an adhesive (not shown). In addition, since the positional deviation of the board | substrate side terminal 4 with respect to the said connection terminal 3 at the time of sticking a semiconductor chip shall be small, and there is almost no positional deviation of an angle direction, it does not consider here.
After mounting the semiconductor chip 2 on the substrate 1, as in the first embodiment, the inclined portion 5 that makes the upper surface of the semiconductor chip 2 and the upper surface of the substrate continuous is formed.

液滴吐出装置（図示せず）のステージ上に半導体チップ２が貼着された基板１を保持した後、液滴吐出ヘッド１１から導電材料を吐出して前記接続端子３と基板側端子４とを接続する接続配線を形成する。なお、接続端子３及び基板側端子４を本実施形態のように千鳥状に配置した場合に、形成した接続配線が前記接続端子３及び基板側端子４を完全に覆っていないと隣り合う接続配線が露出した端子部に接触することでショートする場合がある。このようなショートを解消する手段として、前記接続端子３及び基板側端子４上に形成する接続配線がこれら端子を覆うようにすることが好ましい。このようにすれば、前述したように接続配線を絶縁層によって覆うので、前記端子部が露出することは無く隣り合う接続配線がこれら端子部に接触することによるショートを防止することができる。
また、接続配線が前記接続端子３及び基板側端子４を完全に覆わないでこれら端子の一部が露出している場合に、前記接続端子３及び基板側端子４を覆うように絶縁層を形成することが好ましい。このようにすれば、前述したように接続配線を絶縁層によって覆うので、前記端子部が露出することは無く隣り合う接続配線がこの端子部に接触することによるショートを防止することができる。なお、本実施形態においては、特に前述したように接続配線で端子を覆うようにして接続配線及び絶縁層を形成するようにしている。 After holding the substrate 1 on which the semiconductor chip 2 is adhered on the stage of a droplet discharge device (not shown), the conductive material is discharged from the droplet discharge head 11 to connect the connection terminal 3 and the substrate side terminal 4. A connection wiring for connecting the two is formed. When the connection terminals 3 and the board-side terminals 4 are arranged in a staggered manner as in the present embodiment, the adjacent connection wirings do not cover the connection terminals 3 and the board-side terminals 4 completely. May be shorted by contacting the exposed terminal. As means for eliminating such a short circuit, it is preferable that the connection wiring formed on the connection terminal 3 and the board-side terminal 4 cover these terminals. In this case, since the connection wiring is covered with the insulating layer as described above, the terminal portion is not exposed and a short circuit due to the adjacent connection wiring coming into contact with these terminal portions can be prevented.
In addition, when the connection wiring does not completely cover the connection terminal 3 and the substrate side terminal 4 and a part of these terminals is exposed, an insulating layer is formed so as to cover the connection terminal 3 and the substrate side terminal 4 It is preferable to do. In this case, since the connection wiring is covered with the insulating layer as described above, the terminal portion is not exposed and a short circuit due to the adjacent connection wiring coming into contact with the terminal portion can be prevented. In the present embodiment, as described above, the connection wiring and the insulating layer are formed so as to cover the terminal with the connection wiring.

接続配線の形成する際に、前記接続端子３からなる複数の列と前記基板側端子４からなる複数の列との間において、まず、内側の各列間（第１列）から前記接続端子を形成する。
本実施形態では、具体的に図４（ａ）に示したように、第１列間における接続端子３ａと基板側端子４ａとを接続する接続配線を形成する。このとき、接続配線を形成する方法としては、前述した第１の実施形態又は第２の実施形態と同様の方法を用いた。例えば、前記第１の実施形態と同様にした場合、第１列における接続端子３ａの配列のうち、奇数番毎に配列された隣り合わない複数の接続端子３ａとこれに対応する基板側端子４ａとを接続する接続配線を形成し、この接続配線を絶縁層で覆う。そして、偶数番毎に配列された接続端子３ａとこれに対応する基板側端子４ａとを接続する接続配線を形成し、この接続配線を覆うようにして絶縁層を形成する。
また、前記第２の実施形態のようにして全ての接続端子３に対応する基板側端子４に接続する接続配線を形成するようにしてもよい。
このようにして、前記第１列間における接続端子３ａと基板側端子４ａとを接続する接続配線によるショートを防止し、すべての接続配線を形成することができる。 When forming the connection wiring, between the plurality of columns composed of the connection terminals 3 and the plurality of columns composed of the substrate-side terminals 4, first, the connection terminals are connected from the inner columns (first column). Form.
In the present embodiment, as specifically shown in FIG. 4A, a connection wiring for connecting the connection terminal 3a and the substrate side terminal 4a between the first columns is formed. At this time, as a method for forming the connection wiring, the same method as that in the first embodiment or the second embodiment described above was used. For example, in the same manner as in the first embodiment, among the arrangement of the connection terminals 3a in the first row, a plurality of non-adjacent connection terminals 3a arranged for each odd number and the board-side terminal 4a corresponding thereto. Is formed, and the connection wiring is covered with an insulating layer. Then, a connection wiring for connecting the connection terminals 3a arranged for each even number and the corresponding substrate side terminal 4a is formed, and an insulating layer is formed so as to cover the connection wiring.
Further, as in the second embodiment, connection wirings connected to the board side terminals 4 corresponding to all the connection terminals 3 may be formed.
In this way, it is possible to prevent a short circuit due to the connection wiring connecting the connection terminals 3a and the substrate side terminals 4a between the first columns, and to form all the connection wirings.

第１列間のすべての接続端子３及び基板側端子４を接続する第１列間接続配線（接続配線）１２を形成した後、図４（ｂ）に示すように、第１列の外側となる第２列間の接続端子３ｂ及び基板側端子４ｂを接続する第２列間接続配線（接続配線）１３を前述した第１列間接続配線１２と同様にして形成する。このとき、第１列間を接続している第１列間接続配線１２が絶縁層で覆われているので、第２列間の接続端子３ｂと基板側端子４ｂとを接続する第２列接続配線１３を形成する際に、先に形成された第１列間接続配線１２上に第２列間接続配線１３を積層した場合でも、これら２つの接続配線が直接接触することは無く導通することがない。また、前記第１列間接続配線１２を覆っている絶縁層を第２列間接続配線１３を形成する際の隔壁として利用することができる。よって、この隔壁間に導電材料を吐出することで、前記第２列間接続配線１３を形成できるので、導電材料の吐出精度を適度に抑えることができる。   After forming the first inter-row connection wiring (connection wiring) 12 for connecting all the connection terminals 3 between the first rows and the board side terminals 4, as shown in FIG. The second inter-column connection wiring (connection wiring) 13 for connecting the connection terminals 3b between the second columns and the substrate side terminals 4b is formed in the same manner as the first inter-column connection wiring 12 described above. At this time, since the first inter-column connection wiring 12 connecting the first columns is covered with the insulating layer, the second column connection for connecting the connection terminals 3b between the second columns and the substrate side terminals 4b. When the wiring 13 is formed, even when the second inter-column connection wiring 13 is laminated on the first inter-column connection wiring 12 formed in advance, the two connection wirings are not in direct contact but are conducted. There is no. Further, the insulating layer covering the first inter-column connection wiring 12 can be used as a partition wall when the second inter-column connection wiring 13 is formed. Therefore, since the second inter-column connection wiring 13 can be formed by discharging a conductive material between the partition walls, the discharge accuracy of the conductive material can be moderately suppressed.

そして、図４（ｃ）に示すように、第２列間の端子間を接続する前記第２列間接続配線１３を絶縁層で覆った後、順次外側の列間に接続配線を形成していき、すべての接続端子３とこれに対応する基板側端子４とを接続する接続配線を形成する。このようにして、順次外側の列間まで接続配線を形成することで、対応する接続端子３及び基板側端子４の間をショートすることなく接続させることができる。また、本発明を採用すれば、接続配線を絶縁層を介して多層化して形成することができ、狭ピッチ化を図った半導体チップ２を基板１上に実装することができる。
なお、本実施形態では、各列間のすべての接続配線を形成した後、絶縁層を形成しているが、各接続配線を形成した後に絶縁層で覆うようにしてもよい。また、前記接続端子３が後述する第４の実施形態のように、半導体チップ２の半導体素子が形成された素子領域上に配置されていてもよい。このようにすれば、半導体チップ２の接続配線形成領域を小さくすることができ、この半導体チップ２を実装した半導体デバイスを小型化することができる。 Then, as shown in FIG. 4C, after covering the second inter-column connecting wiring 13 connecting the terminals between the second columns with an insulating layer, connecting wirings are sequentially formed between the outer columns. Then, connection wirings for connecting all the connection terminals 3 and the corresponding board side terminals 4 are formed. In this manner, the connection wiring is formed sequentially between the outer columns, so that the corresponding connection terminals 3 and the board-side terminals 4 can be connected without short-circuiting. If the present invention is adopted, the connection wiring can be formed in multiple layers via an insulating layer, and the semiconductor chip 2 with a narrow pitch can be mounted on the substrate 1.
In this embodiment, the insulating layer is formed after all the connection wirings between the columns are formed. However, the insulating layer may be covered after the connection wirings are formed. Further, the connection terminal 3 may be arranged on an element region in which a semiconductor element of the semiconductor chip 2 is formed as in a fourth embodiment described later. In this way, the connection wiring formation region of the semiconductor chip 2 can be reduced, and the semiconductor device on which the semiconductor chip 2 is mounted can be reduced in size.

（第４の実施形態）
次に、本発明の第４の実施形態について説明する。
図５は、第４の実装方法を用いる際の半導体チップ２の構造を模式的に示した要部拡大図である。なお、本実施形態における基板１及び半導体チップ２の構造は、後述するように接続端子３の配置する領域が異なる以外は前記第１の実施形態と同じであって、接続配線を形成するための導電材料及び接続配線の配線幅などは同じものとする。
まず始めに、本実施形態の半導体チップ２の構造について説明する。図５に示すように、半導体チップ２は矩形状であって、この半導体チップ２には、トランジスタ等の半導体素子が形成された図５中破線で示した素子領域１６が形成されている。この素子領域１６は、前述したようにトランジスタなどが形成されているため、外力に対して弱く前記半導体チップ２を基板１上に実装する際に、前記素子領域１６に圧力をかけないようにする必要がある。前記接続端子３は、前記素子領域１６上の一辺の外周部に沿って配列されている。なお、前記接続端子３は前記素子領域１６の四辺の外周部に沿って配列されていてもよい。また、接続端子３を前記第２の実施形態のように千鳥状に配列することでの狭ピッチ化を図ることができる。 (Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 5 is an enlarged view of a main part schematically showing the structure of the semiconductor chip 2 when the fourth mounting method is used. The structures of the substrate 1 and the semiconductor chip 2 in the present embodiment are the same as those in the first embodiment except that the area where the connection terminals 3 are arranged is different as will be described later. The conductive material and the wiring width of the connection wiring are the same.
First, the structure of the semiconductor chip 2 of this embodiment will be described. As shown in FIG. 5, the semiconductor chip 2 has a rectangular shape, and an element region 16 indicated by a broken line in FIG. 5 in which a semiconductor element such as a transistor is formed is formed on the semiconductor chip 2. Since the element region 16 is formed with a transistor or the like as described above, the element region 16 is weak against external force so that no pressure is applied to the element region 16 when the semiconductor chip 2 is mounted on the substrate 1. There is a need. The connection terminals 3 are arranged along the outer periphery of one side on the element region 16. The connection terminals 3 may be arranged along the outer periphery of the four sides of the element region 16. Moreover, the pitch can be reduced by arranging the connection terminals 3 in a staggered manner as in the second embodiment.

本実施形態において、半導体チップ２は前記第１の実施形態及び第２の実施形態と同様の方法を用いることですべての接続配線をショートさせることなく半導体チップ２を基板１上に実装することができる。
また、本発明は液滴吐出法によって前記接続配線３と基板側端子４とを接続する接続配線を形成するので、例えばワイヤーボンディングによって半導体チップ２を実装する場合に必要となる接続端子３への加圧が不要となり、半導体チップ２の素子領域１６に圧力がかかることを防止できる。よって、半導体チップ２の外力によるダメージを防止することができ、基板１上に半導体チップ２が実装された半導体デバイスを良好に機能させることができる。 In the present embodiment, the semiconductor chip 2 can be mounted on the substrate 1 without using a short circuit for all the connection wirings by using the same method as in the first and second embodiments. it can.
In addition, since the present invention forms the connection wiring for connecting the connection wiring 3 and the substrate side terminal 4 by the droplet discharge method, the connection to the connection terminal 3 required when the semiconductor chip 2 is mounted by wire bonding, for example. Pressurization is unnecessary, and it is possible to prevent pressure from being applied to the element region 16 of the semiconductor chip 2. Therefore, damage due to the external force of the semiconductor chip 2 can be prevented, and the semiconductor device in which the semiconductor chip 2 is mounted on the substrate 1 can be made to function satisfactorily.

なお、前述した実施形態においては、絶縁層を形成する際に液滴吐出法を用いたが、スピンコート法によって絶縁膜を形成した後、例えばリソグラフィ法などのパターニング法を用いることで絶縁層を形成するようにしてもよい。   In the above-described embodiment, the droplet discharge method is used when forming the insulating layer. However, after forming the insulating film by spin coating, the insulating layer is formed by using a patterning method such as a lithography method. You may make it form.

（ａ）は、第１の実施形態の構造説明図、（ｂ）は（ａ）の側断面図。(A) is structure explanatory drawing of 1st Embodiment, (b) is a sectional side view of (a). （ａ）〜（ｄ）は、第１の実施形態における工程説明図。(A)-(d) is process explanatory drawing in 1st Embodiment. 第３の実施形態に用いる半導体チップの要部拡大図。The principal part enlarged view of the semiconductor chip used for 3rd Embodiment. （ａ）〜（ｃ）は、第３の実施形態における工程説明図。(A)-(c) is process explanatory drawing in 3rd Embodiment. 第４の実施形態における半導体チップの平面図。The top view of the semiconductor chip in a 4th embodiment.

符号の説明Explanation of symbols

１…基板、２…半導体チップ、３…接続端子、４…基板側端子、５…傾斜部（傾斜面）、７…奇数端子配線（第１の接続配線）、８…奇数端子絶縁膜（第１の絶縁膜）、９…偶数端子配線（第２の接続配線）、１０…偶数端子絶縁層（第２の絶縁膜）、１２…第１列間接続配線（接続配線）、１３…第２列間接続配線（接続配線）、１６…素子領域 DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Semiconductor chip, 3 ... Connection terminal, 4 ... Board | substrate side terminal, 5 ... Inclined part (inclined surface), 7 ... Odd terminal wiring (1st connection wiring), 8 ... Odd terminal insulating film (1st) 1... Even terminal wiring (second connecting wiring), 10. Even terminal insulating layer (second insulating film), 12. First inter-column connecting wiring (connecting wiring), 13. Inter-column connection wiring (connection wiring), 16 ... element region

Claims (5)

複数の基板側端子が配列された基板上に、複数の接続端子が配列された半導体チップを、該各接続端子の配列方向が前記各基板側端子の配列方向と同じ方向となるように実装し、液滴吐出法で導電材料を吐出することによって接続配線を形成する半導体チップの実装方法において、
前記半導体チップを基板上に実装した後、一あるいは複数の前記接続端子と該接続端子に対応する前記基板側端子とを接続する第１の接続配線を形成する工程と、
前記第１の接続配線を覆って第１の絶縁層を形成する工程と、
前記第１の接続配線が形成されていない前記接続端子の一あるいは複数の前記接続端子と該接続端子に対応する前記基板側端子とを接続する第２の接続配線を形成する工程と、
前記第２の接続配線を覆って第２の絶縁層を形成する工程とを、全ての前記接続端子について対応する基板側端子に接続する接続配線が形成されるまで、繰り返すことを特徴とする半導体チップの実装方法。 A semiconductor chip on which a plurality of connection terminals are arranged is mounted on a substrate on which a plurality of board side terminals are arranged so that the arrangement direction of the connection terminals is the same as the arrangement direction of the board side terminals. In a semiconductor chip mounting method for forming a connection wiring by discharging a conductive material by a droplet discharge method,
Forming a first connection wiring for connecting one or a plurality of the connection terminals and the substrate-side terminals corresponding to the connection terminals after mounting the semiconductor chip on the substrate;
Forming a first insulating layer covering the first connection wiring;
Forming a second connection wiring for connecting one or a plurality of the connection terminals of the connection terminals in which the first connection wiring is not formed and the substrate-side terminals corresponding to the connection terminals;
A step of covering the second connection wiring and forming the second insulating layer until all the connection terminals are connected to the corresponding substrate side terminals until the connection wiring is formed. Chip mounting method. 前記半導体チップの接続端子が千鳥状に複数列配列されてなるとともに、前記基板の基板側端子が前記接続端子の配列と対応した千鳥状に複数列配列されてなり、
前記半導体チップを基板上に実装する際に、前記接続端子が前記基板の基板側端子に対して線対称となるように該半導体チップを前記基板上に配し、
前記接続配線の形成を、前記接続端子からなる複数の列と前記基板側端子からなる複数の列との間において、まず、内側の各列間で行い、その後、順次それぞれの外側の列間で行うことを特徴とする請求項１に記載の半導体チップの実装方法。 The connection terminals of the semiconductor chips are arranged in a plurality of rows in a zigzag pattern, and the substrate-side terminals of the substrate are arranged in a plurality of rows in a zigzag pattern corresponding to the arrangement of the connection terminals,
When the semiconductor chip is mounted on the substrate, the semiconductor chip is arranged on the substrate so that the connection terminal is line-symmetric with respect to the substrate-side terminal of the substrate,
The connection wiring is formed between each of the inner rows between the plurality of rows of the connection terminals and the plurality of rows of the board-side terminals, and then sequentially between the outer rows. The semiconductor chip mounting method according to claim 1, wherein the semiconductor chip mounting method is performed. 前記絶縁層を形成する工程では、液滴吐出法を用いて前記絶縁層を形成することを特徴とする請求項１又は請求項２に記載の半導体チップの実装方法。   3. The semiconductor chip mounting method according to claim 1, wherein the insulating layer is formed by a droplet discharge method in the step of forming the insulating layer. 前記半導体チップは、半導体素子が形成された素子領域上に前記接続端子を配列していることを特徴とする請求項１〜３のいずれか一項に記載の半導体チップの実装方法。   The semiconductor chip mounting method according to claim 1, wherein the connection terminals are arranged on an element region in which the semiconductor elements are formed. 前記半導体チップを前記基板上に実装した後、該半導体チップの側方部であって、前記接続端子と前記基板側端子との間に、該半導体チップの上面と基板の上面とを連続させる傾斜面を形成する工程を有し、前記接続配線及び前記絶縁膜の形成に際しては、その一部を前記傾斜面上に形成することを特徴とする請求項１〜４のいずれか一項に記載の半導体チップの実装方法。   After the semiconductor chip is mounted on the substrate, the side surface of the semiconductor chip is inclined so that the upper surface of the semiconductor chip and the upper surface of the substrate are continuous between the connection terminal and the substrate-side terminal. 5. The method according to claim 1, further comprising a step of forming a surface, wherein when forming the connection wiring and the insulating film, a part thereof is formed on the inclined surface. Semiconductor chip mounting method.
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JP2010114221A (en) * 2008-11-05 2010-05-20 Seiko Epson Corp Electronic apparatus, and method of manufacturing the same

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