JP2006135069A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a semiconductor device constituted to include a plurality of wiring layers covering the highest wiring layer with a protection film that when a cavity is formed among wires to reduce wiring capacitance, junction interface is formed within the protection film at the upper part of the cavity, and the wiring is corroded with water invaded through the junction interface. <P>SOLUTION: A first moisture-proof protection film is formed of silicon nitride to generate a cavity among a plurality of wires after the highest wire is formed, and then a stress easing layer of silicon oxide is formed. In this case, a junction interface is also formed within the first moisture-proof protection film at the upper part of cavity but a second moisture-proof protection film is formed by suspending growth of the junction interface through exposure of the surface of above junction interface to the atmosphere or through formation of an insulating film with a different kind of method. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device having a plurality of wiring layers and a method of manufacturing the same, and in particular, in the finest uppermost wiring layer, when a cavity is formed between the wirings in order to reduce the capacitance between the wirings, the moisture resistance of the protective film The present invention relates to a semiconductor device having a protective film structure that avoids the problem of deterioration of the semiconductor device and a method for manufacturing the same.

As is well known, since semiconductor devices are strongly affected by the operating environment in use, protection is provided after the top wiring layer is formed in order to suppress the influence from the external environment in order to ensure long-term stable operation. It is essential to provide a film. Moisture and alkali ions are factors that adversely affect the external environment. The former is known to cause disconnection due to corrosion of wiring, and the latter to cause fluctuations in characteristics of semiconductor elements. Further, it is a well-known fact that silicon nitride is effective as a material for protecting a semiconductor device from these influences, and has already been put into practical use.

Each of (a), (b), and (c) shown in FIG. 1 shows an example of the prior art relating to a protective film covering the uppermost wiring layer. Both are shown in cross-sectional views in which the uppermost wiring portion is extracted. In an actual semiconductor device, a lower wiring layer is located below these drawings, and a semiconductor element formed on the surface of the semiconductor substrate is located below the lower wiring layer, but is omitted here.

Referring to FIG. 1A, the uppermost wiring layer 12 is formed on the interlayer insulating film 11, the silicon nitride film 13 is formed as a protective film, and a state in which the space between the wirings is filled with silicon nitride is shown. Yes. This protective film structure was sufficient when the degree of integration of the semiconductor device was small and there was a margin in the wiring width and wiring spacing. However, as the degree of integration increases and the spacing between wires narrows, the capacitance between wires increases due to the relative dielectric constant of silicon nitride being as large as about 8, and the influence on the delay in signal processing speed cannot be ignored. I came.

FIG. 1B shows a structure proposed for avoiding the above problem, and is described in JP-A-5-326501. After the uppermost wiring layer 22 is formed on the interlayer insulating film 21, the wiring is filled with a relatively small silicon oxide 23 having a relative dielectric constant of about 4, and a protective film is formed only on the upper surface layer of the wiring 22 and the buried silicon oxide 23. As a result, silicon nitride 24 having a thickness of about 7000 to 10,000 angstroms is formed. In this known example, since the space between the wirings is made of silicon oxide having a relative dielectric constant smaller than that of silicon nitride, there is an effect that the wiring capacitance can be further reduced. However, when the degree of integration is further improved and the wiring interval is narrowed, there is a problem that the wiring capacity cannot be ignored.

FIG. 1C shows a further improved structure for reducing the wiring capacitance, which is described in Japanese Patent Laid-Open No. 2-151032. After the uppermost wiring layer 32 is formed on the interlayer insulating film 31, a silicon oxide film 33 having a thickness of 1200 nm is deposited so that a cavity 34 is formed between the wirings, and a silicon nitride film having a thickness of 800 nm is formed thereon as a protective film. 35 is formed. The cavity 34 can be formed by actively utilizing the fact that the step coverage of silicon oxide deposited at a relatively low temperature of about 400 ° C. is poor. The poor step coverage means that the deposition rate on the upper surface is faster than the deposition rate of silicon oxide on the side wall and bottom of a groove formed by adjacent wirings. As a result, the upper part is closed earlier than the inside of the groove is filled with silicon oxide, and a cavity is generated. The cavity has a relative dielectric constant of about 1, which is smaller than that of silicon oxide 4 and has the effect of drastically reducing the wiring capacitance.

However, in the structure having the above-described cavity, the cavity is formed with silicon oxide, and the protective film silicon nitride is laminated thereon, so that the thickness of the insulating film deposited above the wiring is increased, and as a result The film stress increases. If the width of the wiring is further reduced, the adverse effect of this film stress becomes obvious, or the semiconductor substrate itself is warped, resulting in new problems such as deterioration of the characteristics of the fine elements.

In order to deal with the new problem, the inventor examined the structure shown in cross section in FIG. The structure shown here has a very fine top wiring with a top wiring width of 400 nm, a wiring height of 700 nm, and a wiring spacing of 400 nm. The uppermost wiring 42 is formed on the interlayer insulating film 41, a silicon oxide film 43 having a thickness of 100 nm is formed as a stress relaxation layer so as to cover the uppermost wiring 42, and a cavity 45 is generated between the wirings. A silicon nitride 44 having a thickness of 550 nm serving as a protective film is stacked. In this structure, since the thickness of the silicon nitride serving as the protective film is reduced, the silicon oxide used as the stress relaxation layer can also be reduced. Therefore, the thickness of the entire insulating film can be reduced. Further, since the cavity is provided between the wirings, there is an advantage that the capacitance between the wirings can be reduced. However, as a result of actually performing a moisture resistance test, the following problems occurred.

For the uppermost wiring having the above protective film, a PIQ (polyimide resin) is formed on the protective film, assembled into a package, and then left in an environment of 2 atm, 120 ° C. and 100% humidity for 96 hours. When applied, significant wiring corrosion was observed. On the other hand, as shown in FIG. 2 (b), as a result of simultaneously filling the cavity with PIQ 47 and subjecting the sample with the cavity disappeared to the moisture resistance test, no corrosion of the wiring was observed.

In order to clarify the cause, the sample of FIG. 2A was observed in detail with an electron microscope. As a result, it was found that the bonding interface 46 exists at a position above the central portion of the wiring interval where the protective film deposited and grown from the adjacent wiring is combined. As shown in the figure, after dipping in hydrofluoric acid with the cross-section exposed, when dried and observed with an electron microscope, a streak-like dent is observed at the position of the bonding interface 46, which is clearly different from other parts. There were microscopic gaps with different film quality. In FIG. 2A, the cavity 45 is open to the outside at the end of the wiring. However, since the resin is formed before assembling the package, the resin closes the open end. The structure at the end is the same as the structure shown in FIG. 2B, and it can be determined that there was no direct moisture intrusion from the open end within the test condition range. Therefore, it is considered that the corrosion of the wiring is caused by the moisture that has entered through the bonding interface accumulated in the cavity.

If the cavity is filled, the corrosion of the wiring can be remarkably reduced, but the original purpose of reducing the wiring capacity cannot be achieved. An example in which the influence of the stress of the protective film is avoided and a cavity is formed between the wirings to reduce the wiring capacity is described in Japanese Patent Laid-Open No. 5-90255. Is not mentioned.

JP-A-5-326501 Japanese Patent Laid-Open No. 2-151032 Japanese Patent Laid-Open No. 5-90255

As described above, in the protective film of the conventional miniaturized semiconductor device, when a cavity is formed between the wirings in order to reduce the wiring capacity, a bonding interface is formed in the protective film above the wiring, and from the bonding interface There has been a problem that the wiring corrodes due to the ingress of moisture and accumulation of the infiltrated moisture.

In view of the above-described problems of the prior art, the object of the present invention is to make a finer top that has a higher wiring height than a wiring width, a wiring interval equal to the wiring width, and reduced mechanical strength. In this wiring layer, even if the thickness of the protective film is reduced in order to reduce the influence of the film stress on the wiring and a cavity is formed between the wirings so as to avoid an increase in wiring capacity, An object of the present invention is to provide a semiconductor device having a structure in which corrosion does not occur and a method for manufacturing the same.

In order to solve the above problems, a semiconductor device according to the first aspect of the present invention includes a semiconductor having a plurality of wiring layers and a protective film formed to cover the uppermost wiring layer formed on the insulating film. The uppermost wiring layer includes at least a region in which a plurality of wirings having a wiring width smaller than the wiring height and a plurality of wirings having a wiring interval equivalent to the wiring width are arranged at the same repetition pitch. The protective film covering the uppermost wiring layer includes a stress relaxation film formed so as to cover an upper surface, a side surface of the wiring, and a surface of the insulating film, and a first moisture-resistant protective film formed on the stress relaxation film And a second moisture-resistant protective film formed on the first moisture-resistant protective film, the first moisture-resistant protective film comprising a cavity formed in the center of the wiring interval, and the cavity Continuation interface from the cavity in the protective film located above Have the second moisture-resistant protective film is characterized to have no joint interface in the film.

In the semiconductor device according to the first aspect, the film thickness of the first moisture-resistant protective film on the upper surface of the wiring is required to form a cavity between the wirings so that the thickness is 1/2 of the wiring interval. A characteristic is that the value obtained by subtracting the thickness of the stress relaxation film from the value divided by the cosine determined by the elevation angle of the position where the one moisture-resistant protective film is in contact is minimized.

Furthermore, in the semiconductor device according to the first aspect, the width of the wiring is 450 nm or less, the height of the wiring is 600 to 800 nm, the wiring interval is 450 nm or less, and the thickness of the stress relaxation film is 80 to 120 nm. The film thickness on the upper surface of the wiring of the first moisture-resistant protective film is 50 to 350 nm, and the film thickness on the upper surface of the wiring of the second moisture-resistant protective film is combined with the film thickness of the first moisture-resistant protective film. It is characterized by the finest uppermost wiring and its protective film set to a film thickness of 400 nm or more necessary for ensuring moisture resistance on the upper surface.

The method for manufacturing a semiconductor device according to the second aspect of the present invention is a method for manufacturing a semiconductor device having a plurality of wiring layers and forming a protective film so as to cover the uppermost wiring layer formed on the insulating film. Forming a plurality of semiconductor elements on a semiconductor substrate, forming a plurality of lower wiring layers including at least one wiring layer, forming an insulating film on the lower wiring layer, and planarizing the surface thereof A step, a step of forming a conductor plug connecting the lower wiring layer and the uppermost wiring layer, a step of forming the uppermost wiring layer, a step of forming a stress relaxation layer made of silicon oxide by a CVD method at a temperature of about 400 ° C. A step of depositing a first moisture-resistant protective film by a CVD method at a temperature of about 400 ° C. so as to form a cavity at the center of the wiring interval, and being formed in the first moisture-resistant protective film above the cavity Bonding interface deposited on it At least a step of treating the surface of the first moisture-resistant protective film so as not to grow in the second moisture-resistant protective film, and a step of depositing the second moisture-resistant protective film by a CVD method at a temperature of about 400 ° C. It is characterized by that.

In the method for manufacturing a semiconductor device according to the second aspect, the bonding interface formed in the first moisture-resistant protective film above the cavity does not grow in the second moisture-resistant protective film deposited thereon. Thus, the step of treating the surface of the first moisture-resistant protective film is characterized by comprising a step of exposing to the atmosphere or forming a different kind of insulating film.

In the present invention, since the first moisture-resistant protective film itself forms cavities between the wirings, the wiring capacity can be reduced, and the bonding interface existing in the first moisture-resistant protective film has no bonding interface. Since the second moisture-resistant protective film is laminated and coated, it is possible to prevent the wiring from being corroded by the ingress of moisture. In addition, since the protective film is formed substantially only with the moisture-resistant protective film, the thickness of the protective film can be reduced, the influence of the film stress on the miniaturized wiring is reduced, and the reliability of the semiconductor device is improved. There is an effect that can be improved.

Hereinafter, an embodiment of the present invention will be described with reference to the cross-sectional view of FIG. There is a semiconductor substrate in which semiconductor elements are formed on the surface of the substrate and these semiconductor elements are covered with an insulating film, which should be explained, but in FIG. 3A, the semiconductor substrate is omitted. . A lower wiring layer 51 located below the uppermost wiring layer is formed on the omitted semiconductor substrate, an interlayer insulating film 52 is formed on the lower wiring layer 51, and a predetermined layer of the interlayer insulating film 52 is formed. Conductive plugs 53 connecting the wiring layers are formed at the positions, and the uppermost wiring layer 54 is formed on the interlayer insulating film 52.

The wiring layer 54 is configured such that the minimum wiring width is 400 nm, the wiring height is 700 nm, and the wiring interval is 400 nm. A stress relaxation film 55 made of silicon oxide having a thickness of 100 nm is deposited on the entire surface including the uppermost wiring layer 54 in the previous period, and a first moisture-resistant protective film 56 made of silicon nitride is further laminated. As a result, a cavity 57 is formed between the wirings. In order to form the cavity 57, the thickness of the first moisture-resistant protective film 56 on the upper surface of the wiring is set to 200 nm which is ½ of the wiring interval of 400 nm. The value 180 nm obtained by subtracting the film thickness 100 nm of the stress relaxation film from the value 280 nm divided by the cosine determined by the elevation angle 45 degrees at the position where the moisture-resistant protective film contacts is set to a minimum.

In order to explain the elevation angle in more detail, FIG. 3B shows an enlargement within the frame indicated by A in FIG. The elevation angle is indicated by Θ in the figure. This is an angle formed by a line segment B extended so as to be in contact with the ridge line of the first moisture-resistant protective film deposited on the adjacent opposing wiring from the vertex of the wiring upper surface corner and the extended line C of the wiring upper surface. In the observation result of the actually prepared sample using the scanning electron microscope, Θ was about 45 degrees. Therefore, the cosine is about 0.7. The required film thickness L1 of the first moisture-resistant protective film is 180 nm by subtracting the film thickness L2 (100 nm) of the stress relaxation film from the above-mentioned 280 nm.

In this embodiment, the film thickness of the first moisture-resistant protective film 56 is set to 300 nm in consideration of the processing variation of the wiring interval and the film thickness variation of the stress relaxation film and the first moisture-resistant protective film itself. A second moisture-resistant protective film 59 having a thickness of 250 nm is deposited on the first moisture-resistant protective film 56, and the total thickness of the first moisture-resistant protective film and the second moisture-resistant protective film is 550 nm. Thus, moisture resistance on the upper surface of the wiring is ensured.

According to the present embodiment, the wiring density is increased due to the improvement in the degree of integration, and the wiring width becomes smaller than the height of the wiring, so that even if the wiring has a reduced mechanical strength against stress, it becomes a stress relaxation layer. By forming the silicon oxide thinly and forming the substantial protective film with a moisture-resistant protective film, the thickness of the entire insulating film on the upper surface of the wiring can be reduced, so that an increase in capacitance between wirings can be avoided at the same time. This has the effect of avoiding adverse effects on the wiring due to stress. Further, when the first moisture-resistant protective film 56 is formed, the cavity 57 and the bonding interface 58 whose water intrusion prevention ability is inferior to that of the flat portion are formed. Since the second moisture-resistant protective film 59 that does not have a bonding interface is formed thereon, the moisture can be prevented from entering.

Hereinafter, an embodiment relating to a method for manufacturing a semiconductor device of the present invention will be described with reference to a series of cross-sectional views of FIGS. Referring to FIG. 4A, a state in which the uppermost wiring layer is formed on the lower wiring layer via the conductor plug is shown. The lower wiring layer 61 formed on the semiconductor substrate is made of Cu (copper) -containing Al (aluminum) formed by sputtering. Thin titanium nitride is also formed above and below the Al layer by the sputtering method. An interlayer insulating film 62 made of silicon oxide formed by plasma CVD is formed on the lower layer wiring 61. Contact holes are formed in a predetermined region of the interlayer insulating film 62 by lithography and dry etching, titanium nitride by sputtering and W (tungsten) by CVD are formed, and then W and titanium nitride on the interlayer insulating film 62 are The conductor plug 63 is formed by removing and filling only the contact hole with W and titanium nitride. Next, the uppermost wiring layer 64 is formed so as to ensure conduction with the conductor plug 63. The uppermost wiring layer 64 is also made of Cu-containing Al by sputtering, and thin titanium nitride is formed above and below it. The total thickness of the uppermost wiring layer 64 is 700 nm.

FIG. 4B shows a state in which the stress relaxation film 65 is formed on the uppermost wiring layer 64 that has been subjected to patterning. Although not shown in the drawing, after the uppermost wiring layer 64 is formed, a photoresist pattern is formed in a desired region by a lithography technique, and the uppermost wiring layer 64 is processed by dry etching using the photoresist pattern as a mask. is doing. The dry etching process can be performed by using a well-known high-frequency excitation plasma and various conditions can be selected. For example, the dry etching process can be performed by plasma etching in a gas atmosphere mainly containing chlorine at a pressure of about 10 to 100 mTorr.
The uppermost wiring layer is formed so that the wiring width is 400 nm and the wiring interval is 400 nm. Since the thickness of the wiring is 700 nm, the structure is longer in the vertical direction than the conventional wiring structure described in the background art described above, and the resistance to mechanical stress is weakened. This tendency becomes more conspicuous as the degree of integration of semiconductor elements increases.

The stress relaxation film 65 is formed of silicon oxide having a relatively small film stress in order to prevent the film stress of the moisture-resistant protective film formed thereon from directly affecting the wiring. Various conditions can be selected for forming the stress relaxation film 65. For example, a well-known high-frequency plasma is used, temperature 400 ° C., pressure 3 Torr, high-frequency power 500 W, TEOS (tetraethoxysilane (Si (OC2H5) 5). And a plasma CVD method using oxygen as a reactive gas. The thickness of the stress relaxation film 65 is 100 nm.

Referring to FIG. 4C, a state where the first moisture-resistant protective film 66 is formed is shown. The first moisture-resistant protective film 66 is made of silicon nitride known to be effective as a protective film. For the formation of the first moisture-resistant protective film 66, various conditions can be selected using a well-known high-frequency plasma. For example, a temperature of 400 ° C., a pressure of 4.5 Torr, a high-frequency power of 300 W, monosilane (SiH 4) A plasma CVD method using ammonia (NH3) as a reaction gas can be used. The thickness of the first moisture-resistant protective film 66 is 300 nm.

At the stage where the first moisture-resistant protective film 66 is formed, a cavity 67 is formed between the wirings. Since the above-described step coverage of the stress relaxation film itself is 50%, when 100 nm is deposited on the upper surface of the wiring, the thickness of the side surface of the wiring is 50 nm, and when the stress relaxation film 65 is deposited, The interval formed by the stress relaxation film is 300 nm by subtracting twice the stress relaxation film 50 nm from the wiring interval 400 nm.
Further, when the first moisture-resistant protective film is finally deposited on the upper surface of the wiring by 300 nm, the upper part between the wirings is closed at the stage of 180 nm deposition. Since the step coverage of the first moisture-resistant protective film is 40%, the thickness of the wiring side surface is 72 nm, and the total thickness of the first moisture-resistant protective film occupying between the wirings is twice as large as 72 nm. It becomes 144 nm. Therefore, at the stage where the first moisture-resistant protective film 66 is formed, a cavity having a width of 156 nm obtained by subtracting 144 nm from 300 nm is formed.

On the other hand, in the upper part between the wirings, a bonding interface 68 is formed because the first moisture-resistant protective film deposited and grown from the upper surface end of the adjacent wirings is combined. As described above, this bonding interface is presumed that the etching rate by the solution is faster than the other parts, and the silicon and nitrogen network constituting the film is in a state of being cut off. It is thought that the ability to prevent intrusion of moisture and the like is reduced. Also, since the bonding interface grows reflecting the history of the bonding interface formed first when the film is deposited, it is not eliminated even if it is formed thick.

FIG. 4D shows a state in which the second moisture-resistant protective film 69 made of silicon nitride having a thickness of 250 nm is formed. The second moisture-resistant protective film 69 can be deposited under the same conditions as the first moisture-resistant protective film 66. However, as described above, when the first moisture-resistant protective film 69 is continuously formed as one layer, the history of the bonding interface remains. Sufficient resistance as a protective film cannot be maintained.

In view of this, the second moisture-resistant protective film is deposited after processing to cut off the history of the bonding interface formed in the first moisture-resistant protective film. FIG. 5B schematically shows the state. Actually, the joining interface is also in a state where there is no thickness, but FIG. 5B shows an exaggerated extreme state where there is the thickness of the interface. FIG. 5 (a) exaggerates the state of FIG. 2 (a) described above. This shows that the bonding interface 72 does not disappear even if the first moisture-resistant protective film 71 is continuously deposited as a single layer thickly.

On the other hand, FIG. 5B shows that the formation of the first moisture-resistant protective film is stopped at a film thickness that allows a cavity to be formed between the wirings, and the semiconductor substrate is temporarily removed from the first moisture-resistant protective film forming apparatus. The state is shown in the case where it is taken out and exposed to the atmosphere and returned to the same device again, or the second moisture-resistant protective film 74 is formed by another device. No bonding interface is formed in the second moisture-resistant protective film. When exposed to the atmosphere, oxygen in the atmosphere is adsorbed on the surface, and an interface 73 made of a silicon oxide-like substance different from silicon nitride is formed. Although the thickness of the interface 73 is about 0.5 nm, it prevents the bonding interface in the first moisture-resistant protective film from growing in the second moisture-resistant protective film.

In addition, it is possible to form the interface 73 by actively forming silicon oxide having a thickness of about 1 nm instead of exposing to the atmosphere. In this case, the film formation conditions can be changed and formed stepwise without removing the semiconductor substrate from the apparatus. When actively forming a thin film, a metal oxide such as tantalum oxide may be used, and it can be formed with good controllability by the ALD (Atomic Layer Deposition) method in addition to the usual thermal CVD method. .

After forming the second moisture-resistant protective film as described above, a PIQ was formed thereon, assembled into a package, and then subjected to a moisture resistance test under conditions of 2 atm, 120 ° C., and humidity of 100%. As described above, in the first moisture-resistant protective film single layer shown in FIG. 2A, when the bonding interface is exposed on the surface, significant wiring corrosion was observed even for 96 hours. In the structure in which the second moisture-resistant protective film of this example was laminated so that the bonding interface was not exposed on the surface, wiring corrosion was not observed even in the 400-hour test.

As described above, according to the present embodiment, the heterogeneous interface is formed so as to block the bonding interface generated when the first moisture-resistant protective film is formed so that a cavity is formed between the wirings. By providing the second moisture-resistant protective film having no bonding interface, it is possible to prevent wiring corrosion due to the ingress of moisture from the outside environment.

In this embodiment, silicon nitride is used as the moisture-resistant protective film, but the same effect can be obtained with silicon oxynitride.

(A) (b) (c) Individual cross-sectional views showing examples of conventional top wiring and protective film Sectional view showing a conventional structure in a semiconductor device with improved integration Sectional drawing which shows the structure of the uppermost wiring layer and protective film of this invention (A) to (d) a series of process cross-sectional views showing an embodiment of the present invention Sectional view schematically enlarging the microstructure of the conventional and the present invention

Explanation of symbols

11, 21, 31, 41, 52, 62 ... interlayer insulating films 12, 22, 32, 42, 54, 64 ... uppermost wiring layers 13, 24, 35, 44 ... silicon nitride film 23, 33, 43 ... Silicon oxide films 34, 45, 57, 67 ... Cavities 46, 58, 68, 72 ... Bonding interface 47 ... PIQ
51, 61 ... lower wiring layers 53, 63 ... conductor plugs 55, 65 ... stress relaxation films 56, 66, 71 ... first moisture-resistant protective films 59, 69, 74 ... first Two moisture-resistant protective film 73 ... interface

Claims (5)

A semiconductor device having a plurality of wiring layers and having a protective film formed to cover the uppermost wiring layer formed on the insulating film, wherein the uppermost wiring layer has a wiring width higher than that of the wiring. Including at least a region where a plurality of wires having a smaller wiring and a wiring interval equivalent to the width of the wiring are arranged at the same repetition pitch, and the protective film covering the uppermost wiring layer includes an upper surface, a side surface and the wiring A stress relieving film formed to cover the surface of the insulating film; a first moisture-resistant protective film formed on the stress-relaxing film; and a second moisture-resistant film formed on the first moisture-resistant protective film The first moisture-resistant protective film has a cavity formed at the center of the wiring interval, and a bonding interface continuous from the cavity in the protective film located above the cavity. However, the second moisture-resistant protective film has no bonding interface in the film. Wherein a. The first moisture-resistant protective film has a film thickness on the upper surface of the wiring at a position where the first moisture-resistant protective film necessary for forming a cavity between the wirings is ½ of the wiring interval. 2. The semiconductor device according to claim 1, wherein a value obtained by subtracting the thickness of the stress relaxation film from a value divided by a cosine determined by an elevation angle is a minimum. The width of the wiring is 450 nm or less, the height of the wiring is 600 to 800 nm, the wiring interval is 450 nm or less, the thickness of the stress relaxation film is 80 to 120 nm, and the film on the upper surface of the wiring of the first moisture-resistant protective film The film thickness on the upper surface of the wiring of the second moisture-resistant protective film is 50 to 350 nm, and the film thickness of 400 nm necessary for ensuring the moisture resistance on the upper surface of the wiring together with the film thickness of the first moisture-resistant protective film. The semiconductor device according to claim 1, which is as described above. A method of manufacturing a semiconductor device having a plurality of wiring layers and forming a protective film so as to cover an uppermost wiring layer formed on an insulating film, the step of forming a plurality of semiconductor elements on a semiconductor substrate, Forming a plurality of lower wiring layers including at least one wiring layer; forming an insulating film on the lower wiring layer; and planarizing a surface thereof; connecting the lower wiring layer and the uppermost wiring layer; The step of forming the conductor plug, the step of forming the uppermost wiring layer, the step of forming the stress relaxation layer made of silicon oxide by the CVD method at a temperature of about 400 ° C., and the first so as to form a cavity in the center of the wiring interval Depositing a moisture-resistant protective film by a CVD method at a temperature of about 400 ° C., and a second moisture-resistant protective film on which a bonding interface formed in the first moisture-resistant protective film above the cavity is deposited The first to not grow in Treating the wet surface of the protective film, a method of manufacturing a semiconductor device which process, characterized in that it comprises at least deposited in a second moisture-resistant protective film CVD method at approximately the temperature 400 ° C. The. The surface of the first moisture-resistant protective film is formed so that the bonding interface formed in the first moisture-resistant protective film above the cavity does not grow in the second moisture-resistant protective film deposited thereon. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the processing is performed by exposing to the atmosphere or forming an insulating film by a different method.

Images