JP2006127536A - Discrete cosine transform system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the necessity of using a high speed dual port RAM and to prevent increase in power consumption accompanying the use of the dual port RAM in a two-dimensional discrete cosine transform system. <P>SOLUTION: A memory space 3 is constituted using a plurality of dual port RAMs 3a, 3b. A transpose control part 4 to which a one-dimensional discrete cosine coefficient is supplied from a one-dimensional discrete cosine transform circuit 2 at the previous stage is equipped with a write control part 41 which repeatedly and individually controls write operations of N dual port RAMs 3a, 3b with frequency of once in N clock cycles and a read control part 42 which repeatedly and individually controls reading operations with frequency of once in N clock cycles, write frequency and read frequency of the one-dimensional discrete cosine transform coefficient are lowered, respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention performs two-dimensional discrete cosine transform performed in units of blocks of m × n pixels (m, n is an integer, m = n or m ≠ n), such as 8 × 8 pixels, in the row direction and the column direction. The present invention relates to a discrete cosine transform device realized by decomposing into one-dimensional discrete cosine transform and executing it.

  Hereinafter, “discrete cosine transform” may be abbreviated as “DCT”. As shown in FIG. 31, a conventional two-dimensional discrete cosine transform device 101 that performs two-dimensional discrete cosine transform in units of 8 × 8 pixels is an image of 8 pixels in the horizontal direction of a block composed of 8 × 8 pixels. The previous one-dimensional DCT conversion circuit 102 that receives the data PXLD and performs horizontal one-dimensional DCT conversion, a memory space 103 having an area for storing 64 one-dimensional DCT coefficients, and one-dimensional DCT coefficients A transposition control unit 104 that replaces (transposes) row positions and column positions, and a subsequent one-dimensional DCT conversion circuit 105 that performs vertical one-dimensional DCT conversion.

The memory space 103 is composed of one dual port RAM 103a of 64 words.
The transposition control unit 104 includes a write control unit 141 and a read control unit 142. Among these, the write control unit 141 includes a write counter 1411 and a write address generation unit 1412, and performs write control of the dual port RAM 103a. The read control unit 142 includes a read counter 1421 and a read address generation unit 1422 and performs read control.

  The preceding one-dimensional DCT conversion circuit 102 receives as input image data PXLD sequentially supplied in synchronization with the system clock SCLK, performs one-dimensional DCT conversion for every eight pixels in the horizontal direction, and produces a one-dimensional DCT coefficient DCTI. (K0 to K63) are sequentially output from the first one-dimensional DCT coefficient K0, one coefficient per clock cycle.

  The dual port RAM 103a has a data storage area of 64 words, a write data input terminal WD, a write address input terminal WA, a write enable input terminal WEN, a read address input terminal RA, a read enable input terminal REN, A read data output terminal RD and a clock input terminal CLK are provided. In this dual port RAM 103a, the write data input to the write data input terminal WD is synchronized with the rising edge of the system clock SCLK input to the clock input terminal CLK only when the write enable input WEN is a logical value “0”. The input DCTI is written at the address supplied to the write address input terminal WA. Further, only when the read permission input REN is the logical value “0”, the data stored in the read address supplied to the read address input terminal RA is read from the read data output RD of the dual port RAM 103a.

  The write counter 1411 of the write controller 141 is composed of a 7-bit binary counter, and is counted up sequentially in synchronization with the system clock SCLK only when the externally input write start signal WSTART is a logical value “0”. To go. The write start signal WSTART supplied from the outside is a signal whose logical value becomes “0” at the same timing when the first one-dimensional DCT coefficient K0 output from the one-dimensional DCT conversion circuit 102 in the previous stage is output. It is a signal indicating the write start timing.

  The write address generator 1412 receives the 7-bit outputs WCNT6 to WCNT0 of the write counter 1411. When the output WCNT6 is a logical value “0”, the write address WAA of the dual port RAM 103a is 0, 1, 2, 3, ..., 62, 63, that is, outputs WCNT5 to WCNT0 are supplied as they are. When WCNT6 is logical “1”, the write address WAA is an address in the order of 0, 8, 16, 24,..., 47, 55, 63, that is, in the column direction of the 8 × 8 pixel block. Supply.

  The read counter 1421 of the read control unit 142 is composed of a 7-bit binary counter, and is counted up sequentially in synchronization with the system clock SCLK only when the read start signal RSTART input from the outside is a logical value “0”. To go. The read start signal RSTART supplied from the outside is a logical value at the timing when it is written in the dual port RAM 103a when the one-dimensional DCT coefficient output from the one-dimensional DCT conversion circuit 102 in the previous stage is 50 or more and 63 or less. Is a signal indicating “0”, and is a signal indicating the read start timing.

  The read address generator 1422 receives the 7-bit outputs RCNT6 to RCNT0 of the read counter 1421. When the output RCNT6 has a logical value “0”, the write address RAA of the dual port RAM 103a is 0, 8, 16, 24, ..., 47, 55, 63, that is, addresses in the column direction of the 8 × 8 pixel block are supplied. When the output RCNT6 is the logical value “1”, the write addresses RAA are supplied in the order of 0, 1, 2, 3,..., 62, 63, that is, the outputs RCNT5 to RCNT0.

  The subsequent one-dimensional DCT conversion circuit 105 inputs the read data output RDA from the dual port RAM 103a, which is read-controlled by the read control unit 142, one coefficient at a frequency of once per clock cycle, and the vertical one for every eight coefficients. One-dimensional DCT conversion is performed, and two-dimensional DCT coefficients KK0 to KK63 are sequentially output from the two-dimensional DCT coefficient output terminal DCTOUT in synchronization with the system clock SCLK.

  FIG. 32 is a diagram showing the order of writing the one-dimensional DCT coefficient to the dual port RAM 103a in the first 8 × 8 pixel block. The one-dimensional DCT coefficients K0 to K63 output one by one from the one-dimensional DCT conversion circuit 102 in the previous stage are addresses 0, 1, 2, 3,... 62 of the write address WA designated by the write address generator 1412. , 63, when the write start START is a logical value “0”, one coefficient is sequentially written to the dual port RAM 103a in one clock cycle.

  FIG. 33 is a diagram showing the reading order of the one-dimensional DCT coefficient from the dual port RAM 103a in the first 8 × 8 pixel block. Addresses 0, 8, 16, 24,... Of the read address RA designated by the read address generator 1422 from the time when the horizontal one-dimensional DCT coefficients are written in the dual port RAM 103a from 50 to 63 inclusive. , 47, 55, 63, when the read start signal RSTART is a logical value “0”, the one-dimensional DCT coefficients are transferred from the dual port RAM 103a in the order of K0, K8, K16,..., K47, K55, K63. One coefficient is sequentially read in one clock cycle. Thereby, the row position and column position of the one-dimensional DCT coefficient are transposed.

  FIG. 34 is a diagram showing the order of writing the one-dimensional DCT coefficients (K′0 to K′63) to the dual port RAM 103a in the next 8 × 8 pixel block unit. That is, the first one-dimensional DCT coefficient of the first 8 × 8 pixel block is in the order of addresses 0, 8, 16, 24,..., 47, 55, 63 of the read address RA designated by the read address generator 1422. The one-dimensional DCT coefficients K0, K8, K16,..., K47, K55, and K63 are sequentially read from the dual port RAM 103a. After that, when the write start signal WASTRT has a logical value “0” in the order of addresses 0, 8, 16, 24,..., 47, 55, 63 of the write address WA specified by the write address generator 1412. The one-dimensional DCT coefficients K′0 to K′63 in the horizontal direction are sequentially overwritten on the dual port RAM 103a one coefficient at a time in one clock cycle.

  FIG. 35 is a diagram illustrating the reading order of the one-dimensional DCT coefficients K′0 to K′63 from the dual-port RAM 103a in the next 8 × 8 pixel block unit. Addresses 0, 1, 2, 3,... Of the read address RA designated by the read address generator 1422 from the time when the horizontal one-dimensional DCT coefficient is overwritten in the dual port RAM 103a by 50 to 63. , 61, 62, and 63, when the read start signal RSTART is a logical value “0”, the one-dimensional DCT coefficients K′0, K′8, K′16,. , K′55, K′63 in order, one coefficient at a time in one clock cycle, thereby transposing the row position and the column position of the one-dimensional DCT coefficient.

  As described above, with respect to the writing control unit 141, the writing order of FIGS. 32 and 34 is alternately switched for every 64 one-dimensional DCT coefficients, and with respect to the reading control unit 142, FIGS. By alternately switching the reading order of 64 one-dimensional DCT coefficients, the row position and the column position of the one-dimensional DCT coefficients are always exchanged.

  FIG. 36 is a diagram showing the timing of the write operation of the dual port RAM 103a. The write operation to the dual port RAM 103a is performed every cycle at a frequency of once per clock cycle when the write start signal WSTART is a logical value "0". For this reason, regarding the writing of the one-dimensional DCT coefficient sequentially supplied from the row-direction one-dimensional DCT conversion circuit 102, the setup specification Tsu (RAM) between the write data and the clock, which is the timing specification of the dual port RAM 103a to be used, and hold It is necessary to satisfy the time Th (RAM). That is, when the clock cycle is T and the delay from the system clock SCLK of the one-dimensional DCT coefficient sequentially supplied from the preceding one-dimensional DCT conversion circuit 102 is Td, (Expression-1) and (Expression-2) are satisfied. There is a need.

T−Td> Tsu (RAM) (Formula-1)
Td> Th (RAM) (Formula-2)
FIG. 37 is a diagram showing the timing of the read operation of the dual port RAM 103a. The read operation from the dual port RAM 103a is performed every cycle at a frequency of once per clock cycle when the read start signal RSTART is a logical value “0”. Therefore, in order for the subsequent one-dimensional DCT conversion circuit 105 to accurately receive the read data RDA from the dual-port RAM 103a, the access time of the dual-port RAM 103a is Tpd, and the input timing specification of the subsequent one-dimensional DCT conversion circuit 105 is used. When a certain setup time is Tsu (FF) and a hold time is Th (FF), the conditions of (Expression-3) and (Expression-4) must be satisfied.

T−Tpd> Tsu (FF) (Formula-3)
Tpd> Th (FF) (Formula-4)
If all the conditions of (Expression-1) to (Expression-4) are satisfied, the one-dimensional DCT conversion circuit 105 at the subsequent stage of writing the one-dimensional DCT coefficient into the dual-port RAM 103a and the read data from the dual-port RAM 103a is used. Propagation is accurately performed. The one-dimensional DCT conversion circuit 105 receives the transposed one-dimensional DCT coefficient as input, sequentially receives data under the conditions of (Expression-3) and (Expression-4), and performs a one-dimensional DCT conversion for eight vertical coefficients. I do.

As described above, in the conventional two-dimensional discrete cosine transform device, the memory space is configured by one dual-port RAM 103a having a data storage area of 64 words, and write / read control is performed once per clock cycle. Since it was repeatedly performed, there was a problem that a high-speed dual port RAM had to be used in order to realize a high-speed two-dimensional discrete cosine transform device. In particular, the memory access time Tpd is generally larger than the delay value of other logic circuits, and is one of the factors that determine the maximum operable frequency of the entire discrete cosine transform device. Although it is possible to increase the maximum operable frequency of the entire discrete cosine transform device by using a high-speed dual-port RAM, the power consumption increases by operating the dual-port RAM at high speed. There was a problem.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve such problems and eliminate the need for a high-speed dual-port RAM in a two-dimensional discrete cosine transform device, and to prevent an increase in power consumption associated therewith. .

  In order to solve the above-described problem, a two-dimensional discrete cosine transform device according to the present invention has a memory space composed of a plurality of dual-port RAMs and a writing frequency of a one-dimensional DCT coefficient supplied from a preceding one-dimensional DCT transform circuit. By reducing the frequency of reading the one-dimensional DCT coefficient supplied to the one-dimensional DCT conversion circuit at the subsequent stage, it is possible to reduce the power consumption in the memory and realize low power consumption, and to the dual port RAM. The write timing margin is increased and the restriction on the circuit operating frequency due to the access time of read data is relaxed.

Specifically, N, m, and n are integers, and m = n or m ≠ n, and the memory space is configured by a dual port RAM having N (m × n) / N word data storage areas, The transposition control unit outputs a horizontal one-dimensional DCT coefficient group, which is output by N coefficients at a frequency of once every N clock cycles from the preceding one-dimensional DCT conversion circuit, to m × N or n × N coefficient units. Then, the coefficients in the same column are written to different dual-port RAMs, and for writing to each dual-port RAM, the write control unit that controls writing once every N clock cycles and the divided one-dimensional DCT coefficients are , M × n coefficients are repeated in increments of N coefficients one by one at a frequency of once every N clock cycles from each dual-port RAM in the order of the block units in the column direction. Which is constituted by a read control unit for reading control.

  In other words, according to the present invention, a memory space for temporarily storing m × n one-dimensional DCT coefficients is configured by using a plurality of dual-port RAMs, and obtained by one-dimensional discrete cosine transform in the row direction. Write control of individual transposition control units for transposing (transposing) the row positions and column positions of all the one-dimensional DCT coefficients to the one-dimensional DCT conversion circuit in the column direction to a plurality of dual port RAMs. It is composed of a write control unit that performs read operations and a read control unit that performs read control individually, and by reducing the frequency (number of times) of write and read access to each dual port RAM, the operating frequency is increased and the power consumption is reduced. Can be achieved.

  As described above, the discrete cosine transform device of the present invention uses a plurality of dual port RAMs for transposing one-dimensional DCT coefficients, and reduces the frequency (number of times) of write and read accesses, thereby enabling high speed dual port. High speed operation can be performed without using RAM. Furthermore, since the number of times of writing and reading operations (frequency) of the dual port RAM is reduced, the power consumption of the dual port RAM is reduced, and low power consumption can be realized.

  According to the first aspect of the present invention, m and n are integers (m = n or m ≠ n), and a one-dimensional DCT transformation in the horizontal direction is performed for each of m pixels or n pixels in block units of pixels of m columns × n rows. A DCT conversion circuit in the previous stage, a memory space for temporarily storing m × n one-dimensional DCT coefficients supplied from the DCT conversion circuit, and a row position and a column position of the memory space are transposed to form a one-dimensional A transposition control unit that controls writing and reading of DCT coefficients, and a DCT conversion circuit in a subsequent stage that performs one-dimensional DCT conversion in the vertical direction for each m coefficient or n coefficient with the DCT coefficient output from the memory space as an input. In the DCT conversion apparatus, the memory space is configured using N (m × n) / N word dual-port RAMs, where N is an integer, and the transposition control unit is configured to be used once every N clock cycles. A write control unit that repeatedly and individually controls the write operations of the N dual-port RAMs, and a read control unit that individually and repeatedly controls the read operation once every N clock cycles. Is.

According to the second aspect of the present invention, the DCT conversion circuit in the previous stage performs one-dimensional DCT conversion for every m or n pixels in the horizontal direction, and sequentially outputs in parallel as a one-dimensional DCT coefficient group by N coefficients every N clock cycles. Configured to
The write control unit sequentially writes the one-dimensional DCT coefficient group sequentially supplied from the DCT conversion circuit in the preceding stage into different dual-port RAMs in which the coefficient in the same column is different in units of m × N or n × N coefficients. As for the writing of each dual port RAM, in the case of the first m × n one-dimensional DCT coefficients, the addresses are designated so that the DCT coefficients sequentially written to arbitrary addresses are not overwritten. , Write control is performed at the same timing once every N clock cycles, and in the case of the next m × n one-dimensional DCT coefficients, the first m × n one-dimensional DCT coefficients are sequentially overwritten in the column direction. The address is individually specified so that the one-dimensional DCT coefficient is written at the same timing once every N clock cycles. , Configured to repeatedly perform the above two write controls alternately,
The read control unit is configured to read, in the dual port RAM, addresses at which N one-dimensional DCT coefficients written in the N dual port RAMs by the write control unit can be simultaneously read in the order of columns in m × n pixel blocks. Are repeatedly supplied individually, and the coefficients are exchanged in the order of columns in the order of blocks of m × n pixels for each one-dimensional DCT coefficient read at the same timing once every N clock cycles. The one-dimensional DCT coefficient group composed of the replaced N coefficients is latched at the same timing at a frequency of once every N clock cycles and repeatedly supplied to the subsequent DCT conversion circuit. ,
The DCT conversion circuit in the subsequent stage is configured to perform one-dimensional DCT conversion for each of the m coefficient or n coefficient, with N DCT coefficient groups output at a frequency of once every N clock cycles from the read control unit as an input. It is what has been done.

In the invention according to claim 3, the DCT conversion circuit in the previous stage performs one-dimensional DCT conversion for every m pixels or n pixels in the horizontal direction, and determines the output order of the coefficients for the obtained one-dimensional DCT conversion coefficients according to the row position. It is configured to sequentially output one coefficient at a frequency of once per clock cycle,
The write control unit sequentially supplies the one-dimensional DCT coefficients sequentially supplied one by one from the DCT conversion circuit in the previous stage to the dual port RAMs having different coefficients in the same column in units of m × N or n × N coefficients. In the case of the first m × n one-dimensional DCT coefficients, the addresses are individually set so that the DCT coefficients sequentially written to arbitrary addresses are not overwritten. Specify and write control at different timings once every N clock cycles. In the case of the next m × n one-dimensional DCT coefficients, the first m × n one-dimensional DCT coefficients are in the column direction. The addresses are individually specified so that they are overwritten sequentially, and the one-dimensional DCT coefficients are written at different timings once every N clock cycles. Configured to control only
The read control unit reads the one-dimensional DCT coefficients written in the N dual-port RAMs by the write control unit in the order of m × n pixels in the column direction in the column direction, and sets the N addresses Each of the dual-port RAMs is individually supplied, and the one-dimensional DCT coefficients are read out from the N dual-port RAMs at a frequency of once every N clock cycles, and the read one-dimensional DCT coefficients are read out. Are latched at different timings once every N clock cycles and sequentially time-divisionally output one-dimensional DCT coefficients, and are repeatedly supplied to the subsequent DCT conversion circuit once every clock cycle. Composed of
The subsequent DCT conversion circuit recognizes the one-dimensional DCT coefficient output at a frequency of once per clock cycle by the read control unit, recognizes the row position of the coefficient based on the column position, and outputs each m coefficient or n coefficient. It is configured to perform one-dimensional DCT transformation.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a two-dimensional discrete cosine transform apparatus according to an embodiment of the present invention. The two-dimensional discrete cosine transform device 1 includes a preceding one-dimensional DCT transform circuit 2, a memory space 3, a transposition control unit 4, and a succeeding one-dimensional DCT transform circuit 5.

The memory space 3 is composed of two dual port RAMs 3a and 3b.
The transposition control unit 4 includes a write control unit 41 and a read control unit 42. The write control unit 41 includes a write counter 411, a write address generation unit 412, a write data selection circuit 413, and a write permission generation unit 414, and individually controls writing to the two dual port RAMs 3a and 3b. Do. The read control unit 42 includes a read counter 421, a read address generation unit 422, a read data selection circuit 423, and a read permission generation unit 424, and individually performs read control on the two dual port RAMs 3 a and 3 b. Do.

The preceding one-dimensional DCT conversion circuit 2 receives pixel data PXLD for 8 pixels in the horizontal direction of an image divided into 8 × 8 pixel blocks, one pixel at a time in synchronization with the system clock SCLK. Then, horizontal one-dimensional DCT conversion is performed on the pixel data PXLD, and when the WDLAT supplied from the write counter 411 is a logical value “0”, the one-dimensional DCT coefficient (K0) is synchronized with the system clock SCLK. ˜K63), the odd-numbered coefficient is the higher coefficient DCTI1, and the even-numbered coefficient is the lower coefficient DCTI0. As will be described later, the signal WDLAT supplied from the write counter 411 to the one-dimensional DCT conversion circuit 2 is a signal obtained by dividing the system clock SCLK by 2. More specifically, the signal WDLAT causes the DCTI1 and DCTI0 to have two clocks. It is controlled to output sequentially at a frequency of once per cycle.

  The dual port RAMs 3a and 3b of the memory space 3 have a data storage area of 32 words, and a write data input terminal WD, a write address input terminal WA, a write enable input terminal WEN, and a read address input terminal RA, respectively. , A read permission input terminal REN, a read data output terminal RD, and a clock input terminal CLK. In each of the dual port RAMs 3a and 3b, only when the write enable input WEN is the logical value “0”, the write data input input to the write data input terminal WD is written in synchronization with the rising edge of the clock input terminal CLK. The address is supplied to the address supplied to the address input terminal WA. Further, each of the dual port RAMs 3a and 3b is stored in the read address supplied to the read address input terminal RA in synchronization with the rising edge of the clock input terminal CLK only when the read permission input REN is a logical value “0”. The read data is read from the read data output RD.

The write counter 411 of the write control unit 41 is composed of a 7-bit binary counter. When the reset signal RST is input, the 7-bit count outputs WCNT6 to WCNT0 are all set to the initial value 0, and the write start signal WSTART is When the logical value is “0”, the count is incremented in synchronization with the system clock SCLK. The write start signal WSTART supplied from the outside has a logical value of “0” at the same timing when the first two one-dimensional DCT coefficient groups K0 and K1 output from the one-dimensional DCT conversion circuit 2 in the previous stage are output. Is a signal indicating the write start timing. The write counter 411 supplies the inverted signal of the least significant bit WCNT0 as WDLAT to the preceding one-dimensional DCT conversion circuit 2, and generates the one-dimensional DCT coefficient DCT at a frequency of once every two clock cycles.
Control is performed so that I1 and DCTI0 are supplied.

  The write address generator 412 receives the count outputs WCNT6 to WCNT1 of the write counter 411 and generates write addresses WAA and WAB of the dual port RAMs 3a and 3b. FIG. 2 is a diagram showing the relationship between WCNT6 to WCNT1, WAA, and WAB. When the most significant bit WCNT6 is a logical value “0”, both addresses WAA and WAB are 0, 1, 2, 3, 16, 17, 18, 19,..., 12, 13, 14, 15, 28, 29. , 30, 31 are supplied. When the most significant bit WCNT6 is a logical value “1”, as WAA, addresses converted to 0, 4, 8, 12, 16, 20, 24, 28,..., 19, 23, 27, 31 are supplied. , WAB, addresses converted into 16, 20, 24, 28, 0, 4, 8, 12,..., 3, 7, 11, 15 are supplied.

  Note that WAA and WAB when the most significant bit WCNT6 is a logical value “0” may be any address that does not overwrite the sequentially written one-dimensional DCT coefficient, even if the address order is not as described above. . However, when such an arbitrary address is supplied, WAA and WAB when the most significant bit WCNT6 is a logical value “1” are dual port RAMs 3a and 3b when the most significant bit WCNT6 is a logical value “0”. In addition, 8 × 8 = 64 coefficients that have already been written need to be written addresses that can be overwritten in the column direction, that is, in the order of K0, K8, K16, K24,..., K47, K55, K63. There is.

  The write data selection circuit 413 receives the count output WCNT3 of the write counter 411 as a data selection signal WDSEL, and selects data to be written to the dual port RAMs 3a and 3b using odd row coefficients and even row coefficients. When the data selection signal WDSEL is a logical value “0”, that is, when the coefficient is an odd-numbered row, the higher-order coefficient DCTI1 sequentially supplied from the one-dimensional DCT conversion circuit 2 in the previous stage is sequentially supplied once every two clock cycles. Select and output as write data WDA in the port RAM 3a, and select and output the lower coefficient DCTI0 as write data WDB in the dual port RAM 3b. When the data selection signal WDSEL is a logical value “1”, that is, in the case of an even row coefficient, the lower coefficient DCTI0 is selected and output as write data WDA and the higher coefficient DCTI1 is selected and output as write data WDB. .

  The write permission generation unit 414 supplies the logical sum (OR) of the write start signal WSTART supplied from the outside and the inverted signal of the least significant bit WCNT0 of the write counter 411 as the write permission signal WENB of the dual port RAMs 3a and 3b. The write operation is reduced to a frequency of once every two clock cycles.

  The read counter 421 of the read control unit 42 is composed of a 7-bit binary counter. When the reset signal RST is input, all the 7-bit count outputs RCNT6 to RCNT0 are set to the initial value 0, and the read start RSTART is logically set. When the value is “0”, it is counted up in synchronization with the system clock SCLK. Note that the timing at which the logical value of the read start signal RSTART becomes “0” is the 50th, after the write start signal WSTART becomes the logical value “0”, the one-dimensional DCT coefficients are sequentially written in the dual port RAMs 3a and 3b. This is the time when the ˜62nd coefficient is written. Further, the read counter 421 supplies the inverted signal of the least significant bit RCNT0 as RDLAT to the subsequent one-dimensional DCT conversion circuit 5. A signal obtained by delaying RCNT3 by two clock cycles is supplied to the read data selection circuit 423 as RDSEL, and control is performed so that data can be exchanged in accordance with the output timing of read data from the dual port RAMs 3a and 3b. .

  The read address generator 422 receives the count outputs RCNT6 to RCNT1 of the read counter 421 and generates read addresses RAA and RAB of the dual port RAMs 3a and 3b. FIG. 3 is a diagram showing the relationship between the count outputs RCNT6 to RCNT1 and the addresses RAA and RAB. When the most significant bit RCNT6 is logical “0”, RAA is 0, 4, 8, 12, 16, 20, 24, 28,..., 3, 7, 11, 15, 19, 23, 27, Address converted to 31 is supplied, and converted into RAB as 16, 20, 24, 28, 0, 4, 8, 12, ..., 19, 23, 27, 31, 3, 7, 11, 15 Supply. When the most significant bit RCNT6 is a logical value “1”, RA, 0, 1, 2, 3, 16, 17, 18, 19,..., 12, 13, 14, 15, 28, 29, 30 and 31 converted addresses are supplied, and RAB is converted to 0, 1, 2, 3, 16, 17, 18, 19, ..., 12, 13, 14, 15, 28, 29, 30, 31 Supply the address. That is, the read address generation unit 422 outputs one-dimensional DCT coefficients written in the dual port RAMs 3a and 3b by the write control unit 41, one by one from the dual port RAMs 3a and 3b in the order of 8 × 8 coefficient blocks in the column direction. The addresses that can be read at the same timing may be supplied to the read addresses RAA and RAB. Specifically, the read addresses RAA and RAB when the RCNT6 has the logical value “1” are equal to the write addresses WAA and WAB when the WCNT6 supplied from the write address generation unit 412 has the logical value “0”. The read addresses RAA and RAB at the time when the logical value is “0” may be individually supplied with the addresses equal to the write addresses WAA and WAB when the WCNT 6 is the logical value “1”.

  The read data selection circuit 423 receives the signal RDSEL supplied from the read counter 421 and selectively outputs the one-dimensional DCT coefficients read from the dual port RAMs 3a and 3b. Specifically, when the RDSEL is a logical value “0”, that is, when reading the one-dimensional DCT coefficient of the odd-numbered column of the 8 × 8 coefficient block, the read data RDA from the dual port RAM 3a is output as the upper coefficient DCTO1, The read data RDB from the dual port RAM 3b is output as the lower coefficient DCTO0. Further, when RDSEL is a logical value “1”, that is, when reading an even column of an 8 × 8 coefficient block, RDA is output as a lower coefficient DCTO0 and RDB is output as an upper coefficient DCTO1. The read data selection circuit 423 always outputs odd row coefficients out of 8 × 8 coefficient block units to the higher coefficient DCTO1 output, and repeatedly outputs even row coefficients to the lower coefficient DCTO0 output. .

  The read permission generation unit 424 supplies the logical sum (OR) of the read start signal RSTART supplied from the outside and the inverted signal of the least significant bit RCNT0 of the read counter 421 as the read permission RENB of the dual port RAMs 3a and 3b. The read operation is reduced to a frequency of once every two clock cycles.

  The subsequent one-dimensional DCT conversion circuit 5 receives the signal RDLAT supplied from the read counter 421, receives the one-dimensional DCT coefficients DCTO1, DCTO0 at the same timing every two clock cycles, and receives two clock cycles. 1-times DCT conversion in the vertical direction every eight coefficients, and two-dimensional DCT coefficients KK0 to KK63 are sequentially output as DCTOUT in synchronization with the system clock SCLK.

4 and 5 are diagrams showing data storage positions when the one-dimensional DCT coefficients are written in the dual port RAMs 3a and 3b in accordance with the write control unit 41. FIG.
FIG. 4 is a diagram showing a data storage position when the one-dimensional DCT coefficients K0 to K63 of the first 8 × 8 pixel block are written in the dual port RAMs 3a and 3b. The odd-numbered column coefficients K0, K2, K4,..., K60, K62 and the even-numbered coefficient K1 as the lower coefficient DCTI0 from the preceding one-dimensional DCT conversion circuit 2 at a frequency of once every two clock cycles. , K3, K5,..., K61, K63 are sequentially output at the same timing, and for the one-dimensional DCT coefficients K0 to K7, K16 to K23, K32 to K39, and K48 to K55 in the odd rows, the upper coefficient DCTI1 is set. The lower coefficient DCTI0 is written in the address numbers 0, 1, 2, 3,..., 13, 14 of the dual port RAM 3a. , 15 are written. For the even-numbered one-dimensional DCT coefficients K8 to K15, K24 to K31, K40 to K47, and K56 to K63, the low-order coefficient DCT1DI0 is assigned to the address numbers 16, 17, 18,. The higher coefficient DCTI1 is written to the address numbers 16, 17, 18,..., 29, 30, 31 of the dual port RAM 3b.

  FIG. 5 is a diagram showing data storage positions when the one-dimensional DCT coefficients K′0 to K′63 of the next 8 × 8 pixel block are written in the dual port RAMs 3a and 3b. The one-dimensional DCT coefficients K0 to K63 of the first 8 × 8 pixel block are transferred to the vertical directions K0, K8, K16, K24,..., K47, K55, and K63 from the dual port RAMs 3a and 3b, one coefficient each for two clocks. Reading begins once a cycle. Then, among the one-dimensional DCT coefficients K′0 to K′63 of the next 8 × 8 pixel block, the odd-numbered one-dimensional DCT coefficients K′0 to K′7, K′16 to K′23, and K For '32 to K'39 and K'48 to K'55, the higher coefficient DCTI1 is the address number 0, 4, 8, 12, 1, 5, 9, 13, ... 3, 7, 11 of the dual port RAM 3a. , 15 and the lower coefficient DCTI0 is written to the address numbers 16, 20, 24, 28, 17, 21, 25, 29,..., 19, 23, 27, 31 of the dual port RAM 3b. For even-numbered one-dimensional DCT coefficients K′8 to K′15, K′24 to K′31, K′40 to K′47, and K′56 to K′63, the lower coefficient DCT1DI0 is the address of the dual port RAM 3a. 16, 20, 24, 28, 17, 21, 25, 29,..., 19, 23, 27, 31, and the high-order coefficient DCTI1 is the address number 0, 4, 8, 12, 1, 5, 9, 13,..., 3, 7, 11, 15 are written. The one-dimensional DCT coefficient is repeatedly controlled by the writing control unit 41 so that 64 coefficients are alternately written in the data storage positions in FIGS. 4 and 5.

  6 and 7 are diagrams showing the address order and the one-dimensional DCT coefficients that are read when the one-dimensional DCT coefficients are read from the dual port RAMs 3a and 3b according to the read control unit 42. FIG.

  FIG. 6 shows the order of read addresses and the one-dimensional DCT coefficients to be read when the one-dimensional DCT coefficients K0 to K63 of the first 8 × 8 pixel block are written in the dual port RAMs 3a and 3b as shown in FIG. FIG. From the read control unit 42, address numbers 0, 4, 8, 12, 16, 20, 24, 28,..., 3, 7, 11, 15, 19, 23, 27, 31 as read addresses RAA of the dual port RAM 3a. Are sequentially supplied, and the one-dimensional DCT coefficients K0, K16, K32, K48, K9, K25, K41, K57,..., K6, K22, K38, K54, K15, K31, K47, and K63 are sequentially read out. Further, address numbers 16, 20, 24, 28, 0, 4, 8, 12,..., 19, 23, 27, 31, 3, 7, 11, 15 are sequentially supplied as the read address RAB of the dual port RAM 3b. The one-dimensional DCT coefficients K8, K24, K40, K56, K1, K17, K33, K49,..., K14, K30, K46, K62, K7, K23, K39, K55 are sequentially read out. The high-order coefficient and low-order coefficient of these one-dimensional DCT coefficients simultaneously read out from the dual port RAMs 3a and 3b at a frequency of once every two clock cycles are replaced by the read data selection circuit 423, and the high-order coefficient DCTO1 is K0, K16, K32, K48, K1, K17, K33, K49,..., K6, K22, K38, K54, K7, K23, K39, K55 are sequentially output, and the lower coefficients DCTO0 are K8, K24, K40, K56. , K9, K25, K41, K57,..., K14, K30, K46, K62, K15, K31, K47, K63 are sequentially output.

  FIG. 7 shows the order of read addresses and the one-dimensional read out when the one-dimensional DCT coefficients K′0 to K′63 of the next 8 × 8 pixel block are written in the dual port RAMs 3a and 3b as shown in FIG. It is a figure which shows a DCT coefficient. From the read control unit 42, address numbers 0, 1, 2, 3, 16, 17, 18, 19,..., 12, 13, 14, 15, 28, 29, 30, 31 are used as the read address RAA of the dual port RAM 3a. Are sequentially supplied, and the one-dimensional DCT coefficients K0, K16, K32, K48, K9, K25, K41, K57,..., K6, K22, K38, K54, K15, K31, K47, and K63 are sequentially read out. Further, address numbers 0, 1, 2, 3, 16, 17, 18, 19,..., 12, 13, 14, 15, 28, 29, 30, 31 are sequentially supplied as read addresses RAB of the dual port RAM 3b. The one-dimensional DCT coefficients K8, K24, K40, K56, K1, K17, K33, K49,..., K14, K30, K46, K62, K7, K23, K39, K55 are sequentially read out. The high-order coefficient and low-order coefficient of these one-dimensional DCT coefficients simultaneously read out from the dual port RAMs 3a and 3b at a frequency of once every two clock cycles are replaced by the read data selection circuit 423, and the high-order coefficient DCTO1 is K0, K16, K32, K48, K1, K17, K33, K49,..., K6, K22, K38, K54, K7, K23, K39, K55 are sequentially output, and the lower coefficients DCTO0 are K8, K24, K40, K56. , K9, K25, K41, K57,..., K14, K30, K46, K62, K15, K31, K47, K63 are sequentially output. By reading the one-dimensional DCT coefficient by alternately switching the reading addresses in FIGS. 6 and 7 every 64 coefficients by the reading control unit 42, the transposition of the row position and the column position of the one-dimensional DCT coefficient is repeatedly performed. Two coefficients are sequentially supplied to the subsequent one-dimensional DCT conversion circuit 5 at a frequency of once every two clock cycles.

  FIG. 8 is a diagram showing the write timing of the dual port RAMs 3a and 3b controlled by the write control unit 41. As shown in FIG. The upper coefficient DCTI1 and the lower coefficient DCTI0 are sequentially input to the write control unit 41 at the same timing from the preceding one-dimensional DCT conversion circuit 2 at a frequency of once every two clock cycles, and the write address generation unit 412 When the write permission WENB supplied from the write permission generation unit 414 has a logical value “0” at a frequency of once in a clock cycle, the designated address, that is, the write address WAA of the dual port RAMs 3a and 3b is synchronized with the clock. , WAB are sequentially written.

  That is, T is the clock period of the system clock SCLK, Td is the delay time from the system clock SCLK of the higher coefficient DCTI1 and lower coefficient DCTI0 output from the one-dimensional DCT conversion circuit 2 in the previous stage, and the system is a dual port RAM timing specification. Assuming that the setup time and hold time of the write data with respect to the clock SCLK are Tsu (RAM) and Th (RAM), the conditions of (Expression-5) and (Expression-6) As long as you are satisfied.

2T−Td> Tsu (RAM) (Formula-5)
Td> Th (RAM) (Formula-6)
As is clear from (Expression-5) and (Expression-6), the timing margin for the memory setup time of the write operation is higher than that of (Expression-1) and (Expression-2) that define the conventional conditions. It increases by T for one clock cycle.

  FIG. 9 is a diagram showing the read timing from the dual port RAMs 3a and 3b controlled by the read control unit 42. As shown in FIG. The read address generator 422 reads the specified address, that is, the data (one-dimensional DCT coefficients) stored in the read addresses RAA and RAB of the dual port RAMs 3a and 3b at a frequency of once every two clock cycles. When the read permission RENB supplied from 424 is a logical value “0”, the read permission RENB is sequentially read in synchronization with the clock, and is output by the read data selection circuit 423 as an upper coefficient DCTO1 and a lower coefficient DCTO0. In order for the subsequent one-dimensional DCT conversion circuit 5 to accurately receive the output data, the access time of the dual port RAMs 3a and 3b is set to Tpd, the delay time by the read data selection circuit 423 is set to Tdm, and the subsequent one-dimensional DCT conversion is performed. If the setup time and hold time, which are the input timing specifications of the circuit 5, are Tsu (FF) and Th (FF), the conditions of (Expression-7) and (Expression-8) may be satisfied.

2T− (Tpd + Tdm)> Tsu (FF) (Formula-7)
Tpd + Tdm> Th (FF) (Formula-8)
That is, the access time Tpd required for the dual port RAMs 3a and 3b is increased by (T-Tdm) as compared with the conventional conditions (Expression-3) and (Expression-4). Note that the delay time Tdm by the read data selection circuit 423 is the delay time of only the data selector for selecting one data from two read data from the dual port RAMs 3a and 3b, and the access time of the dual port RAMs 3a and 3b. Compared to Tpd, it is very small, and as a whole, it is possible to suppress the influence on the circuit operable frequency due to an increase in memory access time.

  The above is a specific description of the case where the two-dimensional discrete cosine transform device is configured using two 32-word dual-port RAMs in the memory space 3, but the memory space 3 uses four 16-word dual-port RAMs. Alternatively, it may be configured using eight 8-word dual port RAMs.

  FIG. 10 is a block diagram of an example in which the memory space is configured using four 16-word dual port RAMs. The main difference from FIG. 1 is that the memory space 3 is composed of four dual-port RAMs 3a, 3b, 3c, and 3d.

  When the signal WDLAT supplied from the write counter 411 is a logical value “0”, the one-dimensional DCT conversion circuit 2 in the preceding stage synchronizes with the system clock SCLK and accelerates the one-dimensional DCT coefficients (K0 to K63) in the column order. From the other DCT coefficient, DCTI3, DCTI2, DCTI1, and DCTI0 are sequentially output in parallel by four coefficients. As will be described later, the signal WDLAT supplied from the write counter 411 is a signal that becomes a logical value “0” for only one cycle in four cycles of the system clock SCLK. Specifically, DCTI3 to DCTI0 are four clocks in response to the signal WDLAT. It is controlled so that it is sequentially output at a frequency of once per cycle.

The dual port RAMs 3a to 3d are different from those in FIG. 1 in that four dual port RAMs having a data storage area of 16 words are used.
The write control unit 41 has the same configuration as that shown in FIG. 1 except that the write counter 411 gives an inverted signal (NAND) of the logical product of WCNT1 and WCNT0 to the one-dimensional DCT conversion circuit 2 in the previous stage. Is supplied as WDLAT, and control is performed so that the one-dimensional DCT coefficients DCTI3 to DCTI0 are supplied at a frequency of once every four clock cycles.

  The relationship between the write addresses WAA, WAB, WAC, WAD in the write address generator 412 and the outputs WCNT6 to WCNT2 of the write counter 411 is as shown in FIG.

  The write data selection circuit 413 inputs 2 bits of the count outputs WCNT4 and WCNT3 of the write counter 411 as data selection signals WDSEL1 and WDSEL0, and the data selection signals WDSEL1 and WDSEL0 are both logical values “0”, that is, 1 and 5 rows. In the case of the eye coefficient, DCTI3 is set as WDA, DCTI2 is set as WDB, DCTI1 is set as WDC, and DCTI0 is supplied as WDD. When the data selection signal WDSEL1 is a logical value “0” and WDSEL0 is a logical value “1”, that is, the coefficients in the 2nd and 6th rows, DCTI2 is WDA, DCTI3 is WDB, DCTI0 is WDC, and DCTI1 is WDD. Supply. When the data selection signal WDSEL1 is a logical value “1” and WDSEL0 is a logical value “0”, that is, the coefficients in the third and fourth rows, DCTI1 is WDA, DCTI0 is WDB, DCTI3 is WDC, and DCTI2 is WDD. Supply. When the data selection signals WDSEL1 and WDSEL0 are both logical values ‘1’, that is, the coefficients in the fourth and eighth rows, DCTI0 is set to WDA, DCTI1 is set to WDB, DCTI2 is set to WDC, and DCTI3 is supplied as WDD.

  The write permission generation unit 414 calculates the logical sum (OR) of the write start signal WSTART supplied from the outside, the inverted signal of WCNT1 of the write counter 411, and the inverted signal of WCNT0, and the write permission signal of the dual port RAMs 3a to 3d. Supplying as WENB, the write operation is reduced to a frequency of once every four clock cycles.

  The read control unit 42 has the same configuration as that shown in FIG. 1 except that the read counter 421 sends an inverted signal (NAND) of the logical product of RCNT1 and RCNT0 to the subsequent one-dimensional DCT conversion circuit 5. A signal obtained by delaying RCNT4 by 4 clock cycles is supplied as RDSEL1 and a signal obtained by delaying RCNT3 by 4 clock cycles is supplied as RDSEL0 to the read data selection circuit 423 by the dual port RAM 3a. Control is performed so that data can be exchanged in accordance with the output timing of read data from ˜3d.

  The relationship between the read addresses RAA, RAB, RAC, RAD and the outputs RCNT6 to RCNT2 of the read counter 421 in the read address generator 422 is as shown in FIG.

  The read data selection circuit 423 receives the RDSEL1 and RDSEL0 supplied from the read counter 421 as inputs, and combines the four one-dimensional DCT coefficients RDA to RDD read from the dual port RAMs 3a to 3d by the combination of the logical values. The data is exchanged according to the line position and output to DCTO3 to DCTO0. That is, the coefficients in the first and fifth lines for the DCTO3 output, the coefficients in the second and sixth lines for the DCTO2 output, the coefficients in the third and seventh lines for the DCTO1 output, and the fourth and eighth lines for the DCTO0 output. The read data is exchanged so that the coefficients are repeatedly output.

  The read permission generation unit 424 supplies the logical sum (OR) of the read start signal RSTART, the inverted signal of RCNT1 output from the read counter 421, and the inverted signal of RCNT0 as the read permission signal RENB of the dual port RAMs 3a to 3b. The read operation is reduced to a frequency of once every four clock cycles.

  The subsequent one-dimensional DCT conversion circuit 5 receives the signal RDLAT supplied from the read counter 421, receives the one-dimensional DCT coefficients DCTO3 to DCTO0 at the same timing once every four clock cycles, and takes four clock cycles. Shifting at a frequency of one time, vertical one-dimensional DCT conversion is performed every eight coefficients, and two-dimensional DCT coefficients KK0 to KK63 are sequentially output as DCTOUT in synchronization with the system clock SCLK.

  13 and 14 are diagrams showing data storage positions where the one-dimensional DCT coefficients are written in the dual port RAMs 3a to 3d in accordance with the write control unit 41. FIG. That is, FIG. 13 is a diagram showing data storage positions at which the one-dimensional DCT coefficients K0 to K63 of the first 8 × 8 pixel block are written in the dual port RAMs 3a to 3d, and FIG. 14 shows the next 8 × 8 pixel. It is a figure which shows the data storage position where the one-dimensional DCT coefficient K0-K63 of a block is written in dual port RAM3a-3d. The one-dimensional DCT coefficients are repeatedly controlled by the write control unit 41 so that 64 coefficients are alternately written in the data storage positions in FIGS. 13 and 14. Coefficient writing is repeated at a frequency of once every four clock cycles.

  FIGS. 15 and 16 are diagrams illustrating the address order and the one-dimensional DCT coefficients to be read when the one-dimensional DCT coefficients are read from the dual port RAMs 3a to 3d in accordance with the read control unit 42. FIG. In other words, FIG. 15 is a diagram showing the read address order of the one-dimensional DCT coefficients K0 to K63 of the first 8 × 8 pixel block and the one-dimensional DCT coefficients to be read. FIG. 16 is a diagram illustrating the read address order of the one-dimensional DCT coefficients K0 to K63 of the next 8 × 8 pixel block and the one-dimensional DCT coefficients to be read.

  The reading control unit 42 reads the one-dimensional DCT coefficient by alternately switching the reading addresses in FIGS. 15 and 16 every 64 coefficients, thereby repeatedly transposing the row position and the column position of the one-dimensional DCT coefficient. 4 coefficients are sequentially supplied to the subsequent one-dimensional DCT conversion circuit 5 at a frequency of once every four clock cycles.

  FIG. 17 is a diagram illustrating the write timing of the dual port RAMs 3a to 3d controlled by the write control unit 41. The conditions required in the write operation are (Equation-9) and (Equation-10), and the timing margin with respect to the memory setup time is increased by 3T of the system clock SCLK as compared with the conventional case.

4T-Td> Tsu (RAM) (Formula-9)
Td> Th (RAM) (Formula-10)
FIG. 18 is a diagram illustrating the read timing from the dual port RAMs 3a to 3d controlled by the read control unit 42. The conditions required in the read operation are (Expression-11) and (Expression-12), and the access time Tpd required for the dual port RAMs 3a to 3d is only (3T-Tdm) as compared with the conventional case. To increase.

4T− (Tpd + Tdm)> Tsu (FF) (Formula-11)
Tpd + Tdm> Th (FF) (Formula-12)
FIG. 19 is a block diagram of an example in which the memory space 3 is configured using eight 8-word dual port RAMs. The main difference from FIG. 1 is that the memory space 3 is composed of eight dual port RAMs 3a to 3h. In this case, the one-dimensional DCT coefficients (K0 to K63) are generated from the preceding one-dimensional DCT conversion circuit 2 at a frequency of once every eight clock cycles, and eight coefficients are assigned as DCTI7 to DCTI0 from the earlier DCT coefficient in the column order. The signals are sequentially output in parallel, and are sequentially written into the eight dual port RAMs 3a to 3h under the control of the write control unit 41. The addresses to be written are as shown in FIG. 20, and the write timing is controlled by the write permission generation unit 414 so that the write timing is performed once every eight clock cycles.

  The reading of the dual port RAMs 3a to 3h is controlled by the reading control unit 42. The reading address is as shown in FIG. 21, and the reading timing is set by the reading permission generating unit 424 so as to be performed once every eight clock cycles. Be controlled.

  22 and 23 are diagrams showing data storage positions where the one-dimensional DCT coefficients are written in the dual port RAMs 3a to 3h in accordance with the write control unit 41. FIG. FIG. 22 is a diagram showing data storage positions where the one-dimensional DCT coefficients K0 to K63 of the first 8 × 8 pixel block are written in the dual port RAMs 3a to 3h, and FIG. 23 shows the next 8 × 8 pixel block. It is a figure which shows the data storage position where the one-dimensional DCT coefficient K0-K63 is written in dual port RAM3a-3h. The one-dimensional DCT coefficients are repeatedly controlled by the write control unit 41 so that 64 coefficients are written alternately at the data storage positions in FIGS. Coefficient writing is all repeated at a frequency of once every 8 clock cycles.

  24 and 25 are diagrams showing the address order and the one-dimensional DCT coefficients to be read when the one-dimensional DCT coefficients are read from the dual port RAMs 3a to 3d in accordance with the read control unit 42. FIG. FIG. 24 is a diagram illustrating the read address order of the one-dimensional DCT coefficients K0 to K63 of the first 8 × 8 pixel block and the one-dimensional DCT coefficients to be read. FIG. 25 is a diagram illustrating the read address order of the one-dimensional DCT coefficients K0 to K63 of the next 8 × 8 pixel block and the one-dimensional DCT coefficients to be read.

  The reading control unit 42 reads the one-dimensional DCT coefficients by alternately switching the reading addresses shown in FIGS. 24 and 25 every 64 coefficients, thereby repeatedly transposing the row position and the column position of the one-dimensional DCT coefficient. The 8 coefficients are sequentially supplied to the subsequent one-dimensional DCT conversion circuit 5 at a frequency of once every 8 clock cycles.

  FIG. 26 is a diagram illustrating the write timing of the dual port RAMs 3a to 3h controlled by the write control unit 41. The conditions required in the write operation are (Equation-13) and (Equation-14), and the timing margin for the memory setup time is increased by 7T of the system clock SCLK as compared with the conventional case.

8T−Td> Tsu (RAM) (Formula-13)
Td> Th (RAM) (Formula-14)
FIG. 27 is a diagram illustrating the read timing from the dual port RAMs 3a to 3h controlled by the read control unit 42. The conditions required for the read operation are (Expression-15) and (Expression-16), and the access time Tpd required for the dual port RAMs 3a to 3h is increased by (7T-Tdm) compared to the conventional case. To do.

8T− (Tpd + Tdm)> Tsu (FF) (Formula-15)
Tpd + Tdm> Th (FF) (Formula-16)
(Second Embodiment)
FIG. 28 is a block diagram of a two-dimensional discrete cosine transform apparatus according to the second embodiment of the present invention. The two-dimensional discrete cosine transform device 1 shown in the first embodiment described above performs writing control and reading control of two dual-port RAMs individually at the same timing for each of the two coefficients. The two-dimensional discrete cosine transform device 201 has the same writing position (address) and reading position (address) in the memory space of the coefficients as in the first embodiment, but writing control of two dual-port RAMs. The difference is that the readout control is performed individually for each coefficient at different timings. The first embodiment improves the timing margin on the circuit in writing to the memory and reading from the memory, and realizes low power consumption. The second embodiment, The main object is to improve only the read timing margin of the memory and reduce the power consumption.

  As shown in the figure, the two-dimensional discrete cosine transform device 201 includes a preceding one-dimensional DCT transform circuit 202, a memory space 3, a transposition control unit 204, and a succeeding one-dimensional DCT transform circuit 205.

  The preceding one-dimensional DCT conversion circuit 202 receives pixel data PXLD for eight pixels in the horizontal direction of an image divided into 8 × 8 pixel blocks, one pixel at a time in synchronization with the system clock SCLK. When DCT conversion is performed and the signal WDCHG supplied from the write counter 2411 is a logical value '0', that is, for odd row coefficients, odd columns and even columns such as D0, D1, D2,. Sequentially output in synchronization with the system clock SCLK, and when WDCHG is a logical value '1', that is, for even row coefficients, even columns, odd columns such as D9, D8, D11, D10..., D15, D14 In this order, control is performed so that one coefficient is output to the DCTI in synchronization with the system clock SCLK. The signal WDCHG is supplied from the write counter 2411. Specifically, the signal WDCHG is the same as the counter output WCNT3 obtained by dividing the system clock SCLK by 16.

The dual port RAMs 3a and 3b are exactly the same as those in FIG.
The write control unit 241 includes a write counter 2411, a write address generation unit 412, and a write permission generation unit 2414.

  The write counter 2411 is composed of a 7-bit binary counter as in FIG. 1, and the logical value is the same timing at which the first coefficient K0 output from the preceding one-dimensional DCT conversion circuit 202 is output. Control is performed to count up by a signal WSTART which becomes '0'. In addition, the signal WCNT3 is supplied as the signal WDCHG to the one-dimensional DCT conversion circuit 202 in the previous stage so that the write data (coefficient) can be identified as an odd row coefficient or an even row coefficient. The write address generator 412 has the same configuration as that shown in FIG. 1, and generates a coefficient write address as shown in FIG.

  The write permission generation unit 2414 performs a logical sum (OR) of the write start signal WSTART supplied from the outside and the least significant bit WCNT0 of the write counter 2411 so as to individually control writing to the dual port RAMs 3a and 3b at different timings. ) Is supplied as the write enable signal WENBA of the dual port RAM 3a, and the logical sum (OR) of the signal WSTART and the inverted signal of the least significant bit WCNT0 of the write counter 2411 is supplied as the write enable signal WENBB of the dual port RAM 3b. To do.

  FIG. 29 is a diagram showing the write timing in the dual port RAMs 3a and 3b. As shown in the figure, the dual port RAMs 3a and 3b are controlled to be written at different timings.

  In FIG. 28, the read control unit 242 includes a read counter 2421, a read address generation unit 422, a read permission generation unit 2424, and a read data output control unit 2425.

  The read counter 2421 is composed of a 7-bit binary counter as in FIG. 1, and in the present embodiment, the coefficient read from the dual port RAMs 3a and 3b is an odd row coefficient or an even row coefficient. A signal obtained by delaying the counter output RCNT3 by two clock cycles is supplied to the subsequent one-dimensional DCT conversion circuit 205 as RDCHG so that the coefficient can be identified.

The read address generator 422 has the same configuration as that shown in FIG. 1, and generates a coefficient read address as shown in FIG.
The read permission generation unit 2424 can control the read from the dual port RAMs 3a and 3b at different timings, and can latch the read data RDA and RDB at different timings with respect to the read data output control unit 2425. The signal RENBA and the signal RENBB are supplied to the dual port RAMs 3a and 3b. The signal RENBA is a logical sum (OR) signal of the read start signal RSTART supplied from outside and the least significant bit RCNT0 of the read counter 2421. The signal RENBB is the least significant bit RCNT0 of the signal RSTART and the read counter 2421. Is an OR signal with the inverted signal.

  The read data output control unit 2425 receives the read data RDA and RDB read from the dual port RAMs 3a and 3b at different timings as input, and in accordance with the signals RENBA and RENBB supplied from the read permission generation unit 2424, the read data output control unit 2425 takes one coefficient at a time. Split processing.

  FIG. 30 is a diagram showing the read timing from the dual port RAMs 3a and 3b. The read data RDA and RDB read at different timings according to the signals RENBA and RENBB are latched at the rising edge of the system clock SCLK when the signal RENBA supplied from the read permission generation unit 2424 is the logical value “0”. When the signal RENBB is a logical value “0”, the data RDB is latched and becomes RDBLT. That is, the timing at which the read data RDA and RDB are latched is always two clocks after the read timing. In order to accurately latch the data RDA and RDB, the access time of the dual port RAMs 3a and 3b is set to Tpd. Assuming that the input setup time and hold time of the flip-flop to be latched are Tsu (FF) and Th (FF), it is sufficient that the conditions of (Expression-17) and (Expression-18) are satisfied. That is, the access time Tpd required for the dual port RAMs 3a and 3b is increased by T as compared with the conventional conditions (Expression-3) and (Expression-4).

2T−Tpd> Tsu (FF) (Formula-17)
Tpd> Th (FF) (Formula-18)
Thereafter, RDALT is selected when the signal RENBA has a logical value “0”, and RDBLT is selected when the signal RENBB has a logical value “0”, and is controlled to be repeatedly output as DCTO.

  In the subsequent one-dimensional DCT conversion circuit 205, the signal DCTO supplied one coefficient at a time from the read data control unit 2425 is input, and the row position of the coefficient is identified according to the signal RDCHG supplied from the read counter 2421. The signal RDCHG is a signal obtained by dividing the system clock SCLK by 16, and is a signal obtained by delaying the signal RCNT3 by two clock cycles in order to match the output timing of read data. That is, when the logical value of the signal RDCHG is ‘0’, it represents an odd row coefficient, and when the logical value is ‘1’, it represents an even row coefficient. The subsequent one-dimensional DCT conversion circuit 205 identifies the row position of the coefficient DCTO by this signal RDCHG, performs one-dimensional DCT conversion in the vertical direction for every eight coefficients, and uses the two-dimensional DCT coefficients KK0 to KK63 as the system clock SCLK. Synchronously output as DCTOUT sequentially.

  As described above, in the case of the present embodiment, a high-speed discrete cosine transform device can be realized even when a low-speed RAM having a relatively large read access time is used. In the second embodiment, the case where the memory space 3 is configured by two 32-word dual-port RAMs has been described. However, as in the case of the first embodiment, the memory space 3 is a 16-word dual-port RAM. It may be composed of four port RAMs or may be composed of eight 8-port dual port RAMs.

  The condition in the read operation when a 16-word dual port RAM is used is as shown in (Equation-19), and the access time Tpd required for the memory is increased by 3T compared to the conventional case. Also, the condition in the read operation when using an 8-word dual port RAM is as shown in (Equation -20), and the access time Tpd required for the memory is increased by 7T compared to the conventional case.

2T−Tpd> Tsu (FF) (Formula-19)
8T-Tpd> Tsu (FF) (Formula-20)

1 is a block diagram of a two-dimensional discrete cosine transform device according to a first embodiment of the present invention. The figure which shows the write address of two dual port RAM in the write address generation part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read address of two dual port RAM in the read address generation part with which the same two-dimensional discrete cosine transformation apparatus is equipped. The figure which shows the data storage position at the time of writing the first 64 one-dimensional DCT coefficient data in two dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the data storage position at the time of writing the following 64 one-dimensional DCT coefficient data in two dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read address order at the time of reading the first 64 one-dimensional DCT coefficient data from two dual port RAMs, and the one-dimensional DCT coefficient read out in the read control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the order of the read address at the time of reading the next 64 one-dimensional DCT coefficient data from two dual port RAMs, and the one-dimensional DCT coefficient read out in the read control part with which the same two-dimensional discrete cosine transform device is equipped. The figure which shows the write timing at the time of writing one-dimensional DCT coefficient data in two dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read-out timing at the time of reading 1-dimensional DCT coefficient data from two dual port RAMs in the read-out control part with which the same 2-dimensional discrete cosine transform apparatus is equipped. Block diagram of another two-dimensional discrete cosine transform device shown as the first embodiment of the present invention The figure which shows the write address of four dual port RAM in the write address generation part with which the same two-dimensional discrete cosine transformation apparatus is equipped. The figure which shows the read address of four dual port RAMs in the read address generation part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the data storage position at the time of writing the first 64 one-dimensional DCT coefficient data in four dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the data storage position at the time of writing the next 64 one-dimensional DCT coefficient data in four dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read address order at the time of reading the first 64 one-dimensional DCT coefficient data from four dual port RAMs, and the one-dimensional DCT coefficient read out in the read control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read address order at the time of reading the next 64 one-dimensional DCT coefficient data from four dual port RAM, and the one-dimensional DCT coefficient read in the read control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the write timing at the time of writing one-dimensional DCT coefficient data in four dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read-out timing at the time of reading 1-dimensional DCT coefficient data from four dual port RAMs in the read-out control part with which the same 2-dimensional discrete cosine transform apparatus is equipped. Block diagram of still another two-dimensional discrete cosine transform device shown as the first exemplary embodiment of the present invention The figure which shows the write address of eight dual port RAMs in the write address generation part with which the two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read address of eight dual port RAM in the read address generation part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the data storage position at the time of writing the first 64 one-dimensional DCT coefficient data in eight dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the data storage position at the time of writing the next 64 one-dimensional DCT coefficient data in eight dual port RAM in the writing control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read address order at the time of reading the first 64 one-dimensional DCT coefficient data from eight dual port RAMs, and the one-dimensional DCT coefficient read in the read control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read address order at the time of reading the next 64 one-dimensional DCT coefficient data from eight dual port RAM, and the read one-dimensional DCT coefficient in the read control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the write timing at the time of writing one-dimensional DCT coefficient data in eight dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read-out timing at the time of reading 1-dimensional DCT coefficient data from eight dual port RAM in the read-out control part with which the same 2-dimensional discrete cosine transform apparatus is equipped. Block diagram of a two-dimensional discrete cosine transform device according to a second embodiment of the present invention The figure which shows the write timing at the time of writing one-dimensional DCT coefficient data in two dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read-out timing at the time of reading 1-dimensional DCT coefficient data from two dual port RAMs in the read-out control part with which the same 2-dimensional discrete cosine transform apparatus is equipped. Block diagram of a conventional two-dimensional discrete cosine transform device The figure which shows the order of writing at the time of writing the first 64 one-dimensional DCT coefficient data in dual port RAM in the writing control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the reading order at the time of reading the first 64 one-dimensional DCT coefficient data from dual port RAM in the read-out control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the order of writing at the time of writing the next 64 one-dimensional DCT coefficient data in dual port RAM in the write control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the reading order at the time of reading the next 64 one-dimensional DCT coefficient data from dual port RAM in the read control part with which the same two-dimensional discrete cosine transform apparatus is equipped. The figure which shows the write-in timing at the time of writing 1-dimensional DCT coefficient data in dual port RAM in the write-control part with which the same 2-dimensional discrete cosine transform apparatus is equipped. The figure which shows the read-out timing at the time of reading 1-dimensional DCT coefficient data from dual port RAM in the read-out control part with which the same 2-dimensional discrete cosine transform apparatus is equipped.

Explanation of symbols

1 2D Discrete Cosine Transformer 2, 5 1D DCT Converter 3 Memory Space 3a, 3b Dual Port RAM
4 transposition control unit 41 write control unit 42 read control unit 413 write data selection circuit 414 write permission generation unit 421 read data selection circuit 424 read permission generation unit

Claims (3)

a discrete cosine transform circuit in the preceding stage that performs one-dimensional discrete cosine transform in the horizontal direction for each m pixels or n pixels in block units of pixels of m columns × n rows, where m and n are integers (m = n or m ≠ n) , A memory space temporarily storing m × n one-dimensional discrete cosine coefficients supplied from the discrete cosine transform circuit, and transposing the row position and the column position of the memory space, the one-dimensional discrete cosine coefficient A transposition control unit that controls writing and reading; and a discrete cosine transform circuit at a subsequent stage that performs one-dimensional discrete cosine transform in the vertical direction for each of the m coefficient or n coefficient with the discrete cosine coefficient output from the memory space as an input. A discrete cosine transform apparatus comprising: N (m × n) / N word dual-port RAMs, where N is an integer, and the transposition control A write control unit that repeatedly and individually controls the write operation of the N dual-port RAMs once every N clock cycles, and a read that individually controls the read operation repeatedly and once every N clock cycles. A discrete cosine transform device characterized by comprising a control unit. The previous stage discrete cosine transform circuit is configured to perform one-dimensional discrete cosine transform for every m or n pixels in the horizontal direction and sequentially output in parallel as a one-dimensional discrete cosine coefficient group by N coefficients every N clock cycles. ,
The writing control unit sequentially converts the one-dimensional discrete cosine coefficient groups sequentially supplied from the preceding stage discrete cosine transform circuit to dual port RAMs having different coefficients in the same column in units of m × N or n × N coefficients. In addition to controlling the writing to each dual port RAM, in the case of the first m × n one-dimensional discrete cosine coefficients, the addresses are set so that the discrete cosine coefficients sequentially written to arbitrary addresses are not overwritten. , And write control is performed at the same timing once every N clock cycles, and in the case of the next m × n one-dimensional discrete cosine coefficients, the first m × n one-dimensional discrete cosine coefficients The address is individually specified so that is sequentially overwritten in the column direction, and the one-dimensional discrete cosine is applied once every N clock cycles. The number is controlled to be written at the same timing, and thereafter, the above two writing controls are repeatedly performed alternately.
The read control unit is configured to obtain addresses which can simultaneously read N one-dimensional discrete cosine coefficients written in N dual-port RAMs by the write control unit in the column direction of m × n pixels in the column direction. For each one-dimensional discrete cosine coefficient that is repeatedly and individually supplied to the port RAM and read out at the same timing once every N clock cycles, the coefficients of the coefficients in the column direction of the block unit of m × n pixels. 1-dimensional discrete cosine coefficient group composed of the replaced N coefficients is latched at the same timing once every N clock cycles and repeatedly supplied to the subsequent discrete cosine transform circuit. Configured to
The discrete cosine transform circuit at the subsequent stage performs one-dimensional discrete cosine transform for each of the m coefficient or n coefficient, with N discrete cosine coefficient groups output at a frequency of once every N clock cycles from the read control unit as an input. The discrete cosine transform device according to claim 1, which is configured as described above. The discrete cosine transform circuit in the previous stage performs one-dimensional discrete cosine transform for every m pixels or n pixels in the horizontal direction, determines the output order of the coefficients for the obtained one-dimensional discrete cosine transform coefficients according to the row position, and takes one clock cycle. It is configured to sequentially output one coefficient at a time,
The write control unit is a dual port RAM in which the one-dimensional discrete cosine coefficients sequentially supplied one by one from the discrete cosine transform circuit in the preceding stage are different from each other in units of m × N or n × N coefficients in the same column. In the case of the first m × n one-dimensional discrete cosine coefficients, the discrete cosine coefficients sequentially written at arbitrary addresses are not overwritten. The address is individually specified, and writing control is performed at different timings once every N clock cycles. In the case of the next m × n one-dimensional discrete cosine coefficients, the first m × n one-dimensional Specify individual addresses so that discrete cosine coefficients are overwritten sequentially in the column direction, one-dimensional with a frequency of once every N clock cycles It is configured to control writing of discrete cosine coefficients at different timings,
The read control unit reads N-dimensional discrete cosine coefficients written in the N dual-port RAMs by the write control unit in the order of m × n pixel blocks in the column direction, and outputs N addresses. Each of the dual-port RAMs is individually supplied, and the one-dimensional discrete cosine coefficients are read out from the N dual-port RAMs at different timings with a frequency of once every N clock cycles. The cosine coefficient is latched at different timings once every N clock cycles, and one-dimensional discrete cosine coefficients are sequentially time-divisionally output, and the subsequent discrete cosine transform circuit is once per clock cycle. Configured to repeatedly feed to
The discrete cosine transform circuit in the subsequent stage recognizes the one-dimensional discrete cosine coefficient output at a frequency of once per clock cycle by the read control unit, recognizes the row position of the coefficient by its column position, and outputs each m coefficient or n 2. The discrete cosine transform apparatus according to claim 1, wherein the discrete cosine transform apparatus is configured to perform a one-dimensional discrete cosine transform for each coefficient.

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