JP2006127231A - Abnormality detection device for memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the abnormality detection device of a memory control circuit for monitoring data in actually performing communication between a memory control circuit and a nonvolatile memory, and for detecting the communication abnormality of the memory control circuit. <P>SOLUTION: An MPU 1 is provided with a transmission port for transmitting data constituted of a write command, address information and write data being the target of writing in writing data in an EEPROM 2, and for transmitting data constituted of an erase command and address information in erasing the data of the EEPROM 2 and a reception port for receiving information to be transmitted from the EEPROM 2. The data to be transmitted from the transmission port, and to be received by the EEPROM 2 are received, and when the data are not matched with the data transmitted from the transmission port, it is decided that a communicating status to the EEPROM 2 is abnormal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an abnormality detection device for a memory control circuit that detects an abnormality between a nonvolatile memory and a memory control circuit.

  2. Description of the Related Art Conventionally, a device that detects a communication abnormality between a memory control circuit and a nonvolatile memory at the time of data writing to or erasing data from a nonvolatile memory such as an EEPROM is known.

  However, the above-described conventional technique has a problem that even if the data actually transmitted from the memory control circuit to the nonvolatile memory is abnormal, this abnormality cannot be detected.

  Accordingly, the present invention has been proposed in view of the above-described circumstances, and monitors data when communication is actually performed between the memory control circuit and the nonvolatile memory, thereby detecting a communication abnormality in the memory control circuit. An object of the present invention is to provide an abnormality detection device for a memory control circuit that can be detected.

  The present invention relates to an abnormality detection device for detecting an abnormality in a memory control circuit of a nonvolatile memory that controls writing and erasing of data to and from the nonvolatile memory. Transmitting data composed of information and write data to be written and transmitting data transmitted from the non-volatile memory and transmitting means for transmitting transmission data composed of the erase command and address information when erasing the data in the non-volatile memory Receiving means for receiving information, and receiving the transmission data transmitted from the transmission means and received in the nonvolatile memory by the abnormality detection means, and the transmission data and the transmission data transmitted from the transmission means match. If it is determined that the communication status for the non-volatile memory is normal, By determining the communication state is abnormal for Mori, to solve the problems described above.

  According to the abnormality detection device for a memory control circuit according to the present invention, when data transmitted from the transmission means and received by the nonvolatile memory is received, and the data transmitted from the transmission means does not match Since it is determined that the communication state with respect to the non-volatile memory is abnormal, the data when the communication is actually performed between the memory control circuit and the non-volatile memory is monitored to detect an abnormality of the memory control circuit. be able to.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The abnormality detection device for a memory control circuit according to the present invention is applied to a memory system in which an MPU 1 configured as shown in FIGS. 1 and 2, for example, and an EEPROM 2 which is a nonvolatile memory are connected.

  For example, this memory system is mounted on a vehicle that is driven by a diesel engine, and urea water for urea SCR catalyst that decomposes NOx in exhaust gas discharged from the diesel engine vehicle into water and nitrogen. It is connected to a detection circuit (not shown) for detecting the concentration, and the detected value of the urea concentration is inputted by the MPU 1 and is stored and controlled in the EEPROM 2 to realize an exhaust gas purification system. Therefore, this memory system reliably updates the information stored in the EEPROM 2 when the vehicle is powered on, and ensures that various information is reliably stored in the EEPROM 2 even when the vehicle is powered off. Need to hold.

  The MPU 1 is provided with a clock signal port, a reception port (reception unit), and a transmission port (transmission unit). On the other hand, the EEPROM 2 is provided with a clock signal port connected to the clock signal port of the MPU 1, a reception port connected to the transmission port of the MPU 1, and a transmission port connected to the reception port of the MPU 1.

  Such a memory system includes a clock circuit that generates a clock signal in the MPU 1, a clock monitoring circuit that monitors a clock signal state, and the like. This memory system outputs the clock signal generated by the clock circuit in the MPU 1 from the clock signal port to the clock signal port of the EEPROM 2, and the EEPROM 2 performs the data writing operation and the erasing operation at the operating frequency according to this clock signal. Do.

  In addition, in the case where the data writing operation is performed in the EEPROM 2, the memory system transmits commands, address information, and data to be written from the transmission port of the MPU 1 to the EEPROM 2. Thereby, the EEPROM 2 stores the data to be written at the received address in accordance with the command received by the receiving port. Further, this memory system transmits commands and address information to the EEPROM 2 from the transmission port of the MPU 1 when the EEPROM 2 is caused to erase data. Thereby, the EEPROM 2 performs the erasing operation by setting the value corresponding to the received address to “1” in accordance with the command received by the receiving port.

  Further, when the MPU 1 causes the EEPROM 2 to perform a data writing operation or an erasing operation, the data transmitted to the EEPROM 2 is received by the receiving port. Here, the receiving port of the MPU 1 shares the receiving port that receives data from the EEPROM 2 and the receiving port that self-receives data transmitted from the MPU 1.

  In this way, the data transmitted from the MPU 1 can be received by itself because the transmission port of the EEPROM 2 is in a high impedance state during the period when the data transmission from the EEPROM 2 is not performed. It depends on what you can do.

  Then, the MPU 1 compares the transmitted data with the self-received data and determines that the normal processing with the EEPROM 2 is normal if they match, and if they do not match, A communication monitoring circuit (abnormality detection means) that determines that normal processing with the EEPROM 2 is abnormal is provided.

  In such a memory system, as shown in FIG. 3, the MPU 1 starts the communication with the EEPROM 2 as shown in FIG. Step S1), the data is received by the receiving port (step S2).

  Then, the MPU 1 compares the data transmitted in step S1 with the data received in step S2, and determines whether or not they match. If they match, normal processing with the EEPROM 2 is performed. Is determined to be normal, and if they do not match, it is determined that an abnormality has occurred in normal processing with the EEPROM 2.

  As described above, according to the memory system to which the present invention is applied, when the data transmitted from the MPU 1 and received by the EEPROM 2 is received by the MPU 1 and this data and the transmitted data match. When the communication state with respect to the EEPROM 2 is determined to be normal, and when they do not match, it can be determined that the communication state with respect to the EEPROM 2 is abnormal, the MPU1 (memory control circuit) and the EEPROM2 (nonvolatile) The data at the time of communication with the memory) can be monitored to detect an abnormality of the MPU 1.

  Further, according to this memory system, since the reception port for receiving the data transmitted from the EEPROM 2 and the reception port for receiving the data received by the EEPROM 2 are shared, the monitoring circuit for comparing the data is operated. It is possible to detect abnormalities in normal processing only with this.

  The above-described embodiment is an example of the present invention. For this reason, the present invention is not limited to the above-described embodiment, and various modifications can be made depending on the design and the like as long as the technical idea according to the present invention is not deviated from this embodiment. Of course, it is possible to change.

It is a block diagram which shows the structure of the memory system to which this invention is applied. It is a circuit diagram which shows the concrete connection structure of the memory system to which this invention is applied. It is a flowchart which shows the process sequence of the abnormality detection process by the memory system to which this invention is applied.

Explanation of symbols

1 MPU
2 EEPROM

Claims (2)

An abnormality detection device for detecting an abnormality in a memory control circuit of a nonvolatile memory that controls writing and erasing of data with respect to the nonvolatile memory,
At the time of data writing to the nonvolatile memory, transmission data including a write command, address information and write data to be written is transmitted, and at the time of erasing data from the nonvolatile memory, it includes an erase command and address information. A transmission means for transmitting transmission data;
Receiving means for receiving information transmitted from the nonvolatile memory;
When transmission data transmitted from the transmission means and received by the non-volatile memory is received, and the transmission data matches the transmission data transmitted from the transmission means, communication to the non-volatile memory is performed. An abnormality detection device for a memory control circuit, comprising: an abnormality detection unit that determines that the state is normal and determines that the communication state with respect to the nonvolatile memory is abnormal when the states do not match.   2. The receiving port constituting the receiving means and the receiving port of the abnormality detecting means for receiving transmission data transmitted from the transmitting means and received by the nonvolatile memory are shared. An abnormality detection device for a memory control circuit according to claim 1.

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