JP2006126294A - Planar display device - Google Patents

Planar display device Download PDF

Info

Publication number
JP2006126294A
JP2006126294A JP2004311263A JP2004311263A JP2006126294A JP 2006126294 A JP2006126294 A JP 2006126294A JP 2004311263 A JP2004311263 A JP 2004311263A JP 2004311263 A JP2004311263 A JP 2004311263A JP 2006126294 A JP2006126294 A JP 2006126294A
Authority
JP
Japan
Prior art keywords
wiring
display panel
bus
wiring board
line driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004311263A
Other languages
Japanese (ja)
Inventor
Iwane Ichiyama
石根 市山
Kazuaki Igarashi
和明 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Display Central Inc
Original Assignee
Toshiba Matsushita Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Matsushita Display Technology Co Ltd filed Critical Toshiba Matsushita Display Technology Co Ltd
Priority to JP2004311263A priority Critical patent/JP2006126294A/en
Publication of JP2006126294A publication Critical patent/JP2006126294A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To secure a sufficient interval between conductors on a flexible wiring board which is to be integrated with a drive IC. <P>SOLUTION: A planar display device comprises a display panel DP; a wiring substrate section BP whereon a bus wiring BS is formed; drive circuits YD and XD which include a plurality of drive ICs 20, respectively integrated with a plurality of flexible wiring boards 21, each being arranged between the display panel DP and the wiring substrate section BP, and drive the display panel DP; and a controller 5 for controlling the drive circuits YD and XD via the bus wiring BS. Especially, each drive IC 20 is arranged, out of alignment with the center in a direction along the outer periphery of the display panel DP so as to make the wiring pattern of the corresponding flexible wiring board 21 asymmetric. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、複数の駆動ICパッケージが表示パネルの外縁に沿って設けられる平面表示装置に関する。   The present invention relates to a flat display device in which a plurality of driving IC packages are provided along an outer edge of a display panel.

例えば液晶表示装置のような平面表示装置は、コンピュータ、カーナビゲーションシステム、あるいはテレビ受信機等のモニタディスプレイとして広く利用されている。   For example, flat display devices such as liquid crystal display devices are widely used as monitor displays for computers, car navigation systems, television receivers, and the like.

液晶表示装置は、一般に複数の液晶画素のマトリクスアレイを含む液晶表示パネル、およびこの液晶表示パネルを制御する表示制御回路を有する。液晶表示パネルはアレイ基板および対向基板間に液晶層を挟持した構造である。   A liquid crystal display device generally includes a liquid crystal display panel including a matrix array of a plurality of liquid crystal pixels, and a display control circuit that controls the liquid crystal display panel. The liquid crystal display panel has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate.

アレイ基板は略マトリクス状に配置される複数の画素電極、複数の画素電極の行に沿って配置される複数の走査線、複数の画素電極の列に沿って配置される複数の信号線、複数の走査線および複数の信号線の交差位置近傍に配置される複数のスイッチング素子を有する。各スイッチング素子は例えば薄膜トランジスタ(TFT)からなり、対応走査線が駆動されたときに導通して対応信号線の電位を対応画素電極に印加する。対向基板には、アレイ基板に配置された複数の画素電極に対向するように共通電極が設けられる。一対の画素電極および共通電極はこれら電極間に位置する液晶層の一部である画素領域と共に画素を構成し、画素領域において液晶分子配列を画素電極および共通電極間の電界によって制御する。表示制御回路は複数の走査線を駆動する走査線駆動回路、複数の信号線を駆動する信号線駆動回路、並びにこれら走査線駆動回路および信号線駆動回路を制御するコントローラ等を含む。一般に、走査線駆動回路および信号線駆動回路は、表示パネルの外縁に沿って配置される複数の走査線駆動ICおよび信号線駆動ICにより構成される。各駆動ICはフレキシブル配線板と一体化されたテープキャリアパッケージ(TCP)である。   The array substrate has a plurality of pixel electrodes arranged in a substantially matrix, a plurality of scanning lines arranged along a row of the plurality of pixel electrodes, a plurality of signal lines arranged along a column of the plurality of pixel electrodes, and a plurality of And a plurality of switching elements arranged in the vicinity of the intersection positions of the scanning lines and the plurality of signal lines. Each switching element is formed of, for example, a thin film transistor (TFT), and conducts when the corresponding scanning line is driven, and applies the potential of the corresponding signal line to the corresponding pixel electrode. A common electrode is provided on the counter substrate so as to face the plurality of pixel electrodes arranged on the array substrate. The pair of pixel electrodes and the common electrode constitute a pixel together with a pixel region which is a part of the liquid crystal layer located between these electrodes, and the liquid crystal molecule arrangement is controlled by an electric field between the pixel electrode and the common electrode in the pixel region. The display control circuit includes a scanning line driving circuit that drives a plurality of scanning lines, a signal line driving circuit that drives a plurality of signal lines, and a controller that controls the scanning line driving circuit and the signal line driving circuit. In general, the scanning line driving circuit and the signal line driving circuit are configured by a plurality of scanning line driving ICs and signal line driving ICs arranged along the outer edge of the display panel. Each drive IC is a tape carrier package (TCP) integrated with a flexible wiring board.

液晶表示装置が主に動画を表示するテレビ受信機用である場合、液晶分子が良好な応答性を示すOCBモードの液晶表示パネルを用いることが検討されている(特許文献1を参照)。この液晶表示パネルでは、液晶が画素電極および共通電極上で互いに平行にラビングされた配向膜によって電源投入前においてほとんど寝ているスプレー配向になる。液晶表示パネルは、電源投入に伴う初期化処理で印加する比較的強い電界によりこれら液晶をスプレー配向からベンド配向に転移させてから表示動作を行う。   In the case where the liquid crystal display device is mainly used for a television receiver that displays a moving image, use of an OCB mode liquid crystal display panel in which liquid crystal molecules exhibit good response has been studied (see Patent Document 1). In this liquid crystal display panel, the liquid crystal is in a spray orientation almost lying down before power-on by an alignment film rubbed in parallel with each other on the pixel electrode and the common electrode. The liquid crystal display panel performs a display operation after the liquid crystal is changed from the spray alignment to the bend alignment by a relatively strong electric field applied in the initialization process when the power is turned on.

また、テレビ受信機用の液晶表示装置の場合、上述の応答性だけでなく、高精細で高アスペクト比であることが表示パネルに求められている。このため、信号線数が著しく増大する傾向にある。信号線駆動IC数はこの信号線数の増大に伴って増大することから、バス配線を形成したバス配線基板および表示パネル間に複数のテープキャリアパッケージを配置し、バス配線基板から独立なコントローラ基板上に配置されるコントローラからバス配線を介して信号線駆動ICを共通に制御することが考えられる。この場合、コントローラ基板をバス配線基板よりも小型化して製造コストを低減することが可能となる。
特開2002−202491号公報
In the case of a liquid crystal display device for a television receiver, the display panel is required to have not only the responsiveness described above but also high definition and a high aspect ratio. For this reason, the number of signal lines tends to increase significantly. Since the number of signal line driving ICs increases as the number of signal lines increases, a plurality of tape carrier packages are arranged between the bus wiring board on which the bus wiring is formed and the display panel, and the controller board is independent from the bus wiring board. It is conceivable to commonly control the signal line driver ICs from the controller arranged above via the bus wiring. In this case, the manufacturing cost can be reduced by making the controller board smaller than the bus wiring board.
JP 2002-202491 A

ところで、上述のバス配線基板のバス配線は信号線駆動回路用制御バスに加えて走査線駆動回路用制御バスや電源バスを含み、走査線駆動回路用制御信号や電源電圧が信号線駆動回路として表示パネルの外縁に沿って配置された複数のテープキャリアパッケージのうちで最外郭に位置するものを介して表示パネル側に供給される。   By the way, the bus wiring of the above-mentioned bus wiring board includes a scanning line driving circuit control bus and a power supply bus in addition to the signal line driving circuit control bus, and the scanning line driving circuit control signal and power supply voltage are used as the signal line driving circuit. The plurality of tape carrier packages arranged along the outer edge of the display panel are supplied to the display panel side through the one located at the outermost contour.

従来のテープキャリアパッケージは、図5に示すように信号線駆動ICをフレキシブル配線板の中央に配置した構造を有する。フレキシブル配線板は走査線駆動回路用制御バスや電源バスを表示パネルに引き込むためのブリッジ配線を含み、このブリッジ配線は信号線駆動ICの両側に冗長的に形成されている。走査線駆動回路は表示パネル内に形成される配線および信号線駆動ICの両側に形成されるブリッジ配線の一方を介してバス配線基板上の走査線駆動回路用制御バスに接続される。   A conventional tape carrier package has a structure in which a signal line driving IC is arranged at the center of a flexible wiring board as shown in FIG. The flexible wiring board includes a bridge wiring for drawing a control bus for the scanning line driving circuit and a power supply bus into the display panel, and the bridge wiring is formed redundantly on both sides of the signal line driving IC. The scanning line driving circuit is connected to the scanning line driving circuit control bus on the bus wiring substrate via one of wiring formed in the display panel and bridge wiring formed on both sides of the signal line driving IC.

しかしながら、表示パネルの大型化により、各テープキャリアパッケージの信号線駆動ICのサイズが増大したり走査線駆動回路用制御バスや電源バスの配線数が増大すると、信号線駆動ICと一体化されるフレキシブル配線板において十分な配線間隔を確保することが困難になる。   However, if the size of the signal line driving IC of each tape carrier package increases due to the increase in the size of the display panel or the number of wirings of the control bus for the scanning line driving circuit and the power supply bus increases, it is integrated with the signal line driving IC. It becomes difficult to ensure a sufficient wiring interval in the flexible wiring board.

本発明の目的は、駆動ICと一体化されるフレキシブル配線板において十分な配線間隔を確保できる平面表示装置を提供することにある。   An object of the present invention is to provide a flat display device capable of ensuring a sufficient wiring interval in a flexible wiring board integrated with a driving IC.

本発明によれば、表示パネルと、バス配線を形成した配線基板部と、各々表示パネルおよび配線基板部間に配置される複数のフレキシブル配線板とそれぞれ一体化した複数の駆動ICを含み表示パネルを駆動する駆動回路と、バス配線を介して駆動回路を制御するコントローラとを備え、各駆動ICは対応フレキシブル配線板の配線パターンを非対称にするように表示パネルの外縁に沿った方向において中央からずれて配置される平面表示装置が提供される。   According to the present invention, a display panel includes a display panel, a wiring board portion on which bus wiring is formed, and a plurality of driving ICs each integrated with a plurality of flexible wiring boards respectively disposed between the display panel and the wiring board portion. Drive circuit and a controller for controlling the drive circuit via the bus wiring, and each drive IC from the center in the direction along the outer edge of the display panel so as to make the wiring pattern of the corresponding flexible wiring board asymmetric. A flat display device is provided that is offset.

この平面表示装置では、各駆動ICが対応フレキシブル配線板の配線パターンを非対称にするように表示パネルの外縁に沿った方向において中央からずれて配置される。すなわち、フレキシブル配線板において駆動ICをずらす側と反対側に広い空きスペースができるため、表示パネルと配線基板部とを結ぶブリッジ配線のような補助配線をこの空きスペースに形成することにより、この補助配線において十分な配線間隔を確保することが可能となる。従って、補助配線を駆動ICの両側に冗長的に設ける場合のようにフレキシブル配線板の幅を無駄にすることなく所望する側に補助配線を配置できる。   In this flat display device, each driving IC is arranged so as to be shifted from the center in the direction along the outer edge of the display panel so as to make the wiring pattern of the corresponding flexible wiring board asymmetric. That is, since a wide empty space is created on the side opposite to the side where the drive IC is shifted in the flexible wiring board, an auxiliary wiring such as a bridge wiring connecting the display panel and the wiring board portion is formed in this empty space. It is possible to secure a sufficient wiring interval in the wiring. Therefore, the auxiliary wiring can be arranged on the desired side without wasting the width of the flexible wiring board as in the case where the auxiliary wiring is redundantly provided on both sides of the drive IC.

以下、本発明の一実施形態に係るアクティブマトリクス方式の液晶表示装置について添付図面を参照して説明する。図1はこの液晶表示装置の回路構成を概略的に示す。液晶表示装置は液晶表示パネルDP、および表示パネルDPに接続される表示パネル制御回路CNTを備える。液晶表示パネルDPは一対の電極基板であるアレイ基板1および対向基板2間に液晶層3を挟持した構造である。表示パネル制御回路CNTはアレイ基板1および対向基板2から液晶層3に印加される液晶駆動電圧により液晶表示パネルDPの透過率を制御する。   Hereinafter, an active matrix liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 schematically shows a circuit configuration of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel DP and a display panel control circuit CNT connected to the display panel DP. The liquid crystal display panel DP has a structure in which a liquid crystal layer 3 is sandwiched between an array substrate 1 and a counter substrate 2 which are a pair of electrode substrates. The display panel control circuit CNT controls the transmittance of the liquid crystal display panel DP by the liquid crystal driving voltage applied from the array substrate 1 and the counter substrate 2 to the liquid crystal layer 3.

アレイ基板1は、例えばガラス等の透明絶縁基板上に略マトリクス状に配置される複数の画素電極PE、複数の画素電極PEの行に沿って配置される複数の走査線Y(Y1〜Ym)、複数の画素電極PEの列に沿って配置される複数の信号線X(X1〜Xn)、並びにこれら走査線Yおよび信号線Xの交差位置近傍に配置され各々対応走査線Yを介して駆動されたときに対応信号線Xおよび対応画素電極PE間で導通して複数の画素スイッチング素子Wを有する。各画素スイッチング素子Wは例えば薄膜トランジスタからなり、薄膜トランジスタのゲートが走査線Yに接続され、ソース−ドレインパスが信号線Xおよび画素電極PE間に接続される。   The array substrate 1 includes a plurality of pixel electrodes PE arranged in a substantially matrix on a transparent insulating substrate such as glass, and a plurality of scanning lines Y (Y1 to Ym) arranged along a row of the plurality of pixel electrodes PE. , A plurality of signal lines X (X1 to Xn) arranged along a column of the plurality of pixel electrodes PE, and arranged near the intersection position of the scanning lines Y and the signal lines X and driven through the corresponding scanning lines Y, respectively. In this case, the corresponding signal line X and the corresponding pixel electrode PE are conducted to have a plurality of pixel switching elements W. Each pixel switching element W is formed of, for example, a thin film transistor, the gate of the thin film transistor is connected to the scanning line Y, and the source-drain path is connected between the signal line X and the pixel electrode PE.

対向基板2は例えばガラス等の透明絶縁基板上に配置されるカラーフィルタ、および複数の画素電極PEに対向してカラーフィルタ上に配置される共通電極CE等を含む。各画素電極PEおよび共通電極CEは例えばITO(Indium Tin Oxide)等の透明電極材料からなり、配向膜でそれぞれ覆われ、画素電極PEおよび共通電極CEからの電界に対応した液晶分子配列に制御される液晶層3の一部である画素領域と共に画素PXを構成する。   The counter substrate 2 includes, for example, a color filter disposed on a transparent insulating substrate such as glass, and a common electrode CE disposed on the color filter so as to face the plurality of pixel electrodes PE. Each pixel electrode PE and common electrode CE is made of a transparent electrode material such as ITO (Indium Tin Oxide), and is covered with an alignment film, and is controlled to a liquid crystal molecular arrangement corresponding to the electric field from the pixel electrode PE and common electrode CE. A pixel PX is configured together with a pixel region which is a part of the liquid crystal layer 3.

また、複数の画素PXは各々画素電極PEおよび共通電極CE間に液晶容量CLCを有し、さらに補助容量Csが液晶容量CLCに並列に接続される。   Each of the plurality of pixels PX has a liquid crystal capacitor CLC between the pixel electrode PE and the common electrode CE, and an auxiliary capacitor Cs is connected in parallel to the liquid crystal capacitor CLC.

表示パネル制御回路CNTは、複数のスイッチング素子Wを行単位に導通させるように複数の走査線Y1〜Ymを順次駆動する一対の走査線駆動回路YD、各行のスイッチング素子Wが対応走査線Yの駆動によって導通する期間において画素電圧Vsを複数の信号線X1〜Xnにそれぞれ出力する信号線駆動回路XD、外部から入力される映像信号に対して一対の走査線駆動回路YDおよび信号線駆動回路XDの動作タイミング等を制御するコントローラ5を含む。画素電圧Vsは共通電極CEのコモン電圧Vcomを基準として画素電極PEに印加される電圧であり、コモン電圧Vcomに対して周期的に極性反転される。   The display panel control circuit CNT includes a pair of scanning line drive circuits YD that sequentially drive the plurality of scanning lines Y1 to Ym so that the plurality of switching elements W are conducted in units of rows. A signal line driving circuit XD for outputting the pixel voltage Vs to the plurality of signal lines X1 to Xn during a period of conduction by driving, and a pair of scanning line driving circuit YD and signal line driving circuit XD for a video signal input from the outside. Including a controller 5 for controlling the operation timing and the like. The pixel voltage Vs is a voltage applied to the pixel electrode PE with the common voltage Vcom of the common electrode CE as a reference, and the polarity is periodically inverted with respect to the common voltage Vcom.

一対の走査線駆動回路YDは互いに同一の構造であり、複数の走査線Yに沿った方向においてアレイ基板1の両側に配置される。信号線駆動回路XDは複数の信号線Xに沿った方向においてアレイ基板1の一方側に配置される。コントローラ5は、順次複数の走査線Yを駆動するための制御信号CTYおよび、映像信号から1行分の画素PX単位に得られる直列な画素データDATA、出力極性を指定してこれら画素データDATAを複数の信号線Xにそれぞれ割り当てるための制御信号CTX、画像データDATAを画素電圧Vsに変換するために用いられる所定数の階調基準電圧VREF等を発生する。制御信号CTYおよび補償電圧はコントローラ5から一対の走査線駆動回路YDに供給され、制御信号CTX、画素データDATA、階調基準電圧VREFはコントローラ5から信号線駆動回路XDに供給される。   The pair of scanning line drive circuits YD have the same structure and are arranged on both sides of the array substrate 1 in the direction along the plurality of scanning lines Y. The signal line drive circuit XD is disposed on one side of the array substrate 1 in the direction along the plurality of signal lines X. The controller 5 designates the control signal CTY for sequentially driving the plurality of scanning lines Y, the serial pixel data DATA obtained from the video signal in units of pixels PX for one row, and the output polarity, and the pixel data DATA. A control signal CTX to be assigned to each of the plurality of signal lines X, a predetermined number of gradation reference voltages VREF used to convert the image data DATA to the pixel voltage Vs, and the like are generated. The control signal CTY and the compensation voltage are supplied from the controller 5 to the pair of scanning line drive circuits YD, and the control signal CTX, pixel data DATA, and gradation reference voltage VREF are supplied from the controller 5 to the signal line drive circuit XD.

走査線駆動回路YDは制御信号CTYの制御により1フレーム期間において複数の走査線Y1〜Ymを順次選択し、各行の画素スイッチング素子Wを1水平走査期間だけ導通させるオン電圧を選択走査線Yに供給する。信号線駆動回路XDは1水平走査期間毎に1行分の画素PXに対して供給される画素データDATAを所定数の階調基準電圧VREFを参照してそれぞれ画素電圧Vsに変換し、複数の信号線X1〜Xnに並列的に出力する。   The scanning line driving circuit YD sequentially selects a plurality of scanning lines Y1 to Ym in one frame period under the control of the control signal CTY, and turns on the on-voltage that causes the pixel switching elements W in each row to conduct only for one horizontal scanning period. Supply. The signal line driving circuit XD converts the pixel data DATA supplied to the pixels PX for one row every horizontal scanning period into pixel voltages Vs with reference to a predetermined number of gradation reference voltages VREF, and Output in parallel to the signal lines X1 to Xn.

走査線駆動回路YDが例えば走査線Y1をオン電圧により駆動してこの走査線Y1に接続された全ての画素スイッチング素子Wを導通させると、信号線X1〜Xn上の画素電圧Vsがこれら画素スイッチング素子Wをそれぞれ介して1行分の画素電極PEに供給される。   For example, when the scanning line driving circuit YD drives the scanning line Y1 with an on-voltage to make all the pixel switching elements W connected to the scanning line Y1 conductive, the pixel voltage Vs on the signal lines X1 to Xn is switched to these pixels. It is supplied to the pixel electrodes PE for one row through the elements W, respectively.

図2は図1に示す液晶表示装置の外部配線構造を示す。図2に示すように、この液晶表示装置は、表示パネルDPの外縁に沿って延びるバス配線BSを形成した配線基板部BPとして、第1〜第4バス配線基板BPA,BPB,BPC,BPDを有する。第1および第2バス配線基板BPA,BPBは信号線駆動回路XDに対して設けられ、第3および第4バス配線基板PBC,BPDは一対の走査線駆動回路YDに対して設けられる。これら走査線駆動回路YDはいずれも各々所定数ずつ複数の走査線Yに接続される複数のテープキャリアパッケージTCP1により構成される。各テープキャリアパッケージTCP1は走査線駆動IC10をフレキシブル配線板11にマウントして一体化したものである。信号線駆動回路XDは各々所定数ずつ複数の信号線Xに接続される複数のテープキャリアパッケージTCP2により構成される。各テープキャリアパッケージTCP2は信号線駆動IC20をフレキシブル配線板21にマウントして一体化したものである。   FIG. 2 shows an external wiring structure of the liquid crystal display device shown in FIG. As shown in FIG. 2, the liquid crystal display device includes first to fourth bus wiring boards BPA, BPB, BPC, and BPD as wiring board portions BP in which bus wirings BS extending along the outer edge of the display panel DP are formed. Have. The first and second bus wiring boards BPA and BPB are provided for the signal line driving circuit XD, and the third and fourth bus wiring boards PBC and BPD are provided for the pair of scanning line driving circuits YD. Each of these scanning line drive circuits YD is constituted by a plurality of tape carrier packages TCP1 each connected to a plurality of scanning lines Y by a predetermined number. Each tape carrier package TCP1 is formed by mounting a scanning line driving IC 10 on a flexible wiring board 11 and integrating them. The signal line driving circuit XD is configured by a plurality of tape carrier packages TCP2 each connected to a plurality of signal lines X by a predetermined number. Each tape carrier package TCP2 is obtained by mounting a signal line driving IC 20 on a flexible wiring board 21 and integrating them.

一対の走査線駆動回路YDの各々では、全テープキャリアパッケージTCP1のフレキシブル配線板11が表示パネルDPおよび第3バス配線基板BPC間、または表示パネルDPおよび第4バス配線基板BPD間に配置される。信号線駆動回路XDでは、半数のテープキャリアパッケージTCP2のフレキシブル配線板21が表示パネルDPおよび第1バス配線基板BPA間に配置され、残り半数のテープキャリアパッケージTCP2のフレキシブル配線板21が表示パネルDPおよび第2バス配線基板BPB間に配置される。   In each of the pair of scanning line driving circuits YD, the flexible wiring board 11 of all the tape carrier packages TCP1 is disposed between the display panel DP and the third bus wiring board BPC or between the display panel DP and the fourth bus wiring board BPD. . In the signal line driving circuit XD, half of the flexible wiring boards 21 of the tape carrier package TCP2 are arranged between the display panel DP and the first bus wiring board BPA, and the remaining half of the flexible wiring boards 21 of the tape carrier package TCP2 are connected to the display panel DP. And between the second bus wiring boards BPB.

コントローラ5はバス配線BSに接続して配線基板部BPから独立なコントローラ基板CP上に配置され、バス配線BSを介して走査線駆動回路YDおよび信号線駆動回路XDを制御する。第1および第2バス配線基板BPA,BPBとコントローラ基板CPとは、コネクタCNおよびフレキシブル配線材FBによって接続される。フレキシブル配線材FBとしては、フレキシブル配線板およびフレキシブルフラットケーブル等が用いられる。第1および第2バス配線基板BPA,BP2のバス配線BSは制御信号CTY等を供給する走査線駆動回路YD用制御バス、制御信号CTX、画素データDATA、および階調基準電圧VREF等を供給する信号線駆動回路XD用制御バス、および走査線駆動回路YD、信号線駆動回路XD等の動作電圧を供給する電源バスを含む。第3および第4バス配線基板BPC,BPDのバス配線BSは制御信号CTY等を供給する走査線駆動回路YD用制御バスを含む。第1バス配線基板BPAのバス配線BSと第2バス配線基板BPBのバス配線BSとは互いに独立であり、コントローラ基板CP上で共通になっている。   The controller 5 is connected to the bus wiring BS and disposed on the controller board CP independent of the wiring board portion BP, and controls the scanning line driving circuit YD and the signal line driving circuit XD via the bus wiring BS. The first and second bus wiring boards BPA, BPB and the controller board CP are connected by the connector CN and the flexible wiring material FB. As the flexible wiring material FB, a flexible wiring board, a flexible flat cable, or the like is used. The bus wiring BS of the first and second bus wiring boards BPA and BP2 supplies a control bus for the scanning line driving circuit YD for supplying the control signal CTY, the control signal CTX, the pixel data DATA, the gradation reference voltage VREF, and the like. It includes a control bus for the signal line driving circuit XD, and a power supply bus for supplying operating voltages for the scanning line driving circuit YD, the signal line driving circuit XD, and the like. The bus lines BS of the third and fourth bus wiring boards BPC and BPD include a control bus for the scanning line driving circuit YD that supplies a control signal CTY and the like. The bus wiring BS of the first bus wiring board BPA and the bus wiring BS of the second bus wiring board BPB are independent from each other and are common on the controller board CP.

ここでは、コントローラ5が、第1および第2バス配線基板BPA,BPBの各々で走査線駆動回路YD用制御バス、信号線駆動回路XD用制御バスおよび電源バスに接続される。特に第1バス配線基板BPA上の信号線駆動回路XD用制御バスと第2バス配線基板BPB上の信号線駆動回路XD用制御バスとは、配線長を短くするために独立していることが好ましい。第1および第2バス配線基板BPA,BPBの境界から遠い端部側では、第1バス配線基板BPAのバス配線BSおよび第2バス配線基板BPBのバス配線BS(具体的には、走査線駆動回路YD用制御バスおよび電源バス)が端部に最も近いフレキシブル配線板21をそれぞれ介して表示パネルDPに引き込まれ、さらにバス配線BS(具体的には、走査線駆動回路YD用制御バス)が最も近いフレキシブル配線板11をそれぞれ介して第3および第4バス配線基板BPC,BPDのバス配線BSに接続される。   Here, the controller 5 is connected to the control bus for the scanning line driving circuit YD, the control bus for the signal line driving circuit XD, and the power supply bus in each of the first and second bus wiring boards BPA and BPB. In particular, the control bus for the signal line driver circuit XD on the first bus wiring board BPA and the control bus for the signal line driver circuit XD on the second bus wiring board BPB may be independent in order to shorten the wiring length. preferable. On the end side far from the boundary between the first and second bus wiring boards BPA and BPB, the bus wiring BS of the first bus wiring board BPA and the bus wiring BS of the second bus wiring board BPB (specifically, scanning line driving) Circuit YD control bus and power supply bus) are respectively drawn into the display panel DP through the flexible wiring board 21 closest to the end, and further, the bus wiring BS (specifically, the control bus for the scanning line driving circuit YD) is provided. It is connected to the bus wiring BS of the third and fourth bus wiring boards BPC and BPD via the nearest flexible wiring board 11, respectively.

図3は表示パネルDPおよび第1バス配線基板BPA間に配置される第1グループのテープキャリアパッケージTCP2の平面構造を示し、図4は表示パネルDPおよび第2バス配線基板BPB間に配置される第2グループのテープキャリアパッケージTCP2の平面構造を示す。各テープキャリアパッケージTCP2では、フレキシブル配線板21が信号線駆動IC20の入出力に用いられる信号線駆動用配線22および走査線駆動回路YDを制御するために用いられる走査線駆動用配線23を有する。第1および第2バス配線基板BPA,BPB上の信号線駆動回路XD用バスは信号線駆動用配線22により信号線駆動IC20に接続され、この信号線駆動IC20の出力部は信号線駆動用配線22により所定数の信号線Xに接続される。第1および第2バス配線基板BPA,BPB上の走査線駆動回路YD用バスは走査線駆動用配線23により一対の走査線駆動回路YDにそれぞれ向かう表示パネルDP上の配線に接続される。尚、第1および第2バス配線基板BPA,BPB上の電源バスについては、信号線駆動用配線22が信号線駆動回路XD用の電源バス部分に割り当てられ、走査線駆動用配線23が走査線駆動回路用の電源バス部分に割り当てられる。   3 shows a planar structure of the first group of tape carrier packages TCP2 arranged between the display panel DP and the first bus wiring board BPA, and FIG. 4 is arranged between the display panel DP and the second bus wiring board BPB. The plane structure of the tape carrier package TCP2 of the second group is shown. In each tape carrier package TCP2, the flexible wiring board 21 has a signal line driving wiring 22 used for input / output of the signal line driving IC 20 and a scanning line driving wiring 23 used for controlling the scanning line driving circuit YD. The signal line driving circuit XD bus on the first and second bus wiring boards BPA and BPB is connected to the signal line driving IC 20 by the signal line driving wiring 22, and the output portion of the signal line driving IC 20 is the signal line driving wiring. 22 is connected to a predetermined number of signal lines X. The scanning line driving circuit YD buses on the first and second bus wiring boards BPA and BPB are connected to wirings on the display panel DP respectively directed to the pair of scanning line driving circuits YD by the scanning line driving wirings 23. For the power buses on the first and second bus wiring boards BPA and BPB, the signal line driving wiring 22 is assigned to the power bus portion for the signal line driving circuit XD, and the scanning line driving wiring 23 is the scanning line. Allocated to the power supply bus portion for the drive circuit.

第1グループのテープキャリアパッケージTCP2では、信号線駆動IC20が表示パネルDPの外縁に沿った方向においてフレキシブル配線板21の中央からずれて右寄りに配置される。他方、第2グループのテープキャリアパッケージTCP2では、信号線駆動IC20が表示パネルDPの外縁に沿った方向においてフレキシブル配線板21の中央からずれて左寄りに配置される。これにより、広い空きスペースがフレキシブル配線板21において信号線駆動IC20とは反対側にでき、走査線駆動用配線23がこの空きスペースに形成さる。ここで、走査線駆動用配線23は第1および第2配線基板BPA,BPB上のバス配線BSの少なくとも一部を表示パネルDPに引き込むためのブリッジ配線として、表示パネルDPの外縁に沿った方向において信号線駆動IC20によって占有されない空きスペースに配置されている。   In the first group of tape carrier packages TCP2, the signal line driving IC 20 is arranged on the right side of the flexible wiring board 21 in the direction along the outer edge of the display panel DP. On the other hand, in the tape carrier package TCP2 of the second group, the signal line driving IC 20 is shifted to the left from the center of the flexible wiring board 21 in the direction along the outer edge of the display panel DP. Thereby, a wide empty space can be formed on the side opposite to the signal line driving IC 20 in the flexible wiring board 21, and the scanning line driving wiring 23 is formed in this empty space. Here, the scanning line driving wiring 23 is a direction along the outer edge of the display panel DP as a bridge wiring for drawing at least a part of the bus wiring BS on the first and second wiring boards BPA and BPB into the display panel DP. In the empty space not occupied by the signal line driving IC 20.

従って、走査線駆動用配線23は第1バス配線基板BPAおよび表示パネルDP間に配置される第1グループのフレキシブル配線板21において信号線駆動IC20の一方側に位置し、第2バス配線基板BPBおよび表示パネルDP間に配置される第2グループのフレキシブル配線板21において信号線駆動IC20の他方側に位置することになる。   Accordingly, the scanning line driving wiring 23 is located on one side of the signal line driving IC 20 in the first group of flexible wiring boards 21 arranged between the first bus wiring board BPA and the display panel DP, and the second bus wiring board BPB. And in the 2nd group flexible wiring board 21 arrange | positioned between display panels DP, it will be located in the other side of the signal line drive IC20.

このような構成において、第1バス配線基板BPA上のバス配線BSの一部である走査線駆動回路YD用制御バスおよび電源バスは第1グループのフレキシブル配線板21のうちで左側の走査線駆動回路YDに最も近い配線板21の走査線駆動用配線23を介して表示パネルDPに引き込まれ、第2バス配線基板BPB上のバス配線BSの一部である走査線駆動回路YD用制御バスおよび電源バスは第2グループのフレキシブル配線板21のうちで右側の走査線駆動回路YDに最も近い配線板21の走査線駆動用配線23を介して表示パネルDPに引き込まれる。   In such a configuration, the scanning line driving circuit YD control bus and the power supply bus, which are part of the bus wiring BS on the first bus wiring board BPA, are the left scanning line driving among the flexible wiring boards 21 of the first group. A control bus for the scanning line driving circuit YD, which is drawn into the display panel DP through the scanning line driving wiring 23 of the wiring board 21 closest to the circuit YD and is part of the bus wiring BS on the second bus wiring board BPB, and The power supply bus is drawn into the display panel DP through the scanning line driving wiring 23 of the wiring board 21 closest to the right scanning line driving circuit YD among the flexible wiring boards 21 of the second group.

上述の実施形態では、各信号線駆動IC20が対応フレキシブル配線板21の配線パターンを非対称にするように表示パネルDPの外縁に沿った方向において中央からずれて配置される。すなわち、フレキシブル配線板21において信号線駆動IC20をずらす側と反対側に広い空きスペースができるため、表示パネルDPとバス配線基板BPA,BPBとを結ぶブリッジ配線(走査線駆動用配線23)のような補助配線をこの空きスペースに形成することにより、この補助配線において実装を容易にしこの実装時の信頼性を向上させる十分な配線間隔Gを確保することが可能となる。従って、補助配線を信号線駆動IC20の両側に冗長的に設ける場合のようにフレキシブル配線板21の幅を無駄にすることなく所望する側に補助配線を配置できる。   In the above-described embodiment, each signal line driving IC 20 is arranged so as to be shifted from the center in the direction along the outer edge of the display panel DP so that the wiring pattern of the corresponding flexible wiring board 21 is asymmetric. That is, since a wide empty space is formed on the side opposite to the side where the signal line driving IC 20 is shifted in the flexible wiring board 21, it is like a bridge wiring (scanning line driving wiring 23) connecting the display panel DP and the bus wiring boards BPA and BPB. By forming a simple auxiliary wiring in this empty space, it is possible to secure a sufficient wiring interval G that facilitates the mounting of the auxiliary wiring and improves the reliability at the time of mounting. Therefore, the auxiliary wiring can be arranged on the desired side without wasting the width of the flexible wiring board 21 as in the case where the auxiliary wiring is redundantly provided on both sides of the signal line driving IC 20.

尚、本発明は上述の実施形態に限定されず、その要旨を逸脱しない範囲で様々に変形可能である。   In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

上述の実施形態では、一対の走査線駆動回路YDを表示パネルDPの両側に配置したが、単一の走査線駆動回路YDを表示パネルDPの一方側に配置する構造にしてもよい。   In the above-described embodiment, the pair of scanning line driving circuits YD are arranged on both sides of the display panel DP. However, a single scanning line driving circuit YD may be arranged on one side of the display panel DP.

また、上述の実施形態では、アクティブマトリクス方式の液晶表示装置を一例として説明したが、本発明は液晶の駆動方式によらず様々な液晶表示装置に適用できる。従って、例えば画素スイッチング素子Wを用いずに走査線Xおよび信号線Xを介して直接的に液晶画素を駆動するような液晶表示装置にも適用できる。さらに本発明は、外部から表示パネルを制御する構成であれば、例えばTN液晶画素を用いる液晶表示装置や、自己発光素子を画素として用いるFED装置および有機EL表示装置等の平面表示装置にも適用できる。   In the above-described embodiment, the active matrix liquid crystal display device has been described as an example. However, the present invention can be applied to various liquid crystal display devices regardless of the liquid crystal driving method. Therefore, for example, the present invention can be applied to a liquid crystal display device that directly drives a liquid crystal pixel via the scanning line X and the signal line X without using the pixel switching element W. Further, the present invention can be applied to a flat display device such as a liquid crystal display device using a TN liquid crystal pixel, an FED device using a self-light emitting element as a pixel, and an organic EL display device as long as the display panel is controlled from the outside. it can.

本発明の一実施形態に係るアクティブマトリクス方式の液晶表示装置の回路構成を概略的に示す図である。1 is a diagram schematically showing a circuit configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. 図1に示す液晶表示装置の外部配線構造を示す図である。It is a figure which shows the external wiring structure of the liquid crystal display device shown in FIG. 図2に示す表示パネルおよび第1バス配線基板間に配置される第1グループのテープキャリアパッケージの平面構造を示す図である。It is a figure which shows the planar structure of the tape carrier package of the 1st group arrange | positioned between the display panel shown in FIG. 2, and a 1st bus wiring board. 図2に示す表示パネルおよび第2バス配線基板間に配置される第2グループのテープキャリアパッケージの平面構造を示す図である。It is a figure which shows the planar structure of the tape carrier package of the 2nd group arrange | positioned between the display panel shown in FIG. 2, and a 2nd bus wiring board. 従来のテープキャリアパッケージの平面構造を示す図である。It is a figure which shows the planar structure of the conventional tape carrier package.

符号の説明Explanation of symbols

1…アレイ基板、2…対向基板、3…液晶層、5…コントローラ、10…走査線駆動IC、11…フレキシブル配線板、20…信号線駆動IC、21…フレキシブル配線板、22…信号線駆動用配線、23…走査線駆動用配線、TCP1,TCP2…テープキャリアパッケージ、BP…配線基板部、BPA,BPB,BPC,BPD…バス配線基板、BS…バス配線、PS…バイパス配線、CP…コントローラ基板、DP…液晶表示パネル、PE…画素電極、CE…共通電極、CLC…液晶容量、Cs…補助容量、PX…液晶画素、W…スイッチング素子、Y…走査線、X…信号線、CN…コネクタ、FB…フレキシブル配線材、CNT…表示パネル制御回路、YD…走査線駆動回路、XD…信号線駆動回路。   DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 5 ... Controller, 10 ... Scan line drive IC, 11 ... Flexible wiring board, 20 ... Signal line drive IC, 21 ... Flexible wiring board, 22 ... Signal line drive Wiring, 23 ... scanning line driving wiring, TCP1, TCP2 ... tape carrier package, BP ... wiring board, BPA, BPB, BPC, BPD ... bus wiring board, BS ... bus wiring, PS ... bypass wiring, CP ... controller Substrate, DP ... liquid crystal display panel, PE ... pixel electrode, CE ... common electrode, CLC ... liquid crystal capacitor, Cs ... auxiliary capacitor, PX ... liquid crystal pixel, W ... switching element, Y ... scanning line, X ... signal line, CN ... Connector, FB ... flexible wiring material, CNT ... display panel control circuit, YD ... scanning line drive circuit, XD ... signal line drive circuit.

Claims (7)

表示パネルと、バス配線を形成した配線基板部と、各々前記表示パネルおよび前記配線基板部間に配置される複数のフレキシブル配線板とそれぞれ一体化した複数の駆動ICを含み前記表示パネルを駆動する駆動回路と、前記バス配線を介して前記駆動回路を制御するコントローラとを備え、各駆動ICは対応フレキシブル配線板の配線パターンを非対称にするように前記表示パネルの外縁に沿った方向において中央からずれて配置されることを特徴とする平面表示装置。 The display panel is driven by including a display panel, a wiring board portion on which bus wiring is formed, and a plurality of driving ICs respectively integrated with the display panel and a plurality of flexible wiring boards arranged between the wiring board portions. A driving circuit and a controller for controlling the driving circuit via the bus wiring, each driving IC from the center in the direction along the outer edge of the display panel so as to make the wiring pattern of the corresponding flexible wiring board asymmetrical A flat display device characterized by being displaced. 前記フレキシブル配線板は前記配線基板部上のバス配線の少なくとも一部を前記表示パネルに引き込むためのブリッジ配線を含み、前記ブリッジ配線は前記表示パネルの外縁に沿った方向において前記駆動ICによって占有されない空きスペースに配置されることを特徴とする請求項1に記載の平面表示装置。 The flexible wiring board includes a bridge wiring for drawing at least a part of the bus wiring on the wiring board portion into the display panel, and the bridge wiring is not occupied by the drive IC in a direction along an outer edge of the display panel. The flat display device according to claim 1, wherein the flat display device is disposed in an empty space. 前記配線基板部は第1および第2バス配線基板を含み、前記ブリッジ配線は前記第1バス配線基板および表示パネル間に配置される第1グループのフレキシブル配線板において前記駆動ICの一方側に位置し、前記第2バス配線基板および表示パネル間に配置される第2グループのフレキシブル配線板において前記駆動ICの他方側に位置することを特徴とする請求項2に記載の平面表示装置。 The wiring board portion includes first and second bus wiring boards, and the bridge wiring is positioned on one side of the drive IC in a first group of flexible wiring boards disposed between the first bus wiring board and the display panel. 3. The flat display device according to claim 2, wherein the flat panel display device is located on the other side of the drive IC in a second group of flexible wiring boards disposed between the second bus wiring substrate and the display panel. 前記第1バス配線基板上のバス配線の一部が前記第1グループのフレキシブル配線板のいずれかのブリッジ配線を介して前記表示パネルに引き込まれ、前記第2バス配線基板上のバス配線の一部が前記第2グループのフレキシブル配線板のいずれかのブリッジ配線を介して前記表示パネルに引き込まれることを特徴とする請求項3に記載の平面表示装置。 A part of the bus wiring on the first bus wiring board is drawn into the display panel via any bridge wiring of the first group of flexible wiring boards, and one of the bus wirings on the second bus wiring board is drawn. The flat display device according to claim 3, wherein the portion is pulled into the display panel through any bridge wiring of the second group of flexible wiring boards. 前記表示パネルは略マトリクス状に配置される複数の画素、前記複数の画素の行に沿って配置される複数の走査線、前記複数の画素の列に沿って配置される複数の信号線、および前記複数の走査線および前記複数の信号線の交差位置近傍に配置され各々対応走査線を介して選択されたときに対応信号線を対応画素に接続する複数のスイッチング素子を含み、前記駆動回路は前記複数の走査線を駆動する走査線駆動回路および前記複数の信号線を駆動する信号線駆動回路を含み、前記信号線駆動回路が前記複数の駆動ICにより構成されることを特徴とする請求項2に記載の平面表示装置。 The display panel includes a plurality of pixels arranged in a substantially matrix, a plurality of scanning lines arranged along a row of the plurality of pixels, a plurality of signal lines arranged along a column of the plurality of pixels, and A plurality of switching elements that are arranged in the vicinity of intersection positions of the plurality of scanning lines and the plurality of signal lines and that connect the corresponding signal lines to corresponding pixels when selected via the corresponding scanning lines, A scanning line driving circuit for driving the plurality of scanning lines and a signal line driving circuit for driving the plurality of signal lines, wherein the signal line driving circuit is constituted by the plurality of driving ICs. 2. A flat display device according to 2. 前記ブリッジ配線は前記走査線駆動回路用制御バスおよび電源バスの少なくとも一方を含むことを特徴とする請求項5に記載の平面表示装置。 The flat display device according to claim 5, wherein the bridge line includes at least one of the control bus for the scanning line driving circuit and a power supply bus. 前記駆動ICは前記フレキシブル配線板と一体化してテープキャリアパッケージを構成することを特徴とする請求項1に記載の平面表示装置。 2. The flat display device according to claim 1, wherein the driving IC is integrated with the flexible wiring board to constitute a tape carrier package.
JP2004311263A 2004-10-26 2004-10-26 Planar display device Pending JP2006126294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004311263A JP2006126294A (en) 2004-10-26 2004-10-26 Planar display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004311263A JP2006126294A (en) 2004-10-26 2004-10-26 Planar display device

Publications (1)

Publication Number Publication Date
JP2006126294A true JP2006126294A (en) 2006-05-18

Family

ID=36721130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004311263A Pending JP2006126294A (en) 2004-10-26 2004-10-26 Planar display device

Country Status (1)

Country Link
JP (1) JP2006126294A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010060813A (en) * 2008-09-03 2010-03-18 Hitachi Displays Ltd Display apparatus
JP2020525807A (en) * 2017-07-03 2020-08-27 京東方科技集團股▲ふん▼有限公司Boe Technology Group Co.,Ltd. Array substrate and display device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222086A (en) * 1997-02-12 1998-08-21 Canon Inc Driving circuit connecting structure of display device
JPH11185850A (en) * 1997-12-25 1999-07-09 Canon Inc Connection structure of circuit substrate and judging method for connection state of circuit substrate
JPH11231337A (en) * 1998-02-10 1999-08-27 Sanyo Electric Co Ltd Liquid crystal display device
JP2001196422A (en) * 2000-01-14 2001-07-19 Matsushita Electric Ind Co Ltd Thermocompression bonding device
JP2002108311A (en) * 2000-07-24 2002-04-10 Sharp Corp Plural column electrode driving circuits and display device
JP2003167269A (en) * 2001-11-29 2003-06-13 Sharp Corp Display device
JP2004133474A (en) * 2002-10-14 2004-04-30 Lg Philips Lcd Co Ltd Liquid crystal display, its manufacturing method and driving method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222086A (en) * 1997-02-12 1998-08-21 Canon Inc Driving circuit connecting structure of display device
JPH11185850A (en) * 1997-12-25 1999-07-09 Canon Inc Connection structure of circuit substrate and judging method for connection state of circuit substrate
JPH11231337A (en) * 1998-02-10 1999-08-27 Sanyo Electric Co Ltd Liquid crystal display device
JP2001196422A (en) * 2000-01-14 2001-07-19 Matsushita Electric Ind Co Ltd Thermocompression bonding device
JP2002108311A (en) * 2000-07-24 2002-04-10 Sharp Corp Plural column electrode driving circuits and display device
JP2003167269A (en) * 2001-11-29 2003-06-13 Sharp Corp Display device
JP2004133474A (en) * 2002-10-14 2004-04-30 Lg Philips Lcd Co Ltd Liquid crystal display, its manufacturing method and driving method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010060813A (en) * 2008-09-03 2010-03-18 Hitachi Displays Ltd Display apparatus
US8836675B2 (en) 2008-09-03 2014-09-16 Japan Display Inc. Display device to reduce the number of defective connections
JP2020525807A (en) * 2017-07-03 2020-08-27 京東方科技集團股▲ふん▼有限公司Boe Technology Group Co.,Ltd. Array substrate and display device

Similar Documents

Publication Publication Date Title
JP5078851B2 (en) Liquid crystal display device and driving method thereof
US6903717B2 (en) Display device having driving circuit
US7495737B2 (en) Horizontal stripe liquid crystal display device
US8218121B2 (en) Liquid crystal display having a printed circuit board combined with only one of the tape carrier packages
US9576520B2 (en) Display device with groove in a non-display area and method of manufacturing the same
US8836675B2 (en) Display device to reduce the number of defective connections
US20060022920A1 (en) Display device and driving method thereof
US9633615B2 (en) Liquid crystal display device
JP2008077007A (en) Display device
JP4163611B2 (en) Liquid crystal display
US7414694B2 (en) Liquid crystal display device
US20080018849A1 (en) Display element
KR101336851B1 (en) Liquid crystal display device and method of driving the same
JP2003167269A (en) Display device
US20070242011A1 (en) Display Device
JP2006126294A (en) Planar display device
JP4851782B2 (en) Liquid crystal display
JP2008003192A (en) Display device
JP5072639B2 (en) Liquid crystal display
KR102403459B1 (en) Display device
US20060158408A1 (en) Liquid crystal display device
US7663727B2 (en) Display device
JP2006126295A (en) Planar display device
JP2002357807A (en) Liquid crystal display device
KR20060089410A (en) Apparatus for video display

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070925

A977 Report on retrieval

Effective date: 20100827

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100914

A02 Decision of refusal

Effective date: 20110125

Free format text: JAPANESE INTERMEDIATE CODE: A02