JP2006121400A - Equalizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make both residual amplitude error compensation and residual phase error compensation optimally function by one equalizer. <P>SOLUTION: This one tap equalizer is configured to update one complex tap coefficient by an LMS algorithm, and to converge the imaginary part of the tap coefficient into 0 when the phase error of an input signal is 0, and provided with step gains μi(n) and μq(n) respectively for amplitude compensation and phase compensation, wherein the real part and imaginary part of the update quantity of the tap coefficient are respectively multiplied by the μi(n) and μq(n), and added to the current tap coefficient, so that the tap coefficient can be updated. Those μi(n) and μq(n) are respectively set according to the speeds of the amplitude fluctuation and phase fluctuation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an equalizer, and more particularly to an equalizer having improved demodulation characteristics by high-precision waveform equalization in a digital radio receiver.

In a modulation / demodulation apparatus using a multilevel QAM modulation system, modulation / demodulation is usually performed using a carrier signal from a local oscillator that oscillates at the same local frequency in both transmission / reception apparatuses. Frequency offset is caused by frequency accuracy error, temperature fluctuation, aging, etc.
This frequency offset is a major problem to be solved in the field of subscriber wireless access systems (FWA), and not only in the flow of higher frequency of wireless communication or multi-value modulation. Yes, the importance of frequency offset compensation is increasing.

This frequency offset appears as a phase rotation at a constant speed in the baseband signal after quadrature detection in the receiver, and it is necessary to compensate for this frequency offset in order to obtain a correct demodulated signal.
Further, not only the frequency offset but also the AGC control residual error and the amplitude compensation when the level fluctuates in the middle of the frame are required.

Conventionally, an equalizer having a small number of taps (for example, 1) is known as one that compensates for such residual frequency offset and residual amplitude fluctuation with high accuracy (see, for example, Patent Document 1).
FIG. 8 is a block diagram of a one-tap equalizer disclosed in Patent Document 1. In FIG. The equalizer of FIG. 8 operates using an LMS algorithm expressed by the following equation.
h (n + 1) = h (n) + μu (n) ^* e (n)
e (n) = d (n) −u (n) h (n)
u (n) is an input signal, h (n) is a tap coefficient, d (n) is a reference symbol of the symbol determination result, e (n) is an equalization error with the reference symbol, and these are I phase and Q phase Expressed as a complex number consisting of * Means a complex conjugate, and μ is a step gain related to the convergence speed of the equalizer, which is a real number. Increasing the step gain μ increases the convergence speed but increases the residual equalization error. Conversely, decreasing the step gain μ decreases the residual equalization error but decreases the convergence speed. Therefore, it is necessary to select an optimal value for the step gain μ according to the object to be equalized.

The operation of the equalizer of FIG. 8 will be described. Based on the modulation scheme information notified from the modulation scheme determination means, the results of symbol determination of yi (n) and yq (n) of the equalizer output are used as reference symbols di (n) and dq (n), and the difference is obtained. Equalization errors ei (n) and eq (n) are obtained. Equalization errors ei (n), eq (n) and input signals ui (n), uq (n) are complex-multiplied and multiplied by a step gain μ to perform tap update processing. Using the tap coefficients hi (n) and hq (n) obtained in this way, the input signals ui (n) and uq (n) are subjected to complex multiplication, and the output signals yi (n) and yq (n) are obtained. can get. This equalizer has no distortion, that is, when equalization up to the previous stage is converged and the same input signals ui (n) and uq (n) as the reference symbols are inputted, hi (n) = 1, hq (n ) = 0. Therefore, the tap coefficient hi (n) can be regarded as a coefficient for mainly correcting the amplitude error of the input signals ui (n) and uq (n), and the tap coefficient hq (n) can be regarded as a coefficient for mainly correcting the phase error.

The equalizer of FIG. 8 is mainly able to compensate for the residual frequency offset of AFC (Automatic Frequency Control) that mainly controls the local frequency and the residual phase error due to the phase noise of the local oscillator. Or residual amplitude errors such as level fluctuations after the UW section in which the equalizer up to the previous stage trains can be compensated. Usually, the equalization error is suppressed to a certain level by the equalization means up to the previous stage. In this equalizer, the residual phase error is compensated mainly by the hq (n) component, and the residual amplitude error is mainly hi ( n) Compensated by component. As described above, it is necessary to select an optimum value for the step gain μ that determines the convergence speed of the equalizer according to the target to be equalized.

Here, hi (n) compensates for the residual amplitude error. For example, in a fixed radio such as FWA, the step gain μ can be reduced because there is little sudden amplitude fluctuation. In such a system with a large amplitude fluctuation, it is necessary to increase the step gain μ in order to increase the convergence speed. The step gain of amplitude fluctuation is a parameter related to the magnitude of control error of the AGC loop and the amplitude fluctuation in the frame with respect to the radio frame length and symbol rate.
The purpose of hq (n) is to compensate the residual phase error, but the step gain μ is determined by the amount of residual frequency offset depending on the accuracy of AFC control and the magnitude of the phase noise of the local oscillator.

JP 2004-7487 A

In the conventional equalizer of FIG. 8, since the step gain μ of hi (n) for compensating the residual amplitude error and hq (n) for compensating the residual phase error are the same value, it is fixed as in the FWA system, for example. In a wireless system with a small residual amplitude error and a radio frequency as high as several tens of GHz, and a large residual phase error, it is necessary to set the optimum step gain μ for residual phase error compensation that requires a high convergence speed. In this case, an excessive step gain μ is given to hi (n), which has a small residual amplitude error and the convergence speed may be slow, and as a result, a residual equalization error becomes large, which is the error of the equalizer. There was a problem that the error rate was adversely affected due to equipment deterioration. That is, the optimum step gain cannot be set for each of the residual amplitude error compensation and the residual phase error.

The present invention has been made from the above-described background, and provides an equalizer that can optimally function both residual amplitude error compensation and residual phase error compensation to minimize signal degradation. With the goal.

An equalizer characterized in that, in a single equalizer, step gains for determining respective convergence speeds of amplitude equalization and phase equalization are separately set. (However, “single” does not mean one tap, but means that tap coefficients are controlled together by one algorithm, and the number of taps is arbitrary.)

One (or more) tap coefficients are updated by an adaptive algorithm, and converged to make the imaginary part of the tap coefficients zero when the phase error of the input signal is zero. Because
Step gain μi (n) and μq (n) are provided for amplitude compensation and phase compensation,
The real part and the imaginary part of the update amount (for each of the tap coefficient (s)) are multiplied by the hi (n) and hq (n) separately and added to the current tap coefficient. An equalizer characterized in that the tap coefficient is updated by.

  According to the distortion-compensating quadrature modulator according to the present invention, both residual amplitude error compensation and residual phase error compensation function optimally, so that signal degradation can be minimized.

Hereinafter, the present invention will be described through examples. However, the examples are merely examples of the present invention, and the present invention is not limited to the numerical values, processing order, and implementation means (hardware) specifically described in the examples. , May be different. For example, although the first embodiment describes a one-tap equalizer that operates at a symbol rate, the present invention is not limited to this.
In addition, the present invention does not preclude combining with the description of the previous patent application by the same applicant as the present application referred to in Patent Document 1 to Examples.

FIG. 1 is a block diagram of an FWA receiver to which an equalizer of the present invention is applied.
The mixer 1 down-converts the input intermediate frequency signal IF1 into a sampleable IF2.
The AGC 2 performs gain control so that the amplitude of the varying IF 2 is stabilized within the dynamic range of the ADC 3.
An ADC (Analog to Digital Converter) 3 performs A / D conversion on the output signal of the AGC 2 at a sample rate twice the symbol rate.
The quadrature detection unit 4 converts the digital signal sampled by the ADC 3 into I-phase and Q-phase baseband signals.
The synchronization processing unit 5 operates during the UW period, obtains a known UW (unique word) signal and a correlation value from the baseband signal after quadrature detection, and performs AGC control, AFC control, symbol synchronization, and frame synchronization from the result. Do.
A VCO (Voltage Controlled Oscillators) 6 oscillates a local signal applied to the mixer 1 in accordance with AFC control of the synchronization processing unit 5.
The VCO 7 generates the symbol timing reproduced by the symbol synchronization function of the synchronization processing unit 5 and provides it as an internal clock for the subsequent digital processing.
When the frame synchronization established by the synchronization processing unit 5 is notified, the equalization processing unit 8 performs initial phase error detection, adaptive equalization processing, and decoding of modulation scheme information from the baseband signal after quadrature detection. .
The initial phase correction 9 performs constant phase rotation in one radio frame on the baseband signal after quadrature detection based on the initial phase error notified from the equalization processing unit 8. The initial phase correction 9 is, for example, a complex multiplier.
The equalizer 10 is an equalizer that performs training during the UW section and operates with a constant tap coefficient in the subsequent sections. The number of taps is eight. Since the equalizer 10 also has a role of improving the accuracy of symbol synchronization, it operates with double oversampling.
The equalizer 11 is a decision feedback equalizer and has one tap. The output of the equalizer 11 is subjected to symbol determination and becomes output data of the receiver. The equalizer 11 operates at a symbol rate.

FIG. 2 is a diagram illustrating a radio frame configuration and an operation period of each function. The radio frame is composed of CW, UW, CCH, and DATA. In UW (Unique Word), PN4 (15 symbols) is repeated (8 + 8/15) times. CCH (Control CHannel) is control information such as modulation scheme information. The modulation scheme of UW and CCH is always BPSK. In the DATA section, adaptive modulation using a modulation scheme from QPSK to 1024QAM is performed, and modulation scheme information in the CCH is used when performing symbol determination.

FIG. 3 is an example of the UW correlation value calculated by the synchronization processing unit 5. The synchronization processing unit 5 includes a correlator (for example, a matched filter) that calculates a correlation value with PN4 (15 symbols) at intervals of 1 or 0.5 symbols, but UW has (8 + 8/15) as PN4 (15 symbols). ) Times, 8 peak values (A (1) to A (8)) appear in the UW section.
In the AGC control, the AGC loop is controlled by the difference (or ratio) between the sum P of the power of the eight correlation peak values and the target power. Specifically, for example, a method described in JP-A-2004-242137 may be used.
AFC also controls the AFC loop from the relative phase difference Φ of seven pairs of adjacent correlation peak values. For example, the relative phase difference Φ is
And this is given to the control voltage of the VCO 6. Or the method described in Japanese Patent Application No. 2004-19558 may be used.
Symbol synchronization is controlled by a PLL that accumulates the difference of correlation power values at positions around 1/2 symbol of the correlation peak position for eight peaks and divides this by the accumulated value of correlation peak power values as a phase error. To do.
If the system synchronization is thus established, the equalization processing unit 8 is notified. In the processing after symbol synchronization is established, the sample rate may be the same as the symbol rate.

4, 5 and 6 are diagrams showing the constellation of each part. 4A to 4C show constellations through the CW and UW sections, and FIGS. 5 and 6 show constellations through the entire radio frame, that is, through the CW, WU, CCH, and DATA (1024QAM) sections.
The equalization processing unit 8 detects an initial phase error from the baseband signal after quadrature detection shown in FIG. 4A in the CW section, and notifies the initial phase correction unit 8 of the initial phase error information. For example, as described in Japanese Patent Application No. 2004-19558, the initial phase error is detected by calculating the difference between the declination angle of each symbol and 45 ° and averaging the value for the time of the CW section as the initial phase error. To do. The complex conjugate multiplication value may be averaged instead of the declination difference. As a result, the initial phase correction unit 9 rotates the constellation so that the CW symbol is positioned at an angle of 45 °, and outputs a signal as shown in FIG.
Next, the equalization processing unit 8 cooperates with the equalizer 10 in the UW section, and updates the tap coefficient of the equalizer 10 (adaptive equalization processing) using the UW as a training signal by the LMS algorithm. The equalizer 10 sequentially performs waveform equalization using the updated tap coefficient, and outputs a signal as shown in FIG.

FIG. 5 is a constellation of the output of the equalizer 10. In the CW and UW sections, symbol points (points that appear dark at 45 ° and −135 ° angles) are clearly visible due to the functions of the initial phase correction 8 and the equalizer 10, but in the 1024QAM DATA section, the residual phase The constellation rotates gradually due to the error, making it difficult to determine the symbol. This residual phase error is caused by the residual frequency offset of the AFC control performed by the synchronization processing unit 5 in the UW section and the phase noise of the local transmitter. An equalizer 11 compensates for this residual phase error.

FIG. 6 is a constellation of the output of the equalizer 11. The equalizer 11 performs a through operation with the tap coefficients fixed at hi (n) = 1 and hq (n) = 0 in the UW interval, and is decoded from the CCH by the equalization processing unit 8 in the CCH interval and the DATA interval. A tracking operation is performed using the determined modulation scheme information with the symbol determination result as a reference symbol.
As shown in FIG. 6, it can be seen that symbol determination is possible by compensating the residual phase error. The equalizer 11 can also compensate for a residual error of AGC control performed by the synchronization processing unit 5 in the UW interval, or a residual amplitude error such as level fluctuation after the UW interval.

FIG. 7 is a block diagram of the equalizer 11 and includes the features of the present invention. The difference from the conventional one-tap equalizer is that the step gain determines the convergence speed of hi (n) for residual amplitude error compensation and the step gain that determines the convergence speed of hq (n) for residual phase error compensation. It is divided into μq. That is, the tap coefficient update formula is expressed as follows.
hi (n + 1) = hi (n) +. mu.i.Re [u (n) ^* e (n)]
hq (n + 1) = hq (n) + μq · Im [u (n) ^* e (n)]
The step gain μ is complex, but μi and μq are multiplied separately by the real and imaginary parts of u (n) e (n), respectively, and μ and u (n) e (n) are It is not complex multiplied.

When the amplitude variation is small (slow) and the phase variation is large (fast) as in this embodiment, μi is set smaller than μq. As a result, it is possible to prevent unnecessary vibrations in the converged state while achieving a convergence speed capable of following the fluctuation with respect to both the amplitude error and the residual phase error.

FIG. 1 is a block diagram of an FWA receiver according to the first embodiment. The figure which shows the radio | wireless frame structure of the receiver for FWA which concerns on Example 1, and the operation area of each function. Example of UW correlation value calculated by synchronization processing unit of FWA receiver according to embodiment 1 Constellation of each part of FWA receiver according to embodiment 1 Constellation of equalizer 10 output of FWA receiver according to embodiment 1 Constellation of equalizer 11 output of FWA receiver according to embodiment 1 FIG. 3 is a block diagram of the equalizer 11 of the FWA receiver according to the first embodiment. Block diagram of a conventional one-tap equalizer

Explanation of symbols

1 Mixer 2 AGC
3 ADC (Analog to Digital Converter)
4 Quadrature detection unit 5 Synchronization processing unit 6, 7 VCO
8 Equalizer 9 Initial phase correction 10, 11 Equalizer

Claims (2)

An equalizer characterized in that, in a single equalizer, step gains for determining respective convergence speeds of amplitude equalization and phase equalization are separately set. A one-tap equalizer that updates one complex tap coefficient with an adaptive algorithm and converges so that the imaginary part of the tap coefficient becomes zero when the phase error of the input signal is zero;
Step gain μi (n) and μq (n) are provided for amplitude compensation and phase compensation,
The tap coefficient is updated by multiplying the real part and the imaginary part of the update amount of the tap coefficient separately by the μi (n) and μq (n), respectively, and adding to the current tap coefficient. Equalizer.