JP2006114800A - Testpiece edge processor, testpiece edge processing method, and semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a testpiece edge processor and a testpiece edge processing method that can detect the edge of a testpiece with less efforts. <P>SOLUTION: This testpiece edge processor consists of a testpiece desk 10 mounting a testpiece 2, a driving mechanisom 12 for moving the testpiece desk 10 within a plane, an imaging device 22 for imaging the edge 2a of the testpiece 2 on the testpice desk 10, an arithmetic device 24 for detecting the edge 2a based on a brightness difference within the picture taken by the imaging device 22, and a control mechanism 24 for moving the testpiece desk 10 to the driving mechanism 12 using the detected result of the arithmetic device 24 in a way that the edge 2a from one end to another passes the imaging area of the imaging device 22. In addition, this processor can mount a grinder 14 to grind the edge 2a. In this case, the control mechanism 24 can additionally mount a memory 24a to store the edge 2a position detected by the arithmetic deice 24 so that the edge 2a can be moved along the grinder 14, while operating the grinder 14 using the edge 2a position data stored in the memory 24a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a sample edge processing apparatus and a sample edge processing method for detecting and processing a sample edge, and a method for manufacturing a semiconductor device. In particular, the present invention relates to a sample edge processing apparatus and a sample edge processing method that can detect the edge of a sample with little effort. The present invention also relates to a sample edge processing apparatus and a sample edge processing method that can accurately polish the edge of a sample with little effort. The present invention also relates to a method of manufacturing a semiconductor device that facilitates confirming that the operating conditions of the semiconductor manufacturing apparatus are appropriate.

  In a semiconductor device, a plurality of wiring layers are formed on a semiconductor element such as a transistor. An interlayer insulating film is formed between each wiring layer. Each wiring layer is partially embedded in a connection hole of the interlayer insulating film or a W plug embedded in the connection hole of the interlayer insulating film. For example, the wiring layer is connected to a wiring layer or a semiconductor element located above or below.

  In order to increase the yield and reliability of the semiconductor device, it is necessary to sufficiently embed a wiring layer or a W plug in the connection hole in the interlayer insulating film. In addition, the dimensions of the wiring forming the wiring layer need to be as specified.

As shown in FIG. 6, as a method for confirming the embedding property of a wiring layer or a W plug in a connection hole, or confirming the dimensions of a wiring, a TEG (Test Element Group) of each wiring and connection hole is formed on a silicon substrate 100. ) 101 and 102 are formed, the silicon substrate 100 is cleaved, and the cleaved surface 100a is directly confirmed by SEM.
Kobayashi Satoshi and Nakajima Satoshi "VLSI Process Technology", Nikkan Kogyo Shimbun, June 30, 1993

  In order to confirm the embeddability of the wiring layer and the W plug and the dimensions of the wiring with the SEM, the cleavage plane needs to pass through the TEGs of the wiring and the connection holes. In order to confirm this, before observing with SEM, it is desirable to first observe almost the entire cleavage plane using an optical microscope and confirm that the cleavage plane passes through the TEG. When the cleavage plane is obliquely positioned with respect to the sample stage of the optical microscope, in order to detect the entire cleavage plane, the sample is manually alternated in the X-axis direction and the Y-axis direction while observing the cleavage plane. (See, for example, FIG. 7A), and labor was required.

  Further, when the cleavage plane does not pass through the TEG, it is necessary to polish the cleavage plane to expose the cross section of the TEG. In order to perform this polishing, it is necessary to fix the sample to the sample holder using wax.

  As shown in FIG. 7B, when the sample (for example, the silicon substrate 100) is fixed obliquely with respect to the sample holder 110, the polishing surface (for example, the cleaved surface 100a) is also inclined, and the wiring accuracy is increased. It becomes impossible to measure a large dimension (for example, width). If the polished surface is slanted, it is necessary to grind again and confirm with an optical microscope that the cross section is not slanted. As described above, it is difficult and accurate to polish the sample.

  Further, when the wiring layer is formed of an Al alloy film, the wiring layer may be deformed at the time of cleavage, so that an accurate finished shape cannot be confirmed as it is. Also in this case, since the cleaved surface needs to be polished, the problems associated with the above-described polishing occur.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a sample edge processing apparatus and a sample edge processing method capable of detecting the edge of a sample with little effort. Another object of the present invention is to provide a sample edge processing apparatus and a sample edge processing method capable of accurately polishing the edge of a sample with little effort. Another object of the present invention is to provide a method of manufacturing a semiconductor device that makes it easy to confirm that the operating conditions of the semiconductor manufacturing device are appropriate.

In order to solve the above problems, a sample edge processing apparatus according to the present invention includes a sample stage on which a sample is placed,
A drive unit for moving the sample stage in a plane;
An imaging unit for imaging the edge of the sample on the sample stage;
A calculation unit for detecting the edge based on a brightness difference in an image captured by the imaging unit;
Using the detection result of the arithmetic unit, a control unit that moves the sample stage to the drive unit so that one end to the other end of the edge passes through the imaging area of the imaging unit;
It comprises.

  According to the sample edge processing apparatus, the calculation unit detects the edge of the sample by processing the image, and the control unit uses the detection result to detect the imaging area of the imaging unit from one end of the edge to the other end. The sample stage is moved to the drive unit so as to pass inside. For this reason, the labor for detecting the edge of the sample is reduced.

  The calculation unit may determine that the portion of the image in which the brightness contrast is a certain value or more is an edge. In this case, the amount of calculation required to detect the edge can be reduced.

  You may further provide the grinding | polishing part which grind | polishes an edge. In this case, a storage unit that stores the position of the edge detected by the calculation unit is further provided, and the control unit operates the polishing unit and uses the edge position stored in the storage unit so that the edge is aligned with the polishing unit. It is preferable to polish the entire edge by moving the sample stage so as to move. In this way, the edge can be accurately polished with little effort.

  In the image, when the brightness of the sample is higher than that of the part where the sample does not exist, the control unit detects that the increase rate of the area where the brightness is lower than the sample in the image becomes a predetermined value or more. In addition, it can be determined that the edge of the sample has entered the image.

  You may further comprise the optical mechanism in which the image of the imaging area of an imaging device is confirmed visually. An example of the optical mechanism is a half mirror, a lens system, or a combination thereof.

The sample edge processing method according to the present invention includes a step of positioning one end of the edge of the sample placed on the sample stage within the imaging area of the imaging device;
While causing the calculation unit to detect the edge based on the brightness difference in the image captured by the imaging device, the control unit passes through the imaging area from one end of the edge to the other end based on the detection result. The step of moving the sample stage,
It comprises.

  In the step of moving the sample stage while detecting the edge, the position of the edge may be stored in the storage unit. In this case, after the sample stage is moved along the edge, the control unit further includes a step of polishing the entire edge while moving the sample stage using the edge position stored in the storage unit. May be.

  The sample is, for example, a silicon substrate on which a plurality of layers are stacked. In this case, the edge may be a cleavage plane of the silicon substrate.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor substrate,
Forming a connection hole in the insulating film;
Using a semiconductor manufacturing apparatus, embedding a conductor in the connection hole;
Cleaving the semiconductor substrate;
Confirming that the cleavage plane passes through the connection hole and the conductor;
Observing the cross section with a microscope to confirm the embeddability of the conductor;
Adjusting the operating conditions of the semiconductor manufacturing apparatus when the embeddability of the conductor is poor, and
A step of manufacturing a semiconductor device using the semiconductor manufacturing apparatus in which operating conditions are adjusted;
Comprising
The step of confirming the cleavage plane is as follows:
Placing the semiconductor substrate on a sample stage movable in a plane, and positioning one end of the cleavage plane within the imaging area of the imaging device;
While causing the calculation unit to detect the cleavage plane based on the brightness difference in the image captured by the imaging device, the control unit detects that the one end to the other end of the cleavage plane is within the imaging area based on the detection result. Moving the sample stage to pass through;
It comprises.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a schematic side view of a sample edge processing apparatus according to the first embodiment of the present invention, and FIG. 1B is a schematic plan view of the sample edge processing apparatus. This sample edge processing apparatus is an apparatus for observing and polishing the cleavage surface 2 a of the silicon substrate 2 placed on the sample stage 10. A holding jig 10 a for holding the silicon substrate 2 is assembled on the upper surface of the sample stage 10. The sample stage 10 is mounted on a driving device 12, and is moved on the driving device 12 in a plane, that is, in the X-axis direction and the Y-axis direction by the driving device 12, respectively. The driving device 12 is controlled by the arithmetic control unit 24. Note that the surface of the driving device 12 is, for example, black. For this reason, when viewed from above, the silicon substrate 2 and the driving device 12 have a large difference in brightness at the cleavage plane 2a.

  The silicon substrate 2 is formed with a TEG for confirming the embedding property of a wiring layer, a W plug, etc., and a TEG for confirming the dimensions of the wiring, and the cleavage plane 2a passes through these TEGs. Is formed.

  A polishing device 14 is attached on the driving device 12. The polishing apparatus 14 is an apparatus for polishing the cleaved surface 2 a of the silicon substrate 2, and is controlled by the arithmetic control unit 24.

At a position above the driving device 12 and not overlapping with the silicon substrate 2, a light source 16 and a mirror 21 are provided.
And the imaging device 22 is arrange | positioned and the half mirrors 18 and 20 are arrange | positioned in this order above the cleavage surface 2a of the silicon substrate 2. FIG. The half mirror 18 and the light source 16 are located at the same height, and the half mirror 20 and the mirror 21 are located at the same height.

  The light source 16 emits light to the imaging range of the imaging device 22 via the half mirror 18. An image of a predetermined range including the cleavage plane 2a of the silicon substrate 2 is sent to the imaging device 22 via the half mirrors 18 and 20 and the mirror 21, and the imaging device 22 captures this image. In addition, from the half mirror 20, the image of the predetermined range containing the cleavage plane 2a is also sent to the direction (direction shown by arrow A) different from the mirror 21, and it can confirm the image visually. . In the direction of arrow A, a lens system for enlarging the image may be provided.

  The imaging device 22 outputs the captured image to the arithmetic control unit 24. The arithmetic control unit 24 detects a portion where the brightness contrast is a certain value or more from the captured image, and recognizes the detected portion as the cleavage plane 2 a of the silicon substrate 2. Then, based on the position of the cleavage plane 2a in the image and the position of the sample stage 10 on the driving device 12, the position of the entire cleavage plane 2a is calculated, and the calculated position is stored in the storage unit 24a.

  FIG. 2 is a flowchart showing the operation of the sample edge processing apparatus. First, the silicon substrate 2 is prepared. A TEG is formed in advance on the silicon substrate 2 by the following steps.

  First, a polysilicon film or an Al alloy film is formed on the silicon substrate 2 using a CVD apparatus or a sputtering apparatus. Next, a resist pattern is formed on the polysilicon film or the Al alloy film, and the polysilicon film or the Al alloy film is etched using an etching apparatus using the resist pattern as a mask. As a result, a TEG for confirming the dimensions of the wiring is formed on the silicon substrate 2.

  Next, a silicon oxide film is formed on the formed TEG and the silicon substrate 2 using a CVD apparatus. Next, a resist pattern is formed on the silicon oxide film, and the silicon oxide film is etched using an etching apparatus using the resist pattern as a mask. Thereby, a plurality of connection holes are formed in the silicon oxide film. Next, using a sputtering apparatus, a conductor is deposited on the silicon oxide film and in each of the plurality of connection holes. Thereby, a TEG for confirming the embedding property of the wiring layer, the W plug, or the like is formed.

  Then, the operator cleaves the silicon substrate 2 so that the cleaved surface 2a passes through the TEG, and fixes the cleaved silicon substrate 2 to the sample stage 10 using the holding jig 10a (S2). Then, by adjusting the position of the silicon substrate 2 on the sample table 10 or moving the sample table 10, one end of the cleavage surface 2 a (edge) of the silicon substrate 2 is positioned within the imaging area of the imaging device 22. (S4).

  Next, the arithmetic control unit 24 detects the position of the entire cleavage plane 2a by analyzing the image captured by the imaging device 22 while moving the sample stage 10 to the drive device 12, and the detected position is stored in the storage unit 24a. (S6). At this time, the operator visually observes the cleavage surface 2a and confirms whether the cleavage surface 2a passes through the target part.

  Next, the operator inputs the polishing amount of the cleavage plane 2a to the calculation control unit 24 via an input unit (not shown) such as a keyboard or a touch panel. This polishing amount may be uniform over the entire cleaved surface 2a, or may gradually change so that the angle of the cleaved surface 2a changes. Next, the calculation control unit 24 uses the input polishing amount and the position of the cleavage surface 2a stored in the storage unit 24a to generate a movement chart indicating how the sample stage 10 is moved during polishing. Calculate (S8). Next, the arithmetic control unit 24 drives the polishing apparatus 14 while moving the sample table 10 according to the calculated movement chart. Thereby, the cleavage surface 2a is polished (S10 in FIG. 2).

  The operator visually confirms that the cleavage plane 2a passes through the target portion. When it is determined that the cleavage plane 2a does not pass through the target portion, the operator performs the above-described processing (S4 to S10) again using the sample edge processing apparatus.

  Thereafter, the operator observes the cleaved surface 2a with an SEM, and confirms whether or not the embedability of the conductor in the connection hole is good and whether or not the dimensions of the wiring are as specified. When the embeddability is good and the wiring dimensions are as specified, the conductor deposition conditions of the CVD apparatus or the sputtering apparatus and the etching conditions of the etching apparatus are maintained as they are, and the semiconductor device is manufactured. If the embeddability is poor, the state of the CVD apparatus or sputtering apparatus is checked, or the conductor deposition conditions are changed, and then the above operation is performed again. If the dimensions of the wiring are not specified, the state of the exposure apparatus or the etching apparatus is confirmed, or the etching conditions of the exposure apparatus or the etching apparatus are changed, and then the above operation is performed again.

  Each drawing in FIG. 3 is a diagram for explaining in detail the method (S6 in FIG. 2) in which the calculation control unit 24 detects the position of the cleavage plane 2a. First, the arithmetic control unit 24 detects, as an edge, a portion of the image captured by the imaging device 22 that has a brightness contrast of a certain value or more. And the corner | angular part of an edge is recognized and this corner | angular part is judged as the one end part of the cleavage surface 2a. Then, using the position of one end in the image and the position of the sample stage 10 on the driving device 12, the position of one end of the cleavage plane 2a is calculated and stored in the storage unit 24a (FIG. 3A). ). Further, the edge extending in the Y-axis direction is determined as the cleavage plane 2a.

  Next, the arithmetic control unit 24 moves the sample stage 10 in the Y-axis direction while continuously detecting the portion where the brightness contrast is a certain value or more as the cleavage plane 2a (FIG. 3A). Then, the position of the cleavage plane 2a is continuously calculated using the position of the cleavage plane 2a in the image and the amount of movement of the sample stage 10 on the driving device 12, and the calculated position is stored in the storage unit 24a. Continue.

  At this time, when the cleavage plane 2a is inclined, the cleavage plane 2a is displaced from the center of the image by the imaging device 22 (dotted line in FIG. 3B). When the arithmetic control unit 24 detects that the cleavage plane 2a is deviated from the center of the image, it moves the sample table 10 also in the X-axis direction (indicated by a dotted arrow), and the cleavage plane 2a is positioned at the approximate center of the image. It should be positioned (solid line in FIG. 3B).

  While the operation described with reference to FIG. 3B is repeated, the other end portion of the cleavage plane 2a appears in the image (FIG. 3C). The arithmetic control unit 24 determines that the region where the brightness is a certain value or more is the silicon substrate 2 and determines that the region where the brightness is the certain value or less is a region where the silicon substrate 2 is not present. When the other end of the cleaved surface 2a appears in the image, the increasing speed of the region where the silicon substrate 2 does not exist is the product of the moving speed of the sample stage 10 in the Y-axis direction and the width of the image in the X-axis direction. Is equal to For this reason, the arithmetic control unit 24 detects the increasing speed of the region where the silicon substrate 2 does not exist, and determines whether or not the value is equal to the above-described product. It can be detected that the end has appeared.

If the calculation control part 24 detects the other end part of the cleavage surface 2a, it will memorize | store the position in the memory | storage part 24a, and complete | finishes the detection operation of the cleavage surface 2a.
In this way, the arithmetic control unit 24 automatically detects the entire cleavage surface 2a and stores the position in the storage unit 24a.

  FIG. 4 is a view for explaining the movement of the sample stage 10 when the cleavage surface 2a is being polished. The arithmetic control unit 24 moves the sample stage 10 along the cleavage surface 2a while bringing the cleavage surface 2a into contact with the polishing plate of the polishing apparatus 14. As a result, the cleaved surface 2a of the silicon substrate 2 on the sample stage 10 is polished by the inputted polishing amount, and the cross section of the target portion is exposed to the cleaved surface 2a.

  As described above, according to the sample edge processing apparatus according to the first embodiment of the present invention, the arithmetic control unit 24 allows the one end to the other end of the cleavage surface 2 a of the silicon substrate 2 to be within the imaging range of the imaging device 22. Next, the sample stage 10 is moved along the cleavage plane 2a. For this reason, even if an operator does not move the sample stand 10, he can confirm whether the cleavage surface 2a is passing the target site | part.

  Further, the arithmetic control unit 24 causes the storage unit 24a to store the position of the cleavage plane 2a when moving the sample stage 10 along the cleavage plane 2a. For this reason, the arithmetic control unit 24 drives the polishing apparatus 14 while moving the sample table 10 along the position of the cleavage surface 2a stored in the storage unit 24a. The amount can be polished. Therefore, the cleaved surface 2a can be accurately polished with little effort.

  Further, since the calculation control unit 24 detects a portion where the brightness contrast is a certain value or more as an edge, the amount of calculation required for edge detection may be small.

  FIG. 5 is a plan view of a sample edge processing apparatus according to the second embodiment of the present invention. This sample edge processing apparatus is different from the first embodiment in that the polishing apparatus 14 has a plurality of polishing plates. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In this embodiment, the polishing apparatus 14 has a roughing polishing plate 14a and a finishing polishing plate 14b. The roughing polishing plate 14a is positioned above the finishing polishing plate 14b in the Y-axis direction. When the polishing apparatus 14 polishes the cleaved surface 2a of the silicon substrate 2, the roughing polishing plate 14a first polishes the cleaved surface 2a, and then the finishing polishing plate 14b polishes the cleaved surface 2a. Other operations of the sample edge processing apparatus are the same as those in the first embodiment.
Also in this embodiment, the same effect as the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A) is a schematic side view of the sample edge processing apparatus according to the first embodiment, and (B) is a schematic plan view of the sample edge processing apparatus. The flowchart which shows operation | movement of a sample edge processing apparatus. Each figure is a diagram for explaining S6 in FIG. 2 in detail. The figure for demonstrating the motion of the sample stand 10 when the cleavage surface 2a is grind | polished. The top view of the sample edge processing apparatus which concerns on 2nd Embodiment. The top view of the silicon substrate which has TEG. (A) is a figure for demonstrating the observation method of the conventional sample, (B) is a figure for demonstrating the method to fix a sample to a sample holder.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2,100 ... Silicon substrate, 2a, 100a ... Cleaving surface, 10 ... Sample stand, 10a ... Holding jig, 12 ... Driving device, 14 ... Polishing device, 14a, 14b ... Polishing plate, 16 ... Light source, 18, 20 ... Half mirror, 21 ... mirror, 22 ... imaging device, 24 ... calculation control unit, 24a ... storage unit, 101, 102 ... TEG

Claims (12)

A sample stage on which the sample is placed;
A drive unit for moving the sample stage in a plane;
An imaging unit for imaging the edge of the sample on the sample stage;
A calculation unit for detecting the edge based on a brightness difference in an image captured by the imaging unit;
Using the detection result of the arithmetic unit, a control unit that moves the sample stage to the drive unit so that one end to the other end of the edge passes through the imaging area of the imaging unit;
A sample edge processing apparatus comprising:   2. The sample edge processing apparatus according to claim 1, wherein the calculation unit determines that a portion having a lightness contrast in the image having a certain value or more is the edge.   The sample edge processing apparatus according to claim 1, further comprising a polishing unit that polishes the edge. A storage unit that stores the position of the edge detected by the calculation unit;
The control unit moves the sample stage so that the edge moves along the polishing unit using the position of the edge stored in the storage unit while operating the polishing unit. The sample edge processing apparatus according to claim 3, wherein the entire edge is polished. In the image, the sample has a higher brightness than the part where the sample does not exist,
The control unit determines that an edge end portion of the sample has entered the image when an increasing speed of an area having a lightness lower than that of the sample in the image is equal to or higher than a predetermined value. Item 5. The sample edge processing apparatus according to any one of Items 1 to 4.   The sample edge processing apparatus according to any one of claims 1 to 5, further comprising an optical mechanism for visually confirming an image of an imaging area of the imaging apparatus. Positioning one end of the edge of the sample placed on the sample stage within the imaging area of the imaging device;
While causing the calculation unit to detect the edge based on the brightness difference in the image captured by the imaging device, the control unit passes through the imaging area from one end of the edge to the other end based on the detection result. The step of moving the sample stage,
A sample edge processing method comprising:   The sample edge processing method according to claim 7, wherein the position of the edge is stored in a storage unit in the step of moving the sample stage while detecting the edge.   After the sample stage is moved along the edge, the control unit polishes the entire edge while moving the sample stage using the position of the edge stored in the storage unit The sample edge processing method according to claim 8, further comprising:   The sample edge processing method according to any one of claims 7 to 9, wherein the sample is a silicon substrate on which a plurality of layers are stacked.   The sample edge processing method according to claim 10, wherein the edge is a cleavage plane of the silicon substrate. Forming an insulating film on the semiconductor substrate;
Forming a connection hole in the insulating film;
Using a semiconductor manufacturing apparatus, embedding a conductor in the connection hole;
Cleaving the semiconductor substrate;
Confirming that the cleavage plane passes through the connection hole and the conductor;
Observing the cleavage plane with a microscope to confirm the embedding property of the conductor;
Adjusting the operating conditions of the semiconductor manufacturing apparatus when the embeddability of the conductor is poor, and
A step of manufacturing a semiconductor device using the semiconductor manufacturing apparatus in which operating conditions are adjusted;
Comprising
The step of confirming the cleavage plane is as follows:
Placing the semiconductor substrate on a sample stage movable in a plane, and positioning one end of the cleavage plane within the imaging area of the imaging device;
While causing the calculation unit to detect the cleavage plane based on the brightness difference in the image captured by the imaging device, the control unit determines that the one end to the other end of the cleavage plane is within the imaging area based on the detection result. Moving the sample stage to pass through;
A method for manufacturing a semiconductor device comprising:

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