JP2006114568A - Method for forming through electrode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a through electrode penetrating a semiconductor substrate in a direction of its width by which the number of steps can be reduced and step control be eased. <P>SOLUTION: The method for forming a through electrode includes a first step to form an etching mask 12 on one surface of a semiconductor substrate 10, and an etching stop layer 11 on the other surface thereof respectively; a second step to etch an area of the substrate 10 exposing from an opening 13 formed in the etching mask 12 up to the etching stop layer 11 so as to form a recessed part 14; a third step to form an insulating film 11a on the internal surface of the recessed part 14 and one surface of the substrate 10, and to form a conductor 15 in the recessed part 14 thereafter; a fourth step to form a first wiring conductor 16a connected electrically with the conductor 15 on one surface of the substrate 10, and to make an opening 18 in the etching stop layer 11 comprising the bottom surface of the recessed part 14 so as to exposed the conductor 15 thereafter; and a fifth step to form a second wiring conductor 17a connected electrically with the conductor 15 exposing from the opening 18. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming a through electrode penetrating in a thickness direction of a semiconductor substrate.

  Conventionally, a method of forming a through electrode penetrating in the thickness direction of a semiconductor substrate such as silicon, gallium arsenide, indium phosphide, or the like on which an integrated circuit or the like is formed is known (for example, see Patent Document 1). In such a method of forming a through electrode, the key point is how to make a structure that insulates the electrode from the semiconductor substrate. A conventional example will be described with reference to FIG.

  As shown in FIGS. 9A and 9B, an etching mask 91 is formed on one surface (upper surface) of the semiconductor substrate 10 made of a semiconductor, and a recess 93 that does not penetrate the semiconductor substrate 10 through the opening 92 is formed. . The concave portion 93 is formed by laser processing or the like in addition to etching processing. Thereafter, the etching mask 91 is removed, and as shown in FIGS. 9C and 9D, the upper surface of the semiconductor substrate 10 and the inner surface of the recess 93 are made of silicon oxide, silicon nitride, or the like by CVD or thermal oxidation. An insulating film 94 is deposited, and a seed layer 96a for plating is formed on the insulating film 94. Next, as shown in FIG. 9E, a metal 96 such as a plating layer such as copper is deposited on the seed layer 96 a, and the recess 93 is filled with the insulating film 94 and the metal 96. Thereafter, as shown in FIGS. 9F and 9G, the upper surface of the semiconductor substrate 10 is flatly polished by CMP (Chemical Mechanical Polishing) or the like, and a conductor 95a is deposited on the surface by a sputtering film forming method or the like. .

Thereafter, as shown in FIGS. 9H, 9I, and 9J, the back surface (lower surface) is polished by CMP or the like to expose the insulating film 94 on the lower surface, and the lower surface of the semiconductor substrate 10 is etched back. After a portion of the insulating film 94 protrudes from the lower surface (thereby, the recess 93 becomes a through hole), an insulating film 97 is formed on the lower surface. Thereafter, as shown in FIGS. 9 (k) and 9 (l), both the insulating film 97 on the lower surface and the insulating film 94 constituting the bottom surface of the recess 93 are etched to form an opening 98, exposing the metal 96, and sputtering. A conductor 99a is deposited on the lower surface by a film forming method or the like. Finally, the conductors 95a and 99a are patterned to form the electrodes 95 and 99 as shown in FIG. 9 (m). These surface electrodes 95, the metal 96 in the recessed portion 93 penetrated, and the bottom electrode 99, a through electrode penetrating the semiconductor substrate 10 in the thickness direction is formed.
JP 2003-243396 A

  However, in the method of forming the through electrode as shown in FIG. 9 and Patent Document 1 described above, the depth of the recess processed into the semiconductor substrate is set to a value smaller than the thickness of the substrate, and therefore, the substrate is prevented from penetrating. It is necessary to. In this case, when the insulating film of the shallowest concave portion is exposed due to the variation in the depth of the concave portion, the insulating film is also polished in the deepest concave portion, so that the metal inside the concave portion is exposed and the semiconductor substrate is exposed. There is a problem that a sufficient insulation distance cannot be secured, and there are a large number of processes and a problem that process management is difficult.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a through electrode penetrating in the thickness direction of a semiconductor substrate, which can reduce the number of processes and can be easily managed.

  To achieve the above object, according to a first aspect of the present invention, in the method for forming a through electrode penetrating in a thickness direction of a semiconductor substrate, an etching mask is formed on one surface of the semiconductor substrate, and the semiconductor is formed on the other surface. A first step of forming an etching stop layer having an etching rate different from that of the substrate, and a predetermined position of the etching mask is opened, and a region of the semiconductor substrate exposed through the opening is etched to the etching stop layer to form a recess. A second step of forming an insulating film on the inner surface of the recess and one surface of the semiconductor substrate, and then forming a conductor in at least the recess, and the first step on the one surface of the semiconductor substrate. After forming the first wiring conductor electrically connected to the conductor, the etching stop layer constituting the bottom surface of the recess is formed on the other side of the semiconductor substrate. A fourth step of opening the recess to expose the conductor, and forming a second wiring conductor electrically connected to the exposed conductor on the other surface of the semiconductor substrate. A through electrode is formed by the first wiring conductor, the conductor, and the second wiring conductor.

  According to a second aspect of the present invention, in the method for forming a through electrode according to the first aspect, in the fourth step, after the conductor is exposed, the conductor is at least flush with the surface of the etching stop layer. It includes a step of extending by electroplating until it becomes.

  According to a third aspect of the present invention, in the method for forming a through electrode according to the first aspect, in the fourth step, after exposing the conductor, the conductor is at least flush with the surface of the etching stop layer. It includes a step of extending by electroless plating until it becomes.

  According to a fourth aspect of the present invention, in the method for forming a through electrode according to the first aspect, in the fifth step, the second wiring conductor is formed by electroplating or electroless plating.

  According to a fifth aspect of the present invention, in the method of forming a through electrode penetrating in the thickness direction of the semiconductor substrate, an etching mask is formed on one surface of the semiconductor substrate, and an etching rate different from that of the semiconductor substrate is formed on the other surface. A first step of forming a stop layer; a second step of opening a predetermined position of the etching mask; and etching a region of the semiconductor substrate exposed through the opening to the etching stop layer to form a recess; and the recess An insulating film is formed on the inner surface of the semiconductor substrate and one surface of the semiconductor substrate, and then a third step of forming a conductor in at least the concave portion is electrically connected to the conductor on one surface of the semiconductor substrate. After forming the first wiring conductor, the second wiring conductor is formed on the other surface of the semiconductor substrate, and the etching stop layer constituting the bottom surface of the recess is formed. Etching together with the second wiring conductor from the other surface of the semiconductor substrate, opening the recess to expose the conductor, and exposing the exposed conductor and the first on the other surface of the semiconductor substrate. A fifth step of electrically connecting two wiring conductors, and forming a through electrode by the first wiring conductor, the conductor, and the second wiring conductor.

  According to a sixth aspect of the invention, in the through electrode forming method according to the fifth aspect, in the fourth step, the second wiring conductor is used as an etching mask for etching the etching stop layer.

  A seventh aspect of the invention is the method for forming a through electrode according to any one of the first to sixth aspects, wherein the first step includes a step of laminating a reinforcing film that reinforces the etching stop layer.

  According to the invention of claim 1, by providing the etching stop layer made of an insulating film having an etching rate smaller than that of the semiconductor substrate, the etching in the etching stop layer can be stopped after the etching of the semiconductor substrate is completed. This process management becomes easy, a through hole can be formed in the semiconductor substrate body without penetrating the etching stop layer, and the problem of variation in the depth of the recess for forming the through electrode structure is also eliminated. In addition, since the insulating film for forming the bottom of the recess can be formed by the etching stop layer, the polishing process for exposing the insulating film of the recess in the conventional example can be reduced, and the cost for forming the through electrode can be reduced. Can be planned. Further, since the insulating film in the recess is not a structure as in the conventional example in which the insulating film protrudes outside the semiconductor substrate, such a protruding portion is not formed on the other surface of the semiconductor substrate, and the substrate surface can be made substantially flat. There is an effect that mounting and lamination are simplified.

  According to the invention of claim 2 or claim 3, when forming the electrode that is electrically connected to the conductor in the recess exposed by opening the insulating film, the opening of the insulating film is previously electroplated or electrolessly plated. Thus, the conductor is extended and buried, so that reliable electrical connection can be achieved with good coverage to the opening structure of the insulating film, and the electrode formed here can be a flat electrode.

  According to the invention of claim 4, since the electroplating or electroless plating is used for forming the second wiring conductor, the wiring structure can be used for wiring under reliable electrical connection with good coverage with respect to the opening structure of the insulating film. A conductor layer can be formed. With such a conductor layer, a flat electrode of an arbitrary size can be formed, and a wiring and an electrode can be formed simultaneously. Further, by limiting the formation of the second wiring conductor to the periphery of the opening of the insulating film, the shape of the surface electrode constituting the through electrode can be changed to the bump shape without patterning the second wiring conductor, and the bump forming step can be performed. It is possible to reduce.

  According to the invention of claim 5, the same effect as that of the invention of claim 4 is produced.

  According to the invention of claim 6, it is not necessary to separately provide an etching mask for etching the etching stop layer, so that the number of processes can be reduced, and the opening in which the opening of the second wiring conductor is aligned with the opening position is provided with the insulating film. Can be provided.

  According to the invention of claim 7, damage to the etching stop layer after forming the recess can be prevented, and the yield of forming the through electrode can be improved.

  Hereinafter, a method of forming a through electrode penetrating in the thickness direction of the semiconductor substrate of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment will be described with reference to FIGS. 1 and 2. In the first embodiment, in the first step (S1, FIGS. 2A and 2B), the etching stop layer 11 and the etching mask 12 are formed on the semiconductor substrate 10, and the second step (S2, FIG. 2C). )), The recess 14 is formed in the semiconductor substrate 10 up to the etching stop layer 11, and in the third step (S3, FIGS. 2D and 2E), the insulating film 11a and the conductor 15 are embedded in the recess 14 in the fourth step. In (S4, FIGS. 2 (f) to (h)), the conductor 15 is exposed to the opening 18 on the bottom surface of the recess 14. In the fifth step (S5, FIGS. 2 (i) and (j)), the conductor 15 and the second The wiring conductor 17a is connected to form a through electrode. Next, each step will be described.

  In the first step (S1), as shown in FIG. 2A, an etching stop layer 11 having an etching rate different from that of the semiconductor substrate 10 is formed on both surfaces of the semiconductor substrate 10 using silicon, gallium arsenide, indium phosphide, or the like as a substrate material. For example, an insulating film such as an oxide film or a nitride film is deposited by a thermal oxidation method or a CVD method. In this case, since the insulating film functions as the etching stop layer 11, the etching rate of the insulating film is set to be smaller than the etching rate of the semiconductor substrate 10. The etching stop layer 11 may be formed at least on the other surface (the lower surface in the figure) of the semiconductor substrate 10 for the purpose of use. However, as in the case where the thermal oxidation method is used, the etching stop layer 11 is formed. The same layer as the etching stop layer 11 may be formed on the entire surface. Next, as shown in FIG. 2B, an etching mask 12 is formed on one surface of the semiconductor substrate 10 (upper side surface in the figure), and the insulating film is removed through patterning and etching, thereby removing the semiconductor substrate. An opening 13 is formed at a position where a through electrode penetrating in the thickness direction of 10 is formed.

  In the second step (S2), as shown in FIG. 2C, the thickness of the semiconductor substrate 10 is etched by etching the region of the semiconductor substrate 10 exposed through the opening 13 up to the etching stop layer 11 made of an insulating film on the back surface. A plurality of recesses 14 having the same depth as that are formed as necessary. The recess 14 penetrates as far as the semiconductor substrate 10 is concerned, and has a structure in which the through hole is closed with an insulating film.

  In the third step (S3), as shown in FIG. 2D, the etching mask is removed by an ashing (ashing) method or the like, and silicon oxide, silicon nitride, or the like is formed on the side wall and bottom surface of the recess 14 by a CVD method or the like. An insulating film 11a is deposited. Next, as shown in FIG. 2 (e), at least the recesses 14 are made of aluminum, copper, gold, silver, palladium, titanium, niobium, by sputtering, vacuum deposition, plating, plasma spraying, or the like. A conductor 15 such as is deposited. In this case, for example, in the case of a plating method, a seed layer is formed by a sputtering method, a vacuum evaporation method, or the like, and then a plating process is performed. In order to fill the recess 14 with metal, it is desirable to employ a plating process. Such a plating method is disclosed in, for example, U.S. Pat. No. 5421987 and U.S. Pat. No. 6,136,707. The Jets Technology is designed so that the plating rate is accelerated in a fine hole and the plating rate is suppressed on a flat surface. The plating technology called can be applied.

  In the fourth step (S4), as shown in FIG. 2 (f), one surface of the semiconductor substrate 10 is planarized by a planarization method such as a CMP (Chemical Mechanical Polishing) method or the like (insulating film 11a). Alternatively, the conductor 15 is polished so that the insulating film formed during the formation of the etching stop layer 11 is exposed. Next, as shown in FIG. 2G, a metal film is deposited on one surface of the flattened semiconductor substrate 10 so as to be electrically connected to the conductor 15 in the recess 14 by a metal sputtering method or the like. Thus, the first wiring conductor 16a is formed. Thereafter, as shown in FIG. 2 (h), the insulating film (insulating film 11a and etching stop layer 11) constituting the bottom surface of the recess 14 is processed from the other surface of the semiconductor substrate 10 by etching, laser processing, or the like. An opening 18 is formed, and the recess 14 is opened to expose the conductor 15.

  In the fifth step (S5), as shown in FIG. 2I, a metal film is deposited on the other surface of the semiconductor substrate 10 by a metal sputtering method or the like, and the conductor 15 in the recess 14 exposed through the opening 18 is obtained. The second wiring conductor 17a electrically connected to is formed. Thereafter, as shown in FIG. 2J, the first wiring conductor 16a on one surface of the semiconductor substrate 10 and the second wiring conductor 17a on the other surface are patterned by metal RIE (reactive ion etching) or the like. By performing the treatment, a through electrode by the first electrode 16, the conductor 15 in the recess 14, and the second electrode 17 is completed.

(Second Embodiment)
A second embodiment will be described with reference to FIGS. The 1st thru | or 3rd process (S11-S13) in 2nd Embodiment is the same as the 1st thru | or 3rd process (S1-S3) in the above-mentioned 1st Embodiment, and abbreviate | omits description. In the second embodiment, in the fourth step (S14, FIGS. 4A and 4B), the conductor 15 is exposed to the opening 18 on the bottom surface of the recess 14 and then the conductor 15 is extended. 15a is formed, and in the fifth step (S15, FIGS. 4C and 4D), the extended conductor 15a and the second wiring conductor are connected to form a through electrode. Next, each step will be described.

  In the fourth step (S14), as shown in FIG. 4A, the recess 14 is opened and the conductor 15 is exposed from the opening 18 in the same manner as described above. Next, as shown in FIG. 4B, at least the etching stop layer 11 is flattened by performing electroplating using the conductor 15 on the bottom surface of the exposed recess 14 as a seed, or performing electroplating using the conductor 15 as a cathode. The conductor 15 in the recess 14 is extended until it is flush with the outer surface.

  In the fifth step (S15), as shown in FIG. 4C, a metal film is deposited on the other surface of the semiconductor substrate 10 by metal sputtering or the like, and the conductor 15 in the recess 14 exposed by the opening 18 is obtained. The second wiring conductor 17a electrically connected to is formed. Thereafter, as shown in FIG. 4D, the first wiring conductor 16a on one surface of the semiconductor substrate 10 and the second wiring conductor 17a on the other surface are patterned by metal RIE (reactive ion etching) or the like. By performing the treatment, a through electrode by the first electrode 16, the conductor 15 in the recess 14, and the second electrode 17 is completed. Thus, when forming the electrode electrically connected to the conductor 15 in the recess 14, the opening 18 of the insulating film is filled in advance with the extended conductor 15a by electroplating or electroless plating, so it is formed here. The second electrode 17 can be a flat electrode.

(Third embodiment)
A third embodiment will be described with reference to FIG. The first half of the steps in the third embodiment is the same as the first to third steps (S1 to S3) in the first embodiment described above, and a description thereof is omitted. In the subsequent steps of the third embodiment, as shown in FIG. 5A, the recess 14 is opened and the conductor 15 is exposed from the opening 18 as described above. Next, as shown in FIG. 5B, electrolytic plating is performed using the conductor 15 on the bottom surface of the exposed recess 14 as a seed, or electroplating is performed using the conductor 15 as a cathode, and the conductor 15 is extended to the outside. And the second electrode 19 is formed.

  That is, in the third embodiment, the fourth step and the fifth step in the second embodiment described above are completed in one step. According to such a method, by forming the second wiring conductor only in the vicinity of the opening of the insulating film, the shape of the surface electrode constituting the through electrode can be changed to the bump shape without patterning the second wiring conductor. It is possible to reduce the bump forming process. If the relationship between the stacking thickness a of the second electrode 19 and the overlap amount b on the insulating film is substantially equal to a≈b, the outer dimension c of the second electrode 19 can be set to the optimum dimension.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIGS. The 1st thru | or 3rd process (S21-S23) in 4th Embodiment is the same as the 1st thru | or 3rd process (S1-S3) in the above-mentioned 1st Embodiment, and abbreviate | omits description. In the fourth embodiment, after forming the first wiring conductor 16a and the second wiring conductor 17a in the fourth step (S24, FIGS. 4A to 4D), the etching stop layer 11 ( Insulating film) and the second wiring conductor 17a are opened to expose the conductor 15, and in the fifth step (S25, FIG. 4 (e) (f)), the conductor 15 and the second wiring conductor 17a are connected and penetrated. An electrode is formed. Next, each step will be described.

  In the fourth step (S24), as shown in FIG. 7A, metal sputtering is performed on one surface of the flattened semiconductor substrate 10 by the same step up to FIG. 2G of the first embodiment. A first wiring conductor 16a is formed by depositing a metal film so as to be electrically connected to the conductor 15 in the recess 14 by a method or the like. Thereafter, as shown in FIG. 7B, a second wiring conductor 17a is formed on the back surface by a metal sputtering method or the like. Thereafter, as shown in FIG. 7C, the second wiring conductor 17a is etched by metal RIE or the like to pattern the second electrode 17 and the wiring (not shown). At this time, an opening 18a is formed in the central portion of the second electrode, and the etching stop layer 11 immediately below the recess 14 is exposed. After that, as shown in FIG. 7D, the conductor 15 is exposed from the opening 18 at the bottom of the recess 14 by etching the etching stop layer 11 using the opening 18a of the second electrode as an etching mask.

  In the fifth step (S25), as shown in FIG. 7E, the electroplating is performed using the conductor 15 exposed from the opening 18 as a seed, or the electroplating is performed using the conductor 15 as a cathode. And the second electrode 17 are electrically connected by plating metal. Thereafter, as shown in FIG. 7F, the first wiring conductor 16a on one surface of the semiconductor substrate 10 is etched by metal RIE or the like to form the first electrode 16 and a wiring pattern (not shown). Thereby, a through electrode composed of the first electrode 16, the conductor 15 in the recess 14, and the second electrode 17 is completed. According to such a manufacturing method, it is not necessary to separately provide an etching mask for etching the etching stop layer 11, so that the number of processes can be reduced, and an opening in which the opening of the second wiring conductor is aligned with the opening position is formed in the insulating film. Can be provided.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. The fifth embodiment is substantially the same as the above-described first embodiment except that a process of laminating a reinforcing film 21 is further added after the formation of the etching stop layer 11 shown in FIG. 2A of the first embodiment. This is the same as the first embodiment. That is, in the fifth embodiment, in the first step (FIGS. 8A to 8C), reinforcement for reinforcing the etching stop layer 11 on the etching stop layer 11 formed on the other surface of the semiconductor substrate 10 is performed. A film 21 is stacked and an etching mask 12 is formed on one surface of the semiconductor substrate 10. In the second step (FIG. 8D), a recess 14 is formed in the semiconductor substrate 10 up to the etching stop layer 11. In the step (FIGS. 8E and 8F), the insulating film 11a and the conductor 15 are embedded in the concave portion 14, and in the fourth step (FIGS. 8G to 8I), the etching stop layer 11 and the reinforcement are formed on the bottom surface of the concave portion 14. An opening 18 is formed through the film 21, and the conductor 15 is exposed through the opening 18. In the fifth step (FIGS. 8 (j) and (k)), the conductor 15 and the second wiring conductor 17a are connected. Form a through electrode

  As the above-described reinforcing film 21, for example, an insulating film, a polysilicon film, a metal film, or the like formed by a CVD method or the like can be used. Other details are substantially the same as those described in the first embodiment, and a description thereof will be omitted. By using such a reinforcing film 21, it is possible to prevent the etching stop layer 11 from being damaged after the recess 14 is formed, and to improve the yield of through electrode formation. The present invention is not limited to the above-described configuration, and various modifications can be made. For example, the recess 14 may be filled with a conductive paste and cured, and the cured conductive paste may be used as the conductor 15.

The flowchart regarding the formation method of the penetration electrode which concerns on one Embodiment of this invention. (A)-(j) is a board | substrate sectional drawing of the through-hole part in the main stage explaining the formation method of a penetration electrode same as the above. The flowchart regarding the formation method of the penetration electrode which concerns on other embodiment of this invention. (A)-(d) is a board | substrate sectional drawing of the through-hole part in the main stage explaining the formation method of a penetration electrode same as the above. (A)-(b) is a board | substrate sectional drawing of the through-hole part in the main stage explaining the formation method of the through-electrode which concerns on further another embodiment of this invention. The flowchart regarding the formation method of the penetration electrode concerning other embodiments of the present invention. (A)-(f) is a board | substrate sectional drawing of the through-hole part in the main stage explaining the formation method of a penetration electrode same as the above. (A)-(k) is a board | substrate sectional drawing of the through-hole part in the main stage explaining the formation method of the through-electrode which concerns on further another embodiment of this invention. (A)-(m) is a board | substrate sectional drawing of the through-hole part in the main stage explaining the formation method of the conventional penetration electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Etching stop layer 12 Etching mask 13 Opening 14 Recess 15 Conductor 18 Opening 21 Reinforcing film 11a Insulating film 16a First wiring conductor 18a Opening

Claims (7)

In the formation method of the through electrode penetrating in the thickness direction of the semiconductor substrate,
A first step of forming an etching mask on one surface of the semiconductor substrate and forming an etching stop layer having an etching rate different from that of the semiconductor substrate on the other surface;
A second step of opening a predetermined position of the etching mask and etching a region of the semiconductor substrate exposed through the opening to the etching stop layer to form a recess;
A third step of forming a conductor in at least the recess after forming an insulating film on the inner surface of the recess and one surface of the semiconductor substrate;
After forming the first wiring conductor electrically connected to the conductor on one surface of the semiconductor substrate, the etching stop layer constituting the bottom surface of the recess is etched from the other surface of the semiconductor substrate, A fourth step of opening the recess to expose the conductor;
Forming a second wiring conductor electrically connected to the exposed conductor on the other surface of the semiconductor substrate, the first wiring conductor, the conductor, and the second wiring conductor A method for forming a through electrode, comprising forming the through electrode.   2. The through electrode according to claim 1, wherein the fourth step includes a step of extending the conductor by electroplating until the conductor is at least flush with a surface of the etching stop layer after exposing the conductor. Forming method.   The through electrode according to claim 1, wherein the fourth step includes a step of extending the conductor by electroless plating until the conductor is at least flush with the surface of the etching stop layer after exposing the conductor. Forming method.   The method for forming a through electrode according to claim 1, wherein in the fifth step, the second wiring conductor is formed by electroplating or electroless plating. In the formation method of the through electrode penetrating in the thickness direction of the semiconductor substrate,
A first step of forming an etching mask on one surface of the semiconductor substrate and forming an etching stop layer having an etching rate different from that of the semiconductor substrate on the other surface;
A second step of opening a predetermined position of the etching mask and etching a region of the semiconductor substrate exposed through the opening to the etching stop layer to form a recess;
A third step of forming a conductor in at least the recess after forming an insulating film on the inner surface of the recess and one surface of the semiconductor substrate;
A first wiring conductor electrically connected to the conductor is formed on one surface of the semiconductor substrate, and then a second wiring conductor is formed on the other surface of the semiconductor substrate to constitute the bottom surface of the recess. Etching the etching stop layer from the other surface of the semiconductor substrate together with the second wiring conductor, opening the recess and exposing the conductor;
A fifth step of electrically connecting the exposed conductor and the second wiring conductor on the other surface of the semiconductor substrate, wherein the first wiring conductor, the conductor, and the second wiring conductor serve as a through electrode. Forming a through electrode.   6. The through electrode forming method according to claim 5, wherein, in the fourth step, the second wiring conductor is used as an etching mask for etching the etching stop layer.   The through electrode formation method according to claim 1, wherein the first step includes a step of laminating a reinforcing film that reinforces the etching stop layer.

Images