JP2006113278A - Apparatus and method for inspecting mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and a method for inspecting a mask capable of reducing the possibility of the occurrence of an off-specified mask caused by a measurement result of such an inspection spot as to hardly influence device characteristics as a matter of fact in mask inspection. <P>SOLUTION: A preprocessing part 51 inputs information for each region such as an operational frequency (Ifreq.) from a layout design device 1, a dummy pattern information (Idummy1), an operational margin (Imargin) from a timing verification device 2 and a dummy pattern information (Idummy2) from a mask data processing device 3. The preprocessing part 51 sets at least one side of precedence and specification of inspection by using the information for each region and selects the inspection spot from the region of the order in accordance with the precedence. An inspection decision part 52 inspects the inspection spot, based on the specification for each region, indicates a specification nonconformity part of the mask and determines the acceptability. The inspection spot to be inspected which conforms the operational frequency corresponding to a device in a mask region is selected and an inspection with appropriate severity for each region is conducted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inspection apparatus and an inspection method for inspecting a pattern of a mask used for manufacturing a semiconductor device.

  In manufacturing a mask used in manufacturing a semiconductor device (IC), pattern data (layout design data) designed by CAD or the like is converted into mask data, and a pattern based on the mask data is converted into an electron beam or ion beam. It transfers to the photosensitive layer formed on the light shielding film of a glass substrate. The pattern of the photosensitive layer is resolved and transferred to the light shielding layer by etching, whereby a mask is manufactured.

Along with miniaturization of semiconductor devices, high precision of pattern transfer onto a wafer is required, and high quality is also required for a mask that is a transfer source.
The quality of the mask is important because it is determined by items such as the positional accuracy, dimensional accuracy, uniformity, and presence / absence of defects of the pattern of the light shielding layer, and determines the reliability and characteristics of the semiconductor device using the mask. The completed mask is subjected to a strict inspection in an inspection process to ensure high quality, and a pass / fail determination is made based on the result, and a mask that passes this determination is used for manufacturing a semiconductor device.

Mask defect inspection methods using image processing include Die-to-die and Die-to-database (“Design Data Comparison”) methods. Is known (see, for example, Patent Document 1).
In the die-to-die method, an optical image of the same pattern is examined between portions corresponding to two chips on one mask, and the pattern is detected by a predetermined optical detection means and a predetermined light receiving element. By comparing the data of the two patterns by a predetermined data comparison processing algorithm and examining the difference between them, the presence or absence of a pattern deviation, a defect, etc. is examined. This method has a drawback in that if there is a defect at the same position, it is not recognized as a defect because the difference in pattern is relatively examined.
On the other hand, the method based on the design data comparison does not have the above-mentioned disadvantage because the comparison target is an image obtained from the design data, but has another disadvantage that the processing load for generating the comparison target image from the design data is large. .

In addition to the above-described method using image processing (hereinafter referred to as image processing method), there is a method of sampling several tens to several hundreds of light shielding layer locations corresponding to device patterns and measuring the dimensions thereof. In this method, a pattern to be sampled is not an original pattern, but a measurement-dedicated pattern in a TEG (test elements group) may be used, for example. Since the dimensional accuracy of the pattern of the entire mask is indirectly guaranteed based on the measurement result at this time, this method is hereinafter referred to as an indirect measurement method. The number of samplings in the indirect measurement method is a number that can statistically guarantee the reliability that the measurement result of the pattern dimension that is the measurement target represents the same pattern dimension of the entire mask.
In particular, the element isolation layer, the gate electrode, the first layer wiring, and the contact hole in the lowermost layer connecting them have a large influence on the device characteristics because of the pattern accuracy, so the above-mentioned inspection of the mask for forming them is performed. Indirect measurement methods are often applied. In addition, the indirect measurement method and the image processing method may be used alone or in combination.
"Prior art" of JP-A-11-52546

  As the density and performance of semiconductor devices increase, in order to guarantee the reliability and high characteristics of inspection devices that perform mask dimension measurement and defect detection, etc., higher accuracy is required. It has become. For this reason, the mask inspection apparatus becomes expensive, the inspection time becomes long, or high inspection accuracy is required, so that the mask yield is deteriorated. When these problems occur, the manufacturing cost of the mask increases and the mask manufacturing period becomes longer. Therefore, it has become difficult to bring semiconductor devices to the market at a low cost in a timely manner.

In the image processing method and the indirect measurement method described above, the pattern accuracy required for each mask is different, and it is a common practice to inspect each mask according to the required accuracy.
However, in these methods, since the same inspection accuracy is applied to one mask, inspection is performed with high accuracy even to a portion where high accuracy is not originally required, which causes a reduction in mask yield. ing. Hereinafter, this will be described in detail with an example.

Semiconductor devices in recent years have integrated many functions, and not all circuit blocks for realizing each function operate at the highest operating frequency, and the required operating frequency differs for each circuit block of the device. Yes. In general, it is necessary to strictly inspect the dimensional accuracy of the pattern and the allowable size and frequency of the region on the mask corresponding to the device region (circuit block) having a high operating frequency. On the other hand, it is not necessary to perform a very strict inspection on an area on the mask corresponding to a circuit block having a low operating frequency.
The same applies to a region where the operation margin is narrow due to wiring delay or the like and a region where it is not.

In addition, dummy patterns with the required dimensions may be placed at necessary locations in accordance with various purposes such as ensuring the flatness of the wafer surface layer when manufacturing semiconductor devices or improving the uniformity of patterns. . This dummy pattern is added during layout design or mask data processing.
There are several types of dummy patterns, one of which is the original pattern for the purpose of improving the uniformity of the original pattern while considering the influence on other processes on the part of the mask where there is no pattern. A pattern similar to this is arranged nearby. Hereinafter, such a dummy pattern is referred to as a “dummy pattern for improving uniformity”.
As another dummy pattern, there is a pattern in which a pattern such as a simple rectangle is arranged on a portion of a mask having a low pattern density for the purpose of ensuring flatness during a wafer process. Hereinafter, such a dummy pattern is referred to as a “dummy pattern for improving flatness”.
These dummy patterns may or may not be necessary depending on the wafer process using the mask, and the shape, size, and position of the dummy patterns are more effective in the corresponding wafer process. Optimized.

In the conventional mask inspection methods, the entire mask is inspected with the same accuracy regardless of the operation frequency and the operation margin. In addition, an inspection is performed with the same accuracy on an original pattern that requires high accuracy and a dummy pattern that does not. For this reason, if there is even one place where high inspection accuracy is required in one mask, the entire mask is inspected with high accuracy.
For this reason, for example, even when an image comparison region in the image processing method is a region with a low operating frequency, a region with a large operating margin, or a dummy pattern placement region, the region may deviate from the inspection standard. If it occurs once or at a certain frequency, the entire mask is out of specification. This also applies to the indirect measurement method.As a result, non-standard masks are generated due to the measurement results at the inspection points that actually have almost no effect on the device characteristics. Abandoned or remanufactured, there was an extra increase in material costs, equipment costs, labor costs, etc., and mask fabrication was prolonged.

  The problem to be solved by the present invention is to reduce the possibility that a mask out of the standard will be generated due to the measurement result of the inspection location that has practically no influence on the device characteristics. It is an object of the present invention to provide a mask inspection apparatus and inspection method that can effectively prevent an increase in cost and a prolonged mask fabrication.

  A mask inspection apparatus according to the present invention is an inspection apparatus for inspecting a pattern of a mask used for manufacturing a semiconductor device, and is obtained from at least one step of layout design of the pattern, layout verification, and mask data processing. When information for each area of the mask is input, and at least one of the inspection priority and standard is set using the information for each area based on the input information, and the priority is set when the priority is set A pre-processing unit that selects inspection locations from the regions in order according to the conditions, and when the standard is set for each region, the inspection for the inspection locations is performed based on the standards for each region, and the mask is determined based on the inspection results. An inspection determination unit that points out a non-conforming part of the standard and determines pass / fail.

The preprocessing unit preferably uses the information on the position and size of the circuit block on the mask at the time of the layout design and the information on the operating frequency of the circuit block, and the priority of the inspection or the standard Is set for each region.
In this case, the pre-processing unit extracts the inspection location candidates, and selects the inspection location to be actually inspected from the extracted candidates from the circuit block in the descending order of the operating frequency according to the priority. Select until the number of places is satisfied.
Or the said test | inspection determination part performs the said test | inspection according to the said standard set for every said area | region so that the tolerance | permissible_range of a test result becomes narrow, so that the said operating frequency is high.

Preferably, the pre-processing unit preferably performs operation as the layout verification using the post-design pattern after the layout design, information on the size of the operation margin obtained from the simulation result, and the operation At least one of the priority and the standard is set for each circuit part using information on the position and size of the circuit part having a different margin on the mask.
In this case, the pre-processing unit extracts a test location candidate, and selects a test location to be actually tested from the extracted candidate from a predetermined test location from the circuit portion in the order of narrow operation margin according to the priority. Select until the number is satisfied.
Alternatively, the inspection determination unit performs the inspection in accordance with the standard set for each region so that the allowable range of the inspection result is narrowed as the operation margin is small.

In the present invention, the preprocessing unit preferably inputs area information of an additional pattern added to a place where there is no original pattern at the time of layout design or mask data processing for converting layout design data into mask data. The inspection pattern is selected with the lowest priority for the additional pattern area determined from the information, and the inspection determination unit accepts the inspection result for the additional pattern area. The inspection is performed based on the standard having the widest range.
Alternatively, the pre-processing unit preferably inputs area information of an additional pattern added to a place where there is no original pattern at the time of layout design or mask data processing for converting layout design data into mask data. The selection of the inspection location is executed after excluding the additional pattern from the candidates for selection of the inspection location based on the above.

  According to the mask inspection apparatus having the above configuration, the preprocessing unit sets at least one of inspection priority and inspection standard for each mask region. At this time, information obtained from the process before the mask data processing is used. Specifically, for example, as information obtained from layout design, information on the operating frequency or additional pattern of each circuit block is used. Alternatively, when there is a circuit portion having a different operation margin after layout verification, information on the circuit portion is used, and when an additional pattern is added during mask data processing, information on the additional pattern is used. These pieces of information are used when the pre-processing unit preferentially determines the order of the areas where the detection points are selected, or when the inspection determination unit performs the inspection, the allowable range of the inspection result (the severity of the standard) ) Is used when deciding.

  In this way, a reference (priority and standard) is set using information for each mask area, and an inspection according to the standard is performed for each mask area. For this reason, for example, the inspection location is preferentially selected from the area on the mask where the pattern to be inspected strictly exists, and the number of inspection locations is selected in the area of the pattern to be inspected strictly. In the region of the pattern to be strictly performed, the acceptable range (standard) for the pass / fail judgment is narrowed, and the pass / fail judgment is executed after pointing out the non-conforming part. In other words, in the area of the pattern that does not require strict inspection, more measurement points than necessary are not selected, and stricter standards than necessary are not imposed. Furthermore, even if the number of inspection locations is reduced, a pattern to be strictly inspected does not leak from the inspection locations. The inspection method itself may be either an indirect measurement method or an image processing method.

  A mask inspection method according to the present invention is an inspection method for inspecting a pattern of a mask used for manufacturing a semiconductor device, and is obtained from at least one of the pattern layout design, layout verification, and mask data processing. When information for each area of the mask is input, and at least one of the inspection priority and standard is set using the information for each area based on the input information, and the priority is set when the priority is set A pre-processing step for selecting an inspection location from the region in the order according to the step, and when the standard is set for each region in the pre-processing step, the inspection for the inspection location is performed for each region, and an inspection result The inspection non-conformity portion of the mask is pointed out, and an inspection determination step of determining pass / fail is included.

  According to the present invention, it is possible to reduce the possibility of generating a mask that is out of specification due to the measurement result of an inspection point that actually has almost no influence on the device characteristics. Prolonged production can be effectively prevented.

  As described in the problem of the background art, the failure of a mask that has a small influence on the device characteristics and can be passed normally occurs because a high-precision inspection is applied to the entire exposure area of the mask.

  For this reason, in the first method according to the embodiment of the present invention, the operating frequency at which it is possible to determine the severity of the inspection to be applied between the area on the mask that should be strictly inspected with high accuracy and the area that only requires a somewhat rough inspection Or, use the operation margin information when setting the inspection priority, and select the inspection location in the order of the gradually decreasing priority from the set high priority region to each inspection region. Inspect and judge. In other words, the first method is a mask inspection method for repairing a mask that has been rejected in the past even though it is a mask that is originally acceptable as a result of optimizing the inspection location for each region. .

  In the second method, the information on the operating frequency or the operating margin for each area is used when setting the inspection judgment standard (inspection standard), and the pattern of each area is inspected using the set standard for each area. ·judge. In other words, the second method is a mask inspection method for relieving a mask that should not be rejected by making the inspection standard appropriate for each region.

In the third method, an original pattern corresponding to a device pattern is distinguished from other patterns, and all patterns (or a part of them) other than the original pattern are excluded from the inspection location. In other words, the third method restricts the type of pattern at the inspection location to what should be inspected regardless of the area, and as a result, conventionally, a mask that is originally acceptable as a pattern that is not an original pattern is strictly inspected. However, it is a mask inspection method for relieving a mask that has been rejected despite it.
In the present invention, a pattern other than the original pattern is referred to as an “additional pattern” in the sense that it is added at a position where there is no original pattern.

Hereinafter, application examples of the first to third methods will be described in detail with reference to the drawings.
FIG. 1 is an explanatory diagram showing an outline of the configuration and procedure of an apparatus necessary from layout design to mask inspection when all of the first to third methods are applied. This figure is a combination of a block diagram and a flowchart. Each part of the inspection apparatus and other devices (blocks) are represented by “numbers”, and the procedure is represented by “step (ST) followed by numbers”. I am instructing.
In addition, in this Embodiment, the combination of the 1st-3rd method is arbitrary, The schematic block diagram at the time of combining one or two methods is abbreviate | omitted here. However, necessary blocks and procedures in that case will be clarified in the embodiments described later.

  In the layout design apparatus 1 (step ST1) shown in FIG. 1, a layer pattern corresponding to each mask of a semiconductor device (LSI) is designed. This designed pattern data is sent as LSI layout data D1 to the next layout verification apparatus, here the timing verification apparatus 2 (step ST2).

In layout verification, the suitability of the layout is verified from various viewpoints. In this example, the delay of the output signal with respect to the input signal is measured for each circuit block constituting the LSI by a circuit simulator or the like. If there is a circuit block that does not satisfy the delay specification as a result of this measurement, the information is returned to the layout design apparatus (step ST1), and the pattern and LSI structure are corrected.
When it is determined that the corrected data is appropriate in the second timing verification, the LSI layout data D1 is determined and sent to the mask data processing device 3 (step ST3).

  In the mask data processing, the LSI layout data D1 (CAD data) is converted into drawing data D3 suitable for the mask drawing apparatus to be used next. Further, in the mask data processing, the above-described dummy pattern is added as necessary to obtain a pattern to which OPC (Optical proximity effect correction) is applied. As described in the third method described above, the dummy pattern is excluded from the inspection location of the mask in the process described later.

FIG. 2 shows the types of dummy patterns.
In this example, there are two types, a dummy pattern DP1 for improving uniformity and a pattern DP2 for improving flatness.
The dummy pattern DP1 for improving the uniformity is the original pattern P for the purpose of improving the uniformity of the original pattern P in the portion on the mask where the original pattern P does not exist while considering the influence on other processes. Is arranged in a pattern similar to this. This dummy pattern DP1 is a dimension that does not resolve on the wafer at the time of exposure, for example, a dimension that can be resolved, when only the exposure of transferring the pattern from the mask to the wafer is expected and the effect of improving the uniformity is expected. It may be formed with smaller dimensions.
The pattern DP2 for improving the flatness is arranged as a simple rectangular pattern, for example, on a portion of the mask having a low pattern density for the purpose of ensuring flatness during the wafer process.
These dummy patterns DP1 and DP2 may or may not be necessary depending on the wafer process using the mask, and the shape, size and position of the dummy patterns DP1 and DP2 are more effective in the corresponding wafer process. Optimized to be The dummy patterns DP1 and DP2 may be added at the time of layout design (step ST1) in addition to the mask data processing (step ST3) shown in FIG.

  In FIG. 1, the drawing data D3 output from the mask data processing device 3 (step ST3) is sent to the next mask process device group 4 (step ST4).

In the mask process, a light shielding layer is formed on a mask substrate, a photosensitive layer is applied thereon, and then a pattern is transferred (written) to the photosensitive layer by an electron beam (EB) or ion beam based on the drawing data D3. The transferred photosensitive layer is resolved by development, and the pattern of the photosensitive layer is further transferred to the underlying light shielding layer by etching. Thereafter, the formation of the mask M is completed through removal and cleaning of the photosensitive layer.
The completed mask is sent to the next mask inspection apparatus 5 where the mask quality, for example, the positional accuracy, dimensional accuracy, uniformity, presence / absence of defects, etc. of the light shielding layer pattern of the mask is inspected.

As shown in FIG. 1, the mask inspection apparatus 5 includes a mask inspection pre-processing unit 51 (step ST51) and an inspection determination unit 52 (step ST52).
The pre-processing unit 51 obtains basic information I for setting inspection conditions during layout design in step ST1, layout verification in step ST2, and mask data processing in step ST3. This basic information I is the operation frequency information Ifreq. Input for each area of the mask M (for example, a circuit block) from the layout design apparatus 1, and when the layout design apparatus 1 adds dummy patterns DP1 and DP2 (see FIG. 2). Then, dummy pattern information Idummy1 input for each region from there, and operation margin information Imargin input for each region of the mask M from the result of delay verification by the layout verification apparatus 2 are included. It is assumed that the basic information I includes the coordinate information of the position and size of the area of the mask M, and the coordinate information of the positions and sizes of the dummy patterns DP1 and DP2 on the mask M.
The preprocessing unit 51 inputs the basic information I, and executes processing such as setting of inspection conditions and selection of inspection points.

The pre-processing unit 51 sets, for example, a standard for predetermining the inspection locations and the number thereof for each region, that is, a criterion (priority) at the time of selecting an inspection location, and a standard for inspection and / or determination. The preprocessing unit 51 sets these standards based on the basic information I described above. It should be noted that one or both of the type of apparatus used for the inspection by the inspection determination unit 52 and the type of inspection / determination algorithm of the apparatus can be included in the inspection conditions as necessary.
Here, for example, an acceptable range (for example, a pattern, a positional deviation, an allowable range of defects, or an allowable number of defects) in the pass / fail determination of the mask M performed after the inspection can be used as an inspection standard.

The pre-processing unit 51 executes a process of limiting the inspection location candidates according to the priority at the time of selecting the inspection location, and selecting an inspection location to be actually inspected from the candidates. It is possible to use only the original pattern as a candidate for the inspection location. In this case, the preprocessing unit 51 inputs the drawing data D3, excludes the dummy patterns DP1 and DP2 from the patterns therein, and remains. The original pattern P is set as a candidate for the inspection location. At this time, in order to distinguish the dummy pattern to be excluded from other patterns, in the mask data processing, the drawing data D3 is formed with the dummy pattern to be excluded as another layer, and the layer number information is used as dummy pattern information Idummy2. It is given to the processing unit 51.
Note that the preprocessing unit 51 may obtain the dummy pattern information to be excluded as the coordinate information of the position and size in the mask and specify the dummy pattern to be excluded from the information.
Further, only the dummy pattern DP2 for improving the flatness may be excluded. The reason for doing so is that the dummy pattern DP1 for improving uniformity is similar in size and surrounding condition to the original pattern P, whereas the flatness improving pattern DP2 is larger in size. This is because, since the surrounding situation is completely different from the original pattern P, measuring it tends to cause an error in the inspection result.

The inspection determination unit 52 may be composed of one part, or may be divided into an inspection unit and a determination unit. In FIG. 1, the inspection step ST52a and the determination step ST52b are shown separately so that a common concept unrelated to the configuration can be imagined.
In the inspection step ST52a, the inspection portion selected by the preprocessing unit 51 (step ST51) is inspected, and in the next determination step ST52b, the non-conforming part is detected from the inspection result. This is executed according to the standard set by ST51), that is, the inspection standard for each region. Note that when the pass / fail judgment is performed according to the inspection standard, the pre-processing unit 51 may only set the inspection condition and may not perform the process on the actual drawing data D3 (application of only the second method). Case: see Example 2 below). Therefore, in FIG. 1, the drawing data D3 can be supplied to the inspection step ST52a of the inspection determination unit 52.
When the non-conforming part of the mask is pointed out in this way and the pass / fail determination result is output, the inspection determination for the mask M is completed. This output is used in the mask correction process.

  The pre-processing and mask inspection / determination described above are repeatedly executed for all masks while setting unique criteria.

  Next, an embodiment in which the first to third methods are partially applied will be described with reference to the drawings.

[Example 1]
FIG. 3 is a schematic explanatory view showing an example of mask inspection by line width measurement to which the first method and the third method are applied.
In measuring the line width of a mask, there are various methods for specifying the measurement location (inspection location). As the simplest method, a method in which a person indicates a measurement location may be applied. However, this method is not preferable because human instructions are heavy in human burden and may cause an instruction error. Therefore, in the first embodiment, candidate pattern portions having a line width to be measured are extracted from effective drawing areas on all masks using DRC (design rule checker), and the line width guarantee of the semiconductor device is selected from these. This is an example in which a necessary number is selected and an inspection pattern portion is determined and measured.

  The preprocessing unit 51 in the first embodiment includes a candidate extraction unit 51a and a target selection unit 51b. Candidate data D51a extracted by the candidate extraction unit 51a is sent to the target selection unit 51b, where the number of inspection data D51b is further reduced. The inspection location data D51b is sent to the inspection determination unit 52. Since other configurations are the same as those in FIG. 1, description thereof is omitted here. Further, in FIG. 3, the reference numerals of steps ST1 to ST51 are omitted for simplification, but the basic flow of the procedure of the inspection method is as already described with reference to FIG.

  The candidate extraction unit 51a receives the drawing data D3 and the dummy pattern information Idummy2, excludes a predetermined dummy pattern from the drawing data D3 according to the dummy pattern information Idummy2, and then extracts a candidate for measurement using the DRC function. To do. The extracted measurement target candidates are sent as candidate data D51a to the target selection unit 51b.

  In general, DRC has the same device function, for example, the pattern of the finger part of the gate electrode, based on the similarity of the shape of the pattern to be extracted from many patterns and the similarity of the arrangement and shape of the peripheral pattern. Only the pattern part is extracted at random.

Here, in the first embodiment, a case is considered where only the dummy pattern DP2 for improving flatness is excluded from the candidates. For this reason, a set of pattern portions having the line width to be measured (candidate data D51a to be measured) extracted by the DRC-like function includes the portion of the original pattern P (see FIG. 2) to be measured and the corresponding pattern data ( The pattern data DP1) for improving the uniformity is mixed.
However, in general, the line width to be measured is a basic width that determines device characteristics in the mask. In particular, in the case of a large-scale LSI, the number of extracted pattern portions having the line width is considerable. Therefore, it is necessary to reduce the number of candidates for measurement after extraction to the number necessary for actual measurement.

  The object selection unit 51b is provided to reduce this number and to select a pattern part (inspection location) to be actually measured from the candidate data D51a. The number of candidates (number of inspection points) reduced to a number sufficient to guarantee the mask quality according to the scale of LSI, the degree of miniaturization, and the type of mask layer, for example, from several tens to several Predetermined within a hundred range.

  If this processing to reduce the number of measurement target candidates is performed only under the geometric condition of securing the required number of measurement points and sampling so that the distance between any adjacent measurement targets is as far as possible, There is a possibility that the dummy pattern DP1 (see FIG. 2) for improving uniformity unrelated to the circuit operation is used as a measurement location. The dummy pattern DP1 is similar to the original pattern P in surroundings, but is not exactly the same. Even if the width of the dummy pattern DP1 is the same as that of the original pattern P at the time of layout design, it is often slightly different from the width of the original pattern P after the mask process. Further, as described above, the width of the dummy pattern DP1 may be intentionally made smaller than the width of the pattern P on the main body. Therefore, if the dummy pattern DP1 for improving uniformity is a measurement location, it is erroneously determined that the mask has a large variation, and in some cases, it may be determined that the mask needs to be recreated. .

In the first embodiment, layout design information, that is, dummy pattern information Idummy1 is used when selecting a measurement location by the object selection unit 51b.
Here, the dummy pattern DP1 for improving uniformity can be distinguished on the layout data, for example, by a layer number different from the original pattern P at the design stage. This layer number is given as the dummy pattern information Idummy1 from the layout design device 1 to the object selection unit 51b. The object selection unit 51b excludes the measurement pattern corresponding to the dummy pattern DP1 based on the dummy pattern information Idummy1.

  Next, the target selection unit 51b selects a location (measurement location) that is actually a measurement target by further reducing the number from the candidates excluding the dummy pattern. Hereinafter, this selection method will be described with reference to a layout example shown in FIG.

FIG. 4 is a diagram showing a difference in speed and operation margin in a general circuit block of a logic LSI with built-in memory.
An LSI (semiconductor device) 10 shown in FIG. 4 includes a control system circuit such as a CPU and a high-speed logic unit centered on a high-speed bus unit, a memory unit, a medium-speed logic unit centered on a logic circuit (medium-speed signal processing unit), It is divided by circuit blocks (areas) according to speed, such as other parts such as I / O circuits and PAD areas. Among these, the operating frequency of the high-speed logic unit is the highest, and then the operating frequency of the memory unit and the medium-speed logic unit is high. Other I / O circuits and the PAD region are regions where the operating frequency is the lowest. This difference in operating frequency is shown in FIG. 4 by three classifications: a high speed region, a medium speed region, and a low speed region.
In particular, the high-speed region and the low-speed region include regions where the operation margin determined from the timing verification result is small and normal operation is not easily performed unless a pattern is formed almost as designed. This area is called a “critical area”. Since the critical region is usually a very narrow region in many cases, it cannot always be said that the measurement location is selected from this portion. Therefore, there is a need to increase the chances of selecting measurement points from the area centered on the critical area. In addition, if the accuracy of pattern formation is not guaranteed for an area of a certain width (peripheral area), including the critical area, it is critical that the peripheral area is not formed accurately in actual operation. There may be a case in which the operation of the critical region cannot be guaranteed as a result of spreading to the characteristics of the region. For the above reasons, it is desirable to treat the critical region with a small operation margin and its peripheral region as the region with a small operation margin and treat them as the high-speed region.

  The distinction between the high speed region, the medium speed region, and the low speed region and the coordinates (position and size) shown in FIG. 4 are given to the object selection unit 51b from the layout design as the operation frequency information Ifreq. Further, the coordinates (position and size) of the critical area and the surrounding area are given to the target selection unit 51b from the timing verification as the operation margin information Imargin in FIG.

  The object selection unit 51b determines each candidate of the measurement location and the operation frequency or the operation margin of the region to which each candidate belongs based on at least one of the operation frequency information Ifreq. And the operation margin information Imargin, preferably both. Examine the relationship. Then, from the measurement target candidates, those that should be preferentially selected as the measurement location are selected in the order of the operating frequency of the affiliation region in descending order or the operating margin in ascending order.

In the first embodiment, the following method using information on both the operating frequency and the operating margin is adopted.
Based on the operation margin information Imargin, the measurement locations belonging to the critical region and the peripheral region are first selected. When there are many critical regions and the selection satisfies the predetermined number of measurement points, the predetermined number of measurement points are selected such that the sampling positions vary geometrically. However, there are usually few critical areas, and the number of measurement points to be selected is often large. In this case, the remaining shortage is selected in the order of high speed area and medium speed area. At this time, it is desirable to perform a selection method in which the sampling positions of the selected measurement locations, including the already selected measurement locations, vary geometrically as much as possible within the effective drawing area of the mask.

As a result, the pattern of the measurement location selected is only a pattern that should pay attention to the line width accuracy. Using this measurement location, line width measurement and mask pass / fail determination are performed. The measurement result correctly represents the mask quality as an influence on the operation of the device. Therefore, in the pass / fail judgment of the mask, there is no apparent quality degradation caused by measuring a pattern unrelated to the device operation, which may have different finished dimensions.
Further, in the above method in which the measurement in the portion where the operation margin is narrow is given priority and the measurement in the high speed region is given priority next, the measurement location is selected from the portion requiring the most line width accuracy. For this reason, the line width measurement target and the necessity of the measurement are almost completely matched, and the predetermined number of measurement points, which is the number of samples for statistically guaranteeing the same mask quality, needs to be measured. Compared to the method of choosing regardless of gender, it can be greatly reduced. This leads to a significant reduction in the inspection cost by shortening the measurement time and reducing the processing load of the measurement result.

[Example 2]
The present embodiment relates to a mask inspection by defect detection to which the second method is applied.
Defect detection basically requires high-sensitivity (high spec) inspection in the case of a mask such as a gate electrode pattern that requires high accuracy. In this case, the cost required for the inspection becomes higher than the cost required for the inspection of the mask, which may be less accurate, due to the high price of the apparatus and the long inspection time. Therefore, the present invention is also applied to defect detection.

FIG. 5 is a schematic explanatory view showing an example of mask inspection by defect detection.
The pre-processing unit 51 in FIG. 5 includes a standard assigning unit 51c that assigns inspection standards to be applied for each region on the mask. In this example, there are three types of inspection standards: high sensitivity standard, medium sensitivity standard, and low sensitivity standard. When allocating the area for each of these three standards, for example, as shown in FIG. 4, the inspection standard is assigned to each block from high sensitivity to low sensitivity according to the operating frequency of each circuit block, and the operation is performed based on the result of timing verification. Several criteria can be considered, such as assigning critical areas with small margins and their peripheral areas to high sensitivity standards, and assigning dummy pattern DP2 areas for improving flatness to low sensitivity standards, A combination of multiple criteria can be used.

In the following, it is assumed that all three criteria are applied. In other words, the high-sensitivity standard is the standard with the strictest defect size and density allowed (if the area of the area is constant, “the number of defects” is also possible). For example, the high-speed region in FIG. And its surrounding areas. The medium sensitivity standard is a standard in which the size and density of allowed defects are the strictest next to the high sensitivity standard, and excludes the critical region and its peripheral region and the dummy pattern DP2 region for improving flatness in FIG. Applies to the velocity domain. The low sensitivity standard is the standard having the smallest allowable defect size and density, and is applied to, for example, the dummy pattern DP2 region and the low-speed region for improving flatness in FIG.
Standard-specific area information Ispec including area information of high sensitivity standard, area information of medium sensitivity standard, and area information of low sensitivity is sent to the defect inspection step ST52a of the mask M by the inspection determination unit 52.

  In addition, in order to assign a region for each standard, the relationship between the operating frequency and inspection sensitivity, the relationship between the operation margin obtained from timing verification and inspection sensitivity, and the inspection sensitivity for dummy patterns for improving flatness are determined in advance. It is necessary to keep. The sensitivity correspondence information 7 determined in advance is stored as a table in a storage unit (not shown), for example, or is generated by layout design and sent to the standard allocation unit 51c at a necessary timing.

The inspection determination unit 52 inputs the area information Ispec by standard and the drawing data D3, and performs defect inspection for each area under the standard corresponding to the area. In addition, although the method of defect inspection is arbitrary, the image processing method can be employ | adopted suitably, for example.
The pass / fail judgment of the mask is performed based on the result of the defect inspection. However, since the standard of the defect inspection is different for each region, the difference in the standard greatly affects the pass / fail judgment result. In other words, if it is determined that the mask is accepted or rejected based on the criterion that the entire mask M is rejected when there is even one region that is out of the inspection standard, the defect inspection standard is the whole mask as in the background art. However, if it is uniform, all areas must be inspected with the strictest high-sensitivity standard, and mask rejection is likely to occur. However, if the inspection standard is loosened at a place where the speed is not so high as in this embodiment, the mask is less likely to be rejected than in the case of the background art. Keeping the standard of this inspection loose means that the area to which the standard is applied is a place where defects such as the low-speed area are unlikely to affect the operation. Does not affect sex.

  By the way, it is difficult to correct the mask that is out of the dimensional standard because it covers the entire mask, but the defect number is limited in the defect inspection. The mask can be corrected. In this case, as shown in FIG. 5, in the determination step ST52b, the non-conforming part of the mask is pointed out, and the information is sent to the mask correction process device process 4b (mask correction step ST4a). In the mask correction step ST4a, the mask M is corrected based on the information of the non-conforming part, and the corrected mask Ma is sent again to the inspection determination unit 52. If the determination is acceptable, the corrected mask Ma is delivered. To do.

  Note that when “defect” is mentioned in the above description, a defect that is likely to lead to disconnection or short-circuiting of the wiring may not correspond to the “defect” here. The reason is that such a thing is a “fatal defect” and, except for the dummy pattern region, if it is a circuit portion, it should not originally exist regardless of the operating frequency and the operating margin. In order to detect a “fatal defect”, it is preferable that a mask having a fatal defect is rejected in advance by separately checking the entire area.

In addition, the allowable defect size is the same for each standard, and only the number of defects can be a problem. In such a case, the set standard can be used as a criterion for determining the inspection result instead of the inspection. is there.
In this example, the defect inspection conditions are represented by sensitivity, but other inspection conditions such as an inspection algorithm and a type of inspection apparatus can be applied.

[Example 3]
FIG. 6 is a schematic explanatory view showing an example of mask inspection by line width measurement to which only the third method is applied.
In the configuration shown in FIG. 6, since the flow of the procedure has already been described in the first embodiment, redundant description is avoided. The third embodiment is different from the first embodiment in that the object selection unit 51b simply uses a predetermined number of predetermined numbers according to the degree of integration and the minimum dimension width without using the operation frequency and the result of timing verification. The number of measurement points is selected from the candidate data D51a in consideration of the geometric variation of the sampling position. In this case, no reference is made as to whether or not the region is critical in terms of operation, but depending on the type of mask, there is a mask of a layer that has little relation to the operation frequency and the operation margin from the beginning. For such a mask, simply removing the dummy pattern from the inspection location as in this embodiment is effective in improving the accuracy of the line width measurement result, and there is a possibility that a relieved mask may be generated. In addition, since the object selection is simplified, another advantage is that the processing load is small.

  The present invention can be widely applied to inspection of a mask used for manufacturing a semiconductor device.

It is explanatory drawing which shows the outline of the structure of a device required from layout design to a mask test | inspection, and the procedure in connection with embodiment of this invention. It is explanatory drawing which shows the kind of dummy pattern. It is a schematic explanatory drawing of the mask inspection by the line | wire width measurement which applied the 1st method and the 3rd method in connection with Example 1. FIG. It is a figure which shows the difference in speed and an operation margin in the general circuit block of logic LSI with a built-in memory. FIG. 6 is a schematic explanatory diagram of mask inspection by defect detection related to Example 2. FIG. 10 is a schematic explanatory diagram of mask inspection by line width measurement to which only a third method related to Example 3 is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Layout design apparatus, 2 ... Timing verification apparatus, 3 ... Mask data processing apparatus, 4 ... Mask process apparatus group, 4a ... Mask correction process apparatus, 5 ... Mask inspection apparatus, 7 ... Sensitivity correspondence information, 10 ... LSI, 51 ... Pre-processing unit, 51a ... Candidate extraction unit, 51b ... Target selection unit, 51c ... Standard allocation unit, 52 ... Inspection determination unit, M ... Mask, Ma ... Modified mask, P ... Original pattern, DP1 ... Uniformity Dummy pattern for improvement, DP2 ... Dummy pattern for improving flatness, D1 ... LSI layout data, D3 ... Drawing data, D51a ... Candidate data, D51b ... Inspection location data, Ifreq .... Operating frequency information, Imargin ... Operation Margin information, Idummy1, Idummy2 ... Dummy pattern information, Ispec ... Standard area information

Claims (11)

An inspection apparatus for inspecting a pattern of a mask used for manufacturing a semiconductor device,
Input information for each area of the mask obtained from at least one step of layout design, layout verification, and mask data processing of the pattern, and based on the input information, at least one of the priority and standard of the inspection Set using information for each area, and when setting the priority, a pre-processing unit that selects inspection locations from the area in order according to the priority,
When the standard is set for each region, the inspection for the inspection location is performed based on the standard for each region, points out the non-conforming portion of the mask from the inspection result, and an inspection determination unit that determines pass / fail,
Mask inspection apparatus having The preprocessing unit uses the information on the position and size of the circuit block on the mask at the time of the layout design and the information on the operating frequency of the circuit block, and at least one of the priority of the inspection or the standard The mask inspection apparatus according to claim 1, wherein: is set for each circuit block. The pre-processing unit extracts candidates for the inspection locations, and determines the inspection locations that are actually inspected from the extracted candidates from the circuit blocks in a descending order of operating frequency according to the priority. The mask inspection apparatus according to claim 2, wherein the mask inspection apparatus is selected until it is satisfied. The mask inspection apparatus according to claim 2, wherein the inspection determination unit performs the inspection in accordance with the standard set for each region so that an allowable range of an inspection result becomes narrower as the operating frequency is higher. When the simulation is performed as the layout verification using the post-design pattern after the layout design, the preprocessing unit is different from the information on the size of the operation margin obtained from the simulation result. The mask inspection apparatus according to claim 1, wherein at least one of the priority and the standard is set for each circuit part using information on a position and a size of the circuit part on the mask. The pre-processing unit extracts candidates for inspection locations, and the inspection locations that are actually inspected from the extracted candidates are filled with a predetermined number of inspection locations from the circuit portion in the order of narrow operation margin according to the priority. The mask inspection apparatus according to claim 5, wherein the mask inspection apparatus is selected until it is selected. The mask inspection apparatus according to claim 5, wherein the inspection determination unit performs the inspection according to the standard set for each region so that an allowable range of an inspection result becomes narrower as the operation margin is smaller. The pre-processing unit inputs area information of an additional pattern added to a place where there is no original pattern at the time of layout design or mask data processing for converting layout design data into mask data, and is determined from the area information. For the area of the additional pattern, perform the selection of the inspection location with the lowest priority,
The mask inspection apparatus according to claim 1, wherein the inspection determination unit performs the inspection based on the standard having the widest allowable range of inspection results for the area of the additional pattern. The pre-processing unit inputs area information of an additional pattern added to a place where there is no original pattern during layout design or mask data processing for converting layout design data into mask data, and the inspection is performed based on the area information. The mask inspection apparatus according to claim 1, wherein the inspection location is selected after the additional pattern is excluded from candidates at the time of location selection. An inspection method for inspecting a pattern of a mask used for manufacturing a semiconductor device,
Input information for each area of the mask obtained from at least one step of layout design, layout verification, and mask data processing of the pattern, and based on the input information, at least one of the priority and standard of the inspection Set using information for each area, and when the priority is set, a pre-processing step of selecting inspection locations from the area in order according to the priority;
In the pre-processing step, when the standard is set for each region, the inspection for the inspection location is performed for each region, and the non-conforming portion of the mask is pointed out from the inspection result, and the pass / fail step for determining pass / fail When,
Inspection method for masks including In the pre-processing step, set at least one of the apparatus used for the inspection and the algorithm of the program used for the inspection;
The mask inspection method according to claim 10, wherein in the inspection determination step, the inspection is performed for each region using at least one of the set type device and the algorithm.

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