JP2012175080A - Defect inspection method and defect inspection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of removing a defect which does not greatly influence the yield of semiconductor devices and reduces the manufacturing costs needed to cope therewith.SOLUTION: The method includes a step ST11A of inspecting whether a first inspection object includes a defect; a step ST11B of classifying detected defects by features and calculating the numbers of defects by features of the defects; steps ST12B and ST12C of measuring electric characteristics of semiconductor devices on a wafer and creating a defect map of the semiconductor devices on the wafer; steps ST13 and ST14 of collating the defect map with the position of the defect of the inspection object and calculating an electric defect probability of the semiconductor devices; and a step STn of determining whether a second inspection object can be used using the electric defect probability.

Description

  Embodiments described herein relate generally to a defect inspection method and a defect inspection apparatus.

  In the manufacturing process of a semiconductor device, defect management of a template used for a wafer, a mask, or an imprint technique is important for ensuring a predetermined manufacturing yield.

  Therefore, defect inspection of wafers, masks or templates is performed during the manufacturing process of semiconductor devices, so that the status of the equipment used in each manufacturing process can be identified, the cause of defects can be identified, and the use of masks and templates. Verification of fluctuation factors of the semiconductor device manufacturing yield, such as determination of availability, is performed.

  An example of a defect inspection method is that a wafer, a mask or a template as an inspection object is irradiated with light or an electron beam, and a difference signal between a reference signal and a signal obtained from the inspection object by irradiation is set. Compare with threshold. By comparing such a difference signal with a threshold value, it is detected whether or not the inspection object includes a defect.

  However, a portion that is not a defect may be erroneously detected as a defect depending on the threshold setting value and the sensitivity of the defect inspection apparatus. Furthermore, with the recent miniaturization of semiconductor devices, it is difficult to determine defects on a mask, a template, or a wafer.

  Further, the detected defect does not necessarily cause a failure of the semiconductor device. Even a defect that does not significantly affect the yield of such a semiconductor device may be detected in the same manner as a defect that lowers the manufacturing yield. As a result, in order to deal with defects that have little influence on the manufacturing yield, the manufacturing cost of the semiconductor device, such as mask remanufacturing and stoppage of the manufacturing apparatus, increases.

JP 2000-269276 A

  Suppressing the increase in manufacturing cost of semiconductor devices.

  The defect inspection method according to the present embodiment includes a step of inspecting whether or not the first inspection object includes a defect in at least one first inspection object of a wafer, a mask, and a template; Defects detected from the inspection object are classified by feature, the step of calculating the number of defects for each feature of the defect, and measuring the electrical characteristics of the semiconductor device on the wafer, and the defect of the semiconductor device on the wafer Creating a map; collating the defect map with a defect location of the inspection object; calculating an electrical failure probability of the semiconductor device for each feature of the defect; and calculating the electrical failure probability. And determining whether or not the second inspection object including the defect is suitable for use.

The flowchart for demonstrating the defect inspection method of 1st Embodiment. The schematic diagram which shows an example of a defect inspection system. The schematic diagram of the test object and semiconductor device used for a defect inspection method. The schematic diagram for demonstrating the defect inspection method of 1st Embodiment. The schematic diagram for demonstrating the defect inspection method of 1st Embodiment. The schematic diagram for demonstrating the defect inspection method of 1st Embodiment. The schematic diagram for demonstrating the feature of the defect which a test subject contains. The flowchart for demonstrating the calculation method of an electrical failure probability. The schematic diagram for demonstrating a defect rate. The schematic diagram for demonstrating a defect rate. The flowchart for demonstrating the defect inspection method of 2nd Embodiment. The block diagram for demonstrating the defect inspection apparatus of 3rd Embodiment. The schematic diagram for demonstrating the modification of embodiment. The flowchart for demonstrating the example of application of embodiment.

[Embodiment]
Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given as necessary.

(1) First embodiment
The first embodiment will be described with reference to FIGS. 1 to 10. The first embodiment relates to an inspection method (evaluation method) for a defect generated in a mask, a template for imprint technology, or a wafer for manufacturing a semiconductor device.

(A) Overall configuration
The overall configuration of the defect inspection method according to the first embodiment will be described with reference to FIGS.

  In the defect inspection method according to the present embodiment, a wafer, a mask, and a template used for an imprint technique for manufacturing a semiconductor device are used as a defect inspection target (hereinafter referred to as an inspection target). Here, the mask includes various types of masks used in a semiconductor device manufacturing process, such as a photomask and an EUV mask. The template includes a template on which a pattern directly transferred to a wafer is formed, or a master template for forming the template. The wafer includes a semiconductor single crystal substrate (for example, a silicon substrate), an SOI substrate, a substrate on which a member (conductor or insulator) is formed during the manufacturing process, and a substrate onto which a pattern is transferred during the manufacturing process.

  Hereinafter, a wafer, a mask, or a template to be inspected for defects is referred to as an inspection object 10.

  FIG. 1 is a flowchart showing the overall flow of the defect inspection method of the present embodiment. FIG. 2 shows an example of a system for executing the defect inspection method of the present embodiment. The defect inspection method shown in FIG. 1 is executed by the defect inspection system 1 shown in FIG.

  The defect inspection system 1 includes, for example, a computer 2 for inputting / outputting data, a defect inspection apparatus 3, an electrical failure probability distribution storage unit 4A, and a defect database 5A.

The computer 2 includes a control unit 21 and a calculation unit 22.
The defect inspection apparatus 3 includes an inspection unit 31 having a microscope, a camera, and the like. The inspection unit 31 includes a light source for irradiating light on the inspection object. The light source of the inspection unit 31 emits light having a wavelength in a predetermined range from infrared light to deep ultraviolet light, and electron light. The inspection unit 31 irradiates the inspection object with light from the light source and detects reflected light (or transmitted light) from the inspection object.

  The defect inspection apparatus 3 compares, for example, a difference between a reference signal and a signal from an inspection object generated by light irradiation (hereinafter referred to as a difference signal) with a set threshold value. For example, the defect inspection apparatus 3 determines a location or pattern where a difference signal larger (or smaller) than the threshold is obtained as a defect.

  The defect inspection apparatus 3 has a predetermined sensitivity according to the resolution of the microscope of the inspection unit 31 and the characteristics of the light source. The sensitivity in the defect inspection apparatus 3 is indicated by a minimum defect size that can be detected without detecting a pseudo defect (hereinafter referred to as a minimum defect size). The pseudo defect is a portion (pattern) that is erroneously recognized as a defect due to noise. The threshold value for defect determination is preferably set to the minimum defect size in order to reduce defect oversight and false detection.

  The computer 2 controls the operation of the entire defect inspection system 1. The computer 2 includes a control unit 21 and a calculation unit 22. The control unit 21 of the computer 2 controls calculation processing of the calculation unit 22 and data input / output with the other devices 3, 4, and 5. The calculation unit 22 of the computer 2 executes calculation processing based on the inspection result and data. Based on the flow shown in FIG. 1, the computer 2 evaluates the inspection result of the defect inspection apparatus 3 using data held in the electrical failure probability distribution storage unit 4 and the defect database 5.

  The electrical failure distribution storage unit 4 stores an electrical failure probability distribution E (s) described later. The defect database 5 stores a database related to defects included in the inspection object 10 described later.

  The semiconductor device is formed using a wafer, a mask, or a template as the inspection object 10. For example, as shown in FIG. 3A, the pattern formed on the mask 9 is projected onto the surface of the wafer 8 by exposure, whereby the pattern of the mask 9 is transferred to the resist mask on the wafer surface. For example, the pattern of the mask 9 is a quadruple of the pattern projected onto the wafer 8.

  Instead of a mask, an imprint technique may be used to transfer the pattern of the template to the imprint agent on the wafer surface.

  Based on the transferred pattern, the conductive film and the insulating film deposited on the wafer 9 are processed into a predetermined shape by an etching technique. The conductive film and the insulating film are deposited on the wafer 8 using a sputtering method or a CVD method. Then, after a predetermined pattern is formed, the wafer 8 is diced. Then, as shown in FIG. 3B, the chip of the semiconductor device 50 is manufactured. For example, when the semiconductor device 50 is a semiconductor memory, the chip includes a memory cell array 52 and a peripheral circuit group 51 that controls the operation of the memory cell array 52. The pattern included in the memory cell array 52 is formed with a minimum processing dimension (also called a half pitch or a feature size) F. For example, the semiconductor device may include redundancy for relieving an electrical failure.

  The defect inspection method of this embodiment is executed as follows by the defect inspection system of FIG.

  As shown in FIG. 1, an electrical failure probability distribution E (s) is calculated by the defect inspection system 1 of FIG. 2 (step ST1).

  In the present embodiment, the electrical failure probability distribution E (s) indicates a probability distribution that causes an electrical failure to a semiconductor device in which a defect having a certain feature (property) is fabricated. The first inspection object is used as a sample for calculating an electrical failure probability distribution E (s) as a reference value. Hereinafter, the first inspection object is also referred to as a reference sample.

  The defect of the reference sample is detected by inspecting the first inspection object with the defect inspection apparatus 3 of FIG.

  Here, as an example, a case where the electrical failure probability distribution E (s) is created based on the defect size will be described.

  First, the inspection object 10 as a reference sample is inspected by the defect inspection apparatus 3 in FIG. The inspection results are classified for each defect size by the control unit 21 and the calculation unit 22 of the computer 2. Then, as shown in FIG. 3, the probability that the semiconductor device corresponding to each defect size causes an electrical failure (electrical failure probability) is calculated by the computer 2. The electrical failure probability is calculated based on, for example, a test result of a semiconductor device manufactured in the past, a simulation result, or an actual measurement value of a reference sample.

  As a result, as shown in FIG. 4, a distribution E (s) of the electrical failure probability with respect to the defect size is created. As shown in FIG. 4, the horizontal axis of the graph indicates the defect size, and the vertical axis of the graph indicates the electrical failure probability. The change of the electrical failure probability with respect to the feature of the defect is shown as a characteristic line A in the drawing, for example.

  The computer 2 stores the created electrical failure probability distribution E (s) in the electrical failure probability distribution storage unit 4.

  An area where the electrical failure probability distribution E (s) is created and the defect inspection using the distribution E (s) is evaluated is, for example, the memory cell array 12 in FIG. The region where the defect of the inspection object is inspected and the region where the electrical characteristics of the semiconductor device manufactured using the inspection object can be compared.

  A detailed description of features and properties of defects for creating the electrical failure probability distribution E (s) and a method for creating the electrical failure probability distribution will be described later.

  For example, the result of the defect inspection for the reference sample is stored in the defect database 3 by the computer 2.

  After the electrical failure probability distribution E (s) is calculated, the defect inspection system 1 performs defect inspection on the second inspection object (step ST2). For example, the second inspection object is a sample different from the first inspection object (reference sample). The second inspection object is a mask, a template, a wafer, or the like used in an actual semiconductor device manufacturing process. Hereinafter, the second inspection object is referred to as a verification sample.

  The second inspection object as the verification sample is preferably a sample including an electrical failure probability comparable to the electrical failure probability calculated in step ST1, for example. As a more specific example, the verification sample is preferably a sample of the same generation as the reference sample, a sample of the same layer (hierarchy, wiring level), or a sample including the same pattern. Note that the reference sample and the verification sample may be samples of different generations, layers, or patterns as long as it is considered to be the same as the electrical failure probability calculated in step ST1. Further, the defect inspection in step ST2 may be performed by limiting to a specific region to which the electrical failure probability calculated in step ST1 can be applied.

  After the defect inspection, the defect number distribution D (s) is created by the defect inspection system 1 (step ST3).

  In step ST3, the defect detected by the inspection result for the verification sample (second inspection object) is classified for each feature in the same manner as the features classified in step ST1. Then, the number of defects is measured according to the characteristics of the classified defects. For example, FIG. 5 shows the defect number distribution D (s) when the defect size is used as the feature of the defect. As shown in FIG. 5, the horizontal axis of the graph indicates the defect size, and the vertical axis of the graph indicates the number of defects.

  For example, the defect inspection result (defect number distribution) for the verification sample is stored in the defect database 3 by the computer 2.

Then, the number of electrical failure occurrence defects is calculated by the computer 2 of the defect inspection system 1 (step ST4).
Here, the number of defects causing electrical failure indicates the number of defects that cause electrical failure in the semiconductor device manufactured using the verification sample inspected in step ST2. The number of defects that cause electrical failure is calculated for each feature of the defect.

  As an example of a method for calculating the number of defects with electrical defects, the number of defects with electrical defects is calculated by multiplying the probability of electrical defects of a certain feature obtained from a reference sample and the number of defects of a certain feature obtained from a verification sample. ,can get.

  FIG. 6 shows an example in which the number of defects with electrical defects corresponding to the defect size is calculated. In this case, the computer 2 reads the electrical failure probability distribution E (s) corresponding to the defect size in the reference / verification sample from the electrical failure probability distribution storage unit 4, and the number of defects corresponding to the defect size in the reference / verification sample. The distribution D (s) is read from the defect database 5. Then, the computer 2 calculates the number of electrical failure occurrence defects according to the defect size based on the electrical failure probability distribution E (s) corresponding to the defect size and the defect number distribution D (s) corresponding to the defect size.

  In FIG. 6, the horizontal axis of the graph indicates the defect size, the vertical axis on the left side of the graph indicates the number of defects, and the vertical axis on the right side of the graph indicates the electrical failure probability. The electrical failure probability E (s) is indicated by a solid line (characteristic line A) in the graph, and the number of defects D (s) is indicated by a bar graph. The product of the probability of electrical failure and the number of defects, that is, the number of defects with electrical failure, is indicated by diagonal lines in a region B surrounded by a broken line in the bar graph. In this way, the number of defects with electrical defects in the defect size is calculated.

  By such arithmetic processing, the number of defects in which an electrical defect has occurred in the semiconductor device is calculated for each feature of the detected defect. The number of defects with electrical failure may be calculated for the entire wafer, mask, or template, or may be calculated for each predetermined region in the wafer or for each chip in the wafer.

  Thereafter, the total number of defects with electrical defects in the verification sample is calculated (step ST5).

  Here, the total number of defects in which electrical defects have occurred indicates the total number of defects that cause electrical defects in the semiconductor devices in the features of all defects.

  As an example of a method for calculating the total number of defects in which electrical defects have occurred, calculation is performed by integrating the number of defects corresponding to each feature calculated in step ST4. For example, the total number of defects with electrical defects at a defect size in one verification sample is calculated by accumulating the number of defects for each defect size indicated by the hatched portion in the bar graph of FIG. Furthermore, the total number of electrical defects of the entire inspection object can be obtained by accumulating the total number of electrical defects of the features of the plurality of defects.

  Here, the total number of defects in which electrical defects have occurred may be calculated not only for the total number on the verification sample but also for each predetermined region of the wafer and each chip of the wafer.

  Then, it is determined whether or not the inspection object may be used by comparing the total number of defective electrical defects with a threshold value (determination value) as a determination criterion (step ST6). The threshold value as the determination criterion is set based on the manufacturing yield of the semiconductor device.

  Thereby, the defect included in the inspection object is evaluated, and the quality of use of the mask and the template and the quality of the manufacturing process for the wafer are determined. For example, when the total number of defective electrical defects is equal to or greater than a threshold value, it is determined that the use of the inspection object is inappropriate. A defect that does not cause an electrical failure of a semiconductor device is not used to determine whether or not an inspection object can be used.

  As described above, the defect inspection method of the present embodiment uses the electrical failure probability and the result of the defect inspection of the inspection object, and causes the electrical failure of the semiconductor device manufactured based on the inspection object. Calculate the defect. Accordingly, a defect that may cause an electrical failure among a plurality of defects included in the inspection object is used for determination for evaluating the defect inspection of the inspection object. In other words, defects that are less likely to cause an electrical failure of the semiconductor device are excluded from the criteria for stopping the use of the inspection object.

  As a result, the timing for identifying the cause of the occurrence of a device defect between the respective processes of manufacturing the semiconductor device or the timing for determining whether or not the mask can be used is optimized. And the time loss which arises in that case can be made small.

  Therefore, according to the defect inspection method of the first embodiment, an increase in manufacturing cost of the semiconductor device can be suppressed.

(B) Defect classification method
A defect classification method in the defect inspection method of this embodiment will be described with reference to FIG. FIG. 7 is a schematic diagram for explaining the feature of the defect formed in the inspection object. In FIG. 7, patterns 101A, 101B, 101C, and 101D and defects 105A, 105B, 105C, 105D, and 105E in the inspection object 100 are schematically shown. Patterns 101A, 101B, 101C, and 101D indicate patterns included in the mask or template, and patterns transferred or formed on the wafer.

The following examples i) to vi) are shown as features of defects for classifying defects generated in a mask for forming a semiconductor device, a template for imprint technology, or a wafer.
i) Defect size
ii) Black and white defects
iii) Defect location
iv) Pattern density
v) Pattern shape
vi) Difference signal between a defect location and a reference location in defect inspection
The defect size i) indicates the size of the defect output from the defect inspection apparatus in which the inspection object is inspected. The defect size output method differs depending on the defect inspection apparatus. As an example, the defect size is defined by the number of pixels of the inspection camera that exceeds a threshold in the difference signal between the reference image and the defect image detected by the inspection camera of the defect inspection apparatus. In addition, if the model of a defect inspection apparatus is the same, you may use the same value between apparatuses.

  For example, as the number of times the mask is used is increased, a defect is generated on the mask, and there is a growth defect in which the defect gradually grows. As an example of the growth defect, there is a defect in which the size of the member increases due to crystal growth of the member by laser irradiation. For example, a growth defect is transferred onto a wafer when the defect size is larger than a certain defect size. As a result, the manufacturing yield of semiconductor devices on the wafer is degraded.

  Like a growth defect, the defect size may vary depending on the use of the inspection object.

  The black defect and the white defect in ii) indicate the remaining or missing pattern. For example, as shown in FIG. 7A, the black defect 95 </ b> A includes the formation member 105 </ b> A of the patterns 101 </ b> A and 101 </ b> B at a place that is originally a pattern (space pattern) that is removed from the inspection object 100. The defect 105 </ b> A remains on the inspection object 100. As shown in FIG. 7B, the white defect 105 </ b> B is a defect 105 </ b> B in which the pattern is peeled off from the inspection object 100 in a portion where the member is originally a pattern on the inspection object 100. .

  For example, in a template, black defects or white defects increase due to an increase in deposits or missing patterns when the number of uses is repeated.

  For example, the black defect causes a short circuit between the wirings. On the other hand, the white defect causes, for example, disconnection (opening) of the wiring.

  Depending on the presence or absence of such black defects or white defects, the electrical failure probability of the semiconductor device varies. Therefore, it is preferable to calculate the electrical failure probability and the total number of defects with electrical failure by combining the black defect / white defect and the defect size.

  The defect location of iii) indicates a location where a defect is formed.

  For example, as shown in FIG. 7A, an isolated defect 105A is formed at a place where there is no pattern. Further, as shown in FIG. 7C, in the case of a mask or a template, a defect 105C is formed at the edge of the pattern 101A, or a defect 105D is formed at a corner of the pattern 101B. Such defects 105C and 105D may be formed in a pattern on the wafer.

  When the mask patterns 101A and 101B are transferred to the wafer by exposure, the transferability of the defects 105C and 105D varies depending on the location of the defect due to the optical proximity effect or the like. Therefore, the correlation between the defect size on the mask and the defect size transferred onto the wafer differs depending on the location of the defect on the mask. That is, even if two defects 105C and 105D having the same size exist on the mask, the sizes of those defects transferred onto the wafer vary depending on the location of the defect on the mask. As a result, the probability of electrical failure of a semiconductor device manufactured using a mask or template varies depending on the defect location. Therefore, when classifying a defect of a mask or a template, it is also effective to classify a defect portion (defect position or defect coordinate) on the mask or template.

  In addition, when the wafer is an inspection object, a semiconductor device is manufactured according to the position of a defect on the wafer, such as a critical path formation region or a pattern formation region having a relatively large size or a relatively large pitch. In some cases, the probability of occurrence of electrical failure is different. Therefore, such a classification according to the defect location is also effective in the defect inspection for the wafer.

The pattern density of iv) indicates the density of the pattern in the area where the defect exists. For example, like the memory cell array of the semiconductor memory shown in FIG. 3B, the pattern density may be the same even between different layers in the wafer, mask, or template.
Therefore, by classifying by pattern density, a common electrical failure probability distribution E (s) can be used even between different layers, and different layers can be used by a common electrical failure probability distribution E (s). Defect inspection and evaluation can be performed. Even if the generations of semiconductor devices (minimum dimensions / circuit design) are different, a common electrical failure probability distribution E (s) may be used as long as a similar pattern density exists. Good.

  For example, as shown in FIG. 7D, if the density of patterns 101A, 101B, 101C, and 101D within a certain area is high, the number of defects 105E may be small or the size of defects 95E may be small. The probability of electrical failure tends to increase. On the other hand, as shown in FIG. 7E, if the density of the patterns 90A and 95B within a certain area is low, the electrical failure probability is relatively small even if the defect 105E is included.

  The pattern shape v) means the shape of a pattern in which a defect exists. For example, when the probability that an electrical failure of a semiconductor device occurs varies depending on the shape of the pattern, the electrical failure probability distribution E (s) may be calculated by classification for each pattern.

  vi) The difference signal between the defect location and the reference location in the defect inspection is the difference signal between the defect location and the reference location in the comparison inspection such as Cell-to-Cell, Die-to-Die, and Die-to-Database. Show. This difference signal is closely related to the defect size. Therefore, a method of classifying defects for each difference signal is also effective.

  Thus, by classifying the defects in the inspection object according to their features, a more accurate electrical failure probability distribution E (s) can be created. Accordingly, the total number of electrical defect defects for the semiconductor device can be calculated with higher accuracy.

  It should be noted that the electrical failure probability, the defect number distribution, and the total number of defects with electrical failure may be calculated by appropriately combining these examples.

(C) Calculation method of electrical failure probability distribution
A method for calculating the electrical failure probability distribution E (s) in the defect inspection method according to the present embodiment will be described with reference to FIGS. The electrical failure probability distribution E (s) is executed by the defect evaluation system of FIG.

  FIG. 8 shows a flowchart for calculating the electrical failure probability distribution E (s) in step ST1 of FIG.

  First, as shown in FIG. 8, a first inspection object for calculating an electrical failure probability distribution E (s) is selected (step ST10).

  As described above, the inspection object is used to calculate the electrical failure probability distribution E (s). The inspection object for calculating the electrical failure probability distribution E (s) is substantially a reference sample.

  In order to calculate the electrical failure probability distribution E (s) with higher accuracy, an inspection object (called a test pattern) in which the defects shown in i) to vii) are intentionally formed is used. It is preferred that

  As a method for producing an inspection object in which defects having the above-mentioned features are intentionally formed, for example, there is a method of forming on a mask or template black defects and white defects having different defect sizes for each defect location. is there. By transferring the mask or template pattern thus produced onto the wafer, a wafer having defects having different characteristics can be produced. As a result, a semiconductor device is manufactured using an inspection object including an intentionally formed defect, and the probability that the device causes an electrical failure is obtained.

  The inspection object in which the yield is reduced in the semiconductor device manufacturing process may be used as a reference sample for calculating the electrical failure probability distribution E (s). In this case, the defect is randomly formed and arranged on the inspection object. In other words, compared to the case where the defect is intentionally formed on the inspection object, the defect size and shape, the constituent element of the defect, and the formation location of the defect are in a state close to the operation (usage status) of the manufacturing site, Appears on used inspection objects.

  Note that if the number of defects on the inspection object is small, a highly accurate electrical failure probability distribution E (s) may not be created. Therefore, the inspection object preferably includes many defects.

As shown in FIG. 8, a defect inspection is performed on the selected inspection object by the defect inspection apparatus 3 in FIG. 2 (step ST11A).
Then, based on the result of the defect inspection, the detected defects are classified for each feature of the defect, and the number of each defect is calculated. Thereby, for example, the defect number distribution D ′ (s) of the reference sample as shown in FIG. 5 is created (step ST11B). For example, the defect number distribution D ′ (s) of the reference sample is stored in the defect database 5 similarly to the defect number distribution D (s) of the verification sample in step ST3 of FIG.

In addition, a semiconductor device is manufactured using an inspection object or substantially the same object (step ST12A).
The electrical characteristics of the manufactured semiconductor device are measured (step ST12B).
Based on the measurement result of the electrical characteristics, an electrical failure map (Fail Bit Map) of the device is created (step ST12C).

  Note that steps ST11A and ST11B for the inspection target may be executed after steps ST12A, ST12B, and ST12C for the semiconductor device are executed.

The electrical failure map will be described with reference to FIGS. 9 and 10.
As shown in FIG. 9, a semiconductor device (chip) is manufactured by transferring a mask or template pattern to a single wafer 8 a plurality of times by changing the area 9A to be transferred. . Therefore, when a mask or template is selected as the inspection object (reference sample), the method of creating the electrical defect map is different from that when the wafer is selected as the reference sample. When a mask or template is used for the reference sample, the electrical failure map in step ST12C needs to be converted from an electrical failure map obtained from the wafer 8 to a mask / template electrical failure map. For example, the electrical defect map on the wafer 8 is converted into a mask / template defect map by the defect inspection system 1 of FIG. 2 as follows.

  The wafer 8 is classified by the computer 2 of FIG. 2 for each region 9A transferred by the mask / template. The positions of the defects D1, D2, and D3 on the wafer 8 are converted into coordinates in each area 9 by the computer 2. Each coordinate is superimposed by the computer 2. This provides a device electrical failure map in the mask / template.

  FIG. 10 shows an example of an electrical failure map in the mask or template. Region 9 corresponds to one mask / template. After the electrical failure map in the mask / template 9 as shown in FIG. 10 is created, the concept of the number of electrical failures at the positions (coordinates) of the defects D1 ′, D2 ′, D3 ′ included in the mask / template 9 is This is important for the creation of the dynamic failure probability distribution E (s).

  As the concept of the number of electrical defects, there are a method for calculating the number of defects in consideration of the defect rate and a method for calculating the number of defects without considering the defect rate. Here, the defect rate indicates a ratio of the number of periodic defects due to defects at the same coordinates in the mask / template to the total number of times the mask / template is transferred to one wafer.

  As described above, in the semiconductor device manufacturing process, the same mask / template pattern is transferred to a plurality of regions in one wafer. Therefore, if defects D1 ′, D2 ′, and D3 ′ exist on the mask and the template, the defects D1 are periodically formed on the wafer 8 according to the coordinates of the defects in the mask / template, as shown in FIG. , D2, D3 are transferred. However, even if the defect is transferred periodically, the transferability of the defect is slightly different each time the pattern is transferred to the wafer, for example, depending on the coordinates in the wafer or the exposure variation of the exposure apparatus.

  Therefore, even if the feature / property of the defect in the mask / template 9 is the same, the feature / property of the defect transferred to the wafer 8 is not the same in the plurality of regions 9A. The feature / property of the defect may be different for each coordinate of the wafer 8. As a result, each time a pattern including a defect is transferred, an electrical failure caused by the defect occurs and an electrical failure does not occur even if the defect is transferred. Exists. Further, the defects D1 ', D2', D3 'of the mask / template 9 may not be transferred to the wafer.

  Thus, in order to consider the difference between the defect contained in the mask / template and the defect transferred to the wafer, the concept of defect rate is introduced in the calculation of the electrical defect probability.

  For example, the defect rate relating to the coordinates of the defect D1 'in the mask / template 9 shown in FIG. 10 is calculated using the electrical defect map in the wafer 8 in FIG.

  One wafer 8 is classified for each area 9A (hereinafter referred to as a transfer area) transferred by a mask / template.

  The number of transfer areas 9A in the wafer 8 is calculated by a computer. For example, in the example shown in FIG. 9, since the pattern transfer is executed 30 times, 30 transfer regions 9A are formed in one wafer 8.

  In the example shown in FIG. 9, the number of defects D <b> 1 (black circles in FIG. 9) periodically generated on the main wafer 8 is six. Therefore, for the mask / template defect D1 ′, the number of transfer regions 9 is 30 and the number of defects D1 transferred onto the wafer is 6. Therefore, the defect rate DR caused by the defect D1 is (6 / 30) × 100 = 20%.

  When the number of defects is calculated in consideration of the defect rate, the number of defects is indicated by (DR (%) / 100). In the above example, since the defect rate related to the defect D1 is 20%, the number of defects D1 'in the coordinates of the mask / template is counted as 0.2. For the defects D2 'and D3' in the mask / template, similarly to the defect D1 ', the number of defects in consideration of the defect rate can be calculated.

  On the other hand, when the defect rate is not considered, defects at the coordinates of the mask / template 9 are simply counted without considering the number of defects formed on the wafer 8. For example, when the defect rate is not considered, the number of defects D1 'in the coordinates of the mask / template 9 is counted as one.

  After the electrical defect map is created in this way, the position information of the electrical defect map and the number of defects are collated based on the defect coordinates acquired by defect inspection and the number of defects for each feature ( Step ST13). Thereby, the number of defects of each feature is tabulated.

  Based on the verified defect information, the ratio of the number of defects with electrical defects generated for each defect feature out of the calculated number of defects is calculated as an electrical defect probability as shown in FIG. (Step ST14). Note that the number of defects based on the defect rate may be considered when collating the position of the defect, or may be considered when calculating the electrical defect probability.

  As described above, the electrical failure probability distribution E (s) is calculated. Thereafter, the processing from step ST2 to step ST6 in FIG. 1 is executed.

  According to the defect inspection method according to the first embodiment, it is possible to classify defects into various features, and it is possible to produce an electrical failure probability distribution E (s) with higher accuracy. As a result, the total number of defective electrical defects can be calculated with higher accuracy.

  Then, using the electrical failure probability distribution, the defect inspection for the inspection object is performed by treating only the defect causing the electrical failure among the plurality of defects included in the inspection object as a factor that reduces the manufacturing yield of the semiconductor device. evaluate. As a result, unnecessary remanufacture and repair of masks and templates and unnecessary verification of the manufacturing process can be prevented, and an increase in manufacturing cost of semiconductor devices can be suppressed.

(D) Summary
In the defect inspection method of the first embodiment, using the first inspection object (reference sample), the probability of an electrical failure occurring in the semiconductor device according to the feature / property of the defect of the inspection object is calculated, An electrical failure probability distribution E (s) for each defect feature is created. For example, in calculating the electrical failure probability distribution, as described with reference to FIGS. 8 to 10, in consideration of the difference between the feature of the defect included in the mask / template and the feature of the defect transferred to the wafer, The concept of defect rate is introduced.

  Based on the calculated electrical failure probability and the number of defects obtained from the second inspection object (verification sample), the number of electrical failures in the semiconductor device manufactured using the verification sample is calculated. .

  The suitability of the inspection object is determined by comparing the number of defects that cause an electrical failure of the semiconductor device with a predetermined threshold.

  As described above, in the defect inspection method of this embodiment, it is determined whether or not the detected defect is a defect that causes an electrical failure of the semiconductor device in which the detected defect is formed. Of the defects included in the inspection object, defects that do not cause an electrical failure are unlikely to reduce the manufacturing yield of the semiconductor device at the defect inspection stage. Exclude from judgment. Since it is clear that a defect that causes an electrical failure reduces the manufacturing yield of the semiconductor device, the defect that causes an electrical failure of the semiconductor device is used to determine the suitability of the use of the inspection object.

  That is, only defects that cause an electrical failure of the semiconductor device are considered without dealing with defects that do not cause an electrical failure at the stage where the defects are inspected. As a result, it is possible to optimize the use of the mask and the template and the timing for identifying the cause of the defect during the manufacturing process. And the increase in the period and cost for producing a mask and a template, and the time loss by the operation stop of a semiconductor manufacturing apparatus can be suppressed.

  Therefore, according to the defect inspection method of the first embodiment, an increase in the manufacturing cost of the semiconductor device can be suppressed.

(2) Second embodiment
A second embodiment will be described with reference to FIG.

  Based on the above-described defect inspection method, it is also possible to evaluate the yield of a semiconductor device manufactured using an inspection object.

  The defect inspection method described with reference to FIG. 1 calculates the number (probability) that a semiconductor device manufactured using the inspection object causes an electrical failure from the inspection result of the inspection object. For this reason, the manufacturing yield of the semiconductor device can be predicted by considering the total number of defects in which electrical defects have occurred with respect to locations that can be relieved by the redundancy included in the semiconductor device. In consideration of the predicted semiconductor device manufacturing yield, it is possible to determine the suitability of the use of the inspection object.

  FIG. 11 shows a flowchart of the manufacturing yield evaluation method in the defect inspection of the second embodiment.

  As shown in FIG. 11, after the total number of defects with electrical defects is calculated, the semiconductor device manufacturing yield is predicted in consideration of the redundancy of the semiconductor device. (Step ST6A). Then, in consideration of the predicted yield of the semiconductor device, whether or not the inspection object is used is determined (step ST6B).

  For example, consider a case where a semiconductor device manufactured using a certain inspection object has A repairable number in one chip due to redundancy. When the total number of defects causing electrical failure in one chip calculated using the above-described defect inspection method is greater than A, the number exceeds the number that can be remedied, and thus there is a high possibility that the yield will decrease.

  Therefore, if the number of defects that cause an electrical failure exceeds the tolerance for redundancy, the decision to stop using the mask / template as the inspection object and the cause of the failure in each process during the manufacturing process Judgment to verify becomes possible.

  On the other hand, when the total number of defects causing electrical failure in one chip calculated using the above-described defect inspection method is A or less, the total number of defects in one chip is within the allowable range of repair by redundancy. . Therefore, when the number of defects that cause an electrical failure is less than the allowable range of repair by redundancy, the yield of the semiconductor device is reduced even if the semiconductor device is manufactured using a mask, template, or wafer as an inspection object. The possibility of doing is low. Therefore, the use of the inspected mask / template can continue. Moreover, it is not necessary to verify the cause of the defect in each manufacturing process based on the inspected wafer.

  As shown in FIG. 11, in the defect inspection method according to the second embodiment, the manufacturing yield in the manufacturing process using the inspection object is predicted in consideration of the number that can be relieved by redundancy, for example.

  Thereby, it is possible to optimize the determination of the suitability of the use of the mask and the template, and the setting of the timing for identifying the cause of occurrence of a defect that occurs in the wafer during each manufacturing process. As a result, it is possible to reduce the cost / time for re-manufacturing and repairing the mask and template, and to reduce the time required for identifying the cause of the defect.

  Therefore, according to the second embodiment, the manufacturing yield of the semiconductor device can be evaluated, and the increase in the manufacturing cost of the semiconductor device can be suppressed as in the defect inspection method according to the first embodiment.

(3) Third embodiment
The third embodiment will be described with reference to FIG. In the present embodiment, a defect inspection apparatus that executes the defect inspection method of FIG. 1 or FIG. 2 will be described.

  FIG. 12 is a block diagram schematically showing the configuration of the defect inspection apparatus 3A of the present embodiment. The defect inspection apparatus 3A shown in FIG. 12 executes the process shown in FIG.

  The defect inspection apparatus 3A of FIG. 12 includes a control unit 31, an inspection unit 38, and a storage unit 39.

  The control unit 31, the inspection unit 38, and the storage unit 39 are connected to each other. The inspection unit 38 includes a defect inspection unit 32, a defect number distribution creation unit 33, an electrical defect number calculation unit 34, an electrical defect number output unit 35, and a suitability determination unit 36. The storage unit 39 includes an electrical failure probability distribution storage unit 4 and a defect database 5.

  The control unit 31 manages the operation status of the entire apparatus 3A. The control unit 31 controls the operations of the components 32, 33, 34, 35, and 36 in the inspection unit 38 and the operations of the components 4 and 5 in the storage unit 39.

  The electrical failure probability distribution storage unit 4 stores an electrical failure probability distribution E (s). Similar to the first and second embodiments, the electrical failure probability distribution E (s) is a value calculated for each feature of the defect of the inspection object. As in the first and second embodiments, the electrical failure probability distribution E (s) is created in advance based on values calculated by the inspection unit 38 and values obtained from past inspection results. .

  For example, the defect inspection unit 32 inputs inspection objects such as a mask, a template, or a wafer, and inspects defects included in the inspection objects. The defect inspection unit 32 includes, for example, a defect included in an inspection object (verification sample) being used in a manufacturing process or an inspection object (reference sample) for creating an electrical failure probability distribution E (s). Inspect for contained defects. The defect inspection unit 32 stores the inspection result of the inspection object in the defect database 5 under the control of the control unit 31.

  The defect number distribution creating unit 33 reads defect inspection data from the defect database 5 under the control of the control unit 31. Then, the defect number distribution creating unit 33 classifies the defects detected from the inspection object for each feature, and creates a defect distribution in the inspection object. Thereby, the defect number distribution creating unit 33 calculates the defect number distribution D (s) for each feature.

  The electrical defect number calculation unit 34 stores an electrical failure probability distribution E (s) corresponding to the inspection object for which the defect number distribution D (s) is created under the control of the control unit 31. Read from unit 4. Then, the electrical defect number calculation unit 34 calculates the product of the created defect number distribution D (s) and the read electrical defect probability distribution E (s) under the control of the control unit 31. As a result, the number of defects in which an electrical defect has occurred in a semiconductor device manufactured using an inspection object in one wafer is calculated. Note that the electrical defect number calculation unit 34 calculates the product of the defect number distribution D (s) and the electrical defect distribution E (s) for each classified feature.

  Then, the electrical defect number calculation unit 34 calculates the total number of electrical defect occurrence defects by integrating the number of electrical defect occurrence defects for each feature.

  The electrical defect number output unit 35 acquires the calculation result of the electrical defect number calculation unit 34 and outputs the acquired value to the suitability determination unit 36.

  The suitability determination unit 36 determines the quality of the inspection object or the quality of the manufacturing yield of the semiconductor device manufactured using the inspection object based on the total number of defects with electrical defects.

  For example, the control unit 31 sets in advance a predetermined threshold value for the total number of electrical defect occurrence defects. Based on the threshold value, the suitability determination unit 36 determines the quality of the manufacturing process and the manufacturing yield.

  For example, when the number of redundancy of a chip is used as a threshold for determining pass / fail, the pass / fail of a test object is determined in consideration of the yield of semiconductor devices by setting the number of redundancy as a threshold. it can.

  The determination result of the suitability determination unit 36 is output to the outside of the defect inspection apparatus 3A. Based on the determination result, the defect inspection for the inspection object is evaluated. As a result, judgments are made on the use of the inspection object and the continuation of the use of the manufacturing process for the inspection object, the re-creation of the mask / template as the inspection object, the verification of the manufacturing process for the wafer as the inspection object, and the like. The

  As described above, the defect inspection apparatus 3A of the present embodiment calculates the electrical failure probability and the number of defects causing electrical failure in the semiconductor device formed using the inspection target, and based on the calculation result, The inspection result for the inspection object is determined.

  As a result, similar to the first and second embodiments, it is possible to reduce the cost / reproduction time of masks and templates. In addition, the timing for verifying the cause of failure during the manufacturing process can be optimized, and the time required to identify the cause of failure can be reduced.

  Note that the defect inspection apparatus 3 of the defect inspection system of FIG. 2 may have the configuration of FIG.

  Therefore, according to the defect inspection apparatus of the third embodiment, an increase in manufacturing cost of the semiconductor device can be suppressed.

(4) Modification
A modification of the defect inspection method of the first and second embodiments will be described with reference to FIG.

  As shown in FIG. 13, the defect inspection methods of the first and second embodiments may be executed as a program 6B stored in the recording medium 6A. The recording medium 6A is, for example, an optical disk (CD), a magnetic disk (HDD), or a semiconductor memory (flash memory). However, the program 7 may be provided to the computer 2 or the defect inspection apparatus 3 from an external server or storage device via a wired or wireless line. The program 6B may be stored in the storage unit 23 inside the computer 2.

  The computer 2 reads the program 6B from the recording medium 6A and executes the program 6B.

  The defect inspection program 6B is, for example, a plurality of program codes corresponding to the steps ST1 to ST6 shown in FIG. 1, a plurality of program codes corresponding to the steps ST1 to ST6B shown in FIG. 11, or shown in FIG. A plurality of program codes corresponding to the steps ST10 to ST14 are included.

  The computer 2 operates the external defect inspection apparatus 3 based on the program code described in the defect inspection program 7 of the recording medium 6 and executes arithmetic processing on the inspection result.

  As shown in FIG. 13, the first to second mask and template manufacturing apparatuses (hereinafter referred to as mask / template manufacturing apparatuses) 7 and semiconductor device manufacturing apparatuses 8 such as CVD apparatuses and etching apparatuses are used. The result of the defect inspection obtained from the third embodiment may be reflected and used for optimizing semiconductor device manufacturing conditions and mask / template pattern design.

As described above, the defect inspection for the inspection object is evaluated based on the electrical failure probability distribution and the detected number of defects, as in the first and second embodiments.
Therefore, even when the defect inspection method described in the first and second embodiments is executed as a program as in the modification of the present embodiment, an increase in the manufacturing cost of the semiconductor device is suppressed.

(5) Application examples
An application example of the defect inspection method according to the first and second embodiments or the defect inspection apparatus according to the third embodiment will be described with reference to FIG.

  As described above, the mask, template, or wafer used during the manufacturing process becomes an inspection object for defect inspection. Therefore, the defect inspection method and apparatus according to the present embodiment are applied during a period from when a mask / template is manufactured to when a semiconductor device is shipped.

  For example, as shown in FIG. 14, a mask and a template are produced based on the designed circuit (step ST101).

  In addition, an electrical failure probability distribution E (s) is created using the produced mask / template or test pattern as a reference sample (step ST201).

  The produced mask / template pattern is transferred to the wafer surface on which the conductive film or insulating film is deposited. Based on the transferred pattern, the conductive film or the insulating film is processed, and a semiconductor device corresponding to the designed circuit is manufactured (step ST102).

  The manufactured semiconductor device is shipped (step ST103).

  After a predetermined period of use (cycle) in device fabrication and shipment has elapsed, at least one of the wafer, mask, or template used in the fabrication of the semiconductor device is defective as an inspection object (verification sample). It is put into an inspection system or a defect inspection apparatus (step ST301).

A defect of the inspection object is inspected (step ST202).
As in the above-described embodiment, the inspection object is evaluated using the defect included in the inspection object and the electrical failure probability. It is verified whether or not the detected defect is a defect that causes an electrical failure of the semiconductor device. Then, the number of defects that cause an electrical failure included in the inspection object is counted.

  Based on the number of defects that cause an electrical failure, whether or not the inspection object is used is determined (step ST203).

  When it is determined that the defect included in the mask / template or the defect formed by the manufacturing process does not reduce the manufacturing yield of the semiconductor device, the inspection object and the inspection object are used. Existing process conditions are used continuously.

  Due to the determination on the inspection object, the defect included in the mask / template, the current manufacturing process conditions, or the manufacturing apparatus itself may decrease the manufacturing yield of the semiconductor device, or the manufacturing yield may be decreased at a similar time. If it is determined that there is, mask / template re-creation or repair, and process condition verification are performed (step ST204). As a result, the mask / template is recreated or repaired, and the process conditions are optimized.

  As described above, the defect inspection method and the defect inspection apparatus according to the above-described embodiment can be applied to a semiconductor device manufacturing process. This suppresses an increase in manufacturing cost of the semiconductor device.

[Others]
In each of the above-described embodiments, the order of the defect inspection and evaluation processes for the inspection object may be interchanged within a processable range. Further, they may be appropriately combined within a range where processing is possible.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1: defect inspection system, 2: computer, 3, 3A: defect inspection apparatus, 5: defect database, 4: electrical failure probability distribution storage unit, 32: defect inspection unit, 33: defect distribution creation unit, 34: electrical Defect number calculation unit, 35: electrical defect number output unit, and 36: suitability determination unit.

Claims (5)

Inspecting whether or not the first inspection object includes a defect in at least one first inspection object of a wafer, a mask, and a template;
Classifying the defects detected from the first inspection object by feature, and calculating the number of defects for each feature of the defect;
Measuring electrical characteristics of semiconductor devices on the wafer and creating a defect map of the semiconductor devices on the wafer;
Collating the defect map with the position of the defect of the inspection object, calculating an electrical defect probability of the semiconductor device for each feature of the defect;
Using the electrical failure probability to determine the suitability of the use of the second inspection object including a defect;
A defect inspection method comprising: The step of determining the suitability of the use of the second inspection object includes:
Inspecting whether or not at least one second inspection object of the wafer, mask and template used in the manufacturing process of the semiconductor device includes a defect,
Classifying the defects contained in the second inspection object according to the features of the defects;
Calculate the number of defects for each defect feature,
Based on the probability of electrical failure and the number of defects, the number of defects that cause electrical failure in each feature of the defect is calculated,
Calculating the total number of defects that cause electrical failure contained in the second inspection object;
Comparing the determination value and the total number of defects causing the electrical failure to determine the suitability of the second inspection object,
The defect inspection method according to claim 1.   The defect inspection method according to claim 1, further comprising a step of predicting a manufacturing yield of the semiconductor device based on a redundancy number included in the semiconductor device.   The feature of the defect is at least one selected from a defect size, a black or white defect, a formation position of the defect, a density of a pattern in which the defect is formed, and a difference signal between the defect part and the reference part. The defect inspection method according to any one of claims 1 to 3, wherein A storage unit storing a probability of electrical failure of a semiconductor device caused by a defect included in the inspection target;
A defect inspection unit for inspecting defects included in the inspection object;
Based on the inspection result, a defect inspection distribution creating unit for creating a defect number distribution for each feature of the defect,
Based on the electrical failure probability and the defect number distribution, an electrical failure number calculation unit that calculates the number of defects that cause electrical failure in the semiconductor device;
A determination unit that determines the suitability of the inspection object based on the number of defects that cause the electrical failure;
A defect inspection apparatus comprising:

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