JP2006108659A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the device, in which the production process can be simplified and the production cost can be reduced, as compared to prior art. <P>SOLUTION: A one-side copper-foil resin sheet is made contact with and laminated on each of both front and back surfaces of the semiconductor substrate 1 provided with through holes 4, with a resin surface of the sheet kept in contact with each of both surfaces of the substrate 1, and the inner surface of the through hole 4 and both surfaces of the semiconductor substrate 1 are covered with an insulating resin layer 5, formed by laminating one-side copper-foil resin sheets. Outside the insulating resin layer 5, in addition, there are formed wiring layers 6, each having a double-layer structure made up of a copper foil pattern layer and a copper plated layer formed thereon. Furthermore, a post 7 made of electrically conductive material, such as copper, is formed on the insulating resin layer 5 in the inside of the through hole 4 so as to electrically connect the wiring layers on both surfaces of the semiconductor substrate 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device suitable for a multichip package or the like on which a plurality of semiconductor elements (semiconductor chips) are mounted, and a method for manufacturing the same.

2. Description of the Related Art Conventionally, in order to reduce the size of a semiconductor device, a multi-chip type semiconductor device configured by arranging a plurality of semiconductor chips on a substrate is known. In addition, a semiconductor device is also known in which a connection plug that electrically connects the front and back of a semiconductor chip is provided so as to penetrate the semiconductor chip, and is electrically connected to another semiconductor chip by this connection plug, and the semiconductor chips are stacked. (For example, refer to Patent Document 1).
JP-A-10-223833

  Among the above-described conventional semiconductor devices, in a semiconductor device provided with a connection plug that penetrates a semiconductor chip and electrically connects the front and back thereof, the connection plug is formed using a semiconductor manufacturing process. There exists a subject that a process is long and manufacturing cost becomes high.

  The present invention has been made to solve the above-described problems, and provides a semiconductor device and a method for manufacturing the same that can simplify the manufacturing process and reduce the manufacturing cost as compared with the related art. Objective.

  A semiconductor device according to an aspect of the present invention includes a semiconductor substrate having a through hole penetrating the front and back surfaces, a first insulating resin layer formed on the inner surface of the through hole, and at least a front surface and a back surface of the semiconductor substrate. The second insulating resin layer formed on one surface, and continuously formed in the through hole so as to connect at least the front and back surfaces of the semiconductor substrate, and the inner surface of the through hole are the first A conductor layer insulated by the insulating resin layer, and a copper foil formed in a predetermined region on the second insulating resin layer and electrically connected to the conductor layer. It is characterized by.

  A method for manufacturing a semiconductor device according to an aspect of the present invention includes a step of forming a through hole in a semiconductor substrate, and a resin sheet with a single-sided copper foil is disposed on both sides of the semiconductor substrate so that the resin surface comes into contact with each other. A step of laminating, a step of forming a hole having a diameter smaller than that of the through hole in the portion of the through hole of the semiconductor substrate, a conductor layer formed inside the hole, and disposed on both sides of the semiconductor substrate A step of electrically connecting the copper foil and a step of wiring the copper foil.

  According to the semiconductor device and the manufacturing method thereof according to one aspect of the present invention, the through hole has the conductor layer insulated through the insulating resin layer having good adhesion to the inner wall surface, It is possible to easily and inexpensively obtain a semiconductor device with high insulation reliability suitable for a multichip package or the like in which semiconductor chips are stacked and mounted. And a manufacturing process can be simplified compared with the past, and reduction of manufacturing cost can be aimed at.

  Hereinafter, modes for carrying out the present invention will be described. In addition, although embodiment is described based on drawing in the following description, those drawings are provided for illustration and this invention is not limited to those drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor substrate such as a silicon wafer, the surface side of which is an element region, and an integrated element part and a multilayer wiring part 2 for connecting each element are formed. On the surface of the semiconductor substrate 1, electrode pads 3 connected to the multilayer wiring portion and used for signal transmission with the outside are formed. Further, a through hole 4 penetrating the front and back is formed in the semiconductor substrate 1.

  A resin sheet with a single-sided copper foil is laminated on both the front and back surfaces of the semiconductor substrate 1 having the through holes 4 so that the resin surfaces are in contact with each other. Is covered with an insulating resin layer 5 formed of a laminated resin sheet with a copper foil on one side.

  Furthermore, a wiring layer 6 is formed outside the insulating resin layer 5 formed on both the front and back surfaces of the semiconductor substrate 1. The wiring layer 6 has a two-layer structure of a copper foil pattern layer formed by patterning a copper foil of a resin sheet with a single-sided copper foil, and a copper plating layer formed thereon. A plated layer such as Ni / Au can be further formed on the copper plated layer. Further, a conductor post 7 such as copper is formed on the insulating resin layer 5 inside the through hole 4 so as to connect the wiring layers 6 on both surfaces of the semiconductor substrate 1. In FIG. 1, reference numeral 8 denotes a resin hole having a smaller diameter than the through hole 4 formed in the insulating resin layer 5 disposed inside the through hole 4. Reference numeral 9 denotes a conductor (copper) formed in the opening of the insulating resin layer 5 in the electrode pad 3 portion.

  In the semiconductor device according to the first embodiment configured as described above, the insulating resin layer 5 and the wiring layer 6 are formed using a resin sheet with a single-sided copper foil, which is a relatively low-cost member for a printed circuit board. It is comprised by. Moreover, since the wiring layer 6 has a two-layer structure of a copper foil pattern layer formed by patterning a copper foil of a resin sheet with a single-sided copper foil, and a copper plating layer formed thereon. The adhesion strength with the lower insulating resin layer 5 is large, and the impact resistance is excellent.

  That is, the copper foil pattern layer formed by laminating the resin sheet with single-sided copper foil has a large number of fine irregularities at the interface with the insulating resin layer 5, and thus is formed directly on the insulating resin layer 5. The adhesion strength with the lower layer is greater than the copper plating layer. Specifically, the measured value in the 90 ° C. peel test of the copper plating layer is 0.6 to 0.8 kgf / cm, whereas the measured value of the copper foil layer formed by lamination is 1.5 kgf / cm. And has increased significantly.

  Furthermore, according to the semiconductor device of this embodiment, as shown in FIG. 2, a space-saving semiconductor stacked package (stacked multichip package) formed by stacking a plurality of semiconductor devices 21, 22, and 23 in the vertical direction. 20 can be easily realized. Examples of the semiconductor stacked package 20 include a stacked package of a plurality of memory chips, a stacked package of memory and logic, and a stacked package in a module using a sensor chip.

  Next, a second embodiment, which is a method for manufacturing the semiconductor device of the first embodiment described above, will be described with reference to FIG. In this embodiment, first, as shown in FIG. 3A, for example, a laser is applied to a semiconductor substrate 1 having an element part or a multilayer wiring part (silicon wiring layer) 2 on the surface side and having an electrode pad 3 formed thereon. To form the through hole 4. The through hole 4 may be formed at any position on the semiconductor substrate 1 (semiconductor chip), and can be formed at a position suitable for connection with other packages or components. Moreover, although the limit value of the through hole 4 varies depending on the thickness of the semiconductor substrate 1, it is about 0.02 to 0.1 mm.

  Next, as shown in FIG. 3B, a sheet of insulating resin 11 (resin sheet with a single-sided copper foil) having a copper foil 10 deposited on one side is brought into contact with both sides of the semiconductor substrate 1. In this way, the both sides of the semiconductor substrate 1 are covered with the insulating resin 11 and the through hole 4 is filled with the insulating resin 11. This laminating step is performed by vacuum hot pressing in the same manner as the printed wiring board manufacturing step. In the second embodiment, for example, a resin sheet with a single-sided copper foil having a resin thickness of about 30 μm and a copper foil thickness of 12 μm is used.

  Next, as shown in FIG. 3C, a resin hole 8 having a smaller diameter than the through hole 4 is formed in the insulating resin 11 filled in the through hole 4, and the electrode pad 3 on the semiconductor substrate 1 is formed. An opening 3 a is formed in the upper insulating resin 11. A laser processing machine can be used for the opening process of the insulating resin 11, that is, the formation of the resin hole 8 and the opening 3a. The diameter of the resin hole 8 is, for example, about 70 μm. Further, in this embodiment, the resin hole 8 is a non-through hole in which only one side (surface side) is opened. However, the resin hole 8 is a through hole in which the copper foil 10 on both sides of the semiconductor substrate 1 is opened. Also good.

  Next, a conductor such as copper is plated in the resin hole 8, the opening 3 a on the electrode pad 3, and the copper foil 10. By this plating process, as shown in FIG. 3D, a conductor post 7 is formed in the resin hole 8. Further, on both the front and back surfaces of the semiconductor substrate 1, a conductor layer 12 for wiring formation is formed by the copper foil 10 and the copper plating layer laminated and formed thereon. In this embodiment, the plating process for completely filling the resin hole 8 and the opening 3a is performed. However, as described later, a copper plating layer can be formed only on the side wall surface and the bottom of the resin hole 8.

  Next, as shown in FIG. 4 (e), an etching resist 13 is formed in a predetermined portion of the wiring forming conductor layer 12 formed on both the front and back surfaces of the semiconductor substrate 1. Thereafter, as shown in FIG. 4F, the wiring forming conductor layer 12 is etched using the etching resist 13 as a mask to form the wiring layer 6 having a predetermined pattern. Thereafter, as shown in FIG. 4G, the etching resist 13 is removed and a completed state is obtained. The actual manufacturing process is performed in the state of a semiconductor wafer, and after reaching the above-mentioned completed state, it is diced into a finished product of each chip.

  As described above, in the first and second embodiments, processes other than the process of forming the through hole 4 in the semiconductor substrate 1 can be processed by almost the same method as the method for manufacturing a printed wiring board, compared with the conventional method. Thus, a semiconductor device can be easily manufactured at low cost.

  FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention. In FIG. 5, the same parts as those of the semiconductor device shown in FIG. The semiconductor device of the third embodiment has a structure in which the resin hole 8 and the opening 3a described above are not completely embedded with the conductor plating layer. That is, a conductor plating layer is formed only on the side wall surface and bottom of the resin hole 8 and the opening 3a, and the electrodes on both surfaces of the semiconductor substrate 1 are electrically connected by the tubular conductor 12a formed in the resin hole 8. It is connected to the.

  The semiconductor device of the third embodiment is manufactured through the steps shown in FIGS. FIGS. 6A to 6D and FIGS. 7E to 7G are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the fourth embodiment. 6 and 7, parts corresponding to those in the semiconductor device manufacturing process shown in FIGS. 3 and 4 are denoted by the same reference numerals, and description thereof is omitted.

  In the manufacturing process of this semiconductor device, only the plating process shown in FIG. 6 (d) is different from the first embodiment shown in FIG. 3, and the inside of the resin hole 8 and the opening 3a is controlled by controlling the plating conditions. The conductor plating layer 14 is formed only on the side wall surface and the bottom portion. Also in such a method for manufacturing a semiconductor device, it is possible to manufacture the semiconductor device more easily and at a lower cost than conventional methods.

  FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to the fifth embodiment of the present invention. In FIG. 8, the same parts as those of the semiconductor device shown in FIG. The semiconductor device according to the fifth embodiment has a structure in which the conductor portion is not formed in the resin hole 8 by plating, but the resin hole 8 is filled with the conductive resin 15. The electrodes on both sides of the semiconductor substrate 1 are electrically connected by the filling layer of the conductive resin 15.

  The semiconductor device of the fifth embodiment is manufactured through the steps shown in FIGS. FIGS. 9A to 9D and FIGS. 10E to 10H are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the sixth embodiment. In this embodiment, instead of the plating process shown in FIG. 3 (d), the process of filling the conductive resin 15 into the resin hole 8 shown in FIG. 9 (d) and the surface shown in FIG. 10 (e). A polishing step of the side conductive resin 15 is performed. Other steps are the same as those of the second embodiment shown in FIGS. Also by such a method for manufacturing a semiconductor device, it is possible to manufacture a semiconductor device more easily and at a lower cost than conventional methods.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the laminated package using the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the process of the first half of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the process of the latter half of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the process of the first half of the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the process of the latter half of the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows the process of the first half of the manufacturing method of the semiconductor device which concerns on the 6th Embodiment of this invention. It is sectional drawing which shows the process of the second half of the manufacturing method of the semiconductor device which concerns on the 6th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Multi-layer wiring part, 3 ... Electrode pad, 4 ... Through-hole, 5 ... Insulating resin layer, 6 ... Wiring layer, 7 ... Conductor post, 8 ... Resin hole, 10 ... Copper foil, 11 ... Insulating resin, 12 ... conductor layer for wiring formation, 12a ... tubular conductor, 13 ... etching resist, 14 ... conductor plating layer, 15 ... conductive resin.

Claims (6)

A semiconductor substrate having a through-hole penetrating the front and back surfaces;
A first insulating resin layer formed on the inner surface of the through hole;
A second insulating resin layer formed on at least one of the front surface and the back surface of the semiconductor substrate;
A conductor layer formed continuously in the through hole so as to connect at least the front and back surfaces of the semiconductor substrate, and insulated from the inner surface of the through hole by the first insulating resin layer;
A semiconductor device comprising: a processed copper foil formed in a predetermined region on the second insulating resin layer and electrically connected to the conductor layer.   2. The semiconductor device according to claim 1, further comprising a conductor plating layer on the copper foil subjected to wiring processing.   3. The semiconductor device according to claim 2, wherein a copper plating layer is laminated and formed directly on the copper foil that has been subjected to wiring processing. Forming a through hole in a semiconductor substrate;
Placing and laminating a resin sheet with a single-sided copper foil on both sides of the semiconductor substrate so that the resin surface comes into contact with each other;
Forming a hole having a smaller diameter than the through hole in the through hole portion of the semiconductor substrate;
Forming a conductor layer inside the hole and electrically connecting the copper foils disposed on both sides of the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: a step of wiring the copper foil.   The method of manufacturing a semiconductor device according to claim 4, wherein the hole is a non-through hole.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the inside of the hole is filled with the conductor layer.

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