JP2006108443A - Ccd solid-state image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CCD solid-state image pickup element capable of simultaneously realizing the reduction of a read-out voltage and the improvement of blooming resistance. <P>SOLUTION: The CCD solid-state image pickup element is provided with a plurality of light-receiving sensors 3, a vertical transfer register 4, and a read-out gate 7 formed between the light-receiving sensor 3 and the vertical transfer register 4. A first impurity region 25 for setting the read-out voltage is formed to the surface of a semiconductor region of the read-out gate 7. A second impurity region 26 for improving the blooming resistance is formed at a position deeper than the first impurity region 25 apart from the light-receiving sensor 3 by a required distance in the semiconductor region of the read-out gate 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CCD solid-state imaging device, and more particularly, to both reduction of readout voltage and improvement of blooming resistance.

  An interline transfer (IT) type CCD solid-state imaging device includes a plurality of light receiving sensors serving as pixels in an imaging region, a plurality of CCD structure vertical transfer registers corresponding to each light receiving sensor array, and each light receiving sensor and vertical transfer register. And a readout gate section between them, and further includes a horizontal transfer register and the like. In this CCD solid-state imaging device, the signal charge photoelectrically converted according to the amount of received light is accumulated in the light receiving sensor, and the signal charge is read to the vertical transfer register via the read gate unit at a predetermined timing and applied to the transfer electrode. The transfer operation is performed based on the drive pulse. In the light receiving sensor, when the amount of received light increases, excess charge is discharged to the semiconductor substrate side through the overflow barrier.

  In such a CCD solid-state imaging device, when the amount of received light increases and the amount of accumulated charge in the light receiving sensor increases, a blooming phenomenon in which a part of this accumulated charge illegally leaks into the vertical transfer register beyond the read gate portion. It is known to occur. This blooming phenomenon occurs because when the amount of accumulated charge in the light receiving sensor increases, the overflow barrier is affected and fluctuates due to the potential of the light receiving sensor, and the potential difference between the readout gate section and the overflow barrier decreases. To do.

As one of the measures for preventing blooming, a solid-state imaging device has been proposed in which a blooming stopper portion having a high impurity concentration is formed in a certain depth region of a semiconductor substrate immediately below a read gate portion so as to reduce the potential. (See Patent Document 1).
JP 2002-368204 A

  By the way, the gate electrode of the read gate portion is usually formed in common with the transfer electrode of the vertical transfer register. In the region of the gate electrode as a read gate, a read voltage and blooming resistance are required in a predetermined voltage range. On the other hand, in the CCD solid-state imaging device, with the miniaturization of pixel cells, a reduction in readout voltage and a blooming resistance when an amount of electric charge accumulated in the light receiving sensor is increased are required more than ever. Until now, it has been difficult to achieve both operation margins by introducing impurities for determining the read voltage of the read gate portion, that is, the threshold voltage Vth.

  In view of the above-described points, the present invention provides a CCD solid-state imaging device capable of both reducing read voltage and improving blooming resistance.

  A CCD solid-state imaging device according to the present invention includes a plurality of light receiving sensors, a vertical transfer register, and a read gate portion formed between the light receiving sensor and the vertical transfer register, and a semiconductor region surface of the read gate portion A first impurity region for setting a read voltage is formed in the semiconductor region of the read gate portion at a position away from the light receiving sensor by a required distance and deeper than the first impurity region to improve blooming resistance. A second impurity region is formed.

The second impurity region is preferably formed to have the same width as the first impurity region and to be shifted to the vertical transfer register side, and to be formed at a position deeper than the transfer channel region of the vertical transfer register.
It is desirable that the second impurity region has a concentration equal to or lower than that of the first impurity region.

In a CCD solid-state imaging device, a position where a potential barrier (potential corresponding to a so-called buttock) is formed at the time of blooming (so-called light-receiving and accumulation) and a position where a potential (potential corresponding to a so-called buttock) is formed at the time of reading are shifted. The position of potential barrier formation during blooming is close to the vertical transfer register side.
In the CCD solid-state imaging device of the present invention, the readout voltage can be controlled by the first impurity region formed on the semiconductor substrate surface of the readout gate portion. In addition, since the second impurity region is formed at a position deeper than the first impurity region of the semiconductor region of the read gate portion and away from the light receiving sensor and close to the vertical transfer register side, reading during light receiving accumulation is performed. The potential barrier under the gate becomes shallow, and it can cope with blooming prevention.

  According to the CCD solid-state imaging device according to the present invention, by providing the first and second impurity regions, it is possible to suppress an increase in read voltage and improve blooming resistance. That is, the read voltage and the operation margin for blooming resistance can be controlled by the first and second impurity regions, respectively.

In addition, by forming the second impurity region deeper than the transfer channel region of the vertical transfer register, the vertical transfer register can be driven efficiently without affecting the potential of the vertical transfer register when driving the vertical transfer register. To.
By making the concentration of the second impurity region lower than the concentration of the first impurity region, it is possible to suppress the above-described increase in the read voltage and improve blooming resistance.

  Therefore, it is possible to achieve both a reduction in reading voltage and an improvement in blooming resistance accompanying the miniaturization of pixel cells.

  Embodiments of the present invention will be described below with reference to the drawings.

1 to 2 show an embodiment of a CCD solid-state imaging device according to the present invention. In this example, the present invention is applied to an interline transfer (IT) type CCD solid-state imaging device.
As shown in FIG. 1, in the CCD solid-state imaging device 1 according to the present embodiment, a plurality of light receiving sensors 3 serving as pixels are arranged in a matrix in the imaging region 2 and correspond to each light receiving sensor array. A CCD structure vertical transfer register 4 for transferring signal charges in the vertical direction is arranged, and a CCD structure horizontal transfer register 5 for transferring signal charges in the horizontal direction connected to each vertical transfer register 4 is arranged. An output unit 6 is connected to the final stage of the transfer register 5 for charge-voltage conversion and output. In this CCD solid-state imaging device 1, the light received in the imaging region 2 is converted into signal charges by each light receiving sensor 3 and accumulated, and the signal charges of each light receiving sensor 3 are read out to the vertical transfer register 4 via the gate part. Read and transfer vertically. The signal charge read from the vertical transfer register 4 to the horizontal transfer register 5 for each line is transferred in the horizontal direction, converted into a voltage signal by the output unit 6, and output as an imaging signal.

  FIG. 2 shows a cross-sectional structure of the unit pixel of FIG. In the present embodiment, a first semiconductor well region 12 of a second conductivity type, for example, p-type, is formed in a first conductivity type, for example, an n-type silicon semiconductor substrate 11, and this first p-type semiconductor well region is formed. The n-type charge accumulation region 13 is formed in the region where the 12 light-receiving sensors 3 are formed, and the p + accumulation layer 14 is formed on the surface thereof to form the photodiode PD serving as the light-receiving sensor 3. This light receiving sensor 3 is called a HAD sensor (Hole Accumulation Diode sensor). On the other hand, a second p-type semiconductor well region 15 is formed in a region of the first p-type semiconductor well region 12 where the vertical transfer register 4 is formed, and an n-type transfer is performed on the second p-type semiconductor well region 15. A channel region 16 is formed. A transfer electrode 18 made of, for example, polycrystalline silicon is formed on the n-type transfer channel region 16 via a gate insulating film 17. The n-type transfer channel region 16, the gate insulating film 17 and the transfer electrode 17 constitute a vertical transfer register 4.

  The transfer electrode 18 is formed to extend on the read gate portion 7 and the p + channel stop region 19. That is, the transfer electrode 18 is formed in common with the gate electrode 22 of the read gate unit 7. A light shielding layer (not shown) is formed on the entire surface of the other part including the vertical transfer register 4 except for the light receiving sensor 3 via an interlayer insulating film 21, and a color filter is formed via a planarizing film. On-chip microlenses are formed.

  The inventors have formed a potential barrier (a so-called potential ridge) formed in the p-type semiconductor well region 12 which is a semiconductor substrate under the readout gate portion 7 during blooming, and from the light receiving sensor 3 to the vertical transfer register 4. It has been found that when the signal charge is read out, the formation point of the potential formed in the p-type semiconductor well region 12 below the read gate portion 7 (so-called potential ridge) is shifted. That is, the potential barrier at the time of blooming in the read gate unit 7 is formed at a certain depth position from the substrate surface and at a position closer to the vertical transfer register 4 side from the center so as to be away from the light receiving sensor 3. On the other hand, the potential at the time of reading out charges in the readout gate section 7 is formed at a certain depth from the substrate surface and at a position closer to the light receiving sensor side than the center. The potential barrier under the readout gate during blooming corresponds to the potential barrier under the readout gate during accumulation of received light.

  In the present embodiment, in particular, based on the above verification, as shown in FIG. 2, the read voltage across the entire read gate portion, that is, the so-called read voltage on the surface of the p-type semiconductor well region 12 immediately below the gate electrode 22 of the read gate portion 7. A first p-type impurity region 25 for setting the threshold voltage Vth is formed. Further, the p-type semiconductor well region 12 below the read gate portion 7 is located at a certain depth and closer to the vertical transfer register 4 side from the center, that is, a position corresponding to or near the potential barrier formed during blooming. A second p-type impurity region 26 for reducing the potential and improving the blooming resistance is formed at the position.

  The second p-type impurity region 26 is desirably formed at a position deeper than the n-type transfer channel region 16 of the vertical transfer register 4 with the same width d as the first p-type impurity region 25. That is, the second p-type impurity region 26 is formed across the first p-type semiconductor well region 12 and the second p-type semiconductor well region 15 so as to be separated from the photodiode PD by a required distance s. Is done. The concentration of the second p-type impurity region 26 can be set to a low concentration lower than the concentration of the first p-type impurity region 25.

  As a specific condition, the horizontal position of the second p-type impurity region 26 is offset to the vertical transfer register 4 side by a distance s that is ½ or more of the read gate length. The position of the second p-type impurity region 26 in the depth direction is a position deeper than the n-type transfer channel region 16, for example, if the impurity is boron (B), a depth position of 0.2 μm or more from the semiconductor substrate surface. Good. The first and second p-type impurity regions 25 and 26 can be formed by ion implantation. At this time, the relationship between the implantation energy of the first and second p-type impurity regions 25 and 26 and the impurity concentration can be set as follows. As the implantation energy ratio, the ratio of the first p-type impurity region to the second p-type impurity region can be about 1: 5 to 1: 2. As the impurity concentration ratio, the ratio of the first p-type impurity region to the second p-type impurity region can be about 1: 1 to 3: 1.

  FIG. 3 shows a potential distribution on the AA line during operation with or without the second p-type impurity region 26. As shown in this potential distribution diagram, when the second p-type impurity region 26 is not formed, the potential barrier φb1 under the read gate portion during light reception accumulation becomes deep and blooming is likely to occur (see broken line 31). On the other hand, when the second p-type impurity region 26 of the present embodiment is formed, the potential barrier φb2 below the read gate portion at the time of receiving and accumulating becomes shallower than φb1, thereby suppressing the occurrence of blooming. Yes (see solid line 32).

  On the other hand, since the second impurity region 26 is formed closer to the vertical transfer register 4 side, the potential (so-called ridge portion) φb3 below the read gate portion is not affected by the second p-type impurity region 26 at the time of reading. The potential depth can be read at a required read voltage set by one p-type impurity region (see solid line 33).

  As described above, according to the present embodiment, by providing the second p-type impurity region 26, it is possible to suppress an increase in the read voltage and improve blooming resistance. That is, the read voltage and the operation margin for blooming resistance can be controlled by the first and second p-type impurity regions 25 and 26, respectively. That is, the controllability with one read gate can be improved. In the simulation result, for example, in order to improve the blooming resistance, when the concentration of the p-type impurity region 25 is increased with the configuration of only the first p-type impurity region 25, the blooming resistance increases by 1V, but the read voltage increases by 2V. To do. On the other hand, in the configuration having the first and second impurity regions 25 and 26, the blooming resistance is increased by 2V, but the read voltage can be suppressed to an increase of 1V or less.

Further, by forming the second p-type impurity region 26 at a position deeper than the n-type transfer channel region 16, the potential of the vertical transfer register 4 is not affected when the vertical transfer register 4 is driven, and the signal charge is reduced. Improve vertical transfer.
By setting the concentration of the second impurity region 26 to a concentration lower than the concentration of the first impurity region 25, the above-described increase in the read voltage can be suppressed and blooming resistance can be improved.

  Therefore, in the present embodiment, it is possible to achieve both the reduction of the read voltage and the improvement of the blooming resistance accompanying the miniaturization of the pixel cell.

  In the above example, the present invention is applied to an interline transfer (IT) type CCD solid-state image pickup device. However, the present invention can also be applied to a frame interline transfer (FIT) type CCD solid-state image pickup device.

It is a schematic block diagram which shows one Embodiment of the CCD solid-state image sensor which concerns on this invention. It is sectional drawing of the unit pixel part which shows one Embodiment of the CCD solid-state image sensor concerning this invention. FIG. 5 is a potential distribution diagram on the AA line including a portion under a readout gate for explaining the present invention.

Explanation of symbols

1 .... CCD solid-state imaging device, 2 .... imaging area, 3 .... light receiving sensor, 4 .... vertical transfer register, 5 .... horizontal transfer register, 6 .... output unit, 7 .... read gate unit, ... Semiconductor substrate, 12 .... first semiconductor well region, 13 .... charge storage region, 14 .... accumulation layer, PD ... photodiode, 15 .... second semiconductor well region, 16 .... transfer channel ..., Gate insulating film, 18... Transfer electrode, 21.. Interlayer insulating film, 22 .. readout gate electrode, 19... Channel stop region, 25... First impurity region, 26. Impurity region

Claims (3)

A plurality of light receiving sensors, a vertical transfer register, and a read gate portion formed between the light receiving sensor and the vertical transfer register;
A first impurity region for setting a read voltage is formed on a surface of the semiconductor region of the read gate portion;
In the semiconductor region of the read gate portion, a second impurity region for improving blooming resistance is formed at a position away from the light receiving sensor by a required distance and deeper than the first impurity region. CCD solid-state imaging device. The second impurity region has the same width as the first impurity region and is shifted to the vertical transfer register side,
The CCD solid-state image pickup device according to claim 1, wherein the second impurity region is formed at a position deeper than a transfer channel region of the vertical transfer register. The CCD solid-state imaging device according to claim 1, wherein the second impurity region has a concentration equal to or lower than the concentration of the first impurity region.

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