JP2006108283A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable semiconductor device which suppresses power consumption. <P>SOLUTION: The semiconductor possesses at least a first transistor and a second transistor with different kinds formed on a semiconductor substrate 1. The first transistor is created by performing annealing treatment after implanting LDD while the second transistor is created by performing annealing treatment after implanting a source/drain without performing annealing treatment before implanting a source/drain. The minimum distance from the boundary of an LDD domain 20 and a drain region 31 in the first transistor to the boundary of the LDD domain 20 and a channel region 41 is shorter than the minimum distance from the boundary of an LDD domain 22 and a drain region 33 in the second transistor to the boundary of the LDD domain 22 and a channel region 43. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device having an LDD (Lightly Doped Drain) structure with improved reliability. The present invention also relates to a method for manufacturing such a semiconductor device.

  In general, a semiconductor device having a MOS transistor is compatible with a transistor that operates at a low voltage in order to increase the operation speed of the transistor or suppress power consumption and the compatibility of the supply voltage from the outside to the semiconductor device. In order to maintain this, a transistor that operates at a high voltage is held in the same chip.

  FIG. 9 is a cross-sectional view showing a conventional method for manufacturing such a semiconductor device.

  First, as shown in FIG. 9A, a relatively thick insulating film 2 is formed on a semiconductor substrate 1 such as a silicon substrate.

  As shown in FIG. 9B, a resist pattern 3 patterned so as to cover the high-voltage operation region A1 is formed, and the insulating film 2 is etched using the resist pattern 3 as a mask. The insulating film 2 formed in step 1 is removed.

  Thereafter, as shown in FIG. 9C, the resist 3 is removed, and an insulating film having a relatively small thickness is formed on the entire surface, thereby forming the insulating film 4 in the low voltage operation region A2 and The film thickness of the insulating film 2 in the voltage operation area A1 is slightly increased. Thereafter, a conductive layer 5 is deposited on the entire surface.

  Then, as shown in FIGS. 9C and 9D, the conductive layer 5 is selectively etched to form the gate insulating film 61 and the gate electrode 62 in the high voltage operation region A1, and the low voltage operation region A2. A gate insulating film 71 and a gate electrode 72 are simultaneously formed. At this time, the gate insulating film 61 is formed thicker than the gate insulating film 71, and the gate electrode 62 is formed longer than the gate electrode 72.

  Next, impurity ions 64 are implanted only into the high-voltage operation region A1 while covering the low-voltage operation region A2 with a first resist (not shown), thereby forming an impurity diffusion region 63 that becomes the source of the LDD region. Impurity ions 74 are implanted only in the low-voltage operation region A2 while the first LDD implantation process is performed and the high-voltage operation region A1 is covered with a second resist (not shown). A second LDD implantation process for forming the diffusion region 73 is performed.

  As described above, the first and second LDD implantations are performed in separate steps, and the impurity diffusion region 63 is usually formed deeper than the impurity diffusion region 73.

  As shown in FIG. 9E, an insulating layer (sidewall film) to be a lower layer and an upper side wall is sequentially formed and etched back to perform upper layer side wall 65 and lower layer in the high voltage operation region A1. A side wall made of the side wall 66 is formed on the side surface of the gate electrode 62, and a side wall made of the upper layer side wall 75 and the lower layer side wall 76 is formed on the side surface of the gate electrode 72 in the low voltage operation region A2.

  Thereafter, the gate electrode 62, the upper layer side wall 65 and the lower layer side wall 66 are used as a mask in the high voltage operation region A1, and the gate electrode 72, the upper layer side wall 75 and the lower layer side wall 76 are used as a mask in the low voltage operation region A2. The source / drain region forming process is performed by implanting the impurity ions, and the source / drain region 67 and the LDD region 68 (impurity diffusion region 63 under the sidewalls 65 and 66) are formed in the high voltage operation region A1. Then, the source / drain region 77 and the LDD region 78 (impurity diffusion region 73 under the sidewalls 75 and 76) are formed in the low voltage operation region A2.

  As a result, a high-voltage MOS transistor including the gate insulating film 61, the gate electrode 62, the upper sidewall 65, the lower sidewall 66, the source / drain region 67, and the LDD region 68 is formed in the high voltage operation region A1, In the low voltage operation region A2, a low voltage MOS transistor including a gate insulating film 71, a gate electrode 72, an upper sidewall 75, a lower sidewall 76, a source / drain region 77, and an LDD region 78 is formed.

  Now, in such a semiconductor device comprising a high voltage MOS transistor and a low voltage MOS transistor, each transistor has a gate length, a gate oxide film thickness, and so on so as to satisfy an operating voltage and a required ON current / OFF current. Manufactured to optimize the impurity distribution. In the prior art, after the gate electrode is formed as described above, impurity implantation (LDD implantation) for relaxing the electric field at the boundary between the source / drain regions and the channel region, and more preferably further impurity implantation (for suppressing the short channel effect) ( (Halo implantation) is performed under the optimum conditions for each transistor. After that, sidewalls are formed on the side walls of the gate electrodes, and then N-type impurities are implanted into the source / drain regions and NMOSs are implanted with P-type impurities. After completing the impurity implantation, activation annealing is performed.

  However, in such a conventional technique, as the gate length becomes shorter in order to increase the speed of the transistor or reduce power consumption, the transistor is enhanced by accelerated enhanced diffusion (TED: Transient Enhanced Diffusion) introduced into the LDD region. Due to the decrease in the effective channel length, a short channel effect occurs and a threshold voltage is lowered.

  This is because activation annealing is performed after all the impurity implantation is performed. If high-temperature annealing necessary for activating the source / drain / gate portion is performed, impurities in the LDD region are abnormally diffused. It is because it ends. As a method of suppressing this TED, a method of performing defect recovery by performing RTA (Rapid Thermal Annealing) processing at a low temperature after LDD injection is known (see, for example, Patent Documents 1 and 2). FIG. 10 shows a conventional flow of a manufacturing process incorporating an RTA process for crystal defect recovery.

  First, an LDD injection process for the low voltage NMOS transistor is executed in step S1, an LDD injection process for the low voltage PMOS transistor is executed in step S2, and an LDD injection process is executed for the high voltage NMOS transistor in step S3. In step S4, an LDD injection process for the high voltage PMOS transistor is executed. Next, a low temperature RTA process is performed at step S5.

  Then, after forming the gate sidewalls in step S6, in step S7, source / drain region formation processing for all (high voltage and low voltage) NMOS transistors is executed, and in step S8, source / drains for all PMOS transistors. An area formation process is executed. Thereafter, activation annealing is performed in step 9 to complete all MOS transistors.

  FIG. 11 shows another conventional flow of the manufacturing process incorporating the RTA process for crystal defect recovery. Here, first, LDD injection processing for the low-voltage NMOS transistor is executed in step S11, and LDD injection processing for the low-voltage PMOS transistor is executed in step S12. Thereafter, a low temperature RTA process is executed in step S13. In step S14, an LDD injection process for the high voltage NMOS transistor is executed, and in step S15, an LDD injection process for the high voltage PMOS transistor is executed. Thereafter, a low temperature RTA process is executed in step S16.

  After forming the gate sidewalls in step S17, in step S18, source / drain region formation processing is performed on all (high voltage and low voltage) NMOS transistors, and in step S19, source / drain region formation is performed on all PMOS transistors. Execute the process. Thereafter, activation annealing is performed in step 20 to complete all MOS transistors.

JP 11-168209 A

JP 2002-141420 A

  The manufacturing flow incorporating the conventional RTA process for crystal defect recovery is configured as described above. However, in the conventional flow shown in FIGS. 10 and 11, since the annealing is performed after the LDD implantation for all the transistors, the impurity distribution of the transistor (mainly the low voltage transistor) in which the short channel effect is likely to occur is optimized. For transistors whose channel effect is not severe (mainly high-voltage operation transistors), the diffusion of impurities in the LDD region is suppressed, so the electric field strength at the boundary between the source / drain region and the channel region becomes too strong and hot carriers are generated. It becomes easy. Therefore, there is a problem that the reliability of the transistor is deteriorated.

  The present invention has been made to solve the above-described problems. For a transistor that easily causes a short channel effect, diffusion of impurities in the LDD region is suppressed, and for a transistor that does not have a severe short channel effect, hot carriers are used. An object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of the above.

  Another object of the present invention is to provide a method for manufacturing such a semiconductor device.

  The semiconductor device according to claim 1 includes two or more types of transistors having different shortest distances from the boundary between the drain region and the LDD region to the boundary between the LDD region and the channel region. With this configuration, it is possible to suppress the diffusion of impurities in the LDD region for a transistor that easily causes a short channel effect, and to suppress the generation of hot carriers for a transistor that does not have a severe short channel effect.

  A semiconductor device according to a second aspect includes at least a first transistor and a second transistor of different types formed on a semiconductor substrate, and the first transistor performs LDD implantation and before source / drain implantation. Annealing is performed, and the remaining second transistors are subjected to LDD implantation after the LDD implantation and before the source / drain implantation, and then are annealed after the source / drain implantation without performing the annealing treatment before the source / drain implantation. It is created by.

  In the semiconductor device according to claim 3, the shortest distance from the boundary between the drain region and the LDD region in the first transistor to the boundary between the LDD region and the channel region is from the boundary between the drain region and the LDD region in the second transistor. And shorter than the shortest distance to the boundary of the channel area. With this configuration, it is possible to suppress the diffusion of impurities in the LDD region for a transistor that easily causes a short channel effect, and to suppress the generation of hot carriers for a transistor that does not have a severe short channel effect.

  According to a fourth aspect of the present invention, in the semiconductor device according to the second aspect, the first transistor is composed of a low-voltage operation NMOS and a PMOS transistor, and the second transistor is composed of a high-voltage operation NMOS and a PMOS transistor. Is done.

  According to a fifth aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein the first transistor includes a low-voltage operation NMOS transistor, the second transistor includes a low-voltage operation PMOS transistor, and a high-voltage operation NMOS transistor. And a PMOS transistor.

  A semiconductor device according to a sixth aspect is the semiconductor device according to the second aspect, wherein the first transistor is a low-voltage operation PMOS transistor, the second transistor is a low-voltage operation NMOS transistor, and a high-voltage operation NMOS transistor. And a PMOS transistor.

  A semiconductor device according to a seventh aspect is the semiconductor device according to the second aspect, wherein the first transistor includes a low-voltage operation NMOS, a PMOS transistor, and a high-voltage operation NMOS transistor, and the second transistor is a high-voltage operation. PMOS transistors.

  The semiconductor device according to claim 8 is the semiconductor device according to claim 2, wherein the first transistor includes a low-voltage operation NMOS, a PMOS transistor, and a high-voltage operation PMOS transistor, and the second transistor is a high-voltage operation. NMOS transistors.

  A method for manufacturing a semiconductor device according to a ninth aspect relates to a method for manufacturing a semiconductor device having at least first and second transistors having two or more types having an LDD structure. LDD implantation for forming the LDD region is performed on the first transistor, and annealing is performed after the LDD implantation and before the source / drain implantation (first step). LDD implantation for forming an LDD region is performed on the second transistor, and sidewalls are formed on the sidewalls of the gates of the first transistor and the second transistor without annealing after the LDD implantation and before the source / drain implantation (the first transistor). 2 steps). Source / drain implantation is performed to form source / drain regions of the first transistor and the second transistor (third step). An activation annealing process is performed on the first transistor and the second transistor (fourth step).

  According to the present invention, for example, after forming a gate oxide film and a gate electrode on a substrate, LDD implantation is performed on a transistor having short channel characteristics (mainly a low-voltage operation transistor), and then crystal defects caused by the implantation are recovered. Therefore, TED is suppressed and the short channel effect can be suppressed. After that, LDD implantation is performed on transistors (mainly high-voltage transistors) that do not have a short channel effect, and here, annealing is not performed, sidewall formation, source / drain implantation is performed, and activation annealing is performed. Impurities are diffused abnormally, resulting in a broad impurity distribution at the boundary between the source / drain region and the channel region, thereby suppressing the generation of hot carriers and ensuring reliability.

  The method for manufacturing a semiconductor device according to claim 10 is the method for manufacturing a semiconductor device according to claim 9, wherein the annealing after the LDD implantation in the first step is an activation after the source / drain implantation in the fourth step. It is performed at a lower temperature than the annealing process.

  According to the present invention, a highly reliable semiconductor with reduced power consumption, including a low voltage operation transistor capable of suppressing the TED and suppressing the short channel effect and a high voltage transistor suppressing generation of hot carriers. A device is obtained.

  The purpose of obtaining a semiconductor device capable of suppressing the diffusion of impurities in the LDD region for a transistor that is likely to cause a short channel effect and suppressing the generation of hot carriers for a transistor that is not severe in the short channel effect is to provide a drain region and an LDD region. This is realized by forming two or more types of transistors having different shortest distances from the boundary between the LDD region and the channel region. Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment.

  Referring to FIG. 1, the semiconductor device includes a low voltage operation NMOS transistor, a low voltage operation PMOS transistor, a high voltage operation NMOS transistor, and a high voltage operation PMOS transistor formed on a silicon substrate 1. In the drawing, for convenience, these transistors are collected and described in one place. The low voltage operation NMOS transistor includes a gate insulating film 4 and a gate electrode 5. A lower layer sidewall 7 and an upper layer sidewall 12 are formed on the side wall of the gate electrode 5. LDD regions 20 and source / drain regions 31 are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 5. The low-voltage operation PMOS transistor includes a gate insulating film 4 and a gate electrode 5. A lower layer sidewall 7 and an upper layer sidewall 12 are formed on the side wall of the gate electrode 5. LDD regions 21 and source / drain regions 32 are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 5.

  The high voltage operation NMOS transistor includes a gate insulating film 2 and a gate electrode 5. A lower layer sidewall 7 and an upper layer sidewall 12 are formed on the side wall of the gate electrode 5. LDD regions 22 and source / drain regions 33 are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 5. The high voltage operation PMOS transistor includes a gate insulating film 2 and a gate electrode 5. A lower layer sidewall 7 and an upper layer sidewall 12 are formed on the side wall of the gate electrode 5. LDD regions 23 and source / drain regions 34 are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 5.

  The film thickness of the gate insulating film 2 of the high voltage operation transistor is larger than the film thickness of the gate insulating film 4 of the low voltage operation transistor. The gate length of the high voltage operation transistor is longer than the gate length of the low voltage operation transistor.

  In the low voltage operation NMOS transistor, the shortest distance from the boundary between the drain region 31 and the LDD region 20 to the boundary between the LDD region 20 and the channel region 41 is from the boundary between the drain region 33 and the LDD region 22 in the high voltage operation NMOS transistor. The distance between the LDD region 22 and the channel region 43 is shorter than the shortest distance. The shortest distance from the boundary between the drain region 32 and the LDD region 21 in the low voltage operation PMOS transistor to the boundary between the LDD region 21 and the channel region 42 is the LDD from the boundary between the drain region 34 and the LDD region 23 in the high voltage operation PMOS transistor. The distance is shorter than the shortest distance to the boundary between the region 23 and the channel region 44.

  Next, the present invention will be described in more detail while explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a schematic flow.

  As shown in FIG. 2, first, in step S21, LDD injection processing for the low voltage NMOS transistor is executed, and in step S22, LDD injection processing for the low voltage PMOS transistor is executed. Thereafter, a low temperature RTA process is executed in step S23. In step S24, an LDD injection process for the high voltage NMOS transistor is executed, and in step S25, an LDD injection process for the high voltage PMOS transistor is executed.

  Then, the gate sidewall is formed in step S26 without performing the low temperature RTA process. Thereafter, in step S27, source / drain region formation processing for all (high voltage and low voltage) NMOS transistors is executed, and in step S28, source / drain region formation processing is executed for all PMOS transistors. Thereafter, activation annealing is performed in step 29 to complete all MOS transistors.

  3, 4 and 5 are cross-sectional views showing the steps of the manufacturing method.

  First, as shown in FIG. 3A, an oxide film 2 (silicon oxide film) to be a gate oxide film of a high voltage operation transistor is formed on a silicon substrate 1. Next, as shown in FIG. 3B, a resist pattern 3 covering the high voltage operation transistor region is formed by photolithography, and the oxide film 2 in the region other than the high voltage operation transistor region is etched using the resist pattern 3. By removing, the oxide film 2 is left only in the high voltage operation transistor region.

  Next, as shown in FIG. 3C, a thin gate oxide film 4 for a low voltage operation transistor is formed by oxidation. Next, as shown in FIG. 3D, after depositing a gate electrode material (for example, a polysilicon film) and forming a resist pattern 6 for forming the gate electrode by photolithography, the gate electrode material is dried. The gate electrode 5 is formed by etching using an etching method. At this time, the gate length of the gate electrode 5 of the low voltage operation transistor is made shorter than that of the high voltage operation transistor. In addition, when the gate electrode 5 is etched, the silicon substrate 1 is etched so that some oxide film remains in order to prevent etching damage.

  The next LDD implantation and Halo implantation may be carried out through this oxide film, or as shown in FIG. 4 (E), by implantation through the silicon oxide film 7 newly formed by thermal oxidation or deposition. Also good. The silicon oxide film 7 is a source of the lower side wall and is formed on the silicon substrate 1 so as to cover each gate electrode 5. The LDD implantation is performed for each transistor as follows.

First, as shown in FIG. 4E, a resist pattern 8 is formed by photolithography so that only the NMOS region of the low-voltage operation transistor is opened, and an N-type impurity (for example, arsenic) is implanted at an energy of 1-10. LDD injection is performed at [KeV], an injection amount of 0.1 to 5 × 10 ¹⁵ [atoms / cm ² ], and an injection angle of 0 to 50 °. As a result, an impurity diffusion region 20 that is the source of the LDD region is formed. Next, the resist pattern 8 is removed.

Thereafter, as shown in FIG. 4F, a resist pattern 9 is formed by photolithography so that only the PMOS region of the low-voltage operation transistor is opened, and a P-type impurity (for example, BF ₂ ) is implanted at an energy of 1 to 1. LDD injection is performed at 10 [KeV], an injection amount of 0.1 to 5 × 10 ¹⁵ [atoms / cm ² ], and an injection angle of 0 to 50 °. As a result, an impurity diffusion region 21 that is the source of the LDD region is formed. The resist pattern 9 is removed. The order of forming the NMOS and PMOS may be switched.

  Next, as shown in FIG. 4G, annealing for recovering crystal defects and suppressing TED is performed at a lower temperature (800 to 950 ° C., 1 to 6) than the source / drain activation annealing described later by RTA. 60 seconds). As a result, it is possible to suppress the impurity diffusion regions 20 and 21 that are the source of the LDD region from diffusing in the channel direction and to reduce the effective gate length, and to suppress the threshold voltage drop due to the short channel effect as apparent from FIG. it can. FIG. 6 is a diagram showing the relationship between the threshold voltage and gate length of a low-voltage operation NMOS transistor with and without low-temperature RTA after LDD implantation.

Next, as shown in FIG. 4H, a resist pattern 10 is formed so that only the NMOS region of the high-voltage operation transistor is opened, and an N-type impurity (for example, phosphorus) is implanted at an energy of 10 to 100 [KeV]. LDD injection is performed at an injection amount of 0.1 to 10 × 10 ¹³ [atoms / cm ² ] and an injection angle of 0 to 50 °. As a result, an impurity diffusion region 22 that becomes the source of the LDD region is formed. Next, the resist pattern 10 is removed.

  For high-voltage operation transistors, the gate length is not as short as low-voltage operation transistors, and it is not necessary to suppress the short channel effect due to TED. Rather, in order to ensure reliability, the impurity distribution at the boundary between the drain and channel is broadened to increase the electric field strength. Since it is more important to weaken this, annealing treatment for crystal defect recovery is not performed here, and crystal defect recovery is performed during source / drain activation annealing described later.

As shown in FIG. 5I, a resist pattern 11 is formed by photolithography so that only the PMOS region of the high-voltage operation transistor is opened, and a P-type impurity (for example, BF ₂ ) is implanted at an energy of 10 to 100 [ KeV], an injection amount of 0.1 to 10 × 10 ¹³ [atoms / cm ² ], and an LDD injection at an injection angle of 0 to 50 °. As a result, an impurity diffusion region 23 that forms the LDD region is formed. The resist pattern 11 is removed.

  For high-voltage operation transistors, the gate length is not as short as low-voltage operation transistors, and there is no need to suppress the short channel effect due to TED. Rather, in order to ensure reliability, the impurity distribution at the boundary between the drain and channel is broadened to increase the electric field strength. Since it is more important to weaken, annealing treatment for crystal defect recovery is not performed here, and crystal defect recovery is performed during source / drain activation annealing described later.

  Next, as shown in FIG. 5J, for example, an SiN film is deposited to form the upper layer gate sidewall, and the upper layer gate sidewall 12 is formed by etching back the entire surface of the wafer by dry etching. At this time, the deposition temperature of the SiN film is preferably set to 700 ° C. or less so that impurities implanted by LDD in the low voltage operation transistor region diffuse and the short channel effect is not deteriorated. At the time of the etch back, the upper surface of the gate electrode 5 and the silicon oxide film 7 on the surface of the silicon substrate 1 where the source / drain regions are to be formed are removed.

Next, a resist pattern 13 is formed by photolithography so that only the NMOS region is opened, and an N-type impurity (for example, arsenic) is implanted into the source / drain regions 31 and 33 and the gate electrode 5 with an energy of 10 to 100 [ KeV] and an injection amount of 0.1 to 10 × 10 ¹⁵ [atoms / cm ² ]. Next, the resist pattern 13 is removed.

As shown in FIG. 5K, a resist pattern 14 is formed by photolithography so that only the PMOS region is opened, and P-type impurities (for example, boron) are added to the source / drain regions 32 and 34 and the gate electrode 5. The resist pattern 14 is removed by implanting with an implantation energy of 1 to 20 [KeV] and an implantation amount of 0.1 to 10 × 10 ¹⁵ [atoms / cm ² ].

  Thereafter, as shown in FIG. 5L, activation annealing is performed at 900 to 1100 ° C. for 1 to 60 seconds to activate impurities in the source / drain regions 31, 32, 33, and 34 and the gate electrode 5. At this time, TED occurs because the crystal defects in the LDD regions 22 and 23 of the high-voltage operation transistor have not been recovered by the low-temperature RTA treatment after the implantation, the impurity distribution in the LDD region becomes broad, and the gap between the drain and the channel Electric field strength is reduced, generation of hot carriers is suppressed, and reliability is improved.

  Although hot carriers generated by the electric field due to the impurity concentration gradient in the LDD region when the ON current flows are measured as the substrate current, as shown in the relationship diagram between the substrate current and the ON current of the high voltage operation NMOS transistor of FIG. It can be seen that without the low temperature RTA after the LDD implantation, the substrate current is suppressed, so that the impurity concentration gradient becomes gentle.

  Further, as shown in FIG. 8, as a result of suppressing the generation of hot carriers, the NMOS transistor operating at a high voltage does not perform the low temperature RTA after the LDD injection. The stress application time becomes longer, and the transistor reliability is improved.

  In the first embodiment, the method for manufacturing the semiconductor device according to the fourth aspect is described. However, the same applies to the semiconductor device according to the fifth to eighth aspects by changing the process order of the LDD implantation and the low temperature RTA process. To be manufactured.

  That is, when the semiconductor device according to claim 5 is manufactured, LDD injection is performed on the low-voltage operation NMOS transistor, followed by low-temperature RTA processing, and then the low-voltage operation PMOS transistor, the high-voltage operation NMOS, LDD injection is performed on the PMOS transistor.

  When the semiconductor device according to claim 6 is manufactured, a low-temperature RTA process is performed after LDD injection is performed on the low-voltage operation PMOS transistor, and then the low-voltage operation NMOS transistor, the high-voltage operation NMOS and the PMOS transistor are LDD. Make an injection.

  When the semiconductor device according to claim 7 is fabricated, the low-temperature operation NMOS, the PMOS transistor, and the high-voltage operation NMOS transistor are subjected to LDD injection, followed by a low-temperature RTA process, and then the high-voltage operation PMOS transistor is subjected to LDD. Make an injection.

  When the semiconductor device according to claim 8 is manufactured, a low-temperature RTA process is performed after LDD injection is performed on the low-voltage operation NMOS, PMOS transistor and high-voltage operation PMOS transistor, and then the high-voltage operation NMOS transistor is LDD. Make an injection.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, a highly reliable semiconductor device with reduced power consumption can be obtained.

Sectional drawing of the semiconductor device concerning Example 1. FIG. Schematic flow of a semiconductor device manufacturing method according to the first embodiment Sectional drawing of the semiconductor device in the 1st, 2nd, 3rd, and 4th process of the manufacturing method of the semiconductor device concerning Example 1 Sectional drawing of the semiconductor device in the 5th, 6th, 7th, and 8th process of the manufacturing method of the semiconductor device concerning Example 1 Sectional drawing of the semiconductor device in the 9th, 10th, 11th, and 12th process of the manufacturing method of the semiconductor device concerning Example 1 The figure which shows the relation between threshold voltage and gate length of low voltage operation NMOS The figure which shows the relation between the substrate current and the ON current of the high voltage operation NMOS Diagram showing the relationship between threshold voltage change and stress application time Sectional drawing which shows the process of the manufacturing method of the conventional semiconductor device The figure which shows the flow of the manufacturing method of the conventional semiconductor device The figure which shows the flow of the manufacturing method of the other conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 4 Gate insulating film 5 Gate electrode 7 Lower layer side wall 12 Upper layer side wall 20, 21, 22, 23 Impurity diffusion region 31, 32, 33, 34 Source / drain region 41, 42, 43, 44 Channel region

Claims (10)

  A semiconductor device having two or more types of transistors having different shortest distances from the boundary between the drain region and the LDD region to the boundary between the LDD region and the channel region.   At least a first transistor and a second transistor of different types formed on a semiconductor substrate. The first transistor is annealed before the source / drain implantation after the LDD implantation, and the remaining second transistors. A transistor is a semiconductor device manufactured by performing LDD implantation and then performing annealing after source / drain implantation without performing annealing before source / drain implantation.   The shortest distance from the boundary between the drain region and the LDD region in the first transistor to the boundary between the LDD region and the channel region is the shortest distance from the boundary between the drain region and the LDD region in the second transistor to the boundary between the LDD region and the channel region. The semiconductor device according to claim 2, wherein the semiconductor device is shorter.   3. The semiconductor device according to claim 2, wherein the first transistor is composed of an NMOS and a PMOS transistor that operate at a low voltage, and the second transistor is composed of an NMOS and a PMOS transistor that operate at a high voltage.   The first transistor is composed of a low-voltage operation NMOS transistor, and the second transistor is composed of a low-voltage operation PMOS transistor and a high-voltage operation NMOS and PMOS transistor. Semiconductor device.   3. The first transistor according to claim 2, wherein the first transistor comprises a low-voltage operation PMOS transistor, and the second transistor comprises a low-voltage operation NMOS transistor, a high-voltage operation NMOS transistor and a PMOS transistor. Semiconductor device.   The said 1st transistor is comprised from the NMOS transistor of a low voltage operation | movement, a PMOS transistor, and the NMOS transistor of a high voltage operation | movement, The said 2nd transistor is comprised from the PMOS transistor of a high voltage operation | movement, The Claim 2 characterized by the above-mentioned. Semiconductor device.   The said 1st transistor is comprised from the NMOS transistor of a low voltage operation | movement, a PMOS transistor, and the PMOS transistor of a high voltage operation | movement, The said 2nd transistor is comprised from the NMOS transistor of a high voltage operation | movement, The Claim 2 characterized by the above-mentioned. Semiconductor device. A method of manufacturing a semiconductor device having at least first and second transistors having two or more types having an LDD structure,
A first step of performing LDD implantation for forming an LDD region for the first transistor and annealing after the LDD implantation and before source / drain implantation;
A second sidewall is formed on the sidewalls of the gates of the first transistor and the second transistor without LDD implantation for forming an LDD region for the second transistor and without annealing after the LDD implantation and before the source / drain implantation. Process,
A third step of implanting source / drain to form source / drain regions of the first transistor and the second transistor;
And a fourth step of activating annealing the first transistor and the second transistor. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the annealing process after the LDD implantation in the first step is performed at a lower temperature than the activation annealing process after the source / drain implantation in the fourth step.

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