JP2006107470A5 - - Google Patents
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- JP2006107470A5 JP2006107470A5 JP2005258759A JP2005258759A JP2006107470A5 JP 2006107470 A5 JP2006107470 A5 JP 2006107470A5 JP 2005258759 A JP2005258759 A JP 2005258759A JP 2005258759 A JP2005258759 A JP 2005258759A JP 2006107470 A5 JP2006107470 A5 JP 2006107470A5
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- electrically connected
- fuse
- circuit
- transistor
- signal processing
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Claims (14)
前記アンテナ回路は、前記電圧検出回路に電気的に接続し、かつ、ヒューズの第一端と電気的に接続し、
前記電圧検出回路は前記電流増幅回路に電気的に接続し、
前記電流増幅回路は前記ヒューズの前記第二端に電気的に接続し、
前記信号処理回路は前記ヒューズの前記第二端に電気的に接続されることを特徴とする半導体装置。 An antenna circuit, a voltage detection circuit, a current amplification circuit, a signal processing circuit, and a fuse having at least a first end and a second end;
The antenna circuit is electrically connected to the voltage detection circuit and electrically connected to a first end of the fuse;
The voltage detection circuit is electrically connected to the current amplification circuit;
The current amplifier circuit is electrically connected to the second end of the fuse;
The semiconductor device, wherein the signal processing circuit is electrically connected to the second end of the fuse.
前記電圧検出回路は前記アンテナ回路が受信した信号が入力され、The voltage detection circuit receives a signal received by the antenna circuit,
前記入力された信号により前記電圧検出回路に前記電圧検出回路のスレッショルド電圧以上の電圧が印加される場合、前記電流増幅回路に検出信号が入力され、When a voltage equal to or higher than a threshold voltage of the voltage detection circuit is applied to the voltage detection circuit by the input signal, a detection signal is input to the current amplification circuit,
前記入力された検出信号により前記電流増幅回路は前記ヒューズに電流を流し、前記ヒューズが自己発熱によって溶断されることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein the current amplification circuit causes a current to flow through the fuse by the input detection signal, and the fuse is blown by self-heating.
前記アンテナ回路の一端は、前記ダイオードの一端と電気的に接続し、かつ、前記ヒューズの第一端と電気的に接続し、One end of the antenna circuit is electrically connected to one end of the diode, and electrically connected to the first end of the fuse,
前記ダイオードの他端は、前記第一のトランジスタのソースまたはドレインの一方と電気的に接続し、かつ、前記第一のトランジスタのゲートと電気的に接続し、The other end of the diode is electrically connected to one of a source or a drain of the first transistor and electrically connected to a gate of the first transistor;
前記第一のトランジスタのゲートは、前記第二のトランジスタのゲートと電気的に接続し、The gate of the first transistor is electrically connected to the gate of the second transistor;
前記ヒューズの第二端は、前記第二のトランジスタのソースまたはドレインの一方と電気的に接続し、かつ、前記信号処理回路の一端と電気的に接続し、A second end of the fuse is electrically connected to one of a source or a drain of the second transistor, and is electrically connected to one end of the signal processing circuit;
前記アンテナ回路の他端は、前記第一のトランジスタのソースまたはドレインの他方と電気的に接続し、かつ、前記第二のトランジスタのソースまたはドレインの他方と電気的に接続し、かつ、前記信号処理回路の他端と電気的に接続されることを特徴とする半導体装置。The other end of the antenna circuit is electrically connected to the other of the source and the drain of the first transistor, and is electrically connected to the other of the source and the drain of the second transistor, and the signal A semiconductor device which is electrically connected to the other end of the processing circuit.
前記第二のトランジスタのゲート幅は、前記第一のトランジスタのゲート幅のn倍であることを特徴とする半導体装置。The gate width of the second transistor is n times the gate width of the first transistor.
前記アンテナ回路の一端は、前記第一の抵抗の一端と電気的に接続し、かつ、前記ヒューズの第一端と電気的に接続し、One end of the antenna circuit is electrically connected to one end of the first resistor, and electrically connected to the first end of the fuse;
前記第一の抵抗の他端は、第二の抵抗の一端と電気的に接続し、かつ、前記コンパレータの第一の入力端子と電気的に接続し、The other end of the first resistor is electrically connected to one end of a second resistor, and electrically connected to the first input terminal of the comparator;
前記コンパレータの第二の入力端子は、電圧源の一端と電気的に接続し、A second input terminal of the comparator is electrically connected to one end of a voltage source;
前記コンパレータの出力端子は、前記トランジスタのゲートと電気的に接続し、The output terminal of the comparator is electrically connected to the gate of the transistor,
前記ヒューズの第二端は、前記前記トランジスタのソースまたはドレインの一方と電気的に接続し、かつ、前記信号処理回路の一端と電気的に接続し、A second end of the fuse is electrically connected to one of a source and a drain of the transistor, and is electrically connected to one end of the signal processing circuit;
前記アンテナ回路の他端は、前記第二の抵抗の他端と電気的に接続し、かつ、前記電圧源の他端と電気的に接続し、かつ、前記トランジスタのソースまたはドレインの他方と電気的に接続し、かつ、前記信号処理回路の他端と電気的に接続されることを特徴とする半導体装置。The other end of the antenna circuit is electrically connected to the other end of the second resistor, is electrically connected to the other end of the voltage source, and is electrically connected to the other of the source or drain of the transistor. And a semiconductor device which is electrically connected to the other end of the signal processing circuit.
前記コンパレータの第一の入力端子に印加される電位が前記電圧源の電位より大きい場合、前記トランジスタが動作することを特徴とする半導体装置。The semiconductor device is characterized in that the transistor operates when a potential applied to a first input terminal of the comparator is higher than a potential of the voltage source.
前記ヒューズは、過大な電流を流して、溶断することで、前記信号処理回路への電源の供給を停止することを特徴とする半導体装置。 Any Oite to one of claims 1 to 6,
The fuse is drawing too much current, by fusing, and wherein a stopping the supply of power to the signal processing circuit.
前記ヒューズは金属配線でなることを特徴とする半導体装置。 In any one of Claims 1 thru | or 7,
The fuse is a semiconductor device characterized by comprising a metal wire.
前記ヒューズは半導体薄膜でなることを特徴とする半導体装置。 In any one of Claims 1 thru | or 7,
The fuse is a semiconductor device characterized by comprising a semiconductor thin film.
前記アンテナ回路の一端は、前記信号処理回路の一端と電気的に接続し、かつ、前記アンチヒューズの第一端と電気的に接続し、
前記アンテナ回路の他端は、前記信号処理回路の他端と電気的に接続し、かつ、前記アンチヒューズの第二端と電気的に接続されていることを特徴とする半導体装置。 Has a antenna circuit, a signal processing circuit, and a anti-fuse having at least a first end and a second end,
One end of the antenna circuit is electrically connected to one end of the signal processing circuit , and electrically connected to the first end of the antifuse,
The other end of the antenna circuit is electrically connected to the other end of the signal processing circuit and electrically connected to the second end of the antifuse .
前記アンチヒューズは、大電圧を印加して前記アンチヒューズを破壊して、短絡させることで、前記信号処理回路への電源の供給を停止することを特徴とする半導体装置。The semiconductor device is characterized in that supply of power to the signal processing circuit is stopped by applying a large voltage to destroy and short circuit the antifuse.
前記アンチヒューズは、一対の導電層と、前記一対の導電層に狭持された絶縁膜からなることを特徴とする半導体装置。 In claim 10 or claim 11 ,
The anti-fuse is a semiconductor device characterized by a pair of the conductive layer, the pair of conductive layers sandwiched by insulating films.
前記アンチヒューズは、ダイオードからなることを特徴とする半導体装置。 In claim 10 or claim 11,
The anti-fuse to a semiconductor device characterized by comprising the diode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005258759A JP4836523B2 (en) | 2004-09-10 | 2005-09-07 | Semiconductor devices, IC cards, IC tags, RFID, transponders, banknotes, securities, passports, electronic devices, bags, and clothing |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004264718 | 2004-09-10 | ||
JP2004264718 | 2004-09-10 | ||
JP2005258759A JP4836523B2 (en) | 2004-09-10 | 2005-09-07 | Semiconductor devices, IC cards, IC tags, RFID, transponders, banknotes, securities, passports, electronic devices, bags, and clothing |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006107470A JP2006107470A (en) | 2006-04-20 |
JP2006107470A5 true JP2006107470A5 (en) | 2008-10-23 |
JP4836523B2 JP4836523B2 (en) | 2011-12-14 |
Family
ID=36377045
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005258759A Expired - Fee Related JP4836523B2 (en) | 2004-09-10 | 2005-09-07 | Semiconductor devices, IC cards, IC tags, RFID, transponders, banknotes, securities, passports, electronic devices, bags, and clothing |
Country Status (1)
Country | Link |
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JP (1) | JP4836523B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102646681B (en) * | 2006-10-04 | 2015-08-05 | 株式会社半导体能源研究所 | Semiconductor device |
JP5263757B2 (en) | 2007-02-02 | 2013-08-14 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JP5525694B2 (en) | 2007-03-14 | 2014-06-18 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07160960A (en) * | 1993-12-06 | 1995-06-23 | Toyo Alum Kk | Resonance label |
JPH10240889A (en) * | 1997-02-27 | 1998-09-11 | Kokusai Electric Co Ltd | Noncontact ic card |
US6025780A (en) * | 1997-07-25 | 2000-02-15 | Checkpoint Systems, Inc. | RFID tags which are virtually activated and/or deactivated and apparatus and methods of using same in an electronic security system |
UA59498C2 (en) * | 1999-12-07 | 2003-09-15 | Інфінеон Текнолоджіс Аг | Goods label, a method for producing the label, and a method for contactless identification of goods |
WO2004053721A1 (en) * | 2002-12-10 | 2004-06-24 | Shalom Wertsberger | Deactivation of radio frequency identification tags |
-
2005
- 2005-09-07 JP JP2005258759A patent/JP4836523B2/en not_active Expired - Fee Related
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