JP2006107470A - Semiconductor device, ic card, ic tag, rfid, transponder, paper money, securities or the like, passport, electronic equipment, bag and clothing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device used as an ID chip, which subsequent operation is terminated when its role is finished or expires. <P>SOLUTION: According to the invention, an antenna circuit, a voltage detecting circuit, a current amplifier circuit, a signal processing circuit, and a fuse are provided over an insulating substrate. When large power is applied to the antenna circuit, a voltage is detected by voltage detecting circuit and a current corresponding to the current is amplified by the current amplifier circuit, thereby the fuse is melted down. Also, when an anti-fuse is used, the anti-fuse can short by applying an excessive voltage. In this manner, the semiconductor device has a function for disabling by stopping operation of the signal processing circuit when the role of the device is finished or expires. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device used as an IC chip (hereinafter also referred to as “ID chip”) capable of storing necessary information in a memory circuit or reading information by non-contact means such as wireless communication. In particular, the present invention relates to a semiconductor device used as an ID chip formed on an insulating substrate such as glass or plastic.

  Due to the development of computer technology and the improvement of image recognition technology, information recognition using a medium such as a barcode has become widespread and used for product data recognition and the like. In the future, it is expected that more information will be recognized. On the other hand, there is a drawback that the barcode reader needs to be in contact with the barcode and the amount of information recorded on the barcode cannot be increased so much in the case of reading information by barcode. An increase in storage capacity is desired.

  Due to such demands, ID chips using ICs have been developed in recent years. The ID chip stores necessary information in a memory circuit in the IC chip, and reads internal information using non-contact means, generally wireless means. The practical use of such an ID chip is expected to simplify product distribution, reduce costs, and ensure high security.

  An outline of an individual authentication system using an ID chip will be described with reference to FIG. FIG. 4 is a diagram showing an outline of a solid authentication system for the purpose of obtaining the individual information of the bag without contact. An ID chip 401 that stores specific solid information is attached to or embedded in a bag 404. An electromagnetic wave is transmitted from the antenna unit 402 of the interrogator (also referred to as a read dryer) 403 to the ID chip. When receiving the electromagnetic wave, the ID chip 401 sends back individual information held by the ID chip to the antenna unit 402. The antenna unit 402 sends the returned individual information to the interrogator, and the interrogator determines the individual information. In this way, the interrogator can obtain information on the bag 404. Further, by using this system, it is possible to carry out logistics management, aggregation, removal of counterfeit products, and the like.

  An example of such ID chip technology is shown in FIG. The semiconductor device 200 used for the ID chip includes an antenna circuit 201, a rectifier circuit 202, a stabilized power supply circuit 203, an amplifier 208, a demodulation circuit 213, a logic circuit 209, a memory control circuit 212, a memory circuit 211, a logic circuit 207, an amplifier 206, and a modulation. The circuit 205 is configured. The antenna circuit 201 includes an antenna coil 301 and a tuning capacitor 302 (FIG. 3A). The rectifier circuit 202 includes diodes 303 and 304 and a smoothing capacitor 305 (FIG. 3B). A part other than the antenna circuit 201 is referred to as a signal processing circuit 214.

  The operation of such an ID chip will be described below. The AC signal received by the antenna circuit 201 is half-wave rectified by the diodes 303 and 304 and smoothed by the smoothing capacitor 305. Since the smoothed voltage includes a large number of ripples, it is stabilized by the stabilized power supply circuit 203, and the stabilized voltage is converted into the demodulating circuit 213, the amplifier 206, the logic circuit 207, the amplifier 208, and the logic circuit 209. , And supplied to the memory circuit 211 and the memory control circuit 212. On the other hand, a signal received by the antenna circuit 201 is input to the logic circuit 209 through the amplifier 208 as a clock signal. The signal input from the antenna is demodulated by the demodulation circuit 213 and input to the logic circuit 209 as data.

  In the logic circuit 209, the input data is decoded. Since the interrogator encodes the data with a modified mirror code, an NRZ-L code, or the like and transmits it, the logic circuit 209 decodes it. The decoded data is sent to the memory control circuit 212, and the stored data stored in the memory circuit 211 is read out accordingly. The memory circuit 211 needs to be a nonvolatile memory circuit that can be retained even when the power is turned off, and a mask ROM or the like is used. The stored contents are, for example, 16-byte data (see FIG. 12), and there are two types of 4 bytes of family code indicating the ID chip series, 4 bytes of application code, and 4 bytes of user code set by the user. Yes.

Signals to be transmitted and received include 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz, and the like, and ISO standards are set for each. Also, modulation / demodulation schemes for transmission and reception are standardized. An example of such an ID chip is, for example, Patent Document 1.
JP 2001-250393 A

The conventional ID chip semiconductor device described above has the following problems. When an ID chip is attached to a product, etc., even after the consumer purchases the product, the ID chip responds to the interrogator and the third party knows what the consumer has purchased. There was a problem that privacy could not be protected.
Further, there has been a problem that data such as a passport using an ID chip is rewritten and misused even after it expires due to expiration. Therefore, there is a need for an ID chip that can stop its operation when its role ends and expires.

  In view of the above, an object of the present invention is to provide a semiconductor device used as an ID chip capable of stopping the operation of a semiconductor device used for an ID chip when it expires.

  The gist of the present invention is that a fuse or an antifuse is provided in a semiconductor device used for an ID chip or the like, and the function of the ID chip is limited after the fuse is blown or the antifuse is short-circuited. The fuse can be blown by specific signal processing, and the antifuse can be short-circuited by specific signal processing so that information cannot be read or written.

One aspect of the present invention includes an antenna circuit, a voltage detection circuit, a current amplification circuit, a signal processing circuit, and a fuse having at least a first end and a second end. The antenna circuit is electrically connected to the voltage detection circuit and is electrically connected to the first end of the fuse. Further, the voltage detection circuit is electrically connected to the current amplification circuit, the current amplification circuit is electrically connected to the second end of the fuse, and the signal processing circuit is electrically connected to the second end of the fuse. That is, the signal processing circuit is electrically connected to the antenna circuit through the first end and the second end of the fuse.

In other words, one of the present invention includes an antenna circuit, a voltage detection circuit, a current amplification circuit, a signal processing circuit, and a fuse having at least a first end and a second end. Electrically connected to the detection circuit, and electrically connected to the signal processing circuit through at least the fuse and the first and second ends of the fuse, and the voltage detection circuit is electrically connected to the current amplification circuit The current amplification circuit is electrically connected to the second end of the fuse, and the signal processing circuit is electrically connected to the second end of the fuse.

  In the above, the signal processing circuit can include a rectifier circuit and a modulation circuit.

  In the above, the voltage detection circuit may include a diode.

  In the above, the voltage detection circuit may include a comparator.

  In the above, the current amplifier circuit may include a current mirror circuit.

  In the above, the fuse element constituting the fuse can be blown by passing an excessive current.

  In the above, the fuse element may be a metal wiring. Alternatively, the fuse element may be a semiconductor thin film.

  One embodiment of the present invention includes an antenna circuit, a signal processing circuit, and an antifuse on a substrate, and an output of the antenna circuit is electrically connected to the signal processing circuit and the antifuse.

  In the above, the signal processing circuit can include a rectifier circuit and a modulation circuit.

  In the above, the antifuse element constituting the antifuse can be applied with an excessive voltage to short-circuit the insulating film. Note that the antifuse element may include a pair of conductive layers and the insulating film sandwiched between the pair of conductive layers.

  In the above, the antifuse element constituting the antifuse is a diode, and an excessive voltage can be applied to short-circuit the diode junction. The antifuse element may be the diode, and the diode may include the junction.

  In the above, the signal processing circuit can be configured on a glass substrate.

  In the above, the signal processing circuit can be configured on a plastic substrate.

  In the above, the signal processing circuit can be formed on a film-like insulator.

  In the above, the antenna circuit can be provided above the signal processing circuit or a part of the signal processing circuit.

In the above, a radio signal may be used as a signal input to the antenna circuit.

The semiconductor device having the above structure may be used for an IC card, IC tag, RFID, transponder, banknote, securities, passport, electronic device, bag, or clothing having the semiconductor device.

The fuse here refers to a fuse element that melts when an excessive current flows and interrupts the circuit, and the antifuse is an antifuse that is turned on by applying an excessive voltage, contrary to the fuse. Refers to an element.

  By providing a fuse or an antifuse as in the present invention, an ID chip that stops its role after expiration can be realized. In this way, the data of the ID chip cannot be called after the expiration, and it becomes possible to protect the consumer's privacy. In addition, misuse of expired certificates and the like can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  A first embodiment of the present invention is shown in FIG. A semiconductor device 100 used for an ID chip includes an antenna circuit 101, a voltage detection circuit 102, a current amplification circuit 103, a signal processing circuit 104, and a fuse 105. The antenna circuit 101 can be similar to that shown in FIG. The signal processing circuit 104 is the same as the conventional example shown in FIG. In this embodiment mode, the antenna circuit is formed over the semiconductor device 100; however, the present invention is not limited to this, and the antenna circuit may be connected to the outside of the semiconductor device.

  The operation of such an ID chip will be described below. When a normal signal is received from the interrogator, a signal is sent from the antenna circuit 101 to the signal processing circuit 104 and demodulated. However, in FIG. 1, a voltage detection circuit 102, a current amplification circuit 103, and a fuse 105 are added between the antenna circuit 101 and the signal processing circuit 104. A signal received by the antenna circuit 101 is input to the voltage detection circuit 102. Here, when a voltage equal to or higher than a certain threshold voltage is applied, the voltage detection circuit 102 outputs a detection signal and inputs the detection signal to the current amplification circuit 103. When a detection signal is input to the current amplifier circuit 103, a large current flows from the power supply terminal. The fuse 105 is disposed on the power supply path. When a large current flows, the fuse 105 is melted by self-heating.

  When the fuse 105 is melted, no power is supplied to the signal processing circuit 104. Therefore, the semiconductor device 100 loses its function as an ID chip after the melting. As described above, the semiconductor device of the present embodiment is obtained by applying a large signal to the antenna so that the fuse 105 is blown after the end of the role of the ID chip such as when the purchase of the consumer is completed or after the expiration of the certificate. So you can protect the privacy of consumers and prevent misuse after certificate revocation.

  FIG. 8 shows the second embodiment. In this embodiment, an antifuse capacitor 802 is electrically connected between the antenna circuit 801 and the signal processing circuit 803. When a large voltage is applied to the antenna circuit 801, a large voltage is also applied between the antifuse capacitors 802. When the voltage exceeds the withstand voltage of the antifuse capacitor 802, the antifuse capacitor 802 is short-circuited.

  When the antifuse capacitor 802 is short-circuited, power is not supplied to the signal processing circuit 803, and thus the semiconductor device 800 loses its function as an ID chip after the short-circuit. As described above, by adding a large signal to the antenna so that the antifuse capacitor 802 is short-circuited after the end of the role of the ID chip such as when the purchase of the consumer is completed or after the expiration of the certificate, The semiconductor device can protect the privacy of consumers and prevent misuse after certificate revocation.

  FIG. 9 shows a third embodiment. In this embodiment, an antifuse diode 902 is electrically connected between the antenna circuit 901 and the signal processing circuit 903. When a large voltage is applied to the antenna circuit 901, a large voltage is also applied between the antifuse diodes 902, and when the voltage exceeds the withstand voltage of the antifuse diode 902, the antifuse diode 902 is short-circuited.

  When the antifuse diode 902 is short-circuited, the signal processing circuit 903 is not supplied with power, and thus the semiconductor device 900 loses its function as an ID chip after the short-circuit. As described above, by adding a large signal to the antenna so that the antifuse diode 902 is short-circuited after the end of the role of the ID chip such as when the purchase of the consumer is completed or after the expiration of the certificate, Semiconductor devices can prevent consumer privacy and misuse after certificate revocation.

  An example of the fuse element will be described with reference to FIG. The fuse element shown in FIG. 6A melts the metal wiring. Between the electrode 601 and the electrode 602, the thin filament-shaped fusing part 603 which connects both electrodes is provided. The fuse element connects the wiring 606 and the wiring 607. FIG. 6A shows an example in which a fuse element and a wiring are connected through contact holes 604 and 605 formed in an insulating film. As the wiring material, a gate electrode material or a source / drain electrode material constituting a thin film transistor (hereinafter referred to as TFT) can be used. The wiring width should be as narrow as possible so that fusing is possible with little heat generation, and is desirably 1 μm or less.

  Next, an example in which the island-shaped semiconductor region of the TFT is used as a fuse element will be described with reference to FIG. The fuse element shown in FIG. 6B is provided with a fusing part 610 connecting the electrodes between the electrodes 608 and 609. The electrode 608, the electrode 609, and the fusing part 610 are formed of a semiconductor. Since a large amount of current flows in this semiconductor, it is desirable to add a large amount of N-type or P-type impurities to keep the resistance value low. The wiring width should be as narrow as possible so that fusing is possible with little heat generation, and is desirably 1 μm or less.

  FIG. 13 shows a configuration in which a capacitor is used for the antifuse. It is a capacity in the initial state, and is in an open state in terms of direct current. After the large voltage is applied, both ends are short-circuited. This is an antifuse element in which a first conductive layer 1301 and a second conductive layer 1303 are provided on both sides of an insulating film 1302, and a high voltage is applied between the two conductive layers to break and short-circuit the insulating film. It is. According to the present embodiment, the second embodiment described above can be realized.

  The antifuse element shown in FIG. 14 is an antifuse element using a diode. In the initial state, a reverse bias is applied, and the DC state is open. After the large voltage is applied, both ends are short-circuited. This is because a high voltage is applied between the cathode 1404 connected to the N-type impurity region 1401 and the anode 1406 connected to the P-type impurity region 1403 to destroy and short-circuit the I-type region 1402 below the gate 1405. It is. According to the present embodiment, the above-described third embodiment can be realized.

  In FIG. 5, the voltage detection circuit 502 is configured by a diode 506, and the current amplification circuit 503 is configured by a TFT 505 and a TFT 508. Here, the TFT 505 and the TFT 508 constitute a current mirror circuit. The operation is described below. A signal received by the antenna circuit 501 is input to the voltage detection circuit 502. The diode 506 is reverse-biased and no current flows below the breakdown voltage. When the received signal increases and exceeds the breakdown voltage, a current flows through the diode 506.

  By multiplying the gate width of the TFT 508 by n times the gate width of the TFT 505, a current n times the current flowing through the diode 506 can be passed through the TFT 508. By setting n to a sufficiently large value, the drain current of the TFT 508 can be increased and the fuse 507 can be blown.

  In this manner, by supplying a large signal to the antenna circuit 501, power or a signal cannot be supplied to the signal processing circuit 504. Then, the semiconductor device 500 can be prevented from functioning as an ID chip.

  FIG. 7 shows an embodiment using a comparator. The voltage detection circuit 702 includes resistors 706 and 707, a comparator 709, and a voltage source 708. A signal input to the antenna circuit 701 is input to the resistor 706. The resistor 706 is connected to the non-inverting terminal of the resistor 707 and the comparator 709, and the signal of the antenna circuit 701 is divided by the resistor 706 and the resistor 707. On the other hand, a voltage source 708 is input to the inverting input terminal of the comparator 709, and the potential of the voltage source 708 is compared with the potential generated by the resistors 706 and 707. When the potential generated by the resistors 706 and 707 exceeds the potential of the voltage source 708, the TFT 710 operates and a drain current flows. The TFT 710 serves as a current amplification circuit 703. If the drain current of the TFT 710 is large, the fuse 705 can be blown.

  In this manner, by supplying a large signal to the antenna circuit 701, power or a signal cannot be supplied to the signal processing circuit 704. Then, the semiconductor device 700 can be prevented from functioning as an ID chip.

  An example of the comparator circuit will be described with reference to FIG. The comparator circuit includes a differential circuit and a current mirror circuit. The differential circuit includes a transistor 2205, a transistor 2206, and a current supply resistor 2204. The current mirror circuit is composed of transistors 2207 and 2208.

  When the gate potential of the transistor 2205 connected to the resistors 2201 and 2202 becomes higher than the gate potential of the transistor 2206 connected to the power source 2203, a larger amount of current flows through the transistor 2206, and the gate potential of the transistor 2209 is raised. As a result, a current flows through the output terminal 2210. Here, if the size of the transistor 2209 is sufficiently large and a fuse is connected to the output terminal 2210, the fuse can be blown by the output current of the transistor 2209. Thus, the first embodiment described above can be realized in this example. The comparator circuit used in the present invention is not limited to the above, but may be another type of circuit.

  A method for simultaneously manufacturing the memory element described in Embodiment Mode and TFTs used for logic circuit portions such as a decoder, a selector, a writing circuit, and a reading circuit over an insulating substrate will be described with reference to FIGS. Note that, in this embodiment, an n-channel memory element having a floating gate, an n-channel TFT, and a p-channel TFT are shown as examples of the semiconductor element, but are included in the memory portion and the logic circuit portion in the present invention. The semiconductor element is not limited to this. Further, this manufacturing method is an example, and the manufacturing method over an insulating substrate is not limited.

  First, base films 3001 and 3002 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film are formed over the insulating substrate 3000. For example, a silicon nitride film is formed as a base film 3001 in a thickness of 10 to 200 nm, and a silicon oxide film is stacked as a base film 3002 in order of 50 to 200 nm. Further, a silicon nitride film with a thickness of 1 to 5 nm may be formed over the silicon oxide film.

  The island-like semiconductor layers 3003 to 3005 are formed of a crystalline semiconductor film obtained by crystallizing a semiconductor film having an amorphous structure by laser annealing or crystallization by thermal annealing. The island-like semiconductor layers 3003 to 3005 are formed to a thickness of 25 to 80 nm. There is no limitation on the material of the crystalline semiconductor film, and it may be formed using silicon, silicon germanium (SiGe), or the like.

  Here, treatment for providing an overlap region for extracting charge on one side of the source region or the drain region of the island-shaped semiconductor layer 3003 of the TFT used for the memory element may be performed.

  Next, a gate insulating film 3006 is formed to cover the island-shaped semiconductor layers 3003 to 3005. The gate insulating film 3006 is formed of an insulating film containing silicon with a thickness of 10 to 80 nm by using a plasma CVD method or a sputtering method. In particular, in an OTP type non-volatile memory, writing by hot electron injection and charge retention are important. Therefore, it is preferable that the gate insulating film has a thickness of 40 to 80 nm in which a tunnel current does not easily flow.

  Then, first conductive layers 3007 to 3009 are formed on the gate insulating film 3006 and removed by etching except for a region that later becomes a floating gate electrode and a region that becomes a gate electrode of a normal TFT.

  Next, a second gate insulating film 3010 is formed. The second gate insulating film 3010 is formed of an insulating film containing silicon with a thickness of 10 to 80 nm by using a plasma CVD method or a sputtering method. The second gate insulating film 3010 is removed by etching except for a region where the memory element exists.

  Subsequently, second conductive layers 3011 to 3013 are formed, and the stacked first conductive layer 3007 and the second gate insulating film 3010 and the second conductive layer 3011 (memory element), or the stacked first conductive layer 3008 and The second conductive layer 3012 (ordinary TFT) or the stacked first conductive layer 3009 and second conductive layer 3013 (ordinary TFT) are etched at once, so that a floating gate electrode, a control gate electrode, A gate electrode of a normal TFT is formed.

  In this embodiment, the first conductive layers 3007 to 3009 are formed with titanium nitride to a thickness of 50 to 100 nm, and the second conductive layers 3011 to 3013 are formed with tungsten to a thickness of 100 to 300 nm. Of course, the material of the conductive layer is not particularly limited, and any of them may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or the like, or an alloy material or a compound material containing the element as a main component. good.

  Subsequently, doping which imparts n-type to the TFT used for the memory element is performed to form first impurity regions 3014 and 3015. Next, doping for imparting p-type conductivity is performed on the p-channel TFT used in the logic circuit portion, so that second impurity regions 3016 and 3017 are formed. Subsequently, in order to form a low-concentration impurity (LDD) region of an n-channel TFT used in the logic circuit portion, doping for imparting n-type is performed, and third impurity regions 3018 and 3019 are formed. After that, sidewalls 3020 and 3021 are formed, and doping to impart n-type to the n-channel TFT used in the logic circuit portion is performed to form fourth impurity regions 3022 and 3023. These doping methods include an ion doping method (a method in which the impurity ions are not mass-separated) or an ion implantation method (in which the impurity ions are mass-separated). Method). Through the above steps, impurity regions are formed in each island-like semiconductor layer.

  Next, a first interlayer insulating film 3024 is formed using a silicon oxynitride film. The thickness of the first interlayer insulating film 3024 is 10 to 80 nm, which is about the same as that of the gate insulating film 3006. Then, a process of hydrogenating the island-like semiconductor layer by diffusing hydrogen contained in the silicon oxynitride film is performed. The heat treatment for hydrogenation is performed by heating to 450 to 650 ° C. by rapid thermal annealing, for example. Simultaneously with this hydrogenation, the impurity element added to each island-like semiconductor layer can also be activated.

Subsequently, a second interlayer insulating film 3025 made of an organic insulating material such as acrylic is formed. Alternatively, an inorganic material can be used for the second interlayer insulating film 3025 instead of the organic insulating material. Examples of the inorganic materials _SiO 2, SOG prepared in an inorganic SiO _2, a plasma CVD method; such (Spin on Glass coated silicon oxide film) is used. After forming the two interlayer insulating films, an etching process for forming a contact hole is performed.

  Then, electrodes 3026 and 3027 are formed in contact with the source and drain regions of the island-like semiconductor layer in the memory portion. Similarly, the electrodes 3028 to 3030 are formed in the logic circuit portion.

  As described above, a memory portion having an n-channel storage element having a floating gate and a logic circuit portion having an n-channel TFT having an LDD structure and a p-channel TFT having a single drain structure, as shown in FIG. Can be formed on the same substrate.

  Further, in this embodiment, a manufacturing method in the case where a memory portion and a logic circuit portion are formed and transferred to a flexible substrate will be described with reference to FIGS. Note that in this embodiment, an n-channel memory element having a floating gate, an n-channel TFT, and a p-channel TFT are shown as examples of the semiconductor element. However, in the present invention, the memory element and the logic circuit part are included. The semiconductor element to be used is not limited to this. Further, this manufacturing method is an example, and the manufacturing method over an insulating substrate is not limited.

  A peeling layer 4000 is formed over the insulating substrate 3000. As the separation layer 4000, a layer containing silicon as its main component such as amorphous silicon, polycrystalline silicon, single crystal silicon, or microcrystalline silicon (including semi-amorphous silicon) can be used. The peeling layer 4000 can be formed by a sputtering method, a plasma CVD method, or the like. In this embodiment, amorphous silicon having a thickness of about 500 nm is formed by a sputtering method and used as the peeling layer 4000. Subsequently, according to the above-described work process, a memory part and a logic circuit part as shown in FIG. 15 are formed.

  Next, a third interlayer insulating film 4001 is formed over the second interlayer insulating film 3025, and pads 4002 to 4005 are formed. For the pads 4002 to 4005, a conductive material having one or more metals such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al, or a metal compound can be used.

  Then, a protective layer 4006 is formed over the third interlayer insulating film 4001 so as to cover the pads 4002 to 4005. The protective layer 4006 is formed using a material that can protect the pads 4002 to 4005 when the peeling layer 4000 is later removed by etching. For example, the protective layer 4006 can be formed by applying an epoxy, acrylate, or silicon resin soluble in water or alcohols over the entire surface (FIG. 16A).

  Next, a groove 4007 for separating the separation layer 4000 is formed (see FIG. 16B). The groove 4007 may be formed so long as the peeling layer 4000 is exposed. The groove 4007 can be formed by etching, dicing, scribing, or the like.

Next, the peeling layer 4000 is removed by etching (see FIG. 17A). In this embodiment, halogen fluoride is used as an etching gas, and the gas is introduced from the groove 4007. In this embodiment, for example, ClF ₃ (chlorine trifluoride) is used, and the temperature is 350 ° C., the flow rate is 300 sccm, the atmospheric pressure is 800 Pa (6 Torr), and the time is 3 hours. Further, a gas in which nitrogen is mixed with ClF ₃ gas may be used. By using halogen fluoride such as ClF ₃ , the peeling layer 4000 is selectively etched, and the insulating substrate 3000 can be peeled off. The halogen fluoride may be either a gas or a liquid.

  Next, the peeled memory portion and logic circuit portion are attached to a support body 4009 with an adhesive 4008 (see FIG. 17B). As the adhesive 4008, a material capable of bonding the support body 4009 and the base film 3001 is used. As the adhesive 4008, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  As the support 4009, an organic material such as flexible paper or plastic can be used. Alternatively, a flexible inorganic material may be used as the support body 4009. In addition, a support body 4009 may be formed by laminating a glass plate having a thickness of 0.1 to 0.5 mm and an organic resin film having a thickness of about 10 to 100 μm, and combining an inorganic material and an organic material. The support 4009 preferably has a high thermal conductivity of about 2 to 30 W / mK in order to diffuse the heat generated in the integrated circuit.

  Note that the method for peeling the integrated circuit of the memory portion and the logic circuit portion from the insulating substrate 3000 is not limited to the method using etching of the silicon film as shown in this embodiment, and various other methods can be used. . For example, a metal oxide film can be provided between a substrate having high heat resistance and an integrated circuit, and the integrated circuit can be peeled by weakening the metal oxide film by crystallization. Alternatively, the peeling layer can be broken by laser light irradiation, and the integrated circuit can be peeled from the substrate. Further, for example, the integrated circuit can be peeled from the substrate by mechanically removing the substrate on which the integrated circuit is formed or removing the substrate by etching with a solution or gas.

  In addition, when the surface of the object has a curved surface, and the ID chip support bonded to the curved surface is bent so as to have a curved surface drawn by movement of the generatrix such as a cone surface or a column surface, It is desirable to align the direction of the bus and the direction in which the TFT carrier moves. With the above configuration, even if the support is bent, it can be suppressed that the characteristics of the TFT are affected thereby. In addition, by setting the ratio of the area occupied by the island-shaped semiconductor film in the integrated circuit to 1 to 30%, it is possible to further suppress the influence of the TFT characteristics even if the support is bent. . This embodiment can be used in combination with the above embodiment mode and other embodiments.

  An example in the case of forming a flexible ID tag using a peeling process will be described with reference to FIG. The ID tag includes flexible protective layers 2301 and 2303 and an ID chip 2302 formed using a peeling process. In this embodiment, the antenna 2304 is formed not on the ID chip 2302 but on the protective layer 2303 and is electrically connected to the ID chip 2302. In FIG. 21A, the antenna is formed only over the protective layer 2303; however, an antenna may also be formed over the protective layer 2301. The antenna is preferably silver, copper, or a metal plated with them. The ID chip 2302 and the antenna are connected using an anisotropic conductive film and subjected to UV treatment, but the connection method is not limited to this.

  FIG. 21B shows a cross section of FIG. The ID chip 2302 has a thickness of 5 μm or less, and preferably has a thickness of 0.1 μm to 3 μm. Further, the thickness of the protective layers 2301 and 2303 is preferably (d / 2) ± 30 μm, where d is the thickness when the protective layers 2301 and 2303 are overlapped, and in particular, (d / 2) ± 10 μm is the best. The thickness of the protective layers 2301 and 2303 is desirably 10 μm to 200 μm. The area of the ID chip 2302 is 5 mm square or less, and desirably has an area of 0.3 mm square to 4 mm square.

  The protective layers 2301 and 2303 are formed of an organic resin material and have a strong structure against bending. Since the ID chip 2302 itself using a peeling process is more resistant to bending than a single crystal semiconductor, the ID chip 2302 can be closely attached to the protective layers 2301 and 2303. The ID chip surrounded by the protective layers 2301 and 2303 may be disposed on the surface or inside of another individual object. It may also be embedded in paper.

In the case where the ID chip is curved, that is, an example in which TFTs are arranged perpendicular to the direction in which the ID chip draws an arc will be described with reference to FIG. The TFT included in the ID chip in FIG. 19 is arranged so that the current direction 150, that is, the positions of the drain electrode 151 to the gate electrode 152 and the gate electrode 152 to the source electrode 153 are linear, and the influence of stress is reduced. ing. By performing such an arrangement, variation in TFT characteristics can be suppressed. Further, the crystals constituting the TFT are aligned in the current direction 150, and by forming them with CWLC or the like, the S value is 0.35 V / dec or less (preferably 0.09 to 0.25 V / dec), The mobility can be 100 cm ² / Vs or higher.
When a 19-stage ring oscillator is configured using such TFTs, the oscillation frequency is 1 MHz or higher, preferably 100 MHz or higher, at a power supply voltage of 3 to 5 V. At a power supply voltage of 3 to 5 V, the delay time per inverter stage is 26 ns, preferably 0.26 ns or less.

Further, in order not to destroy active elements such as TFTs due to stress, the ratio of the area of the active region (silicon island portion) of the active elements such as TFTs to the entire area is 5% to 50%. It is desirable.
In a region where there is no active element such as a TFT, a base insulating material, an interlayer insulating material, and a wiring material are mainly provided. The area other than the active region of the TFT is desirably 60% or more of the entire area.
The active region has a thickness of 20 to 200 nm, typically 40 to 170 nm, preferably 45 to 55 nm, or 145 to 155 nm.

  In this embodiment, an example in which an external antenna is attached to a circuit using the present invention will be described with reference to FIGS.

  FIG. 10A shows the circuit covered with a single antenna. An antenna 1001 is formed over a substrate 1000, and a circuit 1002 using the present invention is connected. In the drawing, the periphery of the circuit 1002 is covered with the antenna 1001; however, a structure in which the entire surface is covered with the antenna and the circuit 1002 including the electrodes is attached thereon may be employed.

  FIG. 10B shows a thin antenna arranged around the circuit. An antenna 1004 is formed over a substrate 1003 and a circuit 1005 using the present invention is connected. The wiring of the antenna is an example and is not limited to this.

  FIG. 10C illustrates a high frequency antenna. An antenna 1007 is formed over a substrate 1006, and a circuit 1008 using the present invention is connected.

  FIG. 10D illustrates an antenna that is 180 degrees omnidirectional (same reception is possible from any direction). An antenna 1010 is formed over a substrate 1009 and a circuit 1011 using the present invention is connected.

  FIG. 10E shows an antenna elongated in a rod shape. An antenna 1013 is formed over a substrate 1012, and a circuit 1014 using the present invention is connected.

  The circuit using the present invention and connection to these antennas can be made by a known method. For example, the antenna and the circuit may be connected using wire bonding connection or bump connection, or one surface of the circuit formed as a chip may be attached to the antenna as an electrode. In this method, it can be attached using an ACF (anisotropy conductive film).

  The length required for the antenna differs depending on the frequency used for reception. In general, the length is preferably an integral number of a wavelength. For example, when the frequency is 2.45 GHz, it may be about 60 mm (1/2 wavelength) and about 30 mm (1/4 wavelength).

  Further, a substrate may be attached on the circuit of the present invention, and an antenna may be further formed thereon. As an example, FIGS. 11A to 11C are a top view and a cross-sectional view of a circuit in which a substrate is attached on a circuit and a spiral antenna is disposed. The element substrate 1100 includes an antenna circuit, a voltage detection circuit, a current amplification circuit, a signal processing circuit, a fuse, and the like. In addition, a memory circuit, an arithmetic processing circuit, and the like may be included. The antenna wiring 1101 is provided on the element substrate 1100. Since the element substrate 1100 can be a magnetically permeable insulating substrate, it is preferable because the antenna directivity is not impaired even if the antenna wiring 1101 is integrated.

  Note that the example shown in this embodiment is just an example, and does not limit the shape of the antenna. The present invention can be implemented with any shape of antenna. This example can be realized by using a configuration including any combination of the embodiment and the above Examples 1 to 7.

  In this embodiment, a specific method for manufacturing a thin film integrated circuit device including a TFT will be described with reference to FIGS. Here, for the sake of simplicity, a manufacturing method will be described by showing a cross-sectional structure of a CPU and a memory portion using n-type TFTs and p-type TFTs.

  First, the separation layer 61 is formed over the substrate 60 (FIG. 22A). Here, an a-Si film (amorphous silicon film) having a thickness of 50 nm was formed on a glass substrate (for example, a 1737 substrate manufactured by Corning) by a low pressure CVD method. As the substrate, in addition to a glass substrate, a quartz substrate, a substrate formed of an insulating material such as alumina, a silicon wafer substrate, a plastic substrate having heat resistance that can withstand a processing temperature in a later process, or the like can be used. .

  As the separation layer, a film containing silicon as a main component, such as polycrystalline silicon, single crystal silicon, and SAS (semi-amorphous silicon (also referred to as microcrystalline silicon or microcrystalline silicon)) in addition to amorphous silicon. Although it is desirable to use, it is not limited to these. The peeling layer may be formed by a plasma CVD method, a sputtering method, or the like in addition to the low pressure CVD method. Alternatively, a film doped with an impurity such as phosphorus may be used. Further, the thickness of the release layer is desirably 50 to 60 nm. Regarding SAS, it is good also as 30-50 nm.

Next, a protective film 55 (also referred to as a base film or a base insulating film) is formed over the separation layer 61 (FIG. 22A). Here, a three-layer structure of a silicon oxide film with a thickness of 100 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxide film with a thickness of 100 nm is employed. Of course, the material, film thickness, and number of layers of the protective film 55 are not limited thereto. For example, instead of the lower silicon oxide film, a heat-resistant resin such as siloxane having a thickness of 0.5 to 3 μm may be formed by a spin coat method, a slit coater method, a droplet discharge method, or the like. Further, a silicon nitride film (SiN, Si ₃ N ₄ or the like) may be used. Each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

Here, the silicon oxide film may be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD, using a mixed gas such as SiH ₄ and O ₂ , TEOS (tetraethoxysilane) and O _2. it can. The silicon nitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ and NH ₃ . The silicon oxynitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ and N ₂ O.

  In addition, when using the material which has silicon as main components, such as a-Si, as the peeling layer 61 and the island-like semiconductor film 57, it is SiOxNy (x>) from the point of ensuring adhesiveness as a protective film which touches them. y) may be used.

  Next, on the protective film 55, a central processing unit (CPU) of a thin film integrated circuit device and a thin film transistor (TFT) constituting a memory are formed. In addition to TFTs, thin film active elements such as organic TFTs and thin film diodes can also be formed.

  As a method for manufacturing a TFT, first, an island-shaped semiconductor film 57 is formed over the protective film 55 (FIG. 22B). The island-shaped semiconductor film 57 is formed using an amorphous semiconductor, a crystalline semiconductor, or a semi-amorphous semiconductor. In any case, a semiconductor film containing silicon, silicon germanium (SiGe), or the like as a main component can be used.

  Here, amorphous silicon having a thickness of 70 nm was formed, and the surface thereof was further treated with a solution containing nickel. Further, a crystalline silicon semiconductor film was obtained by a thermal crystallization process at 500 to 750 ° C., and crystallinity was improved by laser crystallization. Further, as a film formation method, a plasma CVD method, a sputtering method, an LPCVD method, or the like may be used. As the crystallization method, laser crystallization method, thermal crystallization method, thermal crystallization using other catalysts (Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, etc.), or alternating them You may go multiple times.

Further, a continuous wave laser may be used for the crystallization treatment of the semiconductor film. Typically, if a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) is applied, a crystal having a large grain size can be obtained. As the harmonics of the continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W can be obtained by a nonlinear optical element. In addition, there is a method in which a YVO ₄ crystal or a GdVO ₄ crystal and a nonlinear optical element are placed in a resonator to emit harmonics. The laser beam is shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

  When a pulsed laser is used, a frequency band of several tens Hz to several hundreds Hz is used, but a pulsed laser having an oscillation frequency of 10 MHz or higher that is significantly higher than that may be used. The time from when the semiconductor film is irradiated with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. By using the above high frequency band, the semiconductor film is melted by the laser light. Then, it can be irradiated with the next pulse of laser light until it solidifies. Therefore, unlike the case of using a conventional pulsed laser, the solid-liquid interface can be continuously moved in the semiconductor film, so that a semiconductor film having crystal grains continuously grown in the scanning direction is formed. can do. For example, a set of crystal grains having a width of 10 to 30 μm in the scanning direction of the included crystal grains and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, it is possible to form a semiconductor film having almost no crystal grain boundaries in at least the channel direction of the TFT.

  Note that when siloxane which is a heat-resistant organic resin is used as a part of the protective film 55, heat can be prevented from leaking from the semiconductor film during the crystallization, and crystallization can be efficiently performed. It can be carried out.

A crystalline silicon semiconductor film is obtained by the above method. Note that the crystals are preferably aligned in the source, channel, and drain directions. The thickness of the crystal layer is preferably 20 to 200 nm (typically 40 to 170 nm, more preferably 50 to 150 nm). Thereafter, an amorphous silicon film for gettering the metal catalyst is formed on the semiconductor film via an oxide film, and gettering is performed by heat treatment at 500 to 750 ° C. Furthermore, in order to control the threshold value as the TFT element, boron ions are implanted into the crystalline silicon semiconductor film at a dose of 10 ¹³ / cm ² . Thereafter, the island-shaped semiconductor film 57 is formed by etching using the resist as a mask.

In forming a crystalline semiconductor film, a polycrystalline semiconductor film is directly formed by LPCVD (low pressure CVD) as a source gas of disilane (Si ₂ H ₆ ) and germanium fluoride (GeF ₄ ). Also, a crystalline semiconductor film can be obtained. The gas flow ratio is Si ₂ H ₆ / GeF ₄ = 20 / 0.9, the film forming temperature is 400 to 500 ° C., and He or Ar is used as the carrier gas, but the present invention is not limited to this.

Note that hydrogen or halogen of 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ is preferably added to the channel region in the TFT. . Regarding SAS, it is desirable to set it as 1 * 10 < ¹⁹ > -2 * 10 < ²¹ > / cm < ³ >. In any case, it is desirable to contain more than the content of hydrogen or halogen contained in the single crystal used for the IC chip. Thereby, even if a local crack occurs in the TFT portion, it can be terminated (terminated) by hydrogen or halogen.

  Next, a gate insulating film 58 is formed over the island-shaped semiconductor film 57 (FIG. 22B). The gate insulating film 58 is preferably formed using a thin film formation method such as a plasma CVD method or a sputtering method, and a single layer or a stack of films containing silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride. . In the case of stacking, for example, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film is preferable from the substrate side.

  Next, the gate electrode 56 is formed (FIG. 22C). Here, after the Si and W (tungsten) layers are formed by sputtering, the gate electrode 56 is formed by etching using the resist 62 as a mask. Of course, the material, structure, and manufacturing method of the gate electrode 56 are not limited thereto, and can be selected as appropriate. For example, a stacked structure of Si and NiSi (nickel silicide) doped with an n-type impurity or a stacked structure of tantalum nitride and tungsten may be used. Alternatively, a single layer may be formed using various conductive materials.

  Further, a silicon oxide or silicon oxynitride mask (referred to as a hard mask) may be used instead of the resist mask. In this case, although a hard mask patterning process is added, the gate electrode layer having a desired width can be formed because the mask film thickness during etching is less than that of the resist. Alternatively, the gate electrode 56 may be selectively formed by using a droplet discharge method without using the resist 62.

  As the conductive material, various materials can be selected depending on the function of the conductive film. In the case where the gate electrode and the antenna are formed at the same time, materials may be selected in consideration of their functions.

Note that a mixed gas of CF ₄ , Cl ₂ , and O ₂ or a Cl ₂ gas is used as an etching gas for forming the gate electrode by etching, but the present invention is not limited to this.

Next, the portions to become the p-type TFTs 70 and 72 are covered with a resist 63, and the gate electrode is used as a mask, and the impurity element 64 (typically P-type) imparting n-type is formed in the island-shaped semiconductor films of the n-type TFTs 69 and 71. (Phosphorus) or As (arsenic)) is doped at a low concentration (first doping step, FIG. 22D). The conditions of the first doping step are a dose of 1 × 10 ^{13 to} 6 × 10 ¹³ / cm ² and an acceleration voltage of 50 to 70 keV, but are not limited thereto. In this first doping step, doping is performed through the gate insulating film 58, and a pair of n-type low-concentration impurity regions 65 are formed. The first doping step may be performed on the entire surface without covering the p-type TFT region with the resist.

Next, after removing the resist 63 by ashing or the like, a resist 66 covering the n-type TFT region is newly formed, and p-type is imparted to the island-like semiconductor films of the p-type TFTs 70 and 72 using the gate electrode as a mask. The impurity element 67 (typically B (boron)) to be doped is doped at a high concentration (second doping step, FIG. 22E). The conditions of the second doping step are a dose of 1 × 10 ^{16 to} 3 × 10 ¹⁶ / cm ² and an acceleration voltage of 20 to 40 keV, but are not limited thereto. In the second doping step, doping is performed through the gate insulating film 58, and a pair of p-type high concentration impurity regions 68 are formed.

Next, after removing the resist 66 by ashing or the like, an insulating film 75 was formed on the substrate surface (FIG. 23F). Here, a SiO ₂ film having a thickness of 100 nm was formed by a plasma CVD method. Thereafter, the insulating film 75 and the gate insulating film 58 were removed by etching using an etch back method, and sidewalls (sidewalls) 76 were formed in a self-aligned manner (FIG. 23G). As an etching gas, a mixed gas of CHF ₃ and He was used. Note that the step of forming the sidewall is not limited to these.

  If an insulating film is also formed on the back surface of the substrate when the insulating film 75 is formed, the insulating film on the back surface is removed by etching using a resist covering the entire surface of the substrate as a mask (back surface processing).

The method for forming the sidewall 76 is not limited to the above. For example, the method shown in FIG. 24 can be used. FIG. 24A illustrates an example in which the insulating film 75 has a two-layer structure or more. The insulating film 75 has a two-layer structure of, for example, a 100 nm thick SiON (silicon oxynitride) film and a 200 nm thick LTO film (Low Temperature Oxide). Here, SiON film is formed by plasma CVD method, the LTO layer was formed a SiO ₂ film by low pressure CVD. After that, by performing etch back, the sidewall 76 having an L shape and an arc shape is formed.

  FIG. 24B shows an example in which etching is performed so as to leave the gate insulating film 58 during etch back. In this case, the insulating film 75 may have a single layer structure or a laminated structure.

  The sidewall functions as a mask when a high concentration n-type impurity is doped later to form a low concentration impurity region or a non-doped offset region below the sidewall 76. In any of the formation methods, the etch-back conditions may be appropriately changed depending on the width of the low-concentration impurity region or offset region to be formed.

Next, a resist 77 covering the p-type TFT region is newly formed, and an n-type impurity element 78 (typically P or As) is doped at a high concentration using the gate electrode 56 and the sidewall 76 as a mask. (Third doping step, FIG. 23H). The conditions of the third doping step are a dose amount: 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage: 60 to 100 keV. By this third doping step, a pair of n-type high concentration impurity regions 79 are formed.

  Note that after removing the resist 77 by ashing or the like, the impurity region may be thermally activated. For example, after a silicon oxynitride film with a thickness of 50 nm is formed, heat treatment may be performed in a nitrogen atmosphere at 550 ° C. for 4 hours. In addition, after a silicon nitride film containing hydrogen is formed to a thickness of 100 nm, defects in the crystalline semiconductor film can be improved by performing heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere. This terminates dangling bonds existing in, for example, crystalline silicon, and is called a hydrogenation process. Thereafter, a silicon oxynitride film having a thickness of 600 nm is formed as a cap insulating film for protecting the TFT. Note that the hydrogenation treatment step may be performed after the silicon oxynitride film is formed. In this case, the silicon nitride film and the silicon oxynitride film can be continuously formed. As described above, a three-layer insulating film in which silicon oxynitride, silicon nitride, and silicon oxynitride are sequentially stacked is formed over the TFT, but the structure and material are not limited to these. . In addition, these insulating films have a function of protecting the TFT, so that it is desirable to form them as much as possible.

  Next, an interlayer film 53 is formed over the TFT (FIG. 23I). As the interlayer film 53, a heat-resistant organic resin such as polyimide, acrylic, polyamide, or siloxane can be used. As a forming method, a spin coat, dip, spray coating, droplet discharge method (ink jet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. are adopted depending on the material. be able to. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the interlayer film 53 may be formed by stacking these insulating films.

  Further, a protective film 54 may be formed on the interlayer film 53. As the protective film 54, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like can be used. As a formation method, a plasma CVD method, an atmospheric pressure plasma, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist, or benzocyclobutene, or a heat-resistant organic resin such as siloxane may be used.

  In order to prevent the film from peeling or cracking of these films due to the stress caused by the difference in thermal expansion coefficient between the interlayer film 53 or the protective film 54 and a conductive material or the like constituting the wiring to be formed later, A filler may be mixed in the film 53 or the protective film 54.

Next, after forming a resist, a contact hole is formed by etching, and a wiring 51 for connecting TFTs and a connection wiring 21 for connecting to an external antenna are formed (FIG. 23I). The gas used for etching when opening the contact hole is a mixed gas of CHF ₃ and He, but is not limited to this. Moreover, the wiring 51 and the connection wiring 21 may be formed simultaneously using the same material, or may be formed separately. Here, the wiring 51 connected to the TFT has a five-layer structure in which Ti, titanium nitride (TiN), Al (Si added), Ti, and titanium nitride (TiN) are sequentially stacked, and is formed by sputtering, and then patterned. Formed.

  In addition, by mixing Si in the Al layer, generation of hillocks in resist baking during wiring patterning can be prevented. Further, instead of Si, about 0.5% Cu may be mixed. Further, hillock resistance is further improved by sandwiching an Al (Si addition) layer with Ti or titanium nitride. Note that it is desirable to use the hard mask made of silicon oxynitride or the like for patterning. Note that the wiring material and the formation method are not limited to these, and the material used for the gate electrode described above may be employed.

  In the present embodiment, the case where only the TFT region constituting the CPU 73, the memory 74, etc. and the terminal portion 80 connected to the antenna are integrally formed is shown. However, the present invention can also be applied to the case where the TFT region and the antenna are integrally formed. Embodiments can be applied. In this case, an antenna is preferably formed on the interlayer film 53 or the protective film 54 and further covered with another protective film. As the conductive material of the antenna, Ag, Au, Al, Cu, Zn, Sn, Ni, Cr, Fe, Co, or Ti, or an alloy containing them can be used, but is not limited thereto. Further, the material may be different between the wiring and the antenna. Note that the wiring and the antenna are preferably formed so as to have a metal material having excellent malleability and ductility, and more preferably, the wiring and the antenna are made thick to withstand stress due to deformation.

  As a formation method, after forming a film on the entire surface by a sputtering method, patterning may be performed using a resist mask, or selective formation from a nozzle may be performed by a droplet discharge method. Note that the droplet discharge method here includes not only an inkjet method but also an offset printing method and a screen printing. The wiring and the antenna may be formed at the same time, or may be formed so that the other rides on after forming one first.

  Through the above steps, a thin film integrated circuit device composed of TFTs is completed. Although the top gate structure is used in this embodiment, a bottom gate structure (reverse stagger structure) may be used. Note that a base insulating film material, an interlayer insulating film material, and a wiring material are mainly provided in a region where a thin film active element portion (active element) such as a TFT does not exist, and this region is the entire thin film integrated circuit device. It is desirable to occupy 50% or more, preferably 70 to 95%. This makes it easy to bend the ID chip and facilitates handling of finished products such as ID labels. In this case, the island-shaped semiconductor region (island) of the active element including the TFT portion occupies 1 to 30%, preferably 5 to 15% of the entire thin film integrated circuit device.

Further, as shown in FIG. _23I, a distance ( _tunder ) from the semiconductor layer of the TFT to the lower protective layer in the thin film integrated circuit device, and an upper interlayer film (protective layer is formed from the semiconductor layer). In some cases, it is desirable to adjust the thicknesses of the upper and lower protective layers or interlayer films so that the distance (t _over ) to the protective layer is equal or approximately equal. In this manner, by placing the semiconductor layer in the center of the thin film integrated circuit device, the stress on the semiconductor layer can be relaxed and the occurrence of cracks can be prevented.

  In this embodiment, the semiconductor device of the present invention can be used for IC cards, IC tags, RFIDs, transponders, banknotes, securities, passports, electronic devices, bags, and clothes. Here, examples of an IC card, an ID tag, an ID chip, and the like will be described with reference to FIG.

  FIG. 18A shows an IC card 2000, which is a credit card capable of paying for money without using cash by utilizing the fact that the memory of a built-in circuit can be rewritten in addition to personal identification, or You can use it like electronic money. A circuit unit 2001 using the present invention is incorporated in an IC card 2000.

  FIG. 18B illustrates an ID tag 2010 that can be used for admission management in a specific place because it can be downsized in addition to personal identification. A circuit portion 2011 using the present invention is incorporated in the ID tag 2010.

  FIG. 18C shows an example in which an ID chip 2022 for managing a product when the product 2020 is handled in a retail store such as a supermarket is attached to the product. The present invention is applied to a circuit in the ID chip 2022. By attaching the ID chip 2022 to the product 2020, not only inventory management is facilitated, but also damage such as shoplifting can be prevented. In FIG. 18C, a protective film 2021 that also serves as an adhesive is used to prevent the ID chip 2022 from peeling off, but the structure in which the ID chip 2022 is directly attached to the product 2020 using an adhesive is used. You may take it. Moreover, it is preferable to produce using the flexible substrate mentioned in Example 2 on the structure attached to goods.

  FIG. 18D shows an example in which an ID chip 2031 for identification is incorporated at the time of product manufacture. In the drawing, an ID chip 2031 is incorporated in a display housing 2030 as an example. The present invention is applied to a circuit in the ID chip 2031. By adopting such a structure, it is possible to easily identify the manufacturer, manage the distribution of goods, and the like. Note that although the case of a display is taken as an example in the drawings, the present invention is not limited to this and can be applied to various electronic devices and articles.

  FIG. 18E shows an article transport tag 2040. In the drawing, an ID chip 2041 is incorporated in a tag 2040. The present invention is applied to a circuit in the ID chip 2041. By adopting such a structure, it is possible to easily carry out transport destination selection, merchandise distribution management, and the like. In the drawings, the structure is such that a string-like object that binds the article is attached, but the present invention is not limited to this, and it is directly attached to the article using something like a sealing material. You may take a simple structure.

  FIG. 18F shows an example in which an ID chip 2052 is incorporated in the book 2050. The present invention is applied to a circuit in the ID chip 2052. By adopting such a structure, distribution management at a bookstore or lending processing at a library or the like can be easily performed. In the drawing, a protective film 2051 that also serves as an adhesive is used to prevent the ID chip 2052 from peeling off, but a structure in which the ID chip 2052 is directly attached using an adhesive or a cover of this book 2050 is used. You may take the structure embedded in.

  FIG. 18G illustrates an example in which an ID chip 2061 is incorporated into a banknote 2060. The present invention is applied to a circuit in the ID chip 2061. By adopting such a structure, it is possible to easily prevent the circulation of counterfeit bills. Note that it is more preferable to adopt a structure in which the ID chip 2061 is embedded in the banknote 2060 in order to prevent the ID chip 2061 from peeling off due to the nature of the banknote. The present invention is not limited to banknotes, and can be applied to papers such as securities and passports.

  FIG. 18H shows an shoe in which an ID chip 2072 is incorporated into a shoe 2070. The present invention is applied to a circuit in the ID chip 2072. By adopting such a structure, it is possible to easily identify the manufacturer, manage the distribution of goods, and the like. In the drawing, a protective film 2071 that also serves as an adhesive is used to prevent the ID chip 2072 from peeling off. However, the ID chip 2072 is directly attached using an adhesive or embedded in a shoe 2070. The structure may be taken. The present invention is applicable not only to shoes but also to items worn on bags, clothes, and the like.

  A case will be described in which an ID chip is mounted on various articles for the purpose of ensuring security. Ensuring security can be understood from the aspect of preventing theft or forgery.

  As an example of theft prevention, a case where an ID chip is mounted on a bag will be described. As shown in FIG. 25, an ID chip 2502 is mounted on a bag 2501. For example, the ID chip 2502 can be mounted on a part of the bottom or side surface of the bag 2501. Since the ID chip 2502 is very thin and small, it can be mounted without deteriorating the design of the bag 2501. In addition, the ID chip 2502 has translucency, and it is difficult for a thief to determine whether the ID chip 2502 is mounted. Therefore, there is no possibility that the ID chip 2502 is removed by the theft.

  When such an ID chip mounting bag is stolen, information on the current position of the bag can be obtained using, for example, GPS (Global Positioning System). GPS is a system that captures a signal sent from a GPS satellite, obtains a time difference thereof, and performs positioning based on the time difference.

  Further, in addition to the stolen article, it is possible to obtain information on the current position of forgotten or lost items using GPS.

  In addition to bags, ID chips can be mounted on vehicles such as automobiles and bicycles, watches and accessories.

  Next, as an example of forgery prevention, a case where an ID chip is mounted on a passport or a license will be described.

  FIG. 26A shows a passport 2601 on which an ID chip is mounted. In FIG. 26A, the ID chip 2602 is mounted on the cover of the passport 2601; however, the ID chip 2602 may be mounted on another page. The ID chip 2602 may be mounted on the surface because it has translucency. Further, the ID chip 2602 may be sandwiched between materials such as a cover and mounted inside the cover.

  FIG. 26B shows a license 2603 mounted with an ID chip. In FIG. 26B, the ID chip 2604 is mounted inside the license 2603. Further, since the ID chip 2604 has a light-transmitting property, the ID chip 2604 may be provided on the printing surface of the license 2603. For example. The ID chip 2604 is mounted on the printing surface of the license 2603, and a thermosetting resin film and a resin film are arranged on the upper and lower sides of the ID chip 2604, sandwiched, and thermocompression bonded, whereby the ID chip 2604 is mounted. The evidence 2603 can be covered. Further, the ID chip 2604 can be sandwiched between the materials of the license 2603 and mounted inside.

  Forgery can be prevented by mounting the ID chip on the article as described above. Further, forgery can be prevented by mounting an ID chip on the above-described bag. In addition, since a very thin and small ID chip is used, the design such as a passport and a license is not impaired. Furthermore, since the ID chip has translucency, it may be mounted on the surface.

  The ID chip can easily manage passports and licenses. Furthermore, since information can be stored in the ID chip without directly entering information in a passport or a license, privacy can be protected.

A case where an ID chip is mounted on a commodity such as food for safety management will be described with reference to FIG.
A label 2702 on which an ID chip 2703 is mounted and a meat pack 2701 to which the label 2702 is attached are shown. The ID chip 2703 may be mounted on the surface of the label 2702 or may be mounted inside the label 2702. In the case of fresh food such as vegetables, an ID chip may be mounted on a wrap that covers the fresh food.

  The ID chip 2703 can record basic items related to the product such as the product production location, producer, processing date, expiration date, and application items such as cooking examples using the product. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as MROM. Such application items may be recorded using a rewritable and erasable memory such as EEROM.

  In addition, it is important to be able to know the state of animals and plants before processing in order to carry out food safety management. Therefore, it is preferable to embed an ID chip in animals and plants and acquire information on animals and plants by a reader device. Information on animals and plants includes breeding grounds, feed, breeders, presence of infectious diseases, and the like.

  If the price of the product is recorded on the ID chip, the product can be settled more easily and in a shorter time than a method using a conventional barcode. That is, it is possible to settle a plurality of products on which the ID chip is mounted all at once. However, when reading a plurality of ID chips in this way, it is necessary to mount an anti-collision function in the reader device.

  Furthermore, depending on the communication distance of the ID chip, the product can be settled even if the distance between the register and the product is long. ID chips also help prevent shoplifting.

  Furthermore, the ID chip can be used in combination with other information media such as a barcode and a magnetic tape. For example, basic items that do not need to be rewritten are recorded on the ID chip, and information to be updated, such as discount prices and special price information, may be recorded on the barcode. This is because, unlike an ID chip, a bar code can easily correct information.

  By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

  A case will be described in which an ID chip is mounted on a product such as a beer bottle for distribution management. As shown in FIG. 28A, an ID chip 2802 is mounted on a beer bottle. For example, the ID chip 2802 can be mounted using the label 2801.

  In the ID chip, basic items such as the date of manufacture, the place of manufacture, and the materials used are recorded. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as MROM. In addition, individual items such as the delivery destination and delivery date and time of each beer bottle are recorded in the ID chip. For example, as shown in FIG. 28B, when each beer bottle 2803 flows through the belt conveyor 2806 and passes through the writer device 2805, each delivery destination and delivery date and time are recorded on the ID chip 2807 built in the label 2804. be able to. Such individual items may be recorded using a rewritable and erasable memory such as EEROM.

  When product information purchased from a delivery destination is transmitted to the distribution management center through the network, based on this product information, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date and time. A system that records on a chip should be constructed.

  Since delivery is performed for each case, an ID chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

  By installing an ID chip in such a beverage product in which a plurality of delivery destinations can be recorded, the time required for manual input can be reduced, and input errors caused by the input can be reduced. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by mounting the ID chip, it is possible to carry out low-cost logistics management with few mistakes.

  Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced. Such application items may be recorded using a rewritable and erasable memory such as EEROM. By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

  In order to perform manufacturing management, a manufactured product on which an ID chip is mounted and a manufacturing apparatus (manufacturing robot) controlled based on information on the ID chip will be described.

  Currently, there are many scenes in which original products are produced. In such a case, production is performed on the production line based on the original information of the products. For example, in an automobile production line in which the paint color of a door can be freely selected, an IDF chip is mounted on a part of the automobile, and the coating apparatus is controlled based on information from the ID chip. And you can produce an original car. As a result of mounting the ID chip, it is not necessary to adjust the order of the cars to be put on the production line or the number having the same color in advance. For this reason, it is not necessary to set a program for controlling the painting apparatus to match the order and number of cars. That is, the manufacturing apparatus can operate individually based on the information of the ID chip mounted on the automobile.

  Thus, the ID chip can be used in various places. And the specific information regarding manufacture can be obtained from the information recorded on the ID chip, and the manufacturing apparatus can be controlled based on the information.

  Next, a mode in which an IC card using the ID chip of the present invention is used as electronic money will be described. FIG. 29 shows a state in which payment is performed using an IC card 2901. The IC card 2901 has the ID chip 2902 of the present invention. When the IC card 2901 is used, a register 2903 and a reader / writer 2904 are used. The ID chip 2902 holds information on the amount deposited in the IC card 2901, and the reader / writer 2904 can read the amount information without contact and transmit it to the register 2903. In the register 2903, it is confirmed that the amount deposited in the IC card 2901 is equal to or more than the amount to be settled, and settlement is performed. Then, information on the remaining amount after settlement is transmitted to the reader / writer 2904. The reader / writer 2904 can write the remaining amount information into the ID chip 2902 of the IC card 2901.

Note that a key 2905 for inputting a password or the like may be added to the reader / writer 2904 so that a third party can be prevented from making a settlement using the IC card 2901 without permission.
It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

  As described above, the application range of the present invention is extremely wide and can be applied as a solid recognition chip for any article. In addition, the present embodiment can be realized by using a configuration including any combination of the embodiment and Examples 1 to 10.

1 is a block diagram illustrating a configuration of a semiconductor device of the present invention. The block diagram which shows the structure of the conventional semiconductor device. The block diagram which shows the structure of the conventional semiconductor device. The figure which shows the outline | summary of RF tag system. The figure which shows the Example using a current mirror circuit. The figure which shows the structure of a fuse element. The figure which shows the Example using a comparator circuit. The figure which shows embodiment using a capacitive antifuse element. The figure which shows embodiment using a diode type | mold antifuse element. The figure which shows the Example of the antenna of this invention. The figure which shows the Example of the antenna of this invention. The figure which shows the example of the data memorize | stored in a memory circuit. The figure which shows the structure of a capacitive antifuse element. The figure which shows the structure of a diode type antifuse element. Process sectional drawing of this invention. Process sectional drawing of this invention. Process sectional drawing of this invention. The figure which shows the application example of this invention. The figure which shows arrangement | positioning of TFT in this invention. FIG. 6 is a diagram illustrating an example of a comparator circuit of the present invention. The figure which combined the semiconductor device and protective layer of this invention. Process sectional drawing of this invention. Process sectional drawing of this invention. Process sectional drawing of this invention. The figure which shows the bag using this invention. The figure which shows the certificate using this invention. The figure explaining the foodstuff management using this invention. The figure explaining the physical distribution management using this invention. The figure explaining IC card settlement using the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Antenna circuit 102 Voltage detection circuit 103 Current amplification circuit 104 Signal processing circuit 105 Fuse

Claims (20)

An antenna circuit, a voltage detection circuit, a current amplification circuit, a signal processing circuit, and a fuse having at least a first end and a second end;
The antenna circuit is electrically connected to the voltage detection circuit and electrically connected to a first end of the fuse;
The voltage detection circuit is connected to the current amplification circuit;
The current amplifier circuit is connected to the second end of the fuse;
The semiconductor device, wherein the signal processing circuit is connected to the second end of the fuse. 2. The semiconductor device according to claim 1, wherein the signal processing circuit includes a rectifier circuit and a modulation circuit. 3. The semiconductor device according to claim 1, wherein the voltage detection circuit includes a diode. The semiconductor device according to claim 1, wherein the voltage detection circuit includes a comparator. 5. The semiconductor device according to claim 1, wherein the current amplifying circuit includes a current mirror circuit. 6. 6. The semiconductor device according to claim 1, wherein the fuse element constituting the fuse is blown by passing an excessive current.

In claim 6,
The semiconductor device according to claim 1, wherein the fuse element is made of metal wiring. In claim 6,
A semiconductor device, wherein the fuse element is a semiconductor thin film. Has an antenna circuit, signal processing circuit and antifuse on the substrate,
An output of the antenna circuit is connected to the signal processing circuit and the antifuse. 10. The semiconductor device according to claim 9, wherein the signal processing circuit includes a rectifier circuit and a modulation circuit. 11. The semiconductor device according to claim 9, wherein the antifuse element included in the antifuse is an element that applies an excessive voltage to short-circuit the insulating film. In claim 11,
The antifuse element includes a pair of conductive layers and the insulating film sandwiched between the pair of conductive layers. 11. The antifuse element constituting the antifuse according to any one of claims 9 to 10, wherein the antifuse element is a diode, and an excessive voltage is applied to short-circuit the junction portion of the diode. A semiconductor device. In claim 13,
The antifuse element is the diode, and the diode has the junction. 15. The semiconductor device according to claim 1, wherein the signal processing circuit is formed on a glass substrate. 15. The semiconductor device according to claim 1, wherein the signal processing circuit is formed on a plastic substrate. 15. The semiconductor device according to claim 1, wherein the signal processing circuit is formed on a film-like insulator. 18. The semiconductor device according to claim 1, wherein the antenna circuit is provided above the signal processing circuit or above a part of the signal processing circuit. 19. The semiconductor device according to claim 1, wherein a signal input to the antenna circuit is a radio signal. 21. An IC card, IC tag, RFID, transponder, banknote, securities, passport, electronic device, bag, and clothing having the semiconductor device according to any one of claims 1 to 20.

Images