JP2006099845A - Semiconductor device and its data writing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set a threshold value voltage after writing almost equal to a voltage applied to a gate electrode during data writing when data is written in a MONOS element. <P>SOLUTION: A writing power source circuit 2 supplies a voltage Vg and a voltage Vpp higher than this to the gate electrode of a MONOS element to write data in a memory element 1 constituted of the MONOS element. In this case, when the threshold voltage Vth of the memory element 1 reaches the gate applied voltage Vg, a drain current Ids flowing to the memory element 1 stops flowing. A writing end detection circuit 3 detect the end of the data writing in the memory element 1 by detecting the stopped flowing of the drain current Ids during writing, and sends a stop signal S2 to the writing power source circuit 2. The writing power source circuit 2 receives the stop signal S2 to stop the supply of a voltage to the memory element 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a data writing method thereof, and more particularly to a so-called MONOS (metal-oxide film-nitride film-oxidation) having an ONO (oxide film-nitride film-oxide film) laminated film between a gate electrode and a semiconductor surface. The present invention relates to a semiconductor device having a (film-semiconductor) structure and a data writing method thereof.

  Conventionally, a nonvolatile semiconductor memory device capable of storing at least three values by controlling a threshold value according to a gate voltage, wherein a gate insulating film is formed on a semiconductor substrate by a first oxide film (O), nitrided A structure in which a film (N) and a second oxide film (O) are sequentially stacked, that is, a structure having a MONOS structure has been proposed (for example, see Patent Document 1). According to this proposal, when data is written, the gate voltage is set to 7V, 8V, or 9V for 1 millisecond, so that after the data is written, a verify operation is not performed, and then -1V and -0.3V, respectively. Alternatively, a threshold voltage of 0.5V is obtained.

Japanese Patent Laid-Open No. 9-74146

  However, as a result of investigations by the present inventors, it has been found that the semiconductor memory device disclosed in Patent Document 1 has the following problems. First, since the writing time is as short as 1 millisecond, a threshold voltage (hereinafter referred to as a threshold after writing) in which data has been written due to variations in the thickness of the first oxide film serving as a tunnel oxide film. Value voltage). Even though there is such a variation, the end timing of the write operation is only managed by time, so whether or not the threshold voltage has reached a desired value during the write operation. Cannot be judged.

  Therefore, in order to make the threshold voltage after writing become a desired value, it is necessary to perform a verify operation in the same manner as a normal memory element, although it is unnecessary in the above-mentioned Patent Document 1. It is thought that there is. Second, in order to increase the number of values, it is necessary to increase the tunnel probability to some extent, so that the tunnel oxide film needs to be thinned. However, if the tunnel oxide film is thinned, the data retention characteristics may be degraded.

  An object of the present invention is to provide a semiconductor device in which a threshold voltage after writing is equal to or substantially equal to a voltage applied to a gate electrode at the time of data writing in order to solve the above-described problems caused by the prior art. To do. It is another object of the present invention to provide a semiconductor device having high data retention characteristics even when multi-valued.

  It is another object of the present invention to provide a data writing method for a semiconductor device that can automatically set a threshold voltage after writing to a desired value. It is another object of the present invention to provide a data writing method for a semiconductor device which can be multi-valued without causing deterioration of data retention characteristics.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the first aspect of the present invention includes a tunnel oxide film stacked on a semiconductor layer between a source region and a drain region, and on the tunnel oxide film. A nitride film is stacked, a top oxide film is stacked on the nitride film, and a gate electrode is stacked on the top oxide film. The nitride film is supplied from the semiconductor layer via the tunnel oxide film. A memory element for storing data by accumulating hot electrons, and when writing data to the memory element, a threshold voltage of the memory element is equal to or substantially equal to a voltage applied to the gate electrode. And a power supply circuit for writing which performs a writing operation until they are equal to each other.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the write power supply circuit performs a write operation until the amount of drain current flowing through the memory element becomes zero or substantially zero. It is characterized by that.

  A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the amount of drain current flowing in the memory element of the power supply circuit for writing is 1 of the amount of drain current at the start of writing. The write operation is performed until it becomes less than / 2.

  According to a fourth aspect of the present invention, there is provided a semiconductor device according to the second or third aspect, further comprising: a write end detection circuit that stops a write operation of the write power supply circuit based on a current amount of the drain current. It is characterized by providing.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the write power supply circuit has two types of voltages applied to the gate electrode when data is written. It is characterized by generating the above different voltages.

  According to another aspect of the semiconductor device of the present invention, a tunnel oxide film is stacked on a semiconductor layer between a source region and a drain region, a nitride film is stacked on the tunnel oxide film, and the nitride film is formed on the nitride film. A top oxide film is stacked, a gate electrode is stacked on the top oxide film, and data is stored in the nitride film by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film. And a writing power supply circuit that performs a writing operation for 100 milliseconds or more when data is written to the memory element.

  According to a seventh aspect of the present invention, there is provided a semiconductor device according to the sixth aspect, wherein the write power supply circuit starts measuring time simultaneously with the start of data writing, and when a predetermined time of 100 milliseconds or more has elapsed. It is further characterized by further comprising time measuring means for stopping the writing operation.

  The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the sixth or seventh aspect, wherein the write power supply circuit applies two or more different voltages as voltages applied to the gate electrode when data is written. It is generated.

  According to another aspect of the semiconductor device of the present invention, a tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, and the nitride film is formed on the nitride film. A top oxide film is stacked, a gate electrode is stacked on the top oxide film, and data is stored in the nitride film by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film. In addition, the threshold voltage when data is written is equal to or substantially equal to the voltage applied to the gate electrode at the time of data writing, and data is written to the memory element. And detecting the stop level of the drain current flowing through the memory element and detecting the stop level of the drain current. Characterized in that it comprises a write end detecting circuit for stopping the writing of the.

  According to another aspect of the semiconductor device of the present invention, a tunnel oxide film is stacked on a semiconductor layer between a source region and a drain region, a nitride film is stacked on the tunnel oxide film, and the nitride film is formed on the nitride film. A top oxide film is stacked, a gate electrode is stacked on the top oxide film, and data is stored in the nitride film by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film. And a semiconductor device that realizes a different threshold voltage according to a voltage applied to the gate electrode at the time of data writing, wherein the threshold voltage in a state where data is written is It is characterized by being equal to or approximately equal to the voltage applied to the gate electrode.

  In the data writing method of the semiconductor device according to the invention of claim 11, a tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, A top oxide film is laminated on the nitride film, a gate electrode is laminated on the top oxide film, and hot electrons supplied from the semiconductor layer via the tunnel oxide film are accumulated in the nitride film. When writing data to the memory element that stores data, the write operation is performed until the threshold voltage of the memory element becomes equal to or substantially equal to the voltage applied to the gate electrode. .

  According to a twelfth aspect of the present invention, there is provided a data write method for a semiconductor device according to the eleventh aspect, wherein the write operation is performed until the amount of drain current flowing through the memory element becomes zero or almost zero. And

  According to a thirteenth aspect of the present invention, there is provided a data writing method for a semiconductor device according to the eleventh aspect, wherein the amount of drain current flowing through the memory element is less than or equal to ½ of the amount of drain current at the start of writing. The write operation is performed until

  According to a fourteenth aspect of the present invention, there is provided a data writing method for a semiconductor device according to any one of the eleventh to thirteenth aspects, wherein two or more types are applied to the gate electrode in accordance with data written to the memory element. Any one of the different voltages is applied.

  According to a fifteenth aspect of the present invention, there is provided a data writing method for a semiconductor device in which a tunnel oxide film is stacked on a semiconductor layer between a source region and a drain region, a nitride film is stacked on the tunnel oxide film, A top oxide film is laminated on the nitride film, a gate electrode is laminated on the top oxide film, and hot electrons supplied from the semiconductor layer via the tunnel oxide film are accumulated in the nitride film. When writing data to a memory element that stores data, the writing operation is performed for 100 milliseconds or more.

  According to a sixteenth aspect of the present invention, there is provided a data writing method for a semiconductor device according to the fifteenth aspect of the present invention, in which one of two or more different voltages is applied to the gate electrode in accordance with data written to the memory element. It is characterized by applying these.

  According to the invention of claim 1, 10 or 11, by setting the data write time sufficiently long, hot electrons are accumulated in the nitride film in the gate insulating film during the data write, When the threshold voltage rises and eventually becomes saturated and reaches the voltage applied to the gate electrode at the time of writing (hereinafter referred to as the gate applied voltage at the time of writing), the channel current does not flow in the channel. Thereby, the generation of hot electrons due to impact ionization is stopped, and the data writing is automatically terminated.

  At this time, even if the thickness of the tunnel oxide film varies, the threshold voltage after writing is equal to or substantially equal to the gate applied voltage at the time of writing, so that variation in threshold voltage after writing is small. Become. In addition, since it is not necessary to confirm whether or not the threshold voltage after writing is a desired value, the verify operation is not necessary. Furthermore, even if the tunnel oxide film in the gate insulating film is thick, the threshold voltage after writing is equal to or almost equal to the gate applied voltage at the time of writing. Can be improved.

  According to the second or twelfth aspect of the present invention, when the threshold voltage is saturated and reaches the gate applied voltage at the time of writing and the channel current does not flow in the channel, the amount of drain current becomes zero. By monitoring the current, it can be determined whether a desired threshold voltage has been reached. When the monitored drain current amount is zero or almost zero, the threshold voltage becomes a desired value.

  According to the third or thirteenth aspect of the present invention, when the amount of drain current becomes ½ or less of the amount of drain current at the start of writing, the threshold voltage is almost saturated and the gate application at the time of writing is approximately Since it becomes equal to the voltage, it is possible to determine whether or not the desired threshold voltage has been substantially reached by monitoring the drain current. When the monitored drain current amount is ½ or less of the write start time, the threshold voltage becomes approximately a desired value.

  According to the invention of claim 4, the drain current is monitored by the write end detection circuit, and when the drain current amount is zero or almost zero, or when the drain current amount is ½ or less of the write start time. Then, a stop signal can be sent to the write power supply circuit to stop the write operation of the write power supply circuit. According to the invention of claim 5, 8, 14 or 16, the gate application voltage at the time of writing is two or more different voltages, so that multi-value can be achieved. At this time, since the threshold voltage after writing is equal to or substantially equal to the gate applied voltage at the time of writing, the margin between the multi-value threshold voltages is expanded.

  According to the invention of claim 6 or 15, if the data writing time is 100 milliseconds or more, the threshold voltage after writing is equal to or substantially equal to the gate applied voltage at the time of writing. Therefore, even if the thickness of the tunnel oxide film varies, the variation in threshold voltage after writing becomes small. In addition, since it is not necessary to confirm whether or not the threshold voltage after writing is a desired value, the verify operation is not necessary. Furthermore, even if the tunnel oxide film in the gate insulating film is thick, the threshold voltage after writing is equal to or almost equal to the gate applied voltage at the time of writing. Can be improved.

  According to the seventh aspect of the present invention, when a predetermined time of 100 milliseconds or more has elapsed from the start of writing, the time measuring means sends a stop signal to the writing power supply circuit to stop the writing operation of the writing power supply circuit. be able to. According to the ninth aspect of the present invention, when the amount of drain current reaches a predetermined stop level, the threshold voltage is saturated and becomes equal to the gate applied voltage at the time of writing, or is almost saturated and is approximately at the time of writing. Since it becomes equal to the gate applied voltage, it is possible to determine whether or not the desired threshold voltage or almost the desired threshold voltage has been reached by monitoring the drain current. When the monitored drain current amount reaches a predetermined stop level, the threshold voltage becomes a desired value or approximately a desired value.

  According to the semiconductor device of the present invention, it is possible to obtain a semiconductor device in which the threshold voltage after writing is equal to or substantially equal to the gate applied voltage at the time of writing, and high data retention characteristics even when multi-valued. There is an effect that a semiconductor device can be obtained. In addition, according to the data writing method of the semiconductor device according to the present invention, the threshold voltage after writing can be automatically set to a desired value, and without causing deterioration in data retention characteristics. There is an effect that it can be multi-valued.

  Exemplary embodiments of a semiconductor device and a data writing method thereof according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and description thereof is omitted.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an overall configuration of the semiconductor device according to the first embodiment. As shown in FIG. 1, the first embodiment includes a memory element 1, a write power supply circuit 2, a write end detection circuit 3, and a data output circuit 4. The memory element 1 has a MONOS structure. The write power supply circuit 2 supplies a voltage for writing data to the memory element 1, for example, a gate applied voltage Vg at the time of writing and a voltage Vpp higher than that, which will be described later, based on a write start signal S1 supplied from the outside. Then, a data write operation to the memory element 1 is performed. Further, when the write power supply circuit 2 receives the stop signal S2 from the write end detection circuit 3, the write power supply circuit 2 stops the supply of the gate applied voltage Vg and the high voltage Vpp to the memory element 1.

  The write end detection circuit 3 detects the drain current Ids flowing through the memory element 1 when writing data, and the drain current Ids is a predetermined stop level, for example, zero or almost zero, or less than 1/2 of the current amount at the start of writing. Thus, it is detected that the writing of data to the memory element 1 is completed. The write end detection circuit 3 sends a stop signal S2 to the write power supply circuit 2 when detecting the end of data writing. The data output circuit 4 detects the drain current Ids flowing through the memory element 1 when reading data, and outputs a data read signal S3 to the outside.

  FIG. 2 is a circuit diagram showing a configuration of a main part of the semiconductor device according to the first embodiment. As shown in FIG. 2, the drain of a memory element (hereinafter referred to as a MONOS element) 11 having a MONOS structure is connected to the drain of a read p-channel MOS transistor (hereinafter referred to as a read PMOS) 12 and the write p. It is connected to the drain of a channel MOS transistor (hereinafter referred to as a writing PMOS) 13. The read PMOS 12 and the write PMOS 13 have different channel lengths and channel widths, and the on-resistance of the read PMOS 12 is higher than the on-resistance of the write PMOS 13. That is, the read PMOS 12 has a characteristic that current is less likely to flow than the write PMOS 13. The source of the MONOS element 11 is connected to the drain of an n-channel MOS transistor (hereinafter referred to as NMOS) 14. The MONOS element 11 constitutes the memory element 1.

  The source and bulk of the read PMOS 12 and the source and bulk of the write PMOS 13 are connected to the positive power supply line 17. The source and bulk of the NMOS 14 and the bulk of the MONOS element 11 are connected to the negative power supply line 18. A connection node N 1 between the MONOS element 11 and the read PMOS 12 is connected to an input terminal of the first inverter 15. The first inverter 15 has the function of the data output circuit 4 and outputs a data read signal S3 from its output terminal OUT1.

  A connection node N2 between the MONOS element 11 and the NMOS 14 is connected to the input terminal of the second inverter 16. The second inverter 16 has the function of the write end detection circuit 3 and outputs a stop signal S2 from its output terminal OUT2. For the gate electrode MG of the MONOS element 11, the gate electrode PG1 of the read PMOS 12, the gate electrode PG2 of the write PMOS 13, and the gate electrode NG of the NMOS 14, there are operation modes such as a standby mode, a data write mode, a data read mode, and a data erase mode. Accordingly, a voltage is appropriately applied by a writing power supply circuit 2 (not shown) (see FIG. 1) or the like. Further, the voltage VDD of the positive power supply line 17 and the voltage VSS of the negative power supply line 18 are also appropriately changed according to the operation mode.

  Here, before describing the operation of the semiconductor device of the first embodiment, the characteristics of the MONOS element will be considered with reference to FIGS. FIG. 3 is a characteristic diagram showing the relationship between the threshold voltage Vth and the time for applying the data write voltage (write time) when data is written to the MONOS element. Is a logarithm of the horizontal axis of FIG. In FIGS. 3 and 4, the voltage application time on the horizontal axis was measured by repeatedly measuring the threshold voltage Vth at each measurement time during data writing and then writing data again. Represents the integrated value of the time when the data was written.

In examining the characteristics shown in FIGS. 3 and 4, a MONOS element having the dimensions and concentrations described below was used. The concentration of the p-type well formed in the semiconductor substrate was 1.00 × 10 ¹⁸ cm ⁻³ . The channel width and channel length were 10 μm and 1.0 μm, respectively. The concentration of the n-type LDD (lightly doped drain) region in contact with the channel region was 3.30 × 10 ¹⁹ cm ⁻³ . The thicknesses of the tunnel oxide film, the nitride film, and the top oxide film of the gate insulating film were 34.1 angstrom, 64.0 angstrom, and 35.6 angstrom, respectively.

  Three MONOS elements having the above dimensions and concentrations were prepared, and the gate application voltage Vg at the time of writing was set to 5V (referred to as sample 1), 6V (referred to as sample 2), and 7V (referred to as sample 3). . In Samples 1 to 3, the voltage applied to the drain electrode at the time of writing (hereinafter referred to as the drain applied voltage at the time of writing) was 7V. 3 and 4, in any of samples 1 to 3, the threshold voltage Vth increases rapidly until the data writing time reaches 100 milliseconds, but is almost saturated when the time exceeds 100 milliseconds. You can see that That is, in the MONOS element, when data is written in a writing time of 100 milliseconds or more, the threshold voltage Vth after writing becomes a substantially constant value. Note that the data write time in a general application of the MONOS element is 1 millisecond or less, and the threshold voltage Vth is in a region where it rapidly increases.

  FIG. 5 is a characteristic diagram showing the relationship between the threshold voltage Vth after writing and the gate applied voltage Vg at the time of writing when data is written with a sufficiently long writing time for the MONOS element. is there. In examining the characteristics shown in FIG. 5, four MONOS elements (referred to as Sample 4, Sample 5, Sample 6, and Sample 7) having the dimensions and concentrations described below were used. The concentration of the p-type well, the channel width and the channel length of these four MONOS elements, and the thicknesses of the tunnel oxide film, nitride film, and top oxide film of the gate insulating film were the same as those of the sample 1 respectively. .

The concentration of the n-type LDD region is 4.62 × 10 ¹⁸ cm ⁻³ in sample 4, 1.98 × 10 ¹⁹ cm ⁻³ in sample 5, 3.30 × 10 ¹⁹ cm ⁻³ in sample 6, and sample 7 Then, it was 6.60 × 10 ¹⁹ cm ⁻³ . In Samples 4 to 7, the drain applied voltage at the time of writing was 9 V, and the writing time was 100 milliseconds.

  As shown in FIG. 5, in any of samples 4 to 7, when data is written by applying a voltage of 3 V or more to the gate electrode, is the threshold voltage Vth after writing equal to the gate applied voltage Vg at the time of writing? It can be seen that they are almost equal. This can also be seen from FIG. Specifically, as apparent from FIGS. 3 and 5, the threshold voltage Vth after writing is a value that falls within the range of ± 0.5 V of the gate applied voltage Vg at the time of writing.

  FIG. 6 shows the relationship between the threshold voltage variation ΔVth after writing and the drain applied voltage Vd at the time of writing when data is written with a sufficiently long writing time for the MONOS element. FIG. The change amount ΔVth of the threshold voltage after writing is a difference between the threshold voltage Vth (writeVth) after writing and the initial threshold voltage Vth (asVth). In examining the characteristics shown in FIG. 6, the samples 4 to 7 described above were used. The gate application voltage Vg at the time of writing was 9 V, and the writing time was 100 milliseconds.

  As can be seen from FIG. 6, data writing does not occur in any of samples 4 to 7 unless the drain application voltage Vd is equal to or higher than a certain value. In the example shown in FIG. 6, when the drain application voltage Vd becomes 4.5 V or more (shown by a broken line in the center of FIG. 6), impact ionization occurs, hot electrons are generated, and a data write state is entered.

  FIG. 7 is a characteristic diagram showing the relationship between the drain current Ids at the time of writing and the writing time when data is written to the MONOS element. In examining the characteristics shown in FIG. 7, the respective concentrations of the p-type well and the n-type LDD region, the channel width and the channel length, and the thicknesses of the nitride film and the top oxide film of the gate insulating film were determined as the sample 1. The MONOS element (referred to as sample 8) in which the thickness of the tunnel oxide film of the gate insulating film is 27.3 angstroms was used.

  The gate applied voltage Vg at the time of writing and the drain applied voltage at the time of writing were both set to 7V. As can be seen from FIG. 7, the drain current Ids sharply decreases with the start of data writing. The drain current Ids rapidly decreases until the current amount becomes 1/2 of the current amount at the start of writing, and almost no longer flows thereafter. At this time, the threshold voltage Vth (initial value) before writing data was 1.625V, whereas the threshold voltage Vth after writing was 7.003V.

  FIG. 8 is a characteristic diagram showing the relationship between the writing time, the threshold voltage Vth after writing, and the gate applied voltage Vg during writing when data is written to the MONOS element. In examining the characteristics shown in FIG. 8, except that the thickness of the MONOS element (referred to as sample 9) having the same size and concentration as the sample 8 and the tunnel oxide film of the gate insulating film is 34.1 angstroms. A MONOS element (referred to as Sample 10) having the same dimensions and concentration as Sample 9 was used. In Samples 9 and 10, the drain applied voltage at the time of writing was 7 V, and the writing time was 1 second. For comparison, data was written to Sample 9 and Sample 10 at a drain applied voltage of 7 V and a writing time of 1 millisecond.

  Since the thickness of the tunnel oxide film of the gate insulating film is different between the sample 9 and the sample 10, the threshold voltage Vth (initial value) before data writing of the sample 9 is 1.1 V, whereas the sample 9 The threshold voltage Vth (initial value) before 10 data writing was 2.1V. However, FIG. 8 shows that when the writing time is sufficiently long as 1 second, the threshold voltage Vth after writing is almost equal to the gate applied voltage Vg at the time of writing in both the samples 9 and 10.

  That is, even when the thickness of the tunnel oxide film is varied during the manufacture of the MONOS element, and the initial value of the threshold voltage Vth is thereby different, the threshold value after writing is increased by sufficiently increasing the writing time. The voltage Vth has a similar value (a value within a range of ± 0.5 V of the gate application voltage Vg at the time of writing). On the other hand, when the writing time is 1 millisecond, a difference occurs in the threshold voltage Vth after writing because the initial value of the threshold voltage Vth is different.

  As discussed above, in the MONOS element, when the data writing time becomes sufficiently long, the drain current Ids does not flow or hardly flows, and the threshold voltage Vth after writing is the gate applied voltage Vg at the time of writing. Is equal to or nearly equal to This is because, in the MONOS element, hot electrons generated by impact ionization are stored in the nitride film through the tunnel oxide film of the gate insulating film, but the threshold voltage Vth is reduced by writing. This is because, when the gate applied voltage Vg is increased, the channel current stops flowing in the channel, and the generation of hot electrons due to impact ionization is stopped.

  Accordingly, data writing to the MONOS element automatically stops. That is, the data writing is completed in a self-control manner by sufficiently increasing the data writing time. Based on the above considerations, in the first embodiment, when writing data to the MONOS element, the writing time is made sufficiently long, whereby the threshold voltage Vth after writing is set to the gate applied voltage Vg at writing. It is characterized by being equal or approximately equal.

  Next, the operation of the semiconductor device having the configuration shown in FIG. 2 will be described. In the following description of the operation, the semiconductor device is not particularly limited. For example, the semiconductor device is driven by a negative power source having the positive power line 17 as a ground potential and the negative power line 18 as a negative potential. To do. Although not particularly limited, for example, a relatively high level voltage (hereinafter referred to as H level voltage) is set to 0.0 V, and a relatively low level voltage (hereinafter referred to as L level voltage) is set. -1.5V. For example, the high voltage Vpp is set to −9.0V, and the voltage applied to the gate electrode MG of the MONOS element 11 (gate applied voltage Vg) is set to a voltage in the range of 0 to −9.0V.

  In the standby mode, an H level voltage is applied to the gate electrode PG1 of the read PMOS 12 and the gate electrode PG2 of the write PMOS 13. An L level voltage is applied to the gate electrode MG of the MONOS element 11 and the gate electrode NG of the NMOS 14. Further, the voltage VDD of the positive power supply line 17 is an H level voltage. The voltage VSS of the negative power supply line 18 is an L level voltage. Accordingly, in the standby mode, the MONOS element 11, the read PMOS 12, the write PMOS 13 and the NMOS 14 are all in an off state.

  In the data write mode, an H level voltage is applied to the gate electrode PG1 of the read PMOS 12 and the gate electrode NG of the NMOS. A high voltage Vpp is applied to the gate electrode PG2 of the write PMOS 13. A gate application voltage Vg is applied to the gate electrode MG of the MONOS element 11. The voltage VDD of the positive power supply line 17 is an H level voltage. The voltage VSS of the negative power supply line 18 becomes the high voltage Vpp. At this time, the reading PMOS 12 is in an off state. The writing PMOS 13 and NMOS 14 are turned on.

  After the start of data writing, the drain current Ids flows through the MONOS element 11 until the threshold voltage Vth of the MONOS element 11 reaches the gate applied voltage Vg. Accordingly, a connection node (hereinafter referred to as a first connection node) N1 between the MONOS element 11 and the read PMOS 12 and a connection node (hereinafter referred to as a second connection node) N2 between the MONOS element 11 and the NMOS 14 Are both at the H level. Accordingly, the voltages at the output terminal OUT1 of the first inverter 15 and the output terminal OUT2 of the second inverter 16 are both at the L level.

  When data writing proceeds and the threshold voltage Vth of the MONOS element 11 reaches the gate applied voltage Vg, the drain current Ids does not flow through the MONOS element 11. Thereby, the voltage of the second connection node N2 is switched from the H level to the L level. Accordingly, the voltage at the output terminal OUT2 of the second inverter 16 is switched from the L level to the H level. That is, the potential of the stop signal S2 output from the second inverter 16 is switched, and the end of data writing is detected.

  Based on the switching of the potential of the stop signal S2, the voltage supply from the write power supply circuit 2 is stopped, and the write operation is stopped. On the other hand, since the first connection node N1 remains at the H level even when the MONOS element 11 is turned off, the voltage at the output terminal OUT1 of the first inverter 15 remains at the L level.

  In the data read mode, an L level voltage is applied to the gate electrode PG1 of the read PMOS 12 and the gate electrode MG of the MONOS element 11. An H level voltage is applied to the gate electrode PG2 of the write PMOS 13 and the gate electrode NG of the NMOS 14. The voltage VDD of the positive power supply line 17 is an H level voltage. The voltage VSS of the negative power supply line 18 is an L level voltage. At this time, the read PMOS 12 and the NMOS 14 are in the on state. The writing PMOS 13 is turned off.

  When no data is written in the MONOS element 11 or when data is erased, the drain current Ids flows through the MONOS element 11. As a result, the voltages of the first connection node N1 and the second connection node N2 both become L level. Therefore, the voltages at the output terminal OUT1 of the first inverter 15 and the output terminal OUT2 of the second inverter 16 are both at the H level. On the other hand, when data is written in the MONOS element 11, the drain current Ids does not flow through the MONOS element 11.

  Therefore, the voltage at the first connection node N1 is at the H level, and the voltage at the output terminal OUT1 of the first inverter 15 is at the L level. That is, the voltage of the data read signal S3 is L level when data is written in the MONOS element 11, and is H level when data is not written or erased. This means that the data (memory state) of the MONOS element 11 has been read. On the other hand, since the second connection node N2 remains at the L level voltage even when data is not written in or erased from the MONOS element 11, the voltage at the output terminal OUT2 of the second inverter 16 is It remains at the H level.

  In the data erasing mode, an L level voltage is applied to the gate electrode PG1 of the read PMOS 12 and the gate electrode PG2 of the write PMOS 13. A high voltage Vpp is applied to the gate electrode MG of the MONOS element 11. An H level voltage is applied to the gate electrode NG of the NMOS 14. The voltage VDD of the positive power supply line 17 and the voltage VSS of the negative power supply line 18 are H level voltages. Thereby, in the MONOS element 11, the high voltage Vpp (negative high voltage) is applied to the gate electrode MG in a state where the H level voltage is applied to the source, drain and bulk, so that the data is erased. The

  According to the first embodiment, by setting the data writing time to the MONOS element 11 sufficiently long, the threshold voltage Vth of the MONOS element 11 becomes equal to the gate applied voltage Vg, and data writing is automatically performed. End automatically. Therefore, even if the thickness of the tunnel oxide film of the MONOS element 11 varies, the threshold voltage Vth after writing hardly varies. Therefore, multi-value can be achieved by setting two or more different voltages as the gate application voltage Vg at the time of writing. In the case of multi-value, the margin between multi-value threshold voltages is expanded. Also, the verify operation is not necessary. Further, the data retention characteristics can be improved by increasing the thickness of the tunnel oxide film. Further, by monitoring the drain current during data writing, it is possible to determine whether or not the threshold voltage Vth has reached a desired value, that is, the gate applied voltage Vg.

Embodiment 2. FIG.
FIG. 9 is a block diagram showing an overall configuration of the semiconductor device of the second embodiment. As shown in FIG. 9, the second embodiment has a timing means 5 instead of the write end detection circuit 3, and the timing means 5 outputs a stop signal S 2 to the power supply circuit 2 for writing. . Other configurations are the same as those shown in FIG. 1 of the first embodiment. The time measuring means 5 is constituted by a counter, for example. For example, the counter starts counting after being reset by the input of the write start signal S1, and outputs a stop signal S2 when a preset count number, that is, time is reached. The preset count number (time) is not particularly limited, but for example, from the characteristic diagram of FIG. 4, a value corresponding to 100 milliseconds or more is appropriate. According to the second embodiment, the same effect as in the first embodiment can be obtained.

Embodiment 3 FIG.
FIG. 10 is a circuit diagram showing the overall configuration of the semiconductor device of the third embodiment. As shown in FIG. 10, in the third embodiment, a circuit for detecting fluctuations in the power supply voltage is configured by using a plurality (three in the illustrated example) of MONOS elements 21, 31, and 41. The connection relationship between the read PMOS 12 and the write PMOS 13 between the positive power supply line 17 and the first connection node N1 is the same as the configuration of the first embodiment (FIG. 2). The drains of the three MONOS elements 21, 31, 41 are all connected to the first connection node N1.

  Between the first connection node N1 and the negative power line 18, the connection relationship between the first MONOS element 21 and the first NMOS 24, the connection relationship between the second MONOS element 31 and the second NMOS 34, The connection relationship between the third MONOS element 41 and the third NMOS 44 is the same as the connection relationship between the MONOS element 11 and the NMOS 14 in the first embodiment (FIG. 2). As in the first embodiment (FIG. 2), the first inverter 15 is connected to the first connection node N1.

  As described in the first embodiment with reference to the characteristic diagram of FIG. 6, in order to write data to the MONOS element, it is necessary to apply a voltage higher than a certain value to the drain electrode of the MONOS element. Therefore, in the configuration shown in FIG. 10, first, a voltage sufficient for writing is applied to each drain electrode of the first, second, and third MONOS elements 21, 31, 41, and the gate of the first MONOS element 21. For example, 3.5 V, 3.2 V, and 3.0 V are applied to the electrode MG1, the gate electrode MG2 of the second MONOS element 31, and the gate electrode MG3 of the third MONOS element 41, respectively. Data is written under the condition that the threshold voltage Vth after writing is equal to the gate applied voltage Vg at the time of writing.

  Thereby, the threshold voltages Vth after writing of the first MONOS element 21, the second MONOS element 31, and the third MONOS element 41 become 3.5V, 3.2V, and 3.0V, respectively. In this state, the data reading mode described in the first embodiment is set, and the gate electrode MG1 of the first MONOS element 21, the gate electrode NG1 of the first NMOS 24, the gate electrode MG2 of the second MONOS element 31, and the second A power supply voltage (setting value: 3.5 V) is sequentially applied to the gate electrode NG2 of the NMOS 34, the gate electrode MG3 of the third MONOS element 41, and the gate electrode NG3 of the third NMOS 44.

  If the power supply voltage is higher than 3.5 V, the power supply voltage is applied to any one of the gate electrode MG1 of the first MONOS element 21, the gate electrode MG2 of the second MONOS element 31, and the gate electrode MG3 of the third MONOS element 41. Even if the voltage is applied, the output terminal OUT1 of the first inverter 15 becomes an H level voltage. Therefore, it can be seen that the power supply voltage is higher than 3.5V. If the power supply voltage is between 3.2 and 3.5 V, when the power supply voltage is applied to the gate electrode MG1 of the first MONOS element 21, the output terminal OUT1 of the first inverter 15 is at the L level voltage. It becomes.

  When a power supply voltage of 3.2 to 3.5 V is applied to the gate electrode MG2 of the second MONOS element 31 and the gate electrode MG3 of the third MONOS element 41, the output terminal OUT1 of the first inverter 15 is at the H level. Voltage. Therefore, it can be seen that the power supply voltage is 3.2 to 3.5V. If the power supply voltage is between 3.0 and 3.2 V, when the power supply voltage is applied to the gate electrode MG1 of the first MONOS element 21 and the gate electrode MG2 of the second MONOS element 31, the first inverter The 15 output terminals OUT1 are at L level voltage.

  When a power supply voltage of 3.0 to 3.2 V is applied to the gate electrode MG3 of the third MONOS element 41, the output terminal OUT1 of the first inverter 15 becomes an H level voltage. Therefore, it can be seen that the power supply voltage is 3.0 to 3.2V. As described above, according to the third embodiment, the fluctuation of the power supply voltage can be known by comparing the threshold voltage Vth after the writing of each MONOS element 21, 31, 41 with the power supply voltage. The set value of the power supply voltage is not limited to 3.5 V as long as the voltage is within a range in which no writing occurs in the MONOS element when data is read from the MONOS element. Further, the threshold voltage Vth after writing in each MONOS element is appropriately selected according to the value of the power supply voltage.

Embodiment 4 FIG.
FIG. 11 is a circuit diagram showing the overall configuration of the semiconductor device of the fourth embodiment. As shown in FIG. 1, in the fourth embodiment, a reference voltage generation circuit is configured by using a MONOS element 51. The drain of the MONOS element 51 is connected to one end of the resistor 59. The other end of the resistor 59 is connected to the positive power supply line 17. The source and bulk of the MONOS element 51 are connected to the negative power supply line 18.

  As described in the first embodiment with reference to the characteristic diagram of FIG. 6, in order to write data to the MONOS element, it is necessary to apply a voltage higher than a certain value to the drain electrode of the MONOS element. Therefore, in the configuration shown in FIG. 11, first, a voltage sufficient for writing is applied to the drain electrode of the MONOS element 51, and a voltage Vg that provides a desired reference voltage is applied to the gate electrode MG of the MONOS element 51. . Data is written under the condition that the threshold voltage Vth after writing is equal to the gate applied voltage Vg at the time of writing.

  Thereby, the threshold voltage Vth after writing in the MONOS element 51 becomes a desired reference voltage. In this state, the MONOS element 51 and the resistor 59 are applied to the gate electrode MG of the MONOS element 51 by applying a power supply voltage that is higher than the threshold voltage Vth after writing and within a voltage range in which writing does not occur. The output voltage Vout of the connection node N3 becomes the reference voltage. Thus, according to the fourth embodiment, the reference voltage can be generated.

  Even when the data retention characteristics are improved by increasing the thickness of the tunnel oxide film, by writing data for a sufficiently long time, the threshold voltage Vth after writing becomes the gate applied voltage Vg at the time of writing. Will be equal. Therefore, by increasing the thickness of the tunnel oxide film, it is possible to reduce the amount of fluctuation when the threshold voltage Vth after writing varies with time. In addition, by periodically writing to the gate electrode MG of the MONOS element 51 by applying a voltage Vg that becomes a desired reference voltage, the amount of variation in the threshold voltage Vth after writing is reduced. Can do.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the configuration of the write end detection circuit 3 is not limited to the configuration of the first embodiment. The numerical values such as various dimensions, concentrations, and voltages described above are examples, and the present invention is not limited thereto.

  As described above, the semiconductor device and the data writing method thereof according to the present invention are useful for a semiconductor device using a MONOS element. For example, a power supply voltage incorporated in a watch, a mobile phone, a small electronic device, or the like. It is suitable for a device that detects fluctuations in voltage and a device that generates a reference voltage.

1 is a block diagram showing an overall configuration of a semiconductor device according to a first embodiment. 3 is a circuit diagram showing a configuration of a main part of the semiconductor device of the first embodiment. FIG. It is a characteristic view showing the relationship between the threshold voltage of the MONOS element and the voltage application time at the time of data writing. It is a characteristic view showing the relationship between the threshold voltage of the MONOS element and the voltage application time (logarithm display) at the time of data writing. It is a characteristic view showing the relationship between the threshold voltage after writing of the MONOS element and the gate applied voltage at the time of writing. It is a characteristic view showing the relationship between the amount of change of the threshold voltage after writing of the MONOS element and the drain applied voltage at the time of writing. It is a characteristic view showing the relationship between the drain current and the writing time at the time of writing of the MONOS element. It is a characteristic view showing the relationship between the writing time of the MONOS element, the threshold voltage after writing, and the gate applied voltage at the time of writing. FIG. 6 is a block diagram showing an overall configuration of a semiconductor device according to a second embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 10 is a circuit diagram showing a configuration of a semiconductor device according to a fourth embodiment.

Explanation of symbols

MG, MG1, MG2, MG3 Gate electrode 1, 11, 21, 31, 41, 51 Memory element 2 Power supply circuit for writing 3 Write end detection circuit 5 Timekeeping means

Claims (16)

A tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, a top oxide film is stacked on the nitride film, and a top oxide film is stacked on the top oxide film. A gate electrode, and a memory element that stores data by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film in the nitride film;
A power supply circuit for writing that performs a write operation until a threshold voltage of the memory element is equal to or substantially equal to a voltage applied to the gate electrode when data is written to the memory element;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the write power supply circuit performs a write operation until the amount of drain current flowing through the memory element becomes zero or substantially zero.   The write power supply circuit performs a write operation until a current amount of a drain current flowing through the memory element is equal to or less than a half of a current amount of a drain current at the start of writing. The semiconductor device described.   4. The semiconductor device according to claim 2, further comprising a write end detection circuit that stops a write operation of the write power supply circuit based on a current amount of the drain current.   5. The semiconductor device according to claim 1, wherein the write power supply circuit generates two or more different voltages as a voltage to be applied to the gate electrode when writing data. 6. . A tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, a top oxide film is stacked on the nitride film, and a top oxide film is stacked on the top oxide film. A gate electrode, and a memory element that stores data by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film in the nitride film;
A power supply circuit for writing that performs a writing operation for 100 milliseconds or more when data is written to the memory element;
A semiconductor device comprising:   7. The clocking device according to claim 6, further comprising timing means for starting timing simultaneously with the start of data writing and stopping the writing operation of the power supply circuit for writing when a predetermined time of 100 milliseconds or more has elapsed. A semiconductor device according to 1.   8. The semiconductor device according to claim 6, wherein the write power supply circuit generates two or more different voltages as voltages to be applied to the gate electrode when writing data. A tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, a top oxide film is stacked on the nitride film, and a top oxide film is stacked on the top oxide film. A gate electrode is stacked, data is stored by storing hot electrons supplied from the semiconductor layer via the tunnel oxide film in the nitride film, and data is written. A memory element having a threshold voltage equal to or substantially equal to a voltage applied to the gate electrode during data writing;
A write end detection circuit that detects a stop level of a drain current flowing through the memory element when data is written to the memory element, and that stops writing to the memory element when the stop level of the drain current is detected; ,
A semiconductor device comprising: A tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, a top oxide film is stacked on the nitride film, and a top oxide film is stacked on the top oxide film. A gate electrode is stacked, and data is stored in the nitride film by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film, and is applied to the gate electrode when data is written. A semiconductor device that realizes different threshold voltages depending on the voltage to be
A semiconductor device, wherein a threshold voltage in a state where data is written is equal to or substantially equal to a voltage applied to the gate electrode when data is written. A tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, a top oxide film is stacked on the nitride film, and a top oxide film is stacked on the top oxide film. When writing data to a memory element that stores data by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film, the gate electrode is stacked.
A data writing method for a semiconductor device, wherein a writing operation is performed until a threshold voltage of the memory element becomes equal to or substantially equal to a voltage applied to the gate electrode.   12. The method of writing data in a semiconductor device according to claim 11, wherein the write operation is performed until the amount of drain current flowing through the memory element becomes zero or substantially zero.   12. The data write of the semiconductor device according to claim 11, wherein the write operation is performed until the amount of drain current flowing through the memory element becomes ½ or less of the amount of drain current at the start of writing. Method.   14. The semiconductor device according to claim 11, wherein any one of two or more different voltages is applied to the gate electrode in accordance with data written to the memory element. Data writing method. A tunnel oxide film is stacked on the semiconductor layer between the source region and the drain region, a nitride film is stacked on the tunnel oxide film, a top oxide film is stacked on the nitride film, and a top oxide film is stacked on the top oxide film. When writing data to a memory element that stores data by accumulating hot electrons supplied from the semiconductor layer via the tunnel oxide film, the gate electrode is stacked.
A data writing method for a semiconductor device, wherein a writing operation is performed for 100 milliseconds or more. 16. The data writing method for a semiconductor device according to claim 15, wherein one of two or more different voltages is applied to the gate electrode in accordance with data written to the memory element.

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