JP2004186490A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device of a new structure capable of reducing the area of a peripheral circuit by simplifying it. <P>SOLUTION: In the structure of a flash memory, a high energy electron called DAHE is used for writing operation while a high energy hole called DAHH is used for erasing operation. A coupling ratio is adjusted so that the DAHE and DAHH are generated at a single kind of voltage value. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a charge storage type nonvolatile memory.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for example, a flash memory has been known as a type of non-volatile memory in which charges are stored in a floating gate. FIG. 10 shows a sectional view of a conventional flash memory. As shown in FIG. 10, the flash memory has a semiconductor substrate 62 in which an N-type well 61 and a P-type well 2 are formed on a P-type silicon substrate 1.
[0003]
On the semiconductor substrate 62, a tunnel film 63 composed of a silicon oxide film, a floating gate 5 composed of polysilicon, an interlayer insulating film 6 composed of an ONO film, and a control gate 7 are sequentially formed. Have been. Thus, a two-layer polysilicon gate electrode structure is formed on the surface of semiconductor substrate 3. Further, a side wall 8 made of a silicon oxide film is formed on the side wall of the two-layer polysilicon gate electrode structure.
[0004]
In the surface layer of the semiconductor substrate 3, on both sides of the two-layer polysilicon gate electrode structure, N ⁺ Mold source region 9 and N ⁺ Mold drain region 10 is formed. The P − type pocket layer 11 is formed around the drain region 10. In other words, the drain region 10 having a depth smaller than that of the pocket layer 11 is formed in the pocket layer 11.
[0005]
FIG. 11 shows an example of an operating voltage in a conventional flash memory, and FIGS. 12 and 13 show a memory cell array at the time of writing and erasing bias. In a general flash memory using CHE (Channel Hot Electron) for writing and FN (Fowler-Nordheim) tunnel current from the substrate for erasing, voltages required for writing and erasing are as shown in FIG. . Vcg, Vs, Vd, and Vb are voltage values applied to the control gate 7, the source region 9, the drain region 10, and the P-type well 2, respectively.
[0006]
At the time of writing, a high voltage is applied to the control gate 7 and then a voltage is applied between the drain region 10 and the source region 9. As a result, a current flows between the drain region 10 and the source region 9 to generate high-energy electrons called CHE, which are injected into the floating gate 5. In this case, it is necessary to apply two kinds of voltages, for example, 12V and 6V.
[0007]
This is for the following reasons. In order to generate CHE, it is necessary to apply voltages of the same magnitude to the floating gate 5 and the drain region 10. Since an interlayer insulating film 6 is formed between the floating gate 5 and the control gate 7, in order to apply a desired voltage to the floating gate 5, a voltage higher than the desired voltage is applied to the control gate 7. Must be applied. Therefore, at the time of writing, a higher voltage must be applied to the control gate 7 than to the drain region 10.
[0008]
At the time of erasing, a negative bias is applied to the control gate 7 and a positive bias is applied to the source region 9 and the substrate 3. As a result, electrons stored in the floating gate 5 pass through the gate insulating film 63 separating the floating gate 5 and the substrate 3 by FN tunneling. As a result, electrons are extracted from the floating gate 5 and return to the initial state. In this case, for example, it is necessary to apply two types of voltages, 16v and 8v.
[0009]
This is because a high potential difference needs to be generated between the floating gate 5, the source region 9, and the P-type well 2 in order to perform FN tunneling. For example, when the thickness of the gate insulating film 4 is 8.5 to 11 nm, the magnitude of the electric field applied to the tunnel film 63 needs to be 10 MV / cm. There is a need.
[0010]
Next, writing and erasing when cells are arranged in an array will be described. At the time of writing, as shown in FIG. 12, for a cell 13 to be written, 12 V is applied to a word line (Word line) 23 connected to the control gate 7, and a bit line (bit) connected to the drain region 10 is applied. Writing is performed by applying a voltage of 6 V to the line 32. Further, when writing is performed on the cell 14, after the writing on the cell 13 is completed, a voltage is applied to the word line 21 and the bit line 32 to perform the writing. On the other hand, at the time of erasing, as shown in FIG. 13, 8V is applied to the P-type well 2, -6V to the word lines 21 to 24, and 8V to the source region 9, thereby erasing all cells at once.
[0011]
As described above, Patent Document 1 discloses, for example, Patent Document 1 which describes that voltages of a plurality of magnitudes need to be applied during writing and erasing of a nonvolatile memory.
[0012]
[Patent Document 1]
Japanese Patent No. 2660734
[0013]
[Problems to be solved by the invention]
As described above, in the nonvolatile memory of the type in which charges are stored in the floating gate, a plurality of voltages are required for writing and erasing. For this reason, a booster circuit and a negative bias circuit are required as peripheral circuits for generating these voltages. These circuits are usually composed of a transistor having a higher breakdown voltage than that forming a logic gate, a capacitor having a relatively large capacity, and the like. Therefore, there is a problem that the area of the peripheral circuit increases, and the entire nonvolatile memory increases accordingly.
[0014]
In particular, in a non-volatile memory having a small memory capacity, the smaller the memory capacity, the larger the area occupied by the peripheral circuits in the entire nonvolatile memory. Therefore, since the peripheral circuit area is large, even if the memory capacity is reduced, the area of the entire device cannot be reduced.
[0015]
In view of the above, it is an object of the present invention to provide a nonvolatile semiconductor memory device having a new structure capable of reducing the area of a peripheral circuit by simplifying the peripheral circuit.
[0016]
[Means for Solving the Problems]
As described in the section of the prior art, in the conventional nonvolatile memory, in order to use the CHE phenomenon and the FN tunnel phenomenon for writing and erasing, a voltage having different magnitudes is applied to the control gate, the drain region, and the like. I had to. Therefore, the present inventors have proposed a drain avalanche hot electron (hereinafter abbreviated as DAHE) and a drain avalanche hot hole (Drain Avalanche hot hole) which are observed when the gate voltage is lower than the drain voltage. Focusing on the gate current due to Hot Hole (hereinafter abbreviated as DAHH), the following invention was created.
[0017]
In order to achieve the above object, in the invention according to claim 1, writing can be performed using drain avalanche hot electrons, erasing can be performed using drain avalanche hot holes, and at the time of writing and erasing. Is characterized in that the coupling ratio of the memory element is adjusted so that the magnitude of the applied voltage required for the memory element becomes one.
[0018]
In this manner, by setting the magnitude of the voltage required at the time of writing and erasing to one type, the peripheral circuit is simplified as compared with the case of performing writing and erasing using a plurality of types of voltages. can do. As a result, the peripheral circuit area can be reduced as compared with the case where writing and erasing are performed using a plurality of types of voltages.
[0019]
Specifically, the coupling ratio of the memory element is adjusted to satisfy, for example, the following three conditional expressions.
[0020]
{1} ｛(Cfc + Cfd) / (Cfc + Cfd + Cf + Cfs)｝ × Vw ≒ (１ ／) × Vw,
(2) {Cfd / (Cf + Cfs + Cfc + Cfd)} × Ve = (floating gate voltage at which DAHH occurs),
(3) Vw = Ve,
Here, Cfd is a coupling capacitance between the floating gate and the drain region, Cfc is a coupling capacitance between the floating gate and the control gate, Cfs is a coupling capacitance between the floating gate and the source region, and Cf is Vw is a voltage applied to the control gate and the drain region at the time of writing, and Ve is a voltage applied to the drain region at the time of erasing.
[0021]
According to the invention described in claim 2, the coupling capacitance between the floating gate (5) and the drain region (10) is such that writing is performed using drain avalanche hot electrons and erasing is performed using drain avalanche hot holes. It is characterized in that it is performed so that the magnitude of the applied voltage required for writing and erasing is one type.
[0022]
Generally, Cf and Cfc are largely restricted by conditions such as charge retention characteristics and rewriting time, and have a small degree of freedom in design. Therefore, as in the second embodiment, each of the other coupling capacitances is set so as to satisfy the conditions such as the charge retention characteristics and the rewriting time in the same manner as in a general nonvolatile semiconductor memory device. It is preferable to adjust the coupling capacitance Cfd between the first and second components.
[0023]
For example, the coupling capacitance between the floating gate (5) and the drain region (10) is adjusted by the overlap length (12) between the floating gate (5) and the drain region (10). can do.
[0024]
According to a fourth aspect of the present invention, there is provided a conductive film (51) formed on the floating gate (5) via an insulating film (6) and electrically connected to the drain region (10). The coupling capacitance between the floating gate (5) and the drain region (10) can be adjusted by the overlap length (52) of the floating gate (5) and the conductive film (51).
[0025]
In the case where the memory cells are arranged in an array, it is preferable to simultaneously write all the memory cells to be written among the memory cells connected to the same bit line.
[0026]
In addition, the code | symbol in the parenthesis of each said means shows the correspondence with the concrete means described in embodiment mentioned later.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a sectional view of a flash memory as a nonvolatile semiconductor memory device according to a first embodiment to which the present invention is applied. The same components as those of the flash memory shown in FIG. 10 are denoted by the same reference numerals.
[0028]
As shown in FIG. 1, the flash memory has a semiconductor substrate 3 in which a P-type well 2 is formed on a P-type silicon substrate 1. On the surface of the semiconductor substrate 3, a two-layer polysilicon gate electrode structure including a gate insulating film 4, a floating gate 5, an interlayer insulating film 6, and a control gate 7, and sidewalls 8 are formed.
[0029]
In the surface layer of the semiconductor substrate 3, N ⁺ Mold source region 9 and N ⁺ Formed drain region 10 and P-type pocket layer 11 are formed.
[0030]
In the present embodiment, when the semiconductor substrate 3 is viewed from above, the drain region 10 and the floating gate 5 partially overlap. Hereinafter, the length of the overlapping portion is referred to as an overlap length 12.
[0031]
In this flash memory, as described below, a high-energy electron called DAHE can be used in a write operation, a high-energy hole called DAHH can be used in an erase operation, and these DAHE and DAHH can be combined with one another. The overlap length 12 is adjusted so that various types of voltages can be generated by applying the voltages to the flash memory.
[0032]
Here, DAHE and DAHH will be described. As described in "Hot carrier effect", Eiji Takeda, Nikkei McGraw-Hill, p33, 34, JP-A-2000-306390, etc., a channel current flows due to a gate current caused by hot carrier gate injection. It is known that gate currents such as DAHH, DAHE, and CHE are observed from the lower gate voltage in the gate voltage region.
[0033]
Specifically, the gate current due to the injection of DAHE in the gate electrode (floating gate) becomes largest when the voltage value of the gate electrode is about 1/2 of the voltage value of the drain region. In the former document, it is described that the gate current due to the injection of DAHH in the gate electrode becomes maximum when the drain voltage and the gate voltage are, for example, about 7.0 V and about 1.8 V, respectively. .
[0034]
Therefore, in order to generate DAHE and DAHH in the flash memory, it is necessary to adjust the coupling ratio of the memory element as follows.
[0035]
{Circle around (1)} When the same write voltage Vw is applied to the control gate 7 and the drain region 10, the voltage applied to the floating gate 5 becomes approximately の of the voltage applied to the drain region 10; When the erase voltage Ve is applied to the drain region 10, the voltage applied to the floating gate 5 becomes a voltage at which DAHH is generated (the voltage at this time depends on the drain structure). (3) Vw = Ve It is becoming.
[0036]
These conditions are expressed by the following equations. The coupling capacitance between the floating gate 5 and the drain region 10 is Cfd; the coupling capacitance between the floating gate 5 and the control gate 7 is Cfc; the coupling capacitance between the floating gate 5 and the source region 9 is Cfs; When the voltage applied to the control gate 7 and the drain region 10 at the time of writing is Vw, and the voltage applied to the drain region 10 at the time of erasing is Ve,
{1} ｛(Cfc + Cfd) / (Cfc + Cfd + Cf + Cfs)｝ × Vw ≒ (１ ／) × Vw
{Circle around (2)} {Cfd / (Cf + Cfs + Cfc + Cfd)} × Ve = (floating gate voltage generated by DAHH)
(3) Vw = Ve
It becomes.
[0037]
Generally, Cf and Cfc are largely restricted by conditions such as charge retention characteristics and rewriting time, and have a small degree of freedom in design. For this reason, in the present embodiment, among the coupling ratios of the memory element, Cf, Cfc, and Cfs are set in the same manner as before so as to satisfy the conditions such as the charge retention characteristics and the rewriting time, and the drain region 10 and the floating gate 5 are set. The Cfd is adjusted by adjusting the overlap length 12 with. By adjusting Cfd in this way, the above three conditional expressions are satisfied.
[0038]
Next, the write and erase operations of the flash memory according to the present embodiment will be described.
[0039]
FIG. 2 shows an example of the operating voltage. As shown in FIG. 2, when writing is performed, a writing voltage of, for example, 6 V is applied to the drain region 10 and the control gate 7 in the cell where writing is performed. The source region 9 and the substrate 3 (well 2) are set to 0V. As a result, DAHE is generated in the channel region of the surface layer of the semiconductor substrate 3, and this DAHE is injected into the floating gate 5. Thus, writing is performed by injecting DAHE into the floating gate 5.
[0040]
When erasing is performed, 6 V is applied to the drain region 10 as in the case of writing. The control gate 7, the source region 9, and the substrate 3 are set to 0V. As a result, DAHH is generated in the channel region, and this DAHH is injected into the floating gate 5. In this manner, erasing is performed by setting the floating gate 5 into which electrons have been injected to a neutral state.
[0041]
Next, writing and erasing when a plurality of cells are arranged in an array will be described. 3 and 4 show diagrams when a plurality of cells are arranged in an array. 3 and 4 show examples of biases at the time of writing and erasing, respectively.
[0042]
As shown in FIGS. 3 and 4, the word lines 21 to 24 are connected to the control gate of each cell. The bit lines 31 to 34 are connected to the drain region of each cell.
[0043]
As shown in FIG. 3, for example, when writing is performed to the write cell 13 and the write cell 14, a voltage is applied to the word line 23, the word line 21, and the bit line 32. As described above, of the cells connected to the same bit line, a voltage is applied to all word lines of cells to be written and to this bit line. As a result, of the cells connected to the same bit line, writing is simultaneously performed on all cells to be written.
[0044]
As shown in FIG. 4, when erasing is performed, all word lines 21 to 24 are set to 0 V, and a voltage is applied to all bit lines 31 to 34. Thereby, all the cells are erased collectively.
[0045]
In the case of reading, 3 V is applied to the control gate and 1 V is applied to the drain region as in the conventional case. At this time, "1" and "0" are identified based on whether or not a current flows through the bit line.
[0046]
In the present embodiment, such writing is performed for the following reason. In the cell array according to the present embodiment, similarly to the conventional cell array, when a voltage of 6 V is applied to each of the word line 23 and the bit line 32 to the write cell 13, the write cell 13 is connected to the bit line 32 except the cell 13. Cell has the same bias condition as in the erase operation. Therefore, if writing is performed on the writing cell 14 after writing on the writing cell 13, there is a problem that the writing cell 13 is erased.
[0047]
Therefore, in the present embodiment, writing is performed collectively on cells connected to the same bit line.
[0048]
Further, in the conventional cell array, as shown in FIG. 12, when writing to the writing cell 14 is performed after writing to the writing cell 13, a voltage is applied to the drain region of the cell 13 connected to the same bit line as the cell 14. Is applied. Due to the voltage applied to the drain region, in the cells 13 connected to the same bit line, there is a possibility that the charge accumulated in the floating gate is drawn out (drain disturbance).
[0049]
On the other hand, in the present embodiment, in the cells connected to the same bit line, the write bias is applied to all the cells to be written, so that the occurrence of drain disturbance can be prevented.
[0050]
Further, in a conventional cell array, when a cell is in a depletion state (excessive erasure) even with one bit at the time of erasing, the threshold value of a cell connected to the same bit line cannot be read. For this reason, fine control of the voltage application at the time of erasure was indispensable so as not to generate an excessively erased cell.
[0051]
On the other hand, in the present embodiment, erasing is performed by injecting DAHH into the floating gate 5. As described in Japanese Patent Application Laid-Open No. 2000-306390, etc., in erasing using DAHE / DAHH, the potential of the floating gate is adjusted to a balanced state in a self-aligned manner by the voltage value applied to the drain region. it can. For this reason, even if an over-erased cell occurs during erasing, it can be relieved.
[0052]
For this reason, according to the present embodiment, it is not necessary to perform fine control or the like so as not to generate an excessively erased cell unlike the related art.
[0053]
In this embodiment, the write operation and the erase operation are separately described as shown in FIGS. 3 and 4, but the write operation and the erase operation can be performed simultaneously. As described above, in the writing operation, the erasing operation is performed on the non-written cells. Therefore, the rewriting operation can be performed by performing only the writing operation.
[0054]
As described above, in the non-volatile memory using CHE as the carrier injected into the floating gate 5, a CHE phenomenon occurs at the time of writing, so that a voltage higher than that of the drain region 10 is applied to the control gate 7. Need to be applied.
[0055]
On the other hand, in the present embodiment, DAHE is used for the write operation instead of using the conventional CHE. As described above, the DAHE phenomenon occurs more frequently when the magnitude of the voltage applied to the floating gate is about half the magnitude of the voltage applied to the drain. Therefore, the voltage applied to the control gate 7 can be made lower than in the conventional case.
[0056]
For this reason, in the present embodiment, it is necessary to adjust the coupling ratio of the memory element as described above and to apply the same write voltage to the drain region 10 and the control gate 7 to generate DAHE. A combination of voltages applied to the floating gate and the drain region can be obtained.
[0057]
On the other hand, at the time of erasing, since a conventional nonvolatile memory uses FN tunneling, it is necessary to apply a large electric field to the gate insulating film 4. Therefore, it is necessary to apply different positive and negative voltages to the control gate 7, the P-type well 2, and the drain region 10.
[0058]
On the other hand, in the present embodiment, DAHH is used for erasing without using the FN tunneling phenomenon. The difference between the voltage applied to the drain region 10 required to generate the DAHH phenomenon and the voltage applied to the floating gate 5 is smaller than the magnitude of the electric field required to generate FN tunneling.
[0059]
Therefore, by adjusting the coupling ratio of the memory element as described above, when a voltage having the same magnitude as the voltage applied at the time of writing is applied to the drain region 10, the voltage is applied to the drain region 10. The voltage and the voltage applied to the floating gate 5 can be combined to generate DAHH.
[0060]
Heretofore, in some cases, erasing is performed with one type of voltage at the time of erasing. Specifically, for example, 12 V is applied to the source region 9, and 0 V is applied to each of the control gate 5, the drain region 10, and the P-type well 2. Even in this case, FN tunneling occurs and can be erased. In order to perform erasing by applying one type of voltage in this manner, the electric field in the gate insulating film 4 must be increased as described above, so that a high voltage such as 12 V must be applied. Was. For this reason, as in the case of the voltage required for writing (for example, 6 V), it was not possible to reduce the voltage.
[0061]
On the other hand, the difference between the voltage applied to the drain region 10 required to generate DAHH and the voltage applied to the floating gate 5 is larger than the magnitude of the electric field required to generate FN tunneling. Is also low. From this, the voltage required for erasing can be reduced as compared with the conventional case. The circuit area of the peripheral circuit increases as the voltage generated increases. For this reason, in the present embodiment, the peripheral circuit area can be reduced as compared with the related art.
[0062]
By appropriately setting the coupling ratio of the memory element as described above, it is possible to use only one type of voltage to be generated for rewriting. Therefore, the peripheral circuit can be simplified. As a result, the peripheral circuit area can be reduced.
[0063]
Conventionally, in a flash memory having a small memory capacity, a peripheral circuit area is larger than an area occupied by a memory element. For this reason, even if the memory capacity is reduced, the area of the entire device cannot be reduced. On the other hand, according to the present embodiment, it is possible to reduce the size of the flash memory having a small memory capacity as compared with the related art.
[0064]
Next, a method of manufacturing the flash memory will be described. FIGS. 5A, 5B, 6A, and 6B show manufacturing steps of this flash memory.
[0065]
[Step shown in FIG. 5 (a)]
A semiconductor substrate 3 is formed by forming a P-type well 2 in a surface layer of a P-type silicon substrate 1. Then, although not shown, an element isolation region is formed in the semiconductor substrate 3. Thereafter, although not shown, a silicon oxide film having a thickness of about 8 to 10 nm, a polysilicon film having a thickness of about 200 nm, and an ONO film having a thickness of about 15 to 20 nm are formed on the semiconductor substrate 3. Then, a polysilicon film having a thickness of about 200 nm is sequentially formed. Next, these are patterned by photolithography and an etching process.
[0066]
Thus, a gate insulating film 4 made of a silicon oxide film, a floating gate 5 made of polysilicon, an interlayer insulating film 6 made of an ONO film, and a control gate made of polysilicon are formed. I do. That is, a two-layer polysilicon gate electrode structure is formed.
[0067]
[Step shown in FIG. 5B]
A conductive type impurity such as B (boron) is obliquely ion-implanted with a photoresist 21 having an opening only on the drain side. Thus, the P-type pocket layer 11 is formed on one side of the floating gate 5 in the surface layer of the semiconductor substrate 3.
[0068]
Note that, even when the conventional CHE is used as a carrier at the time of writing, a P-type pocket layer for generating CHE is formed by obliquely ion-implanting the semiconductor substrate 3. On the other hand, in the present embodiment, in order to increase the overlap length 12 between the floating gate 5 and the drain region 10 as compared with the conventional case, the overlap length is set to be smaller than the conventional one (by reducing the angle with respect to the semiconductor substrate 3). Ions are implanted.
[0069]
[Step shown in FIG. 6 (a)]
Using the photoresist 41 as it is, a conductive impurity such as P (phosphorus) is obliquely ion-implanted into the surface region of the semiconductor substrate 3 where the drain region 10 is to be formed. In this ion implantation, in order to make the overlap length 12 between the drain region 10 and the floating gate 5 longer than before, a conductive impurity such as P which is easily diffused is used in a later heat treatment step.
[0070]
[Step shown in FIG. 6B]
After removing the photoresist 41, a silicon nitride film or a silicon oxide film is deposited by a CVD method or the like, and an etch back process is performed. Thereby, sidewalls 8 are formed on the sidewalls of the two-layer polysilicon gate electrode structure. Next, ions of a conductivity type such as As are ion-implanted into a region where the source region 9 is to be formed and the drain region 10 in the surface layer of the semiconductor substrate 3 in a direction perpendicular to the substrate. Then, a heat treatment such as RTP (Rapid Thermal Process) is performed to activate the impurity diffusion layer, thereby forming the source region 9 and the drain region 10 on both sides of the floating gate 5 in the surface layer of the semiconductor substrate 3. .
[0071]
In the present embodiment, the overlap length 12 between the floating gate 5 and the drain region 10 is made larger than before. Thus, the coupling capacitance Cfd between the drain region 10 and the floating gate 5 is appropriately adjusted so as to satisfy the above three conditional expressions.
[0072]
Thereafter, although not shown, the device is completed through a Poly-Meta1 interlayer insulating film, a wiring process, and the like used in a normal LSl process.
[0073]
(2nd Embodiment)
FIG. 7 is a sectional view of a flash memory according to the second embodiment to which the present invention is applied. In the first embodiment, the same components as those of the flash memory shown in FIG. 1 are denoted by the same reference numerals, and the description of the same components will be omitted.
[0074]
In the first embodiment, by setting the overlap length 12 between the floating gate 5 and the drain region 10 to an appropriate length, the distance between the drain region 10 and the floating gate 5 is satisfied so as to satisfy the above three conditional expressions. The case where the coupling capacitance Cfd is adjusted has been described. However, as described below, Cfd can also be adjusted by dividing a part of the control gate and short-circuiting the divided part and the drain region.
[0075]
As shown in FIG. 7, the flash memory according to the present embodiment has a structure in which a control gate 7 and a polysilicon film 51 are provided on a floating gate 5 with an interlayer insulating film 6 interposed therebetween. The polysilicon film 51 is electrically separated from the control gate 7 and is electrically connected to the drain region 10. Although not shown, an electrical connection between the polysilicon film 51 and the drain region 10 can be made using, for example, aluminum wiring.
[0076]
In the present embodiment, the polysilicon film 51 electrically connected to the drain region 10 is formed on the floating gate 5, and the width of the polysilicon film 51 is determined by the above three conditional expressions. Is properly adjusted to meet In this flash memory, when the polysilicon film 51 and the floating gate 5 are viewed from above the semiconductor substrate 3, the polysilicon film 51 and the floating gate 5 partially overlap. The length of the overlapping portion, that is, the overlap length 52 is adjusted. As described above, by adjusting the overlap length 52, Cfd can be appropriately adjusted.
[0077]
FIG. 8 shows a diagram when a plurality of cells are arranged in an array. FIG. 8 shows a cross-sectional structure of the cell shown in FIG. 7 together with an array configuration diagram. In the present embodiment, such an array configuration can be adopted. The operations in writing and erasing are the same as in the first embodiment.
[0078]
Next, a method for manufacturing this flash memory will be described with reference to FIGS. 5 (a), 9 (a), 9 (b) and 9 (c). As in the first embodiment, in the step shown in FIG. 5A, a silicon oxide film, a first polysilicon film, and an ONO film are formed on a region of the semiconductor substrate 3 where a flash memory is to be formed. And a second polysilicon film are sequentially formed. After that, a two-layer polysilicon gate electrode structure is formed by performing photolithography and etching steps.
[0079]
[Step shown in FIG. 9A]
In this step, similarly to the step shown in FIG. 5B in the first embodiment, a conductive type impurity such as B (boron) is obliquely ion-implanted with a photoresist 41 opened only on the drain side. At this time, the angle at which the ions are implanted does not have to be a shallower angle than in the related art, as in the step shown in FIG.
[0080]
[Step shown in FIG. 9B]
After removing the photoresist 41, the photoresist 42 is newly covered and patterned, and the photoresist 42 is opened so that only a part of the second polysilicon film 7 is exposed. The control gate 7 and the polysilicon film 51 are formed by etching the second-layer polysilicon film 7 using the photoresist 42 as a mask.
[0081]
[Step shown in FIG. 9C]
After the photoresist 42 is removed, sidewalls 8 are formed on the side walls of the two-layer polysilicon gate electrode structure in the same manner as in the step shown in FIG. The source region 9 and the drain region 10 are formed on both sides of the floating gate 5.
[0082]
Thereafter, although not shown, the device is completed through a Poly-Meta1 interlayer insulating film, a wiring process, and the like used in a normal LSl process.
[0083]
(Other embodiments)
In each of the above-described embodiments, the above-described three conditional expressions are satisfied by mainly adjusting the coupling capacitance Cfd between the drain region 10 and the floating gate 5. However, the present invention is not limited to Cfd. In addition, the coupling capacitance Cfc between the floating gate 5 and the control gate 7, the coupling capacitance Cfs between the floating gate 5 and the source region 9, and the gate capacitance Cf of the gate insulating film 4 are set so as to satisfy three conditional expressions. It can also be adjusted.
[Brief description of the drawings]
FIG. 1 is a sectional view of a flash memory according to a first embodiment of the present invention.
FIG. 2 is a table showing applied voltages at the time of rewriting and reading of the flash memory according to the first embodiment.
FIG. 3 is a configuration diagram of a cell array in which a bias at the time of writing is also shown in the flash memory according to the first embodiment.
FIG. 4 is a configuration diagram of a cell array in which a bias at the time of erasing is also shown in the flash memory according to the first embodiment.
FIG. 5 is a cross-sectional view for explaining a manufacturing process of the flash memory according to the first embodiment.
FIG. 6 is a cross-sectional view for explaining a manufacturing step following FIG. 5;
FIG. 7 is a cross-sectional view of a flash memory according to a second embodiment of the present invention.
FIG. 8 is a configuration diagram of a cell array of a flash memory according to a second embodiment. In this cell array configuration diagram, the cross-sectional structure of the cell is also shown.
FIG. 9 is a cross-sectional view for explaining a manufacturing step of the flash memory according to the second embodiment.
FIG. 10 is a sectional view of a conventional flash memory.
FIG. 11 is a table showing applied voltages at the time of rewriting and reading of a conventional flash memory.
FIG. 12 is a configuration diagram of a cell array in which a bias at the time of writing is additionally shown in a conventional flash memory.
FIG. 13 is a diagram illustrating a cell array in which a bias at the time of erasing is also described in a conventional flash memory.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate, 2 ... P type well, 3 ... Semiconductor substrate,
4 tunnel film, 5 floating gate, 6 interlayer insulating film,
7: control gate, 8: sidewall, 9: N ⁺ Type source area,
10 ... N ⁺ -Type drain region, 11 ... P-type pocket layer,
12, 52: overlap length, 21 to 24: word line,
31 to 34: bit line, 51: polysilicon film.

Claims (5)

A gate insulating film (4) formed on the semiconductor substrate (3);
A floating gate (5) formed on the gate insulating film (4);
A control gate (7) capacitively coupled to the floating gate (5);
In a nonvolatile semiconductor memory device having a source region (9) and a drain region (10) formed at positions on both sides of the floating gate (5) in a surface layer of the semiconductor substrate (3),
Writing can be performed using a drain avalanche hot electron, erasing can be performed using a drain avalanche hot hole, and the magnitude of an applied voltage required at the time of writing and erasing can be one type. Wherein the coupling ratio of the memory element is adjusted. The coupling capacitance between the floating gate (5) and the drain region (10) enables writing using drain avalanche hot electrons and erasing using drain avalanche hot holes, and 2. The non-volatile semiconductor memory device according to claim 1, wherein the magnitude of an applied voltage required at the time of writing and erasing is adjusted to be one kind. A coupling capacitance between the floating gate (5) and the drain region (10) is adjusted by an overlap length (12) between the floating gate (5) and the drain region (10). 3. The nonvolatile semiconductor memory device according to claim 2, wherein: A conductive film (51) formed on the floating gate (5) via an insulating film (6) and electrically connected to the drain region (10);
A coupling capacitance between the floating gate (5) and the drain region (10) is adjusted by an overlap length (52) between the floating gate (5) and the conductive film (51). The nonvolatile semiconductor memory device according to claim 2. 2. A nonvolatile semiconductor memory device in which a plurality of memory cells are connected in an array, wherein, among the memory cells connected to the same bit line, all of the memory cells to be written are written simultaneously. 5. The non-volatile semiconductor storage device according to any one of items 4 to 4.

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