JP2006099473A - Bus controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus controller capable of preventing data missing by appropriately switching bus priority in accordance with data transfer statuses of a plurality of data processing parts. <P>SOLUTION: The data amount of a storage buffer 1 is calculated in a data amount calculation part 2, and the transfer speed of the data is calculated in a transfer speed calculation part 3. In a time measurement part 4, a time value is calculated from the data amount and the transfer speed. In a switching part 5, the bus priority is switched on the basis of the time value calculated in the time measurement part 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus control device.

  When one bus is shared by a plurality of data processing units, a bus arbiter that arbitrates the connection between the bus and the data processing unit is used. The bus arbiter 101 shown in FIG. 7 switches the bus priority between the bus and the data processing units 103a to 103c in accordance with a bus right request signal from the bus interfaces 102a to 102c connected to the bus arbiter 101.

  Here, when a bus right request signal is simultaneously input from a plurality of data processing units, the bus arbiter 101 switches the bus priority according to a predetermined priority order. Here, the priority order is often stored in the register 104 so that the CPU can arbitrarily set it.

  However, in the configuration of FIG. 7, the CPU cannot grasp the data transfer status of each data processing unit. Therefore, in the configuration of FIG. 7, the bus priority cannot be dynamically switched according to the data transfer status of each data processing unit.

Therefore, in the technique disclosed in Patent Document 1, the bus priority is dynamically switched according to the data storage amount of each data processing unit. The method of Patent Document 1 will be described with reference to FIG. In the configuration of FIG. 8, storage buffers 105a to 105c for temporarily storing data transferred from the bus side or the data processing unit side are provided in the bus interfaces 102a to 102c, respectively. In such a configuration, when the amount of data used in the storage buffers 105a to 105c exceeds a certain threshold, a buffer full signal notifying that is output from the bus interfaces 102a to 102c to the bus arbiter 101. The bus arbiter 101 receives the buffer full signal from the bus interfaces 102a to 102c and switches the bus priority. For example, when the data transfer direction in the bus interface exceeding the threshold is from the bus side to the data processing unit side, the priority is increased. On the other hand, when the data transfer direction in the bus interface exceeding the threshold is from the data processing unit side to the bus side, the priority is lowered.
JP-A-5-28103

  However, in the method of Patent Document 1, since the buffer full signal is not output to the bus arbiter 101 until the data storage amount of the storage buffer reaches the threshold value, the bus priority is not switched. For this reason, when the priority of a data processing unit that takes a long time to reach the threshold value is set high, the amount of time until the data usage amount of the storage buffer of the data processing unit reaches the threshold value Data transfer of other data processing units will be delayed. This may cause data loss.

  The present invention has been made in view of the above circumstances, and provides a bus control device that can prevent data loss by switching the bus priority more appropriately according to the data transfer status of a plurality of data processing units. The purpose is to provide.

  In order to achieve the above object, a bus control device according to a first aspect of the present invention provides bus priority between a bus and a plurality of data processing units having a storage memory for temporarily storing data. A bus control device for controlling, wherein the bus priority is switched according to a data amount of the storage memory and a data transfer rate required by the plurality of data processing units.

  According to the first aspect, the bus priority can be switched more appropriately by switching the bus priority depending not only on the data amount of the storage memory but also on the data transfer rate.

  In order to achieve the above object, a bus control device according to a second aspect of the present invention includes a plurality of data processing units each including a storage memory for temporarily storing data, and the plurality of data processing units. A bus connected to and transferring data to and from the data processing unit, and a time until each storage memory of the plurality of data processing units becomes empty or a time until the storage memory becomes full And a switching unit that switches the priority of the plurality of data processing units to the bus based on the time measured by the time measuring unit.

  According to the second aspect, by switching the bus priority based on the time until the storage memory becomes full or the time until the storage memory becomes empty, a more appropriate bus priority can be set. Switching can be performed.

  According to the present invention, it is possible to provide a bus control device that can prevent data loss by switching the bus priority more appropriately according to the data transfer status of a plurality of data processing units.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a main configuration of a bus control device according to an embodiment of the present invention. Here, the bus control device of FIG. 1 is for one data processing unit. When a plurality of data processing units are connected to the bus, the configuration of FIG. 1 is required for the number of data processing units. 1 may be provided in any of the bus arbiter, the bus interface, and the data processing unit. Further, the configuration shown in FIG. 1 may be distributed to the bus arbiter, the bus interface, and the data processing unit.

  The bus control device shown in FIG. 1 includes a storage buffer 1, a data amount calculation unit 2, a transfer rate calculation unit 3, a time measurement unit 4, and a switching unit 5.

  The storage buffer 1 as a storage memory is a buffer memory in which data transferred from the bus side or the data processing unit side is temporarily stored.

  The data amount calculation unit 2 calculates the data amount of the accumulation buffer 1 as an accumulated data amount or an empty data amount. Here, the data amount of the storage buffer 1 is information indicating the usage amount of the storage buffer 1, and is the amount of data stored in the storage buffer 1 when the data transfer direction is from the bus side to the data processing unit side. . On the other hand, when the data transfer direction is from the data processing unit side to the bus side, the amount of free data in the accumulation buffer 1 is obtained.

  The transfer rate calculation unit 3 calculates the transfer rate of data. The transfer speed here is the number of data required per unit time (per clock in this embodiment), (transfer speed) = (bit width of the data processing unit bus) × (number of data ÷ clock Number). For example, when one data is required in 4 clocks in a data processing unit with a bus bit width of 8 bits, the transfer rate is 8 [bit] × (1 [data] ÷ 4 [clk]) = 2. Become. The parameters used for calculating the transfer rate such as the bus bit width, the number of data, and the number of clocks are given in advance, for example. Further, by storing these parameters in a register or the like, the setting may be changed by a CPU or the like.

  The time measuring unit 4 calculates a time value based on the buffer usage calculated by the data amount calculating unit 2 and the transfer rate calculated by the transfer rate calculating unit 3. That is, (time value) = (buffer usage amount) / (transfer rate). Here, the time value calculated when the data transfer direction is from the bus side to the data processing unit side indicates the time until the accumulation buffer 1 becomes empty. On the other hand, the time value calculated when the data transfer direction is from the data processing unit side to the bus side indicates the time until the storage buffer 1 becomes full.

  The switching unit 5 switches the bus priority based on the time calculated by the time measuring unit 4. Here, in the present embodiment, the bus priority is switched so that the priority of the data processing unit having a small time value becomes high. For example, when the data transfer direction is from the bus side to the data processing unit side, if the time value is small, the time until the storage buffer 1 becomes empty is shortened. Increase the amount of transfer. When the data transfer direction is from the data processing unit side to the bus side, if the time value is small, the time until the storage buffer 1 becomes full is shortened. Increase the amount of transfer.

  Hereinafter, a specific example of one embodiment of the present invention will be described. FIG. 2 is a diagram showing a circuit configuration when the configuration of FIG. 1 is applied to an image output control circuit of an image reproduction apparatus.

  The image output control circuit shown in FIG. 2 is a circuit that displays an image on a display unit configured by an LCD or the like based on video data (Y / Cb / Cr data) input via a bus. Furthermore, in the circuit of FIG. 2, character information and the like can be inserted and displayed on the display unit based on OSD (On Screen Display) data input via the bus.

  The image output control circuit shown in FIG. 2 includes a bus arbiter 11, a weighting coefficient setting unit 11a, data processing units 12a to 12e, a display processing unit 13, and a display unit 14.

  The bus arbiter 11 performs bus priority control between the bus and the data processing units 12a to 12e. Although the detailed configuration of the bus arbiter 11 will be described in detail later, a bus selection determining unit 11b having functions of the time measuring unit 4 and the switching unit 5 of FIG. 1 is provided in the bus arbiter 11 of FIG. Yes. The bus selection determining unit 11b calculates a time value based on the buffer usage (stored data amount in the example of FIG. 2) and the transfer speed input from the data processing units 12a to 12e, and based on the calculated time value. Switch bus priority. Here, the time value may be calculated on the data processing units 12a to 12e side.

  The data processing units 12 a to 12 e also function as a bus interface, temporarily store data transferred via the bus, and transfer the data to the display processing unit 13. Here, the data processing units 12 a to 12 c of FIG. 2 are data processing units for transferring video data (Y data, Cb data, Cr data) to the display processing unit 13. The data processing units 12d and 12e are data processing units for transferring two types of OSD data (OSD1 data and OSD2 data) to the display processing unit 13. Each of these data processing units 12a to 12e includes an accumulation buffer (indicated by reference numerals 1a to 1e in FIG. 2), a data amount calculating section (indicated by reference numerals 2a to 2e in FIG. 2), and a transfer rate calculating section. (Indicated by reference numerals 3a to 3e in FIG. 2).

  The display processing unit 13 converts the Y, Cb, and Cr data transferred from the data processing units 12a to 12c into RGB data to display an image on the display unit 14, or displays based on OSD1 data or OSD2 data. Display control is performed when character information or the like is inserted and displayed on the unit 14.

  Next, bus priority switching performed in the bus selection determination unit 11b of the bus arbiter 11 will be described. Here, as an example, it is assumed that the video data and the OSD data require a bus bit width as shown in FIG. 3A and a data rate as shown in FIG. The bit width and data rate of these buses are given as parameters to the transfer rate calculation unit of each data processing unit.

  As shown in FIGS. 3A and 3B, for Y data, the bit width of the bus is 8 bits, and two pieces of data are required in 4 clocks. Therefore, the transfer rate calculated by the transfer rate calculation unit 3a (hereinafter referred to as Y transfer rate) is 8 [bit] × (2 [data] / 4 [CLK]) = 4.

  Similarly, the transfer rate calculated by the transfer rate calculation unit 3b (hereinafter referred to as Cb transfer rate) is 8 [bit] × (1 [data] / 4 [CLK]) = 2, and the transfer rate calculation unit 3c The transfer rate calculated in step (hereinafter referred to as Cr transfer rate) is 8 [bit] × (1 [data] / 4 [CLK]) = 2, and the transfer rate calculated in the transfer rate calculation unit 3d (hereinafter referred to as “transfer rate”) OSD1 transfer rate) is 4 [bit] × (1 [data] / 4 [CLK]) = 1, and the transfer rate calculated by the transfer rate calculation unit 3e (hereinafter referred to as OSD2 transfer rate) is = 8. [Bit] × (2 [data] / 4 [CLK]) = 4.

  In the bus selection determination unit 11b, a time value is calculated based on the transfer rate calculated by each transfer rate calculation unit and the accumulated data amount in the accumulation buffer in each data processing unit.

  For example, at the timing of calculating the time value, the accumulated data amount of Y data is 40 bits, the accumulated data amount of Cb data is 24 bits, the accumulated data amount of Cr data is 32 bits, the accumulated data amount of OSD1 data is 16 bits, When the accumulated data amount of OSD2 data is 56 bits (see FIG. 4A), the time value for Y data is 40 ÷ 4 = 10, the time value for Cb data is 24 ÷ 2 = 12, and Cr data The time value related to OSD1 data is 16 ÷ 1 = 16, and the time value related to OSD2 data is 56 ÷ 4 = 16.

  In the bus selection determination unit 11b, the priority order is determined based on the time value calculated as described above. Therefore, in the example of FIG. 4A, the priority of the data processing unit 12a is No. 1, the priority of the data processing unit 12b is No. 2, the priority of the data processing unit 12c, the data processing unit 12d, and the data processing unit 12e. Becomes No. 3.

  When the amount of data stored in each storage buffer changes from the state shown in FIG. 4A to the state shown in FIG. 4B, the bus priority is switched. In the example of FIG. 4B, the accumulated data amount of Y data is 60 bits, the accumulated data amount of Cb data is 12 bits, the accumulated data amount of Cr data is 32 bits, the accumulated data amount of OSD1 data is 40 bits, OSD2 Since the accumulated data amount is 20 bits, the time value for Y data is 60 ÷ 4 = 15, the time value for Cb data is 12 ÷ 2 = 6, and the time value for Cr data is 32 ÷ 2 = 16. The time value for OSD1 data is 40 ÷ 1 = 40, and the time value for OSD2 data is 20 ÷ 5 = 4. Accordingly, the priority of the data processing unit 12a is 3, the priority of the data processing unit 12b is 2, the priority of the data processing unit 12c is 4, the priority of the data processing unit 12d is 5, and the data processing unit The priority of 12e is switched to the first.

  Here, when the buffer sizes of the respective storage buffers are different, it is more preferable to switch the bus priority in consideration of the difference in the buffer sizes. Therefore, in this embodiment, in order to consider the difference in buffer size, the bus priority is switched after weighting corresponding to the buffer size of each storage buffer is performed on the time value. Specifically, when the bus selection determination unit 11b calculates the time value, the calculated time value is multiplied by a weighting coefficient (0 <weighting coefficient ≦ 1) held in the weighting coefficient setting unit 11a. Change the bus priority. Here, the weighting coefficient is a coefficient indicating the ratio of the buffer sizes of the respective storage buffers, and is expressed as a ratio to the maximum buffer size, for example. In the example of FIG. 4A, since the buffer sizes of all the accumulation buffers are equal, the weighting coefficients are all 1.

  FIG. 5 is a diagram illustrating a circuit configuration example of the bus selection determination unit 11 b in the bus arbiter 11. The bus selection decision unit 11b switches the bus priority every time an update pulse is input.

  As shown in FIG. 5, the bus selection determination unit 11b includes time measurement units 4a to 4e, a comparator 21, selectors 22a to 22e, flip-flop circuits 23a to 23e, selectors 24a to 24e, and fixed priority levels. And a bus arbiter 25.

  The time measurement units 4a to 4e receive the stored data amount and the transfer rate from the corresponding data processing units, and the weighting coefficient set in the weighting coefficient setting unit 11a. In the time measuring units 4a to 4e, a time value is calculated from the input accumulated data amount and the transfer speed, respectively, and the calculated time value is multiplied by the weighting coefficient set in the weighting coefficient setting unit 11a. The time values weighted by the time measuring units 4 a to 4 e are output to the comparator 21.

  In the comparator 21, the time values input from the time measuring units 4a to 4e are compared. As a result of this comparison, the smallest time value is output to the selector 22a, the second smallest time value is output to the selector 22b, the third smallest time value is output to the selector 22c, and the fourth smallest time value is the selector. 22d and the fifth smallest time value is output to the selector 22e.

  The selectors 22a to 22e select the input from the comparator 21 only when an update pulse is input from the outside. On the other hand, when no update pulse is input, the outputs of the flip-flop circuits 23a to 23e are selected and the values of the flip-flop circuits 23a to 23e are held. The selectors 24a to 24e select an input value to the fixed-order bus arbiter 25 based on the values held in the flip-flop circuits 23a to 23e. As a result, the priority order is switched.

  FIG. 6 is a timing chart showing the bus priority switching operation in the circuit of FIG. In the circuit of FIG. 5, the bus priority is switched every time an update pulse is input. The update pulse may be input in accordance with the data transfer timing. For example, assuming that video data and OSD data are stored in the SDRAM, the number of transfer cycles in burst transfer is determined. Therefore, an update pulse may be input according to the number of transfer cycles.

  The time graph immediately before the update shown in FIG. 6 shows the time value immediately after the update pulse is input, and the shorter the graph, the higher the priority when switching the next bus priority. For example, in FIG. 6, in the time graph in the first cycle, OSD1 is the shortest, and in the following order, OSD2, Y, Cb, and Cr are in order, so the priority in the second cycle is OSD1 first, OSD2 second. Hereinafter, the order is Y, Cb, and Cr. In subsequent cycles, the order is switched in the same way.

  As described above, according to the present embodiment, a time-converted amount of data is stored in the accumulation buffer at an equal rate. Therefore, data loss and the like can be prevented more efficiently.

  Although the present invention has been described based on the above embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention. For example, in the above-described embodiment, only an example in which the bus control device is applied to an image playback device capable of playing back image data has been described. However, the technology described in this embodiment can play back audio data. It can also be applied to various data reproducing apparatuses. In addition, the technique described in the present embodiment can be applied to a data recording apparatus such as a moving image.

  When switching the bus priority, it is not always necessary to prioritize all data processing units. For example, only the smallest time value may be determined, and data transfer may always be performed in the data processing unit having the smallest time value.

  Further, the above-described embodiments include various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

It is a figure shown about the main structures of the bus control apparatus which concerns on one Embodiment of this invention. It is a figure which shows the circuit structure at the time of applying the bus control apparatus of FIG. 1 to the image output control circuit of an image reproduction apparatus. FIG. 3A is a diagram showing an example of the bus bit width required by each data processing unit, and FIG. 3B is a diagram showing an example of the data rate required by each data processing unit. It is a figure which shows the example of the storage data amount of a storage buffer. It is a figure shown about the circuit structural example of the bus selection determination part inside a bus arbiter. It is a timing chart of bus priority switching. It is a figure shown about the 1st structural example of the conventional bus control apparatus. It is a figure shown about the 2nd structural example of the conventional bus control apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1a-1e ... Accumulation buffer, 2, 2a-2e ... Data amount calculation part, 3, 3a-3e ... Transfer rate calculation part, 4, 4a-4e ... Time measurement part, 5 ... Switching part, 11 ... Bus arbiter, DESCRIPTION OF SYMBOLS 11a ... Weighting coefficient setting part, 11b ... Bus selection determination part, 12a-12e ... Data processing part, 13 ... Display processing part, 14 ... Display part, 21 ... Comparator, 22a-22e, 24a-24e ... Selector, 23a- 23e ... flip-flop circuit, 25 ... fixed priority bus arbiter

Claims (14)

A bus control device that controls bus priority between a bus and a plurality of data processing units including a storage memory that temporarily stores data,
A bus control device that switches the bus priority according to a data amount of the storage memory and a data transfer rate required by the plurality of data processing units.   The data amount is a usage amount of the storage memory determined based on a data transfer direction between the bus and each data processing unit of the data processing unit. Bus control device.   3. The bus control device according to claim 2, wherein the usage amount of the storage memory when the data transfer direction is from the bus side to the data processing unit side indicates an accumulated data amount of the storage memory. .   3. The bus control device according to claim 2, wherein when the data transfer direction is from the data processing unit side to the bus side, the use amount of the storage memory indicates an empty data amount of the storage memory. . The above data volume is
A usage amount of the storage memory determined based on a transfer direction of data between the bus and each data processing unit of the plurality of data processing units;
The usage amount of the storage memory when the transfer direction of the data is from the bus side to the data processing unit side indicates the accumulated data amount of the storage memory,
2. The bus control device according to claim 1, wherein when the data transfer direction is from the data processing unit side to the bus side, the use amount of the storage memory indicates an empty data amount of the storage memory.   The bus priority switching is performed based on a time calculated from a data amount of the storage memory and a data transfer rate required by the plurality of data processing units, and based on the calculated time. The bus control device according to 1.   The bus control device according to claim 1, wherein the data includes at least one of image data and audio data. A plurality of data processing units having a storage memory for temporarily storing data;
A bus connected to the plurality of data processing units and transferring data to and from the data processing unit;
A time measuring unit that calculates a time until each storage memory of the plurality of data processing units becomes empty or a time until the storage memory becomes full; and
A switching unit that switches the priority of the plurality of data processing units to the bus based on the time measured in the time measuring unit;
A bus control device comprising:   9. The bus control device according to claim 8, wherein the switching of the priority in the switching unit is performed every predetermined time.   9. The bus control device according to claim 8, wherein the switching unit switches the priority by increasing a priority for a data processing unit whose time measured by the time measuring unit is small.   The time measuring unit calculates a time until the storage memory becomes empty when the data transfer direction is from the bus side to the data processing unit side, and the data transfer direction is the data processing unit. 9. The bus control device according to claim 8, wherein a time until the storage memory becomes full is calculated when the bus is on the bus side.   9. The bus control device according to claim 8, further comprising a weighting unit that weights the time measured by the time measurement unit according to the memory size of each storage memory of the plurality of data processing units.   9. The bus control device according to claim 8, wherein the time is a value obtained by dividing the amount of data in the storage memory by a data transfer rate required by a data processing unit having the storage memory.   14. The bus control device according to claim 13, wherein the parameter for calculating the data transfer rate is a value whose setting can be changed.

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