JP2006094478A - Frequency divider and mobile apparatus equipped with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency divider capable of reducing a probability of output error occurrence caused by circuit configuration by making common a voltage/current converting unit that causes phase error and/or amplitude error generation. <P>SOLUTION: The frequency divider comprises: a voltage/current converting unit 11 that uses a differential pair of transistors (Tr) Q1 and Q2 to convert a clock signal CLK1 of a voltage signal and a clock inverse signal CLK2 of a complementary signal of CLK1 into current signals; and an I-Q signal generating unit 12 including Tr Q11, Q12, and Tr Q5, Q6 which input a current signal i101 output from the Tr Q1 to generate, respectively two first signal and/or second signal of which phases differ from each other at 180°, and Tr Q9, Q10 and Tr Q7, Q8 which input a current signal i102 output from the Tr Q2 to generate, respectively two third and/or fourth signals of which phases differ from each other at 180°. The phase difference between the first and/or third signals of the I-Q signal generating unit 12 is 90° and the phase difference between the second and/or fourth signals is 90°. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a frequency divider suitably implemented in a receiving device having an image rejection function and a portable device including the frequency divider.

  In a receiving apparatus or the like having an image rejection function, the frequency divider and the mixer circuit are each one of the most important blocks. Conventionally, a frequency divider receives a signal generated by a local oscillator, generates an I signal and a Q signal having a phase difference of 90 degrees from the input signal, and supplies the I signal to the I-mixer as a local signal. On the other hand, the Q signal is supplied to the Q-mixer as a local signal. Further, the mixer circuit (I-mixer, Q-mixer) multiplies the high-frequency signal input from the antenna by a local signal to perform frequency conversion, and generates an intermediate-frequency signal as a multiplication result.

  Specifically, as shown in FIG. 12, the frequency divider uses the timing of the CLK signal to generate an I signal and a Q signal that are 90 degrees out of phase with each other, as shown in FIG. It is divided into two functional blocks. That is, the frequency divider D90 includes voltage-current converters 91 and 92 and an IQ signal generator 93. The voltage-current converters 91 and 92 each include a constant current source and two differential pair npn transistors. Although not shown, the I-Q signal generation unit 93 includes four output load resistors and eight npn-type transistors in combination with the I signal generation unit and the Q signal generation unit, and is ½ of the clock frequency. It has a latch function for holding or changing the I signal and the Q signal at the timing of the frequency. In particular, when only the I signal (Q signal) is extracted, it functions as a simple divide-by-2 circuit that divides the clock frequency by two.

  Various specific circuit configurations of the frequency divider have been conventionally proposed.

  For example, as shown in FIG. 14, the frequency divider D90 has a flip-flop function. The voltage-current converter 91 includes signal input npn transistors Q1a and Q2a, a constant current source I91, and an input terminal CLK1. -CLK2 is provided. The voltage-current converter 92 includes signal input npn transistors Q1b and Q2b, a constant current source I92, and input terminals CLK1 and CLK2. The IQ signal generator 93 includes dual differential npn transistors Q15 to Q18 and Q19 to Q22, output load resistors R1 to R4, an output terminal I, and an output terminal Q. Here, the output terminal I outputs an I signal whose phase is 0 degree or 180 degrees, and the output terminal Q outputs a Q signal whose phase is 90 degrees or 270 degrees.

  The voltage-current conversion unit 91 and the voltage-current conversion unit 92 convert the CLK voltage signal input from the input terminals CLK1 and CLK2 into four current signals, respectively. However, the CLK voltage signal input from the input terminal CLK2 is a complementary signal of the CLK signal input from the input terminal CLK1. Here, it should be noted that the four current signals i901 to i904 are composed of two kinds of output current signals.

  Further, the IQ signal generation unit 93 generates an I signal and a Q signal that are half the frequency of the CLK signal and have a phase difference of 90 degrees using the timing of the CLK signal. .

  When the duty ratio is 50% and a CLK signal having a predetermined frequency is input to the input terminal CLK1, the transistors Q1a and Q1b connected to the input terminal CLK1 and the base terminal are turned on and off in accordance with the CLK signal. repeat.

  When a complementary signal of the CLK signal of the input terminal CLK1 is input to the input terminal CLK2, the transistors Q2a and Q2b connected to the input terminal CLK2 and the base terminal are complementary to the ON and OFF timings of the transistors Q1a and Q1b. Repeat ON and OFF. As a result, the IQ signal generator 93 outputs a signal having a phase of 0 degrees and 180 degrees from the output terminal I, and outputs a signal having a phase of 270 degrees and 90 degrees from the output terminal Q. When the CLK input is not received, the previous state (ON, OFF) is held by the cross-connected latch cores (transistors Q17 and Q18 or transistors Q21 and Q22).

  The image rejection performance depends on the phase error and amplitude error of the frequency divider applied to the I-mixer and Q-mixer. However, the frequency divider D90 as shown in FIG. 14 is very layout-dependent, and if not carefully laid out, process variations may occur and the phase error may be 3 degrees or more.

  As a result, the phase error of the local signal becomes the output phase error of the mixer as it is, which deteriorates the image rejection performance.

  For this reason, the actual required phase error specification is less than about 1 degree. That is, as shown in FIG. 15, for example, in order to realize an image rejection ratio of 40 dB or more, Spec. A frequency divider satisfying a phase error of less than ± 1 degree and an amplitude error of less than ± 1% from the region surrounded by 1 is required.

  There are various factors that cause the phase error, but many are due to parasitic components of an asymmetric layout due to human factors and the occurrence of offset voltage due to process variations.

  In the output IQ phase difference when a DC offset is applied to the constant current source I91 in FIG. 14, as the offset voltage increases, the phase error between IQ increases as shown in FIG. I understand. In the figure, the constant current sources I91 and I92 are each composed of a bipolar transistor, and an offset is given to the base DC bias.

  In addition, in the amplitude intensity of the output signal (local signal) of the I signal and the Q signal under the conditions shown in FIG. 16, as shown in FIG. The amplitude intensity of the primary component (LO1st-A) and the tertiary component (LO3rd-A) is substantially constant. On the other hand, it can be seen that the amplitude intensity of the first order component (LO1st-B) and the third order component (LO3rd-B) in the I signal subjected to the change in the operating current due to the DC offset variation greatly deteriorates due to the offset. Such an amplitude error greatly deteriorates the image rejection performance.

  Further, in the output IQ phase difference when a DC offset (ΔVin) is given between CLK1 and CLK2 in FIG. 14, the output phase error greatly changes by receiving the DC offset as shown in FIG. I understand that.

As a workaround method limited to the DC offset dependency characteristic shown in FIG. 18, there are those disclosed in Patent Document 1 and Patent Document 2. These Patent Documents 1 and 2 disclose techniques for reducing phase errors by adjusting the DC bias of the CLK input unit. Patent Document 2 discloses a technique for detecting a phase error and feeding it back as a DC component to compensate for a DC bias offset of a CLK input differential pair.
Japanese Patent Laid-Open No. 2-89412 (Publication date: January 12, 1990) JP-A-8-237077 (Publication date: September 13, 1996)

  By the way, in the conventional configuration, two sets of voltage-current conversion units including a constant current source and a differential pair that performs voltage-current conversion are provided. The two sets of voltage-current converters have the same function.

  However, the provision of two sets of voltage-current converters doubles the possibility of output phase errors and amplitude errors, as shown in FIGS. That is, when the constant current sources are provided separately, the output amplitude error becomes large due to the offset. Therefore, there is a problem that the image rejection performance is remarkably deteriorated. Further, since the DC offset variation between CLK1 and CLK2 in the voltage-current converters 91 and 92 in FIG. 13 is not always equal in sign, even when the conventional techniques of Patent Document 1 and Patent Document 2 are used. The output phase error and the amplitude error are not corrected efficiently. When using feedback to correct the phase, an LPF for supplying only the phase-DC conversion circuit and DC to the frequency divider input in addition to the four buffers forming the feedback path so as not to disturb the balance of the four-phase signal. Is required. These increase the current consumption by 1.5 times or more from the case of only the minute period, and the area becomes about twice. When it is assumed to be mounted on a portable device, it can be easily understood that an increase in current consumption and area is not desirable.

  Furthermore, since the two sets of voltage-current converters 91 and 92 are the main causes of output phase error and amplitude error, there is a tendency that a completely symmetric layout is difficult.

  The present invention has been made in view of the above problems, and an object of the present invention is to share a voltage-current conversion unit that causes a phase error and an amplitude error with respect to the divider having a strong layout dependency. Accordingly, an object of the present invention is to provide a frequency divider that can reduce the probability of output error occurrence due to a circuit configuration, and a portable device including the frequency divider.

  In order to solve the above problem, the frequency divider of the present invention uses a voltage-current conversion unit that receives a voltage input signal and a timing of an output current signal generated by the voltage-current conversion unit to divide the frequency. In the frequency divider having two sets of frequency-divided signal generating units for generating signals, the voltage-current converting unit is composed of a pair of differential pairs and uses the timing of two output current signals to A set of frequency-divided signal generators is driven simultaneously.

  In order to solve the above-described problem, the frequency divider of the present invention uses an input signal that is a voltage signal using a first signal input transistor and a second signal input transistor forming a differential pair. And a complementary voltage-current converter for converting the current signal and its complementary signal into a current signal, and a first current signal output from the first signal input transistor, and two first signals having a phase difference of 180 degrees from each other. The first signal generation unit and the second signal generation unit that respectively generate the second signal and the second signal, and the second current signal output from the second signal input transistor are input to each other and are 180 degrees out of phase with each other. Provided with a third signal generation unit and a fourth signal generation unit for generating two different third signals and fourth signals, respectively, and the first signal of the latch unit and The phase difference with the third signal is 90 degrees Ri, and the phase difference between the second signal and the fourth signal is characterized by a 90 degrees.

  According to said structure, it comprises with the transistor which makes the conventional voltage-current conversion part common and comprises a set of differential pairs. In the case where the conventional voltage-current converter has four signal input transistors, they are shared to form two signal input transistors.

  At this time, one first current signal or second current signal generated by the reference common voltage-current conversion unit is, for example, an I signal from the first signal generation unit, the third signal generation unit, or the like. It is equally distributed to the generation unit and the Q signal generation unit such as the second signal generation unit and the fourth signal generation unit. For this reason, the output phase error and the amplitude error due to process variations can be reduced, and the accuracy between the output signals of the IQ signals can be improved.

  In addition, since the structure is simple, a symmetrical layout in consideration of routing of, for example, a CLK signal wiring for an input signal that is a voltage signal and its complementary signal is facilitated. Further, the chip area can be reduced by reducing the number of elements.

  In addition, since the number of elements in the voltage-current converter is halved, it is possible to reduce the occurrence of deterioration in output signal accuracy due to transistor mismatch layout due to artificial factors.

  Therefore, a frequency divider that can reduce the probability of output error due to the circuit configuration by sharing a voltage-current converter that causes phase error / amplitude error generation with respect to a divider having a strong layout dependency. Can be provided.

  In the frequency divider of the present invention, the emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor forming the common voltage-current converter are connected to each other. The terminal is preferably connected to a current source.

  Furthermore, it is preferable that the common voltage-current converter has one current source.

  According to the above configuration, since the signal is equally distributed to the I signal generation unit and the Q signal generation unit with one operating current as a reference, variation in amplitude between the I signal and the Q signal can be reduced. Thereby, the accuracy between IQ output signals can be further improved.

  In the frequency divider of the present invention, the emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor forming the common voltage-current converter are connected to each other. The terminal is preferably connected to the ground.

  According to the above configuration, the operation margin can be expanded and low voltage operation is possible.

  In the frequency divider of the present invention, the emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor forming the common voltage-current converter are connected to each other. The terminal is preferably connected to the ground via a resistor.

  According to the above configuration, since the resistor acts as a negative feedback resistor, the distortion and characteristics of the differential pair transistor as a constant current source are improved.

  In the frequency divider of the present invention, a resistor is connected between the emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor forming the common voltage-current converter. Preferably it is.

  Here, the resistor is preferably a degeneration resistor.

  According to said structure, the linearity of the input-output characteristic of the said voltage-current conversion part can be improved by setting appropriately the resistance value of the said degeneration resistance. In addition, this reduces distortion current, and can obtain a signal with lower distortion as the output voltage, while reducing the number of elements and improving the accuracy of the output signal while maintaining the characteristics of reducing the harmonics of the local signal. can do.

  In the present invention, it is preferable to connect one current source to the middle point of the resistor.

  According to the above configuration, the operating current can be realized with higher accuracy than when connected to GND through a resistor, and a four-phase output having a desired amplitude can be obtained.

  In the present invention, it is preferable that two current sources are connected to both ends of the resistor.

  According to the above configuration, a potential drop due to a degeneration resistor does not occur, and a current source exists, so that an operation margin can be expanded and an accurate output amplitude can be obtained.

  Further, the frequency divider of the present invention includes a first Darlington connection transistor in which a third signal input transistor is Darlington-connected to a base terminal of the first signal input transistor forming the common voltage-current converter, and the first A second Darlington-connected transistor in which a fourth signal input transistor is Darlington-connected to the base terminal of the second signal input transistor, and the input signal is input to the base terminal of the third signal input transistor, It is preferable that a complementary signal of the input signal is input to the base terminal of the fourth signal input transistor.

  According to said structure, the transconductance (gm) of the said voltage-current conversion part reduces, and the linearity of the input-output characteristic of the said voltage-current conversion part becomes high. As a result, the distortion current is further reduced and a signal with a lower distortion can be obtained as the output voltage. The number of elements is reduced and the accuracy of the output signal is improved while maintaining the feature of reducing the harmonics of the local signal. can do.

  Furthermore, in the frequency divider of the present invention, the collector terminal of the third signal input transistor and the collector terminal of the fourth signal input transistor forming the common voltage-current converter are connected to a power supply voltage. preferable.

  According to said structure, the number of elements can be reduced and the precision of an output signal can be improved, maintaining the characteristic which improves linearity and reduces the harmonic of a local signal. In addition, the common mode voltage range of the input in the Darlington connection configuration can be maximized.

  Furthermore, in the frequency divider of the present invention, it is preferable that the first Darlington connection transistor and the second Darlington connection transistor are connected to cross each other.

  According to said structure, the number of elements can be reduced and the precision of an output signal can be improved with the structure which raises linearity and reduces the harmonic of a local signal. Also, the asymmetry of the input signal can be smoothed and distortion can be reduced.

  Moreover, it is preferable that the portable device of the present invention includes the frequency divider.

  As a result, a frequency divider that can reduce the probability of output error occurrence due to the circuit configuration by sharing a voltage-current conversion unit that causes phase error / amplitude error generation with respect to a frequency divider having strong layout dependency. Can be provided.

  In the frequency divider of the present invention, as described above, the voltage-current conversion unit is composed of a pair of differential pairs, and the two sets of frequency division signal generation units are configured using the timing of two output current signals. Drive at the same time.

  In addition, as described above, the frequency divider of the present invention uses the first signal input transistor and the second signal input transistor that form a differential pair, and the input signal that is a voltage signal and its complementary signal. And a common voltage-current conversion unit that converts the first current signal output from the first signal input transistor and two first signals that are 180 degrees out of phase with each other. The first signal generation unit and the second signal generation unit that respectively generate the two signals, and the second current signal output from the second signal input transistor is input, A latch unit including a third signal generation unit and a fourth signal generation unit for generating a third signal and a fourth signal, respectively, and the first signal and the third signal of the latch unit are provided. And the phase difference is 90 degrees, and 2 signal and the phase difference between the fourth signal is 90 degrees.

  Therefore, since one reference operating current is evenly distributed to the I signal generation unit and the Q signal generation unit, variation in amplitude error can be reduced. Furthermore, since the structure becomes simple, the symmetrical layout considering the routing of the CLK signal wiring becomes easy. In addition, the number of elements is halved, so the output signal accuracy due to the transistor mismatch layout due to human factors is reduced. The occurrence of deterioration can be reduced.

  Further, output phase error and amplitude error due to process variations can be reduced. Further, by combining the degeneration resistor and Darlington connection configuration and the common technology of the voltage-current conversion unit of the present invention, a configuration with improved output accuracy with low distortion and a small number of elements becomes possible.

  Therefore, a frequency divider that can reduce the probability of output error due to the circuit configuration by sharing a voltage-current converter that causes phase error / amplitude error generation with respect to a divider having a strong layout dependency. There is an effect that it can be provided.

  Furthermore, the techniques disclosed in Patent Document 1 and Patent Document 2 can be used most efficiently.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. 1 and 2 as follows.

  As shown in FIGS. 1 and 2, the frequency divider of the present embodiment shares the conventional two voltage-current converters 91 and 92 shown in FIG. 14 with the common voltage shown in FIGS. -It is set as the voltage-current conversion part 11 as a current conversion part. As a result, it is possible to simultaneously reduce the number of elements of the frequency divider, reduce the amplitude error, and reduce the distortion.

  Below, the structure of the frequency divider D10 of this embodiment is shown.

  As shown in FIG. 1, the frequency divider D <b> 10 of this embodiment shares the two voltage-current conversion units 91 and 92 shown in FIG. 14 with one voltage-current conversion unit 11.

  That is, in the frequency divider D10 of the present embodiment, as shown in FIG. 1, the voltage-current conversion unit 11 as a common voltage-current conversion unit current source includes an npn transistor Q1 forming a differential pair. Q2 and a constant current source I11 as a current source are provided.

  The base terminal of the transistor Q1 is connected to an input terminal for inputting the clock signal CLK1. The base terminal of the transistor Q2 is connected to an input terminal for inputting the clock inversion signal CLK2.

  The clock inversion signal CLK2 is a complementary signal to the clock signal CLK1.

  The emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2 are connected. Further, the emitter terminals of the transistors Q1 and Q2 are connected to a constant current source I11.

  The IQ signal generation unit 12 as a latch unit includes four resistors R1, R2, R3, and R4, and eight npn transistors Q5, Q6, Q7, Q8, Q9, Q10, Q11, and Q12. Yes. Here, the transistors Q5 and Q6 form a differential pair. Transistors Q7 and Q8 form a differential pair. Transistors Q9 and Q10 form a differential pair. Transistors Q11 and Q12 form a differential pair.

  The resistor R1 is connected to the transistors Q5 and Q7. Similarly, the resistor R2 is connected to the transistors Q6 and Q8, the resistor R3 is connected to the transistors Q9 and Q11, and the resistor R4 is connected to the transistors Q10 and Q12.

  Further, the emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected. The emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected. The emitter terminal of transistor Q9 and the emitter terminal of transistor Q10 are connected. The emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected.

  The emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected to the collector terminal of the transistor Q1 in the voltage-current converter 11. Further, the emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected to the collector terminal of the transistor Q1 in the voltage-current converter 11.

  Similarly, the emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected to the collector terminal of the transistor Q2 in the voltage-current converter 11. The emitter terminal of the transistor Q9 and the emitter terminal of the transistor Q10 are connected to the collector terminal of the transistor Q2 in the voltage-current converter 11.

  Hereinafter, a current flow in the frequency divider D10 illustrated in FIG. 1 will be described.

  At this time, since the clock inversion signal CLK2 is a complementary signal to the clock signal CLK1, the clock inversion signal CLK2 is turned off when the clock signal CLK1 is on.

  Therefore, when the clock signal CLK1 is ON, the current i101 as the first current signal flowing through the collector terminal of the transistor Q1 flows through the transistor Q1. At this time, since the clock inversion signal CLK2 is OFF, the current i102 as the second current signal flowing through the collector terminal of the transistor Q2 does not flow through the transistor Q2. Therefore, the current i101 flows through the transistor Q1, reaches the constant current source I11, and flows to the ground.

  Therefore, a current flows through the transistors Q5, Q6, Q11, and Q12.

  When the clock inversion signal CLK2 is ON, the current i102 flows through the transistor Q2. At this time, since the clock signal CLK1 is OFF, the current i101 does not flow through the transistor Q1. Therefore, the current i102 flows through the transistor Q2, reaches the constant current source I11, and flows to the ground. Therefore, current flows through the transistors Q7, Q8, Q9, and Q10.

  As described above, in the frequency divider D10 of the present embodiment, the four signal input transistors in the conventional voltage-current conversion unit are shared to form two transistors Q1 and Q2.

  The latch core section (transistors Q11 and Q12 or transistors Q7 and Q8) holds an I or Q signal when there is no current signal. The held ON / OFF signal is set to the base terminal of the output switching section (transistors Q5 and Q6 or transistors Q9 and Q10). In the output switching unit, as soon as the current signal based on the CLK signal is input, the output signal of each collector terminal is switched based on the signal set to the base terminal by the latch core unit. The latch unit holds the changed state again until the next signal current is input. That is, each latch unit (output switching unit) depends on one of the timings of CLK and CLKB, so that the output signal is divided by two from the CLK signal.

  For this reason, the output phase error and the amplitude error due to process variations can be reduced, and the accuracy between the output signals of the IQ signals can be improved.

  In addition, since the structure is simple, a symmetrical layout considering the routing of the CLK signal wiring for the input signal that is a voltage signal and its complementary signal is facilitated. Further, the chip area can be reduced by reducing the number of elements.

  In addition, since the number of elements in the voltage-current converter is halved, it is possible to reduce the occurrence of deterioration in output signal accuracy due to transistor mismatch layout due to artificial factors.

  Therefore, the frequency divider D10 that can reduce the probability of output error occurrence due to the circuit configuration by sharing the voltage-current converter that causes the generation of the phase error / amplitude error in the frequency divider having strong layout dependency. Can be provided.

  In the frequency divider D10 of the present embodiment, the emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2 forming a differential pair are connected to each other, and the emitter terminal is connected to the constant current source I11. .

  Furthermore, the voltage-current converter 11 has one constant current source I11. Accordingly, since the signal is equally distributed to the I signal generator (I generator) and the Q signal generator (Q generator) with one operating current as a reference, variation in amplitude between the I signal and the Q signal can be reduced. it can. Thereby, the accuracy between IQ output signals can be further improved.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  As shown in FIG. 3, the frequency divider D20 of the present embodiment includes a voltage-current conversion unit 21 and an IQ signal generation unit 22. The IQ signal generation unit 22 has the same configuration as the IQ signal generation unit 12 in the frequency divider D10, and a description thereof will be omitted here.

  As shown in FIGS. 4 and 5, the voltage-current conversion unit 21 in the present embodiment can be configured such that the current source is removed. Further, as shown in FIG. 5, the voltage-current converter 21 is provided with negative feedback resistors R5 to R7, and these negative feedback resistors R5 to R7 provide low distortion and characteristics as a current source of the differential pair transistor. It has improved. As a result, the operation margin is expanded and low voltage operation is possible.

  First, as shown in FIG. 4, the voltage-current conversion unit 21 includes a transistor Q1 and a transistor Q2.

  Here, as described above, the emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected to the collector terminal of Q1 in the voltage-current converter 21. The emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected to the collector terminal of the transistor Q1 in the voltage-current converter 21. The emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected to the collector terminal of the transistor Q2 of the voltage-current converter 21. The emitter terminal of the transistor Q9 and the emitter terminal of the transistor Q10 are connected to the collector terminal of the transistor Q2 in the voltage-current converter 21.

  The base terminal of the transistor Q1 is connected to an input terminal for inputting the clock signal CLK1.

  The transistor Q2 is connected to an input terminal for inputting the clock inversion signal CLK2. However, the clock inversion signal CLK2 is a complementary signal of the clock signal CLK1.

  The emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2 are connected. Further, the emitter terminals of the transistors Q1 and Q2 are connected to the ground.

  Hereinafter, a current flow in the voltage-current conversion unit 21 illustrated in FIG. 4 will be described.

  When the clock signal CLK1 is ON, a current i201 flowing through the collector terminal of the transistor Q1 flows through the transistor Q1. At this time, since the clock inversion signal CLK2 is OFF, the current i202 flowing through the collector terminal of the transistor Q2 does not flow through the transistor Q2. Therefore, the current i201 flows through the transistor Q1 and flows to the ground.

  Therefore, a current flows through the transistors Q5, Q6, Q11, and Q12.

  When the clock inversion signal CLK2 is ON, the current i102 flows through the transistor Q2. At this time, since the clock signal CLK1 is OFF, the current i101 does not flow through the transistor Q1. Therefore, the current i102 flows through the transistor Q2 and flows to the ground.

  Therefore, a current flows through the transistors Q7, Q8, Q9, and Q10.

  Thus, in the frequency divider D20 of the present embodiment, the emitter terminal of the transistor Q1 and the emitter terminal of the Q2 forming a differential pair are connected to each other, and the emitter terminal is connected to the ground.

  Therefore, the operation margin can be expanded and low voltage operation becomes possible.

  Next, in the voltage-current converter 21 shown in FIG. 5, the emitter terminal of the transistor Q1 is connected to the resistor R5. The emitter terminal of the transistor Q2 is connected to the resistor R6. Further, a resistor R5 and a resistor R6 are connected. Further, this and the resistor R7 are connected. The resistor R7 is connected to the ground.

  Hereinafter, a current flow in the voltage-current conversion unit 21 shown in FIG. 5 will be described.

  When the clock signal CLK1 is ON, a current i201 flowing through the collector terminal of the transistor Q1 flows through the transistor Q1. At this time, since the clock inversion signal CLK2 is OFF, the current i202 flowing through the collector terminal of the transistor Q2 does not flow through the transistor Q2. Therefore, the current i201 flows through the transistor Q1, flows through the resistors R5 and R7, and flows to the ground.

  Therefore, a current flows through the transistors Q5, Q6, Q11, and Q12.

  When the clock inversion signal CLK2 is ON, the current i102 flows through the transistor Q2. At this time, since the clock signal CLK1 is OFF, the current i101 does not flow through the transistor Q1. Therefore, the current i102 flows through the transistor Q2, flows through the resistors R6 and R7, and flows to the ground.

  Therefore, a current flows through the transistors Q7, Q8, Q9, and Q10.

  Thus, in the frequency divider D20 of the present embodiment, the emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2 forming a differential pair are connected to each other, and the emitter terminal has resistances R5, R6, and R7. Is connected to the ground. Accordingly, since the resistors R5, R6, and R7 function as negative feedback resistors, the distortion is reduced and the characteristics as a constant current source of the differential pair transistor are improved.

  Next, since the voltage-current converter 21 shown in FIG. 6 has a current source, it can realize an operating current with higher accuracy than connecting to GND through a resistor, and can generate a four-phase output having a desired amplitude. Obtainable.

[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. The configurations other than those described in the present embodiment are the same as those in the first embodiment and the second embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 and Embodiment 2 are given the same reference numerals, and explanation thereof is omitted.

  As shown in FIG. 7, the frequency divider D30 of this embodiment includes a voltage-current converter 31 and an IQ signal generator 32. In the frequency divider D30 of the present embodiment, a degeneration resistor Rsrc is inserted between the emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2 of the voltage-current converter 31. By inserting the degeneration resistor Rsrc, the linearity is improved, and the linear conversion characteristic to the output current waveform corresponding to the input voltage waveform is improved. Since two current sources are connected to both ends of the degeneration resistor, a potential drop due to the degeneration resistor does not occur. In addition, since there is a current source, an operation margin can be expanded and an output amplitude with high accuracy can be obtained.

  Below, the structure of the frequency divider D30 of this embodiment in FIG. 7 is shown.

  The voltage-current converter 31 of the frequency divider D30 illustrated in FIG. 7 includes a transistor Q1, a transistor Q2, a degeneration resistor Rsrc, a constant current source I31, and a constant current source I32.

  Here, as described above, the emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected to the collector terminal of Q1 in the voltage-current converter 31. The emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected to the collector terminal of the transistor Q1 in the voltage-current converter 31. The emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected to the collector terminal of the transistor Q2 of the voltage-current converter 31. The emitter terminal of the transistor Q9 and the emitter terminal of the transistor Q10 are connected to the collector terminal of the transistor Q2 in the voltage-current converter 31.

  The base terminal of the transistor Q1 is connected to the input terminal CLK1.

  The transistor Q2 is connected to the input terminal CLK2. However, the CLK signal input from the input terminal CLK2 is a complementary signal of the CLK signal input from the input terminal CLK1.

  A degeneration resistor Rsrc is connected between the emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2. Further, the emitter terminal of the transistor Q1 is connected to the constant current source I31. The constant current source I31 is connected to the ground. The emitter terminal of the transistor Q2 is connected to a constant current source I32, and this constant current source I32 is connected to the ground.

  Hereinafter, a current flow in the voltage-current conversion unit 31 illustrated in FIG. 7 will be described.

  Since the clock inversion signal CLK2 is a complementary signal to the clock signal CLK1, the clock inversion signal CLK2 is turned off when the clock signal CLK1 is on.

  Therefore, when the clock signal CLK1 is ON, the current i301 flowing through the collector terminal of the transistor Q1 flows through the transistor Q1. At this time, since the clock inversion signal CLK2 is OFF, the current i302 flowing through the collector terminal of the transistor Q2 does not flow through the transistor Q2. Therefore, the current i301 flows through the transistor Q1, reaches the constant current source I31, and flows to the ground. The current i301 flows through the transistor Q1, flows through the degeneration resistor Rsrc, reaches the constant current source I32, and flows to the ground. Therefore, a current flows through the transistors Q5, Q6, Q11, and Q12.

  When the clock inversion signal CLK2 is ON, the current i302 flows through the transistor Q2. At this time, since the clock signal CLK1 is OFF, the current i301 does not flow through the transistor Q1. Therefore, the current i302 flows through the transistor Q2, reaches the constant current source I31, and flows to the ground. The current i302 flows through the transistor Q2, flows through the degeneration resistor Rsrc as a resistor, reaches the constant current source I31, and flows to the ground. Therefore, current flows through the transistors Q7, Q8, Q9, and Q10.

  The IQ signal generator 32 includes four resistors R1, R2, R3, R4, eight transistors Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, and four capacitors C1, C2,. C3 and C4. Here, the transistors Q5 and Q6 form a differential pair, and the transistors Q7 and Q8, the transistors Q9 and Q10, and the transistors Q11 and Q12 each form a differential pair. The capacitor C1 is connected in parallel to the resistor R1. The capacitor C2 is connected in parallel with the resistor R2. The capacitor C3 is connected in parallel to the resistor R3. The capacitor C4 is connected in parallel with the resistor R4. The capacitors C1, C2, C3, and C4 are used for fine adjustment of the slew rate in addition to the common mode component and harmonic reduction. The capacitor can suppress malfunction of latch when frequency dividing is performed at an extremely low frequency. Conversely, if very high frequency operation is required, these capacitors are not necessary.

  The resistor R1 is connected to the transistors Q5 and Q7. Similarly, the resistor R2 is connected to the transistors Q6 and Q8, the resistor R3 is connected to the transistors Q9 and Q11, and the resistor R4 is connected to the transistors Q10 and Q12.

  Further, the emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected. Similarly, the emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected, the emitter terminal of the transistor Q9 and the emitter terminal of the transistor Q10 are connected, and the emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected. ing.

  Here, as described above, the emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected to the collector terminal of Q1 in the voltage-current converter 31. The emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected to the collector terminal of the transistor Q1 in the voltage-current converter 31. The emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected to the collector terminal of the transistor Q2 of the voltage-current converter 31. The emitter terminal of the transistor Q9 and the emitter terminal of the transistor Q10 are connected to the collector terminal of the transistor Q2 in the voltage-current converter 31.

  FIG. 8 shows the characteristics of the currents i101 and i102 with respect to the input voltage of the first embodiment and the output current with respect to the input voltage of the present embodiment, that is, the characteristics of the differential pair currents i301 and i302 with improved linearity. In short, by expanding the linear region, a change to the input voltage can be faithfully converted into a linear signal as a current signal. As a result, the AC current flowing through the degeneration resistor Rsrc generates currents i301 and i302 shown in FIG.

  Thus, in frequency divider D30 of the present embodiment, degeneration resistor Rsrc is connected between the emitter terminal of transistor Q1 and the emitter terminal of transistor Q2 that form a differential pair. Therefore, the linearity of the input / output characteristics of the voltage-current converter 31 can be improved by appropriately setting the resistance value of the degeneration resistor Rsrc. In addition, this reduces distortion current, and can obtain a signal with lower distortion as the output voltage, while reducing the number of elements and improving the accuracy of the output signal while maintaining the characteristics of reducing the harmonics of the local signal. can do.

[Embodiment 4]
The following will describe still another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first to third embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 3 are given the same reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 9, the frequency divider D <b> 40 according to the present embodiment includes a voltage-current conversion unit 41 and an IQ signal generation unit 42. The IQ signal generation unit 42 has the same configuration as the IQ signal generation unit 32 in the frequency divider D30, and thus the description thereof is omitted here.

  Below, the structure of the voltage-current conversion part 41 in FIG. 9 is shown.

  The voltage-current converter 41 shown in FIG. 9 includes a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, and a constant current source I41.

  Here, the relationship among the transistor Q1, the transistor Q2, the transistor Q3, and the transistor Q4 will be described.

  Transistor Q1 and transistor Q3 are Darlington connected. Transistor Q2 and transistor Q4 are Darlington connected.

  That is, in the transistors Q1 and Q3, the emitter terminal of the transistor Q3 is connected to the base terminal of the transistor Q1. The collector terminal of the transistor Q3 is connected to the power supply voltage VDD. Further, in the transistors Q2 and Q4, the emitter terminal of the transistor Q4 is connected to the base terminal of the transistor Q2. The collector terminal of the transistor Q4 is connected to the power supply voltage VDD.

  As a result, the emitter resistance of the differential pair appears to be multiplied by (1 + hfe) re as compared with the configurations of the first embodiment, the second embodiment, and the third embodiment, and thus the degeneration resistor Rsrc of the third embodiment. The linearity is improved as in the case of using, and the low distortion operation becomes possible. Here, hfe is a current amplification factor of the collector current with respect to the base current, and re is an emitter resistance.

  In the Darlington connection configuration shown below, the same characteristics as the differential pair currents i301 and i302 with improved linearity can be obtained as shown in FIG. That is, by expanding the linear region, it becomes possible to linearly convert a change with respect to the input voltage as a current signal.

  Here, as described above, the emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected to the collector terminal of Q1 in the voltage-current converter 41. The emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected to the collector terminal of the transistor Q1 in the voltage-current converter 41. The emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected to the collector terminal of the transistor Q2 of the voltage-current converter 41. The emitter terminal of the transistor Q9 and the emitter terminal of the transistor Q10 are connected to the collector terminal of the transistor Q2 in the voltage-current converter 41.

  The base terminal of the transistor Q3 is connected to the input terminal CLK1.

  The base terminal of the transistor Q4 is connected to the input terminal CLK2. However, the CLK signal input from the input terminal CLK2 is a complementary signal of the CLK signal input from the input terminal CLK1.

  The emitter terminal of the transistor Q1 is connected to the emitter terminal of the transistor Q2. The emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2 are connected to the constant current source I41. Further, the constant current source I41 is connected to the ground.

  Hereinafter, a current flow in the voltage-current conversion unit 41 illustrated in FIG. 9 will be described.

  At this time, since the clock inversion signal CLK2 is a complementary signal to the clock signal CLK1, the clock inversion signal CLK2 is turned off when the clock signal CLK1 is on.

  Therefore, when the clock signal CLK1 is ON, the current i401 flowing through the collector terminal of the transistor Q1 flows through the transistor Q1. At this time, since the clock inversion signal CLK2 is OFF, the current i402 flowing through the collector terminal of the transistor Q2 does not flow through the transistor Q2. Therefore, the current i401 flows through the transistor Q1, reaches the constant current source I41, and flows to the ground.

  Therefore, a current flows through the transistors Q5, Q6, Q11, and Q12.

  When the clock inversion signal CLK2 is ON, the current i402 flows through the transistor Q2. At this time, since the clock signal CLK1 is OFF, the current i401 does not flow through the transistor Q1. Therefore, the current i402 flows through the transistor Q2, reaches the constant current source I41, and flows to the ground. Therefore, current flows through the transistors Q7, Q8, Q9, and Q10.

  As described above, the frequency divider D40 of the present embodiment includes the first Darlington-connected transistor in which the transistor Q3 is Darlington-connected to the base terminal of the transistor Q1, and the second Darlington-connected transistor in which the transistor Q4 is connected to the base terminal of the transistor Q2. The input clock signal is input to the base terminal of the transistor Q3, and the complementary signal of the input clock signal is input to the base terminal of the transistor Q4.

  Therefore, the transconductance (gm) of the voltage-current converter 41 is reduced, and the linearity of the input / output characteristics of the voltage-current converter is increased. As a result, the distortion current is further reduced and a signal with a lower distortion can be obtained as the output voltage. The number of elements is reduced and the accuracy of the output signal is improved while maintaining the feature of reducing the harmonics of the local signal. can do.

  In the frequency divider D40 of the present embodiment, the collector terminal of the transistor Q3 and the collector terminal of the transistor Q4 are connected to the power supply voltage. Therefore, the number of elements can be reduced and the accuracy of the output signal can be improved while maintaining the characteristics of increasing the linearity and reducing the harmonics of the local signal. In addition, the common mode voltage range of the input in the Darlington connection configuration can be maximized.

[Embodiment 5]
The following will describe still another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first to fourth embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 4 are given the same reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 10, the frequency divider D50 of the present embodiment includes a voltage-current conversion unit 51 and an IQ signal generation unit 52. The IQ signal generation unit 52 has the same configuration as the IQ signal generation unit 32 in the frequency divider D30, and a description thereof will be omitted here.

  Below, the structure of the voltage-current conversion part 51 in FIG. 10 is shown.

  The voltage-current converter 51 of the frequency divider D50 shown in FIG. 10 includes a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, and a constant current source I51.

  Here, the relationship among the transistor Q1, the transistor Q2, the transistor Q3, and the transistor Q4 will be described.

  Transistor Q1 and transistor Q3 are Darlington connected. Transistor Q2 and transistor Q4 are Darlington connected.

  That is, as described above, in the transistors Q1 and Q3, the emitter terminal of the transistor Q3 is connected to the base terminal of the transistor Q1. In the transistors Q2 and Q4, the emitter terminal of the transistor Q4 is connected to the base terminal of the transistor Q2.

  Further, the emitter terminal of the transistor Q5 and the emitter terminal of the transistor Q6 are connected to the collector terminal of Q1 and the collector terminal of the transistor Q4 in the voltage-current converter 51. The emitter terminal of the transistor Q11 and the emitter terminal of the transistor Q12 are connected to the collector terminal of the transistor Q1 and the collector terminal of the transistor Q4 in the voltage-current converter 51. The emitter terminal of the transistor Q7 and the emitter terminal of the transistor Q8 are connected to the collector terminal of the transistor Q2 and the collector terminal of the transistor Q4 of the voltage-current converter 51. The emitter terminal of the transistor Q9 and the emitter terminal of the transistor Q10 are connected to the collector terminal of the transistor Q2 and the collector terminal of the transistor Q4 in the voltage-current converter 51.

  Further, the base terminal of the transistor Q3 is connected to the input terminal CLK1.

  The base terminal of the transistor Q4 is connected to the input terminal CLK2. However, the CLK signal input from the input terminal CLK2 is a complementary signal of the CLK signal input from the input terminal CLK1.

  The emitter terminal of the transistor Q1 is connected to the emitter terminal of the transistor Q2. The emitter terminal of the transistor Q1 and the emitter terminal of the transistor Q2 are connected to the constant current source I51. Further, the constant current source I51 is connected to the ground.

  Hereinafter, a current flow in the voltage-current conversion unit 51 illustrated in FIG. 10 will be described.

  At this time, since the clock inversion signal CLK2 is a complementary signal to the clock signal CLK1, the clock inversion signal CLK2 is turned off when the clock signal CLK1 is on.

  Therefore, when the clock signal CLK1 is ON, the current i501 flowing through the collector terminal of the transistor Q1 flows through the transistor Q1. At this time, since the clock inversion signal CLK2 is OFF, the current i502 flowing through the collector terminal of the transistor Q2 does not flow through the transistor Q2. Therefore, the current i501 flows through the transistor Q1, reaches the constant current source I51, and flows to the ground. Therefore, a current flows through the transistors Q5, Q6, Q11, and Q12.

  When the clock inversion signal CLK2 is ON, the current i502 flows through the transistor Q2. At this time, since the clock signal CLK1 is OFF, the current i501 does not flow through the transistor Q1. Therefore, the current i502 flows through the transistor Q2, reaches the constant current source I51, and flows to the ground. Therefore, current flows through the transistors Q7, Q8, Q9, and Q10.

  Thus, in the frequency divider D50 of the present embodiment, the first Darlington connection transistor and the second Darlington connection transistor are crossed and connected. Therefore, the number of elements can be reduced and the accuracy of the output signal can be improved with the configuration that increases the linearity and reduces the harmonics of the local signal. Also, the asymmetry of the input signal can be smoothed and distortion can be reduced.

  Further, the frequency divider D50 in the present embodiment is configured such that the Darlington-connected transistors have the above-described configuration, so that the current i501 and the current i502 are the main differential pair transistor and the auxiliary Darlington-connected transistor. The main terminal and the weak current are combined and canceled by reversing the phase of the collector terminal, and the asymmetric waveform at the CLK voltage input is smoothed and output as a current. As a result, the low distortion operation can be performed as in the fourth embodiment.

  In the above description, the configuration in which the frequency divider according to the present invention uses a flip-flop has been described. However, the present invention is not limited to this. That is, the frequency divider according to the present invention can be configured to use a NOR circuit, a NAND circuit, or the like that obtains a desired signal by using the timing of the clock.

  It is also possible to replace all the transistors with MOS transistors instead of bipolar transistors. However, since no current flows through the gate, only the Darlington connection configuration cannot be applied.

In the bipolar transistor, a current obtained by multiplying the base current Ib by the current amplification factor hfe flows as the collector current Ic. That is, the collector current Ic is
Ic = Ib × hfe
It becomes.

  The transconductance gm is expressed by the following formula (1).

  As can be seen from the third term of the above equation (1), the transconductance gm is substantially determined by the amount of current. On the other hand, when the degeneration resistor Rsrc is entered, it is expressed by the following equation (2).

  When the above equation (2) is satisfied, gm deteriorates but linearity increases. As shown in FIG. 7, when a resistor is inserted, the linear region increases as shown by the characteristics of the current i301 and the current i302. The linearity here means how faithfully it can be converted into a current for a minute input signal. When the gm is extremely high, the voltage-current conversion current cannot faithfully reproduce the voltage input waveform, and the input exceeds the threshold value, and becomes close to a square wave. In this case, the waveform contains many odd-order harmonics. When ultra-high speed operation is not the main, linearity may be secured at the expense of gm.

  Thus, when low distortion is realized by common input, the transconductance (gm) in the voltage-current conversion unit according to the present invention is set low, or in the case of a MOS transistor, the channel length is increased.

  With the above configuration, the linearity of the voltage-current converter can be further enhanced.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  Furthermore, in the present invention, as shown in FIG. 11, by mounting the frequency divider having the common voltage-current converter on a portable device or the like, IQ orthogonality accuracy is increased and image rejection performance is improved. Furthermore, when implemented without a feedback system, it is possible to reduce power consumption. Moreover, by using a degeneration or Darlington configuration for the voltage-current converter as described above, a low distortion operation can be expected.

  The frequency divider according to the present invention can simultaneously reduce the number of elements of the frequency divider, reduce the amplitude error, and reduce the distortion, and can be applied to a portable device. The configuration of the voltage-current conversion unit can also be applied to a mixer circuit or the like.

It is a circuit diagram which shows one Embodiment of the frequency divider in this invention. It is a block diagram which shows the concept of the said frequency divider. It is a circuit diagram which shows one Embodiment of the frequency divider in this invention. It is a circuit diagram which shows the structure of the voltage-current conversion part of the said frequency divider. It is a circuit diagram which shows the structure of the voltage-current conversion part which has the resistance of the said frequency divider. It is a circuit diagram which shows the structure of the voltage-current conversion part which has the resistance and current source of the said frequency divider. FIG. 6 is a circuit diagram showing still another embodiment of the frequency divider in the present invention. It is a figure which shows the output signal current of the voltage-current conversion part in the said frequency divider. FIG. 6 is a circuit diagram showing still another embodiment of the frequency divider in the present invention. FIG. 6 is a circuit diagram showing still another embodiment of the frequency divider in the present invention. It is a figure which shows the structure at the time of incorporating the said frequency divider in a portable apparatus. It is a figure which shows the relationship of the basic input / output of a frequency divider. It is a block diagram which shows the conventional frequency divider. It is a circuit diagram which shows the conventional frequency divider. It is a figure which shows the error dependence of the phase and amplitude of the image rejection rate of the conventional frequency divider. It is a figure which shows the output phase error by the current source offset dispersion | variation in the conventional frequency divider. It is a figure which shows the output amplitude error by the current source offset dispersion | variation in the conventional frequency divider. It is a figure which shows the output phase error by CLK input part offset dispersion | variation in the conventional frequency divider.

Explanation of symbols

11 Voltage-current converter (common voltage-current converter)
12 IQ signal generator (latch unit)
21 Voltage-current converter (common voltage-current converter)
31 Voltage-current converter (common voltage-current converter)
32 IQ signal generator (latch unit)
41 Voltage-current converter (common voltage-current converter)
42 IQ signal generator (latch unit)
51 Voltage-current converter (common voltage-current converter)
52 IQ signal generator (latch unit)
CLK1 Clock signal (input signal)
CLK2 Clock inversion signal (complementary signal)
D10 Frequency divider I11 Constant current source (current source)
I31 Constant current source (two current sources)
I32 constant current source (two current sources)
i101 Current (first current signal)
i102 Current (second current signal)
I201 Constant current source (one current source)
i201 current (first current signal)
i202 Current (second current signal)
i301 current (first current signal)
i302 Current (second current signal)
i401 current (first current signal)
i402 current (second current signal)
i501 current (first current signal)
i502 Current (second current signal)
Q1 transistor (first signal input transistor)
Q2 transistor (second signal input transistor)
Q5 transistor (second signal generator)
Q6 transistor (second signal generator)
Q7 transistor (fourth signal generator)
Q8 transistor (fourth signal generator)
Q9 transistor (third signal generator)
Q10 transistor (third signal generator)
Q11 transistor (first signal generator)
Q12 transistor (first signal generator)
R5 Negative feedback resistance (resistance)
R6 Negative feedback resistance (resistance)
Rsrc Degeneration resistance (resistance)

Claims (13)

Frequency division having a voltage-current conversion unit that receives a voltage input signal and two sets of frequency division signal generation units that generate a frequency division signal using the timing of the output current signal generated by the voltage-current conversion unit. In the vessel
The voltage-current converter comprises a pair of differential pairs, and drives the two sets of divided signal generators simultaneously using the timing of two output current signals. A common voltage-current converter that converts an input signal, which is a voltage signal, and its complementary signal into a current signal by using a first signal input transistor and a second signal input transistor forming a differential pair; ,
A first signal generator and a second signal generator that receive the first current signal output from the first signal input transistor and generate two first and second signals that are 180 degrees out of phase with each other. And a second current signal output from the second signal input transistor to generate two third and fourth signals that are 180 degrees out of phase with each other. A latch unit including a signal generation unit and a fourth signal generation unit,
The frequency division characterized in that the phase difference between the first signal and the third signal of the latch unit is 90 degrees, and the phase difference between the second signal and the fourth signal is 90 degrees vessel.   The emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor forming the common voltage-current converter are connected to each other, and the emitter terminal is connected to a current source. The frequency divider according to claim 2.   3. The frequency divider according to claim 2, wherein the common voltage-current converter has one current source.   The emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor constituting the common voltage-current converter are connected to each other, and the emitter terminal is connected to the ground. The frequency divider according to claim 2.   The emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor forming the common voltage-current converter are connected to each other, and the emitter terminal is connected to the ground via a resistor. The frequency divider according to claim 2, wherein:   3. A resistor is connected between the emitter terminal of the first signal input transistor and the emitter terminal of the second signal input transistor forming the common voltage-current conversion unit. Frequency divider.   8. The frequency divider according to claim 7, wherein one current source is connected to a middle point of the resistor.   The frequency divider according to claim 7, wherein two current sources are connected to both ends of the resistor. A first Darlington-connected transistor in which a third signal input transistor is Darlington-connected to a base terminal of the first signal input transistor forming the common voltage-current converter;
A second Darlington connection transistor in which a fourth signal input transistor is Darlington-connected to a base terminal of the second signal input transistor;
3. The input signal is input to a base terminal of the third signal input transistor, and a complementary signal of the input signal is input to a base terminal of the fourth signal input transistor. Frequency divider.   8. The frequency divider according to claim 7, wherein the collector terminal of the third signal input transistor and the collector terminal of the fourth signal input transistor forming the common voltage-current converter are connected to a power supply voltage. vessel.   8. The frequency divider according to claim 7, wherein the first Darlington connection transistor and the second Darlington connection transistor are connected to cross each other.   A portable device comprising the frequency divider according to claim 1.

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