CN107612542B - Regenerative frequency dividing circuit and high-frequency signal frequency dividing method - Google Patents
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Abstract
The invention discloses a regenerative frequency divider circuit, which consists of a frequency divider core unit, an output buffer, a first adjustable bias circuit and a second adjustable bias circuit; the differential input end of the frequency divider core unit is connected with an external high-frequency signal; the frequency divider core unit completes two frequency division of an external high-frequency signal to form a differential voltage signal, the differential voltage signal is transmitted to a differential input end of the output buffer through a differential output end connection of the frequency divider core unit, and the output buffer is used for shaping the output signal of the frequency divider core unit and suppressing common mode influence; the two sets of bias circuits bias the divider core and the output buffer. The circuit can work at a higher working frequency, and is beneficial to debugging of a later-stage circuit. The invention also discloses a frequency division method of the high-frequency signal, which can avoid the influence of non-ideal factors in the frequency division process, so that the circuit works under proper bias and is beneficial to integral correction.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a regenerative frequency dividing circuit and a high-frequency signal frequency dividing method.
Background
With the increasing development of wireless communication technology, the design of millimeter wave radar transceiver modules becomes more and more complex, and frequency dividers are important components of millimeter wave transceivers, and the performance of the frequency dividers directly affects the performance of the whole system. The frequency divider commonly used at present comprises a regenerative frequency divider and a master-slave frequency divider. Compared with a master-slave frequency divider, the regenerative frequency divider has higher highest working frequency and lower power consumption, and is suitable for the first stage of the multistage frequency divider cascade system.
Regenerative frequency dividers were originally proposed by Miller and have a structure as shown in fig. 1, in which an input signal is connected to one end of a Mixer (Mixer) and an output signal is connected to the other end of the Mixer. Under appropriate conditions, the two signals produce harmonic component signals ωin/2 and 3ωin/2, and after passing through a Low-pass Filter (LPF), the ωin/2 signal is left, thereby achieving divide-by-two.
The performance of the regenerative frequency divider is affected by the current of the regenerative frequency divider, and proper current bias can ensure that the regenerative frequency divider can work normally in a certain frequency range. However, in the production process of the regenerative frequency divider, the regenerative frequency divider is affected by various non-ideal factors, so that the circuit cannot normally work under a proper bias point. In the existing regenerative frequency divider technology, the working current is fixed in the design process, but the debugging of the later-stage circuit is not facilitated.
Disclosure of Invention
The invention aims to provide a regenerative frequency dividing circuit and a high-frequency signal frequency dividing method, so that the circuit can work at a higher working frequency, the circuit is ensured to work at a proper direct current point, and the debugging of a later-stage circuit is facilitated. In order to achieve the above purpose, the present invention adopts the following technical scheme:
a regenerative frequency divider circuit is composed of a frequency divider core unit, an output buffer, a first adjustable bias circuit and a second adjustable bias circuit. Differential input ends CLK and CLKx of the frequency divider core unit are connected with external high-frequency signals; the frequency divider core unit completes two frequency division of an external high-frequency signal to form a differential voltage signal, the differential output ends OUT2 and OUTx2 of the frequency divider core unit are connected and transmitted to differential input ends IN3 and INx3 of the output buffer, the output buffer converts the differential voltage signal into a current signal, and then the current signal is converted into a voltage signal to be output through differential output ends OUT3 and OUTx3 of the output buffer; the Bias voltage generated by the first adjustable Bias circuit passes through the Bias port Bias 1 Bias port Bias connected to divider core cell 2 The Bias voltage generated by the second adjustable Bias circuit passes through the Bias port Bias 4 Bias port Bias connected to output buffer 3 The first adjustable bias circuit and the second adjustable bias circuit are respectively connected with external control signals to realize bias adjustment of the frequency divider core unit and the output buffer.
The first adjustable Bias circuit comprises a first control unit for controlling Bias current and a first mirror circuit unit, wherein a plurality of control ports K1 connected with external control signals are arranged on the first control unit, and the ports of the first mirror circuit unit are Bias ports Bias 1 The method comprises the steps of carrying out a first treatment on the surface of the The second adjustable bias circuit comprises a control circuit for controlling biasThe second control unit for setting current and the second mirror circuit unit are provided with a plurality of control ports K4 connected with external control signals, and the ports of the second mirror circuit unit are Bias ports Bias 4 。
The frequency divider core unit comprises a bias circuit, a transconductance stage circuit, a switching stage circuit, a load stage circuit and a follower circuit; the Bias circuit port is Bias port Bias 2 The ports of the transconductance stage circuit are differential input ends CLK and CLKx, and the output ends of the follower circuit are differential output ends OUT2 and OUTx2. The frequency divider core unit passes through Bias 2 The port is connected with the port of the first adjustable Bias circuit Bias1 to form a current mirror Bias circuit, and Bias is provided for the frequency divider core unit; the transconductance stage circuit and the switching stage circuit are combined to form a Gilbert unit serving as a mixing circuit, external high-frequency signals are received through differential input ends CLK and CLKx, the transconductance stage circuit is modulated, current signals are output to the switching stage circuit, the signals are mixed after passing through the switching stage circuit, and the load stage circuit converts the mixed current signals into differential voltage signals and provides the differential voltage signals for the following circuit.
Further, follower circuit output terminals OUT2 and OUTx2 of the frequency divider core unit are respectively connected with switch stage circuit input terminals INx2 and IN2 to form a feedback loop of the circuit, and an output signal generated by the follower circuit is fed back to the switch stage circuit input terminals for mixing.
Further, the load stage circuit and the follower circuit form a low-pass filter to filter the mixed signal.
The output buffer comprises a bias circuit unit, a differential input stage circuit, an output load stage circuit and an output following circuit. The Bias circuit unit port is a Bias port Bias 3 The Bias circuit unit passes through Bias 3 Port and second adjustable Bias circuit Bias 4 The ports are connected and combined into a current mirror bias circuit to provide bias for the output buffer; differential input ends IN3 and INx3 of the differential input stage circuit receive differential signals of the frequency divider core unit, and the differential input stage circuit converts the differential voltage signalsForming a current signal; the output load stage circuit converts the current signal into a voltage signal and provides the voltage signal for the output follower circuit to output.
The invention also discloses a frequency division method of the high-frequency signal, which comprises the following steps,
a. the high-frequency input signal is input through a port, modulated and outputs a current signal;
b. the output current signal is modulated by the fed-back voltage signal, and mixed by the switching stage circuit to generate a 1/2 frequency division signal and a 3/2 frequency division signal;
c. filtering the mixed signal in the step b through a low-pass filter, filtering the 3/2 frequency-divided signal, and outputting the signal with the frequency of 1/2 frequency-divided signal;
d. and c, shaping and outputting the signal in the step, and controlling the amplitude of the output signal by fine tuning the bias current and inhibiting the influence of the common mode.
Preferably, in step c, if the frequency division cannot be performed normally, the frequency division unit is operated at a suitable operating point by trimming the bias current.
Preferably, in steps c, d, the bias current is trimmed by generating a bias voltage by a bias circuit, said bias circuit being controlled by a digital logic level.
Due to the adoption of the structure, the invention has the following beneficial effects:
1. the whole circuit architecture of the invention adopts a regenerative frequency divider structure as a frequency divider core unit of the circuit, so that the circuit can work at higher working frequency, and two groups of adjustable bias circuits are adopted to respectively control the working currents of the frequency divider core unit and an output buffer, thereby adjusting the working bandwidth of the frequency divider, ensuring that the circuit works at a proper direct current point and being beneficial to the debugging of the later-stage circuit.
2. The frequency divider is a dynamic frequency divider, and the circuit is a two-frequency dividing circuit based on an injection stage coupling logic (ECL), and can work at a higher working frequency relative to a static frequency divider.
3. The frequency dividing method can avoid the influence of non-ideal factors in the frequency dividing process, so that the frequency dividing process is beneficial to integral correction under proper bias.
4. The adjustable bias circuit can be expanded and designed through digital logic level control, and later calibration and design are facilitated.
Drawings
FIG. 1 is a diagram of a prior art regenerative divider;
FIG. 2 is a block diagram of a regenerative divider according to the present invention;
FIG. 3 is a block diagram of an adjustable bias circuit of a regenerative divider according to the present invention;
FIG. 4 is a block diagram of a regenerative divider core block according to the present invention;
FIG. 5 is a block diagram of a regenerative divider output buffer according to the present invention;
FIG. 6 is a circuit diagram of a regenerative divider first/second adjustable bias circuit according to embodiment 1 of the present invention;
FIG. 7 is a circuit diagram of a regenerative divider core block according to embodiments 1 and 2 of the present invention;
FIG. 8 is a circuit diagram of a regenerative divider output buffer according to embodiments 1 and 2 of the present invention;
FIG. 9 is a circuit diagram of a regenerative divider first/second adjustable bias circuit according to embodiment 2 of the present invention;
description of main reference numerals:
100: first adjustable bias circuit, 101: first mirror circuit unit, 102: first control unit, 200: frequency divider core unit, 201: bias circuit, 202: transconductance stage circuit, 203: switching stage circuit, 204: load stage circuit, 205: follower circuit, 300: output buffer, 301: bias circuit unit, 302: differential input stage circuit, 303: output load stage circuit, 304: and an output follower circuit. 400: second adjustable bias circuit, 401: a second mirror circuit unit, 402: and a second control unit.
Detailed Description
In order to make the technical scheme of the present invention better understood by those skilled in the art, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The invention discloses a frequency division method of a high-frequency signal, which comprises the following steps,
a. the high-frequency input signal is input through a port, modulated and outputs a current signal;
b. the output current signal is modulated by the fed-back voltage signal, and mixed by the switching stage circuit to generate a 1/2 frequency division signal and a 3/2 frequency division signal;
c. the mixed signal in the step b is filtered through a low-pass filter, the 3/2 frequency division signal is filtered, and the output signal frequency is the 1/2 frequency division signal. If the circuit can not divide frequency normally, the bias current of the frequency division core unit can be finely adjusted (controlled by digital logic level) so that the circuit works at a proper working point, and therefore the circuit can divide frequency normally.
d. And c, shaping and outputting the signal in the step, and controlling the amplitude of the output signal by fine tuning the bias current and inhibiting the influence of a common mode.
Based on the frequency division method, the invention discloses a regenerative frequency divider circuit. The circuit structure is described in detail below with reference to the accompanying drawings.
Example 1
As shown in fig. 2, the present invention discloses a regenerative frequency divider circuit, which is composed of a frequency divider core unit 200, an output buffer 300, a first adjustable bias circuit 100 and a second adjustable bias circuit 400. The integral frequency divider adopts a circuit structure of double-end differential input and double-end differential output.
1. First adjustable bias circuit 100 and second adjustable bias circuit 400
As shown in fig. 3, the first adjustable bias circuit 100 is identical to the overall circuit structure of the second adjustable bias circuit 400. The first adjustable bias circuit 100 comprises a first control unit 102 for controlling the bias current and a first mirror circuit unit 101. The first control unit 102 is provided with a control port K1 for connecting an external control signal 0 、K1 1 、K1 2 、K1 3 . The first mirror circuit unit 101 has a Bias port Bias 1 . The second adjustable bias circuit 400 includes a circuit for controlling biasA second control unit 402 of the current and a second mirror circuit unit 401. The second control unit 402 is provided with a control port K4 for connecting with an external control signal 0 、K4 1 、K4 2 、K4 3 The second mirror circuit unit 401 has a Bias port Bias 4 . The first adjustable bias circuit 100 and the second adjustable bias circuit 400 are respectively connected with external control signals through control ports, so that bias adjustment of the frequency divider core unit 200 and the output buffer 300 is realized.
As shown in fig. 6, the first adjustable bias circuit 100 and the second adjustable bias circuit 400 of the present embodiment each include 4 NMOS transistors M1 0 ~M1 3 7 resistors R1 0 ~R1 6 And 1 bipolar transistor Q1 1 . Control port K1 in default state 0 Connect to low potential to make M1 0 Disconnecting; k1 1 ~K1 3 The port is connected with high potential to make M1 1 ~M1 3 Conducting to obtain default bias current; when K1 is 0 ~K1 3 When all are connected with low potential, M1 0 ~M1 3 Turn off, the bias current is the smallest at this time, when K1 0 ~K1 3 When all are connected with high potential, M1 0 ~M1 3 Conducting, wherein the bias current is the largest; by configuring port K1 0 ~K1 3 The high and low levels are connected to control the magnitude of the current of the first adjustable bias circuit 100 (or the second adjustable bias circuit 400).
2. Frequency divider core unit 200
As shown in fig. 4, the frequency divider core 200 includes a bias circuit 201, a transconductance stage circuit 202, a switching stage circuit 203, a load stage circuit 204, and a follower circuit 205. The Bias circuit 201 has Bias port Bias 2 The ports of the transconductance stage circuit 202 are differential input terminals CLK and CLKx, and the output terminals of the follower circuit 205 are differential output terminals OUT2 and OUTx2. The working principle is as follows: the frequency divider core 200 is connected with Bias of the first adjustable Bias circuit 100 through Bias2 port 1 The port connections are combined into a current mirror bias circuit that provides bias to the divider core 200; the transconductance stage circuit 202 and the switching stage circuit 203 combine to form a gilbert cell acting as a mixer circuit, with external high frequency signals being differentiatedInputs CLK, CLKx are received, and the transconductance stage circuit 202 modulates, outputs a current signal to the switching stage circuit 203, mixes the signal after passing through the switching stage circuit 203, and the load stage circuit 204 converts the mixed current signal into a differential voltage signal and provides the differential voltage signal to the follower circuit 205. The output terminals OUT2, OUTx2 of the follower circuit 205 of the frequency divider core unit 200 are respectively connected with the input terminals INx2, IN2 of the switching stage circuit to form a feedback loop of the circuit, and the output signal generated by the follower circuit 205 is fed back to the input terminal of the switching stage circuit to be mixed. The output signal generated by the follower circuit 205 is fed back to the input terminal of the switching stage circuit 203 to be mixed, a 1/2 frequency-divided signal and a 3/2 frequency-divided signal are generated, and the load stage circuit 204 and the follower circuit 205 form a low-pass filter to filter the mixed signal. The resulting signal frequency at the final output (OUT 2, OUTx 2) is half the frequency of the input signal.
As shown in fig. 7, the core unit 200 of the present embodiment includes 8 bipolar transistors Q2 1 ~Q2 8 7 resistors R2 1 ~R2 7 And 2 capacitors C1, C2. The capacitors C1 and C2 are used to filter out the dc level. Q2 1 And Q2 2 Forms a transconductance stage circuit (202), Q2 3 ~Q2 6 The switching stage circuit 203 is formed and these two circuits are combined into a gilbert cell for achieving mixing of the input signal with the feedback signal. The load stage 204 is implemented with resistors, which form a low pass filter with the follower circuit 205. The output ports OUT2 and OUTx2 of the frequency divider are respectively connected to the input ports INx2 and IN2 of the switching stage circuit 203, and form a feedback loop of the circuit. A high frequency signal Vin passing through the ports CLK, CLKx, wherein the frequency of the high frequency signal Vin is fin, a feedback signal Vf passing through the ports IN2, INx 2; the gilbert cell mixes the high frequency signal Vin with the feedback signal Vf to generate a signal with frequencies 1/2fin and 3/2fin, wherein the 3/2fin signal is filtered by the low pass filter formed by the load stage circuit 204 and the switching stage circuit 203, thereby implementing a frequency division function, and finally the output signal frequency through the output ports OUT2 and OUTx2 is 1/2fin.
3. Output buffer
As shown in fig. 5, the output buffer300 includes a bias circuit unit 301, a differential input stage circuit 302, an output load stage circuit 303, and an output follower circuit 304. The working principle is as follows: the Bias circuit unit 301 has a Bias port Bias 3 Bias circuit unit 301 passes Bias 3 Bias of port and second adjustable Bias circuit 400 4 The port connections combine to form a current mirror bias circuit that provides a bias to the output buffer 300. Differential input stage circuit 302 differential inputs IN3, INx3 receive the differential signal of divider core 200, differential input stage circuit 302 converts the differential voltage signal into a current signal, output load stage circuit 303 converts the current signal into a voltage signal and provides the voltage signal to output follower circuit 304 for output.
Fig. 8 shows a schematic circuit diagram of an output buffer 300 of the present embodiment, including 7 bipolar transistors Q3 1 ~Q3 7 And 5 resistors R3 1 ~R3 5 。Q3 1 And Q3 2 A differential input pair (forming a differential input stage circuit 302) is formed that converts an input differential voltage signal into a current signal. The output load stage circuit 303 is directly implemented with resistors and functions to convert a current signal into a voltage signal. Q3 3 、Q3 6 And R3 4 Constitute a radio follower circuit, Q3 4 、Q3 7 And R3 5 Another emitter follower circuit is formed to realize a level shift function and to increase the driving capability of the circuit. Bias circuit unit 301 passes Bias 3 Bias of port and second adjustable Bias circuit 400 4 The ports are connected to form a current mirror bias circuit, and the bias current of the output buffer 300 can be controlled by the second adjustable bias circuit 400.
Example two
The present embodiment discloses a regenerative frequency divider circuit, which is different from the first embodiment in that the specific structures of the first and second adjustable bias circuits 100 and 400 are different from each other, as shown in fig. 9, the first and second adjustable bias circuits 100 and 400 of the present embodiment each include 4 PMOS transistors M5 0 ~M5 3 7 resistors R5 0 ~R5 6 And 1 bipolar transistor Q5 1 . In default state, control port K5 0 、K5 1 Connect with low level potential, PMOS tube M5 0 、M5 1 Conducting; control port K5 2 、K5 3 Connect with high level potential, PMOS tube M5 2 、M5 3 Turning off; at this point a default bias current is obtained. When K5 is 0 ~K5 3 When all are connected with low potential, M5 0 ~M5 3 Conduction is carried out, the bias current is the largest at the moment, and K5 0 ~K5 3 When all are connected with high potential, M5 0 ~M5 3 Turn off, the bias current at this time is minimal; by configuring port K5 0 ~K5 3 The connected high and low levels can control the magnitude of the current of the adjustable bias circuit (100 or 400).
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention.
Claims (7)
1. A regenerative divider circuit, characterized by: the frequency divider consists of a frequency divider core unit, an output buffer, a first adjustable bias circuit and a second adjustable bias circuit;
differential input ends CLK and CLKx of the frequency divider core unit are connected with external high-frequency signals; the frequency divider core unit completes two frequency division of an external high-frequency signal to form a differential voltage signal, the differential output ends OUT2 and OUTx2 of the frequency divider core unit are connected with differential input ends IN3 and INx3 which are transmitted to the output buffer, the output buffer shapes the output waveform of the frequency divider core unit, and the output waveform is output through differential output ends OUT3 and OUTx3 of the output buffer;
the Bias voltage generated by the first adjustable Bias circuit passes through the Bias port Bias 1 Bias port Bias connected to divider core cell 2 The Bias voltage generated by the second adjustable Bias circuit passes through the Bias port Bias 4 Bias port Bias connected to output buffer 3 The first adjustable bias circuit and the second adjustable bias circuit are respectively connected with external control signals, so that the voltage regulator is realBias adjustment is performed on the frequency divider core unit and the output buffer;
the frequency divider core unit comprises a bias circuit, a transconductance stage circuit, a switching stage circuit, a load stage circuit and a follower circuit; the Bias circuit port is Bias port Bias 2 The ports of the transconductance stage circuit are differential input ends CLK and CLKx, and the output ends of the follower circuit are differential output ends OUT2 and OUTx2;
the frequency divider core unit passes through Bias 2 Port and first adjustable Bias circuit Bias 1 The port connection is combined into a current mirror bias circuit to provide bias for the frequency divider core unit; the transconductance stage circuit and the switching stage circuit are combined to form a Gilbert unit, an external high-frequency signal is received through differential input ends CLK and CLKx, the transconductance stage circuit is modulated, a current signal is output to the switching stage circuit, the signal is mixed after passing through the switching stage circuit, and the load stage circuit converts the mixed current signal into a differential voltage signal and provides the differential voltage signal for the following circuit;
the output buffer comprises a bias circuit unit, a differential input stage circuit, an output load stage circuit and an output following circuit;
the Bias circuit unit port is a Bias port Bias 3 The Bias circuit unit passes through Bias 3 Port and second adjustable Bias circuit Bias 4 The ports are connected and combined into a current mirror bias circuit to provide bias for the output buffer; differential input ends IN3 and INx3 of the differential input stage circuit receive differential signals of the frequency divider core unit, and the differential input stage circuit converts the differential voltage signals into current signals; the output load stage circuit converts the current signal into a voltage signal and provides the voltage signal for the output follower circuit to output.
2. The regenerative divider circuit of claim 1, wherein: the first adjustable bias circuit comprises a first control unit for controlling bias current and a first mirror circuit unit, wherein a plurality of control ports K1 connected with external control signals are arranged on the first control unit, and the ports of the first mirror circuit unit are biasedPort Bias 1 The method comprises the steps of carrying out a first treatment on the surface of the The second adjustable Bias circuit comprises a second control unit for controlling Bias current and a second mirror circuit unit, wherein a plurality of control ports K4 connected with external control signals are arranged on the second control unit, and the ports of the second mirror circuit unit are Bias ports Bias 4 。
3. The regenerative divider circuit of claim 1, wherein: the follower circuit output ends OUT2 and OUTx2 of the frequency divider core unit are respectively connected with the switch stage circuit input ends INx2 and IN2 to form a feedback loop of the circuit, and output signals generated by the follower circuit are fed back to the switch stage circuit input ends for mixing.
4. The regenerative divider circuit of claim 3, wherein: the load stage circuit and the follower circuit form a low-pass filter to filter the mixed signals.
5. A method for dividing a frequency of a high frequency signal, comprising: the regenerative divider circuit according to any one of claims 1 to 4, comprising the steps of,
a. the high-frequency input signal is input through a port, modulated and outputs a current signal;
b. the output current signal is modulated by the fed-back voltage signal, and mixed by the switching stage circuit to generate a 1/2 frequency division signal and a 3/2 frequency division signal;
c. filtering the mixed signal in the step b through a low-pass filter, filtering the 3/2 frequency-divided signal, and outputting the signal with the frequency of 1/2 frequency-divided signal;
d. and c, shaping and outputting the signal in the step, and controlling the amplitude of the output signal by fine tuning the bias current and inhibiting the influence of the common mode.
6. The method for dividing a high frequency signal according to claim 5, wherein: in step c, if the frequency division cannot be performed normally, the frequency division unit is enabled to work at a proper working point by fine tuning the bias current.
7. The high frequency signal dividing method according to claim 5 or 6, wherein: in the steps c and d, the bias voltage is generated through the bias circuit, and the bias current is finely adjusted, wherein the bias circuit is controlled through the digital logic level.
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| CN101521506A (en) * | 2009-03-17 | 2009-09-02 | 浙江大学 | Device for preliminarily dividing frequency of high-speed wideband |
| CN101888245A (en) * | 2010-06-04 | 2010-11-17 | 西安电子科技大学 | GaAs HBT (Heterojunction Bipolar Transistor) super-high-speed 2-frequency divider |
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| CN207399175U (en) * | 2017-11-06 | 2018-05-22 | 厦门意行半导体科技有限公司 | A kind of regenerative frequency dividing circuit |
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| US7002412B2 (en) * | 2004-03-16 | 2006-02-21 | Agency For Science, Technology And Research | Transconductance circuit |
| US7102399B2 (en) * | 2004-03-31 | 2006-09-05 | Broadcom Corporation | Low-noise frequency divider |
| US7298183B2 (en) * | 2005-06-01 | 2007-11-20 | Wilinx Corp. | High frequency divider circuits and methods |
| CN101572549B (en) * | 2008-05-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Self-biased phase-locked loop and phase locking method |
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|---|---|---|---|---|
| CN101521506A (en) * | 2009-03-17 | 2009-09-02 | 浙江大学 | Device for preliminarily dividing frequency of high-speed wideband |
| CN101888245A (en) * | 2010-06-04 | 2010-11-17 | 西安电子科技大学 | GaAs HBT (Heterojunction Bipolar Transistor) super-high-speed 2-frequency divider |
| CN103501175A (en) * | 2013-10-24 | 2014-01-08 | 清华大学 | Millimeter-wave phase-locked loop |
| CN207399175U (en) * | 2017-11-06 | 2018-05-22 | 厦门意行半导体科技有限公司 | A kind of regenerative frequency dividing circuit |
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