JP2006093698A - Ultra-high frequency semiconductor element - Google Patents

Ultra-high frequency semiconductor element Download PDF

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JP2006093698A
JP2006093698A JP2005267652A JP2005267652A JP2006093698A JP 2006093698 A JP2006093698 A JP 2006093698A JP 2005267652 A JP2005267652 A JP 2005267652A JP 2005267652 A JP2005267652 A JP 2005267652A JP 2006093698 A JP2006093698 A JP 2006093698A
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measurement
electrode
pad
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high frequency
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JP5106767B2 (en
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Lee Chin-Ku
イ チン−ク
Lee Son-De
イ ソン−デ
Lee Buku-Hyon
イ ブク−ヒョン
Kim Samu-Don
キム サム−ドン
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Industry Academic Cooperation Foundation of Dongguk University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

<P>PROBLEM TO BE SOLVED: To implement accurate designing and reduction in the time required for designing an ultra-high frequency single-chip integrated circuit, by reducing the time and cost required for measuring a semiconductor element and by reducing the time and cost required in a semiconductor element modeling processes. <P>SOLUTION: The processes of forming and de-embedding measurement pads in a semiconductor element is omitted, and extended electrodes are used in place of de-embedded measurement pads of input-output terminals in a high-frequency semiconductor element, thereby eliminating the discontinuity characteristics, which occur in electrodes and measurement pads, in order to omit de-embedding processes required, when an ultra-high frequency single-chip integrated circuit is designed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は超高周波半導体素子に関する。   The present invention relates to an ultrahigh frequency semiconductor device.

超高周波単一チップ集積回路に用いられる超高周波半導体素子は、電界効果トランジスター（field effect transistor：ＦＥＴ）が主に用いられる。このような電界効果トランジスターの種類にはシリコン（Ｓｉ）を半導体基板として用いる金属−酸化物−半導体電界効果トランジスター（metal-oxide-semiconductor FET：ＭＯＳＦＥＴ）および相補的金属−酸化物−半導体電界効果トランジスター（complementary MOSFET：ＣＯＭＯＳ）などがあり、ガリウム−砒素（ＧａＡＳ）、ガリウム窒素（ＧａＮ）などの化合物半導体基板を用いる金属−半導体電界効果トランジスター（metal-semiconductor FET：ＭＥＳＦＥＴ）および高電子移動度トランジスター（high electron mobility transistor）などがある。   A field effect transistor (FET) is mainly used as an ultrahigh frequency semiconductor element used in an ultrahigh frequency single-chip integrated circuit. Such field effect transistors include metal-oxide-semiconductor FETs (MOSFETs) and complementary metal-oxide-semiconductor field effect transistors using silicon (Si) as a semiconductor substrate. (Complementary MOSFET: COMOS) and the like, metal-semiconductor field effect transistors (metal-semiconductor FETs: MESFETs) using compound semiconductor substrates such as gallium-arsenide (GaAS), gallium nitrogen (GaN), and high electron mobility transistors ( high electron mobility transistor).

これら超高周波半導体素子の構成はゲート、ドレインおよびソース以外に半導体素子の特性を測定するための測定用ゲートパッド、測定用ドレインパッドおよび測定用ソースパッドで構成される。これら素子は測定と素子の内部および外部的パラメーターを抽出するモデリング過程により特性を分析した後、超高周波単一チップ集積回路の能動素子として用いられて回路を設計する。   These ultra-high frequency semiconductor elements are composed of a measurement gate pad, a measurement drain pad and a measurement source pad for measuring the characteristics of the semiconductor element in addition to the gate, drain and source. These elements are characterized by measurement and modeling processes that extract internal and external parameters of the elements, and then used as active elements in ultra-high frequency single chip integrated circuits to design circuits.

従来の超高周波半導体素子は、ソースと測定用ソースパッドは信号接地面と連結されるため、素子の特性には多くの影響を及ぼさない。しかし、ゲートとドレインは素子の入出力に該当する部分では素子の特性に大きな影響を及ぼす。特に、測定用パッドは半導体素子で占める領域が大きいため、パッドによる寄生成分（parasitic element）を無視することができない。素子の使用周波数が高くなるほど周波数による寄生成分は回路設計時に大きな誤差を提供し得る問題点があり、また、従来の超高周波半導体素子はゲートおよびドレインと夫々の測定用パッドで線幅が変わる不連続区間が現われた。この部分での寄生成分により信号の反射が発生して周波数特性が変化するようになって回路設計に大きな誤謬を提供するようになるため、モデリング過程で必ずデ・エンベディング（de-embedding）過程を経なければならなかった。このようなデ・エンベディング過程は測定用パッド部分のみを更に製作しなければならなく、素子特性分析のためのモデリング過程で多くの時間を消耗するという問題点があった。   In the conventional ultra-high frequency semiconductor device, since the source and the measurement source pad are connected to the signal ground plane, the characteristics of the device are not greatly affected. However, the gate and the drain have a great influence on the characteristics of the element in the portion corresponding to the input / output of the element. In particular, since the measurement pad occupies a large area in the semiconductor element, a parasitic element due to the pad cannot be ignored. There is a problem that the parasitic component due to the frequency can provide a large error at the time of circuit design as the operating frequency of the element becomes higher. In addition, the conventional ultrahigh frequency semiconductor element has a problem that the line width does not change between the gate and the drain and each measurement pad. A continuous section appeared. The signal component is reflected due to the parasitic component in this part and the frequency characteristics change, thereby providing a large error in circuit design. Therefore, the de-embedding process must be performed in the modeling process. I had to go through. In such a de-embedding process, it is necessary to further manufacture only the pad portion for measurement, and there is a problem that much time is consumed in the modeling process for element characteristic analysis.

敷衍すると、図１の従来の超高周波半導体素子を集積回路の設計に用いる場合、ゲート電極およびドレイン電極と伝送線路を連結するためには夫々の電極と伝送線路の連結部についての再解釈が要求される。即ち、デ・エンベディング過程を経て測定用パッドおよび連結部に対する特性抽出がなされているとしても、集積回路の信号伝送線路と更に連結すると、また別の不連続性が発生する連結部が現われるようになって、これに対する新たな特性分析がなされなければならなかった。   As a result, when the conventional ultra-high frequency semiconductor device shown in FIG. 1 is used for designing an integrated circuit, it is necessary to reinterpret the connection portion between each electrode and the transmission line in order to connect the gate electrode and the drain electrode to the transmission line. Is done. In other words, even if the characteristics of the measurement pad and the connection part are extracted through the de-embedding process, a connection part that causes another discontinuity appears when it is further connected to the signal transmission line of the integrated circuit. Therefore, a new characteristic analysis for this had to be done.

従来の超高周波半導体素子は、ゲートとドレインは素子の入出力に該当する測定用パッドは半導体素子で占める領域が大きいため、パッドによる寄生成分を無視することができない。素子の使用周波数が高くなるほど周波数による寄生成分は回路設計時に大きな誤差を提供し得る問題点があり、また、従来の超高周波半導体素子はゲートおよびドレインと夫々の測定用パッドで線幅が変わる不連続区間が現われた。この部分での寄生成分により信号の反射が発生して周波数特性が変化するようになって回路設計に大きな誤謬を提供するようになるため、モデリング過程で必ずデ・エンベディング過程を経なければならなかった。このようなデ・エンベディング過程は測定用パッド部分のみを更に製作しなければならなく、素子特性分析のためのモデリング過程で多くの時間を消耗するという問題点があった。   In the conventional ultra-high frequency semiconductor element, the gate and drain have a large area occupied by the semiconductor element corresponding to the input / output of the element, and therefore, parasitic components due to the pad cannot be ignored. There is a problem that the parasitic component due to the frequency can provide a large error at the time of circuit design as the operating frequency of the element becomes higher. In addition, the conventional ultrahigh frequency semiconductor element has a problem that the line width does not change between the gate and the drain and each measurement pad. A continuous section appeared. Since the signal reflection occurs due to the parasitic component in this part and the frequency characteristic changes, which will provide a large error in circuit design, the de-embedding process must be performed in the modeling process. It was. In such a de-embedding process, it is necessary to further manufacture only the pad portion for measurement, and there is a problem that much time is consumed in the modeling process for element characteristic analysis.

本発明は従来の超高周波半導体素子における問題点を解消するために、ゲート電極、ドレイン電極およびソース電極と半導体素子の特性測定用ゲートパッド、測定用ドレインパッドおよび測定用ソースパッドで構成された超高周波半導体において、前記測定用ゲートパッドと測定用ドレインパッドの代わりに拡張電極が夫々構成されるようにして、超高周波単一チップ集積回路設計のために超高周波半導体素子の特性分析のためのモデリング過程でゲートとドレイン測定用パッドによる寄生成分を除去する超高周波半導体素子を提供するものである。   In order to solve the problems in the conventional ultra-high frequency semiconductor device, the present invention provides a gate electrode, a drain electrode, a source electrode, a semiconductor device characteristic measurement gate pad, a measurement drain pad, and a measurement source pad. In high-frequency semiconductors, an extended electrode is configured instead of the measurement gate pad and the measurement drain pad, and modeling for characteristic analysis of an ultra-high-frequency semiconductor device for designing an ultra-high frequency single-chip integrated circuit. It is an object of the present invention to provide an ultra-high frequency semiconductor device that removes parasitic components due to gate and drain measurement pads in the process.

ゲート電極、ドレイン電極およびソース電極と測定用ゲートパッド、測定用ドレインパッドおよび測定用ソースパッドで構成された超高周波半導体において、前記測定用ゲートパッドと測定用ドレインパッドの代わりに拡張電極が夫々構成されて、超高周波単一チップ集積回路設計のための能動素子のモデリング過程で、パッドの寄生成分を除去するためのデ・エンベディング過程を省略することができるので、モデリング過程に所要される費用と時間を最少化し得る。   In an ultra-high frequency semiconductor composed of a gate electrode, a drain electrode and a source electrode and a measurement gate pad, a measurement drain pad and a measurement source pad, an extended electrode is formed instead of the measurement gate pad and the measurement drain pad. In addition, since the de-embedding process for removing the parasitic component of the pad can be omitted in the modeling process of the active device for designing the ultra-high frequency single chip integrated circuit, the cost required for the modeling process is reduced. Time can be minimized.

前記ゲートおよびドレイン拡張電極の大きさは、超高周波単一チップ集積回路の設計時に回路構造と使用周波数帯域の伝送線路インピーダンス整合に合う大きさに製作されて、信号の伝送損失を最小化することをその特徴とする。   The size of the gate and drain extension electrodes should be designed to match the circuit structure and transmission line impedance matching of the frequency band used when designing an ultra-high frequency single-chip integrated circuit to minimize signal transmission loss. Is the feature.

また、前記測定用ソースパッドに入力および出力測定基準点を示す測定浮標を含み、回路に用いられる能動素子の全体の大きさが決定され、デ・エンベディング過程が不要な半導体素子の正確なモデリングがなされて、超高周波単一チップ集積回路の設計時に能動素子部分の正確な設計基準になることを特徴とする。   In addition, the measurement source pad includes a measurement buoy indicating input and output measurement reference points, the entire size of the active element used in the circuit is determined, and accurate modeling of a semiconductor element that does not require a de-embedding process is performed. Thus, it is characterized in that it becomes an accurate design standard for the active element portion when designing an ultra-high frequency single-chip integrated circuit.

本発明は半導体素子で測定用パッドの形成とデ・エンベディング過程を省略することにより、費用と時間を効果的に減らすことができる。即ち、本発明の超高周波半導体素子は入出力端の測定パッドの代わりに拡張電極を代置することにより、電極と測定パッド部分で発生する不連続特性を除去して超高周波単一チップ集積回路の設計時に必要なデ・エンベディング過程を省略することができるため、モデリング過程での時間と費用の節減が可能であり、超高周波単一チップ集積回路の設計において能動素子の正確な特性と大きさを提供することができるため、設計時間短縮と望む仕様への正確な設計が可能になる効果がある。   The present invention can effectively reduce the cost and time by omitting the formation of the measurement pad and the de-embedding process in the semiconductor device. That is, the super-high frequency semiconductor device of the present invention eliminates the discontinuous characteristics generated at the electrode and the measurement pad portion by substituting the extended electrode instead of the measurement pad at the input / output end, thereby removing the super-high frequency single chip integrated circuit. This eliminates the de-embedding process required during design, saving time and money during the modeling process, and the exact characteristics and size of active devices in designing ultra-high frequency single-chip integrated circuits. Therefore, the design time can be shortened and an accurate design to a desired specification can be achieved.

本発明による超高周波半導体素子と従来の超高周波半導体素子の構成を比較して示した添付図面を参照して詳細に説明する。   The super high frequency semiconductor device according to the present invention and a conventional super high frequency semiconductor device will be described in detail with reference to the accompanying drawings.

超高周波半導体素子の構成と本発明による超高周波半導体素子の構成を夫々図１と図２に示した。   The configuration of the ultrahigh frequency semiconductor device and the configuration of the ultrahigh frequency semiconductor device according to the present invention are shown in FIGS. 1 and 2, respectively.

図１は従来の超高周波半導体素子の構成図であって、その構成はゲート電極１１、ドレイン電極１２およびソース電極１３の外に測定のための夫々のパッド、即ち、測定用ゲートパッド１４、測定用ドレインパッド１５および測定用ソースパッド１６で構成されている。   FIG. 1 is a configuration diagram of a conventional ultra-high frequency semiconductor device, which has a configuration in addition to a gate electrode 11, a drain electrode 12, and a source electrode 13, that is, respective pads for measurement, that is, a measurement gate pad 14, a measurement. The drain pad 15 for measurement and the source pad 16 for measurement are comprised.

図２は本発明による超高周波半導体素子の構成図であって、ゲート電極２１、ドレイン電極２２、ソース電極２３および測定用ソースパッド２６とゲート拡張電極２４とドレイン拡張電極２５から成っている。   FIG. 2 is a block diagram of an ultrahigh-frequency semiconductor device according to the present invention, which comprises a gate electrode 21, a drain electrode 22, a source electrode 23, a measurement source pad 26, a gate extension electrode 24, and a drain extension electrode 25.

前記図１と図２において、ゲート電極、ドレイン電極、ソース電極および測定用ソースパッドは、本発明による超高周波半導体素子と従来の超高周波半導体素子が同一の構成を有するが、本発明による超高周波半導体素子が従来の超高周波半導体素子で測定用ゲートパッドと測定用ドレインパッドの代わりにゲート拡張電極およびドレイン拡張電極が代置された構造を有している構造上の差異点を有する。   1 and 2, the gate electrode, the drain electrode, the source electrode, and the source pad for measurement have the same configuration as the ultrahigh frequency semiconductor device according to the present invention and the conventional ultrahigh frequency semiconductor device. The semiconductor device is a conventional ultra-high frequency semiconductor device and has a structural difference in which a gate extension electrode and a drain extension electrode are substituted for the measurement gate pad and the measurement drain pad.

図１の従来の超高周波半導体素子の構成において、ゲート電極と測定用ゲートパッドの連結部分およびドレイン電極と測定用ドレインパッドとの連結部分で線幅が変わる不連続区間で現われる信号伝送の不連続性と、測定用パッドによる寄生成分を除去する過程をデ・エンベディングと言う。   In the configuration of the conventional ultrahigh frequency semiconductor device of FIG. 1, the signal transmission discontinuity appears in the discontinuous section where the line width changes at the connecting portion between the gate electrode and the measuring gate pad and at the connecting portion between the drain electrode and the measuring drain pad. The process of removing the parasitic components from the measurement pads is called de-embedding.

超高周波半導体素子の特性を測定した後、超高周波単一チップ集積回路設計のために超高周波半導体素子の特性を夫々の必要に合うよう抽出する過程を経るようになるが、このような過程全体をモデリングと言い、モデリング過程には電極とパッドの連結部で現われる信号伝送の不連続性とパッドによる寄生成分を除去するデ・エンベディング過程が含まれている。このようなデ・エンベディング過程を遂行するためには超高周波半導体素子の製作時に用いられた半導体基板と同一の基板上に測定用パッドのみを別途に製作してその特性を測定した後、超高周波半導体素子の特性から測定用パッド成分を除くようになる。従って、デ・エンベディング過程を遂行するには超高周波半導体素子の製作工程と同一の方法で測定用パッドのみを製作しなければならなく、同一の方法で測定をしなければならないため、これにより測定用パッド製作と測定のために費用と時間の投資を必要とする短点がある。   After measuring the characteristics of the ultra-high frequency semiconductor device, the process of extracting the characteristics of the ultra-high frequency semiconductor device to meet the respective needs for the design of the ultra-high frequency single-chip integrated circuit is performed. Is called modeling, and the modeling process includes a de-embedding process that removes the discontinuity of signal transmission that appears at the connection between the electrode and the pad and the parasitic component due to the pad. In order to perform such a de-embedding process, only a measurement pad is separately manufactured on the same substrate as the semiconductor substrate used for manufacturing the ultra-high frequency semiconductor element, and its characteristics are measured. The pad component for measurement is removed from the characteristics of the semiconductor element. Therefore, in order to perform the de-embedding process, only the measurement pad must be manufactured by the same method as the manufacturing process of the ultra-high frequency semiconductor device, and the measurement must be performed by the same method. There are shortcomings that require cost and time investment for pad manufacturing and measurement.

本発明による超高周波半導体素子は、構成における若干の変化のみで前記の短点を解消することができる。即ち、測定用ゲートパッドと測定用ドレインパッドの代わりにゲート拡張電極およびドレイン拡張電極を代置することにより、素子のモデリング過程でデ・エンベディング過程を排除することができる。   The super-high frequency semiconductor device according to the present invention can eliminate the shortcomings with only a slight change in configuration. That is, by replacing the gate extension electrode and the drain extension electrode in place of the measurement gate pad and the measurement drain pad, the de-embedding process can be eliminated in the device modeling process.

測定用ゲートパッドと測定用ドレインパッドの代わりにゲート拡張電極とドレイン拡張電極が代置された理由は次の通りである。   The reason why the gate extension electrode and the drain extension electrode are replaced in place of the measurement gate pad and the measurement drain pad is as follows.

図１の従来の超高周波半導体素子の構成において、一点鎖線で表示されたゲート電極１１と測定用ゲートパッド１４の連結部分１７およびドレイン電極１２と測定用ドレインパッド１５との連結部分１８で線幅が急激に変わって信号伝送で不連続特性が現われるようになり、損失が増加するようになる。このような不連続部分は超高周波単一チップ集積回路の設計で誤謬を犯すようになる。   In the configuration of the conventional ultrahigh frequency semiconductor device of FIG. 1, the line width is represented by the connecting portion 17 between the gate electrode 11 and the measuring gate pad 14 and the connecting portion 18 between the drain electrode 12 and the measuring drain pad 15 indicated by a one-dot chain line. Changes abruptly, discontinuous characteristics appear in signal transmission, and loss increases. Such discontinuities can cause errors in the design of ultra-high frequency single chip integrated circuits.

また、図１における各測定用パッド１４，１５，１６は、超高周波単一チップ集積回路の設計において適用されなかった部分で回路設計のための能動素子特性抽出過程で測定用パッドによる寄生成分に対する特性を除去するようになる。測定用パッドは超高周波半導体素子で占める領域が大きく、集積回路の使用周波数が増加するほど測定用パッドによる寄生成分も共に増加するため、能動素子の特性抽出過程ではこのような測定用パッドの寄生成分を必ず除去しなければならない。特に、測定用ゲートと測定用ドレインパッドの寄生成分は一層注意を要するようになる。測定用ソースパッドは信号接地面部分と連結されるため、測定用ソースパッドによる寄生成分が超高周波半導体素子の特性には多くの影響を及ぼさないが、測定用ゲートパッドと測定用ドレインパッドは素子の入出力に該当する部分であるため、それらの寄生成分は素子の特性に至大な影響を及ぼす。このような測定用パッドによる寄生成分は回路の設計時に大きな誤差を与える問題点がある。   Further, each of the measurement pads 14, 15, and 16 in FIG. 1 is a part that is not applied in the design of the ultra-high frequency single chip integrated circuit, and is used for the parasitic component due to the measurement pad in the active element characteristic extraction process for circuit design. The characteristic will be removed. The measurement pad occupies a large area of the super-high frequency semiconductor element, and the parasitic component due to the measurement pad increases as the operating frequency of the integrated circuit increases. Therefore, in the process of extracting the characteristics of the active element, Ingredients must be removed. In particular, the parasitic components of the measurement gate and the measurement drain pad require more attention. Since the measurement source pad is connected to the signal ground plane part, the parasitic component due to the measurement source pad does not greatly affect the characteristics of the ultra-high frequency semiconductor element, but the measurement gate pad and the measurement drain pad are not elements. These parasitic components greatly affect the characteristics of the device. Such a parasitic component due to the measurement pad has a problem of giving a large error when designing a circuit.

図２に図示された通り、本発明による超高周波半導体素子のゲート電極２１およびドレイン電極２２の各拡張電極２４，２５は、夫々その一端の線幅が徐々に減るように形成されて該当ゲート電極２１およびドレイン電極２２に直ちに連結されるので、従来の高周波半導体素子の連結部で発生する不連続性を無くすことができる。   As shown in FIG. 2, each of the extended electrodes 24 and 25 of the gate electrode 21 and the drain electrode 22 of the ultrahigh frequency semiconductor device according to the present invention is formed so that the line width at one end thereof is gradually reduced. 21 and the drain electrode 22 are immediately connected to each other, so that the discontinuity generated at the connecting portion of the conventional high-frequency semiconductor element can be eliminated.

図１におけるような従来の超高周波半導体素子の場合、測定用パッド１４，１５，１６の大きさは超高周波単一チップ集積回路の信号伝送線路３１，４１の大きさとは関係が無く一定の大きさに構成されるため、夫々の電極１１，１２，１３と夫々の測定用パッド１４，１５，１６との連結部で線幅が急激に変わるようになるが、本発明による超高周波半導体素子におけるゲート拡張電極２４とドレイン拡張電極２５は超高周波単一チップ集積回路の信号伝送線路３１，４１と直ちに連結されることができるため、ゲート電極２１およびドレイン電極２２と夫々の拡張電極２４，２５間の線幅変化が急でなく、集積回路の信号伝送線路３１，４１に連続的に連結されるように設計が可能であるため、前記の問題点を解決することができる。   In the case of the conventional ultra-high frequency semiconductor device as shown in FIG. 1, the size of the measurement pads 14, 15, 16 is not related to the size of the signal transmission lines 31, 41 of the ultra-high frequency single chip integrated circuit, and is constant. Therefore, the line width changes abruptly at the connecting portion between each of the electrodes 11, 12, 13 and each of the measurement pads 14, 15, 16 in the ultrahigh frequency semiconductor device according to the present invention. Since the gate extension electrode 24 and the drain extension electrode 25 can be immediately connected to the signal transmission lines 31 and 41 of the ultra-high frequency single chip integrated circuit, the gate electrode 21 and the drain electrode 22 are connected to the respective extension electrodes 24 and 25. The above-mentioned problem can be solved since the design can be made so that the line width of the line is not abruptly changed and is continuously connected to the signal transmission lines 31 and 41 of the integrated circuit.

また、本発明による超高周波半導体素子を超高周波単一チップ集積回路の能動素子として用いる場合、回路の使用周波数によりゲートおよびドレイン拡張電極２４，２５の幅が決定される。   When the ultrahigh frequency semiconductor device according to the present invention is used as an active device of an ultrahigh frequency single chip integrated circuit, the widths of the gate and drain extension electrodes 24 and 25 are determined by the frequency of use of the circuit.

超高周波単一チップ集積回路は、信号の伝送線路を図３のマイクロストリップライン（microstrip line）または図４の同一平面上導波管（coplanar waveguide：ＣＰＷ）のうちいずれを用いるかによって構造を異に用いる。   The ultra-high frequency single-chip integrated circuit has a different structure depending on whether the signal transmission line is a microstrip line in FIG. 3 or a coplanar waveguide (CPW) in FIG. Used for.

図３はマイクロストリップラインの構造を示したもので、半導体基板３３の上面には信号の伝送線路３１を形成し、基板の下面には信号接地面３２を形成したものである。信号伝送線路３１の幅は半導体基板の誘電率と厚さおよび集積回路の使用周波数により決定される。   FIG. 3 shows the structure of a microstrip line, in which a signal transmission line 31 is formed on the upper surface of the semiconductor substrate 33 and a signal ground plane 32 is formed on the lower surface of the substrate. The width of the signal transmission line 31 is determined by the dielectric constant and thickness of the semiconductor substrate and the operating frequency of the integrated circuit.

図４は図３とは異に半導体基板４３の上面に信号の伝送線路４１と信号接地面４２が同一平面上導波管の構造を示している。同一平面上導波管は使用周波数によって信号伝送線路４１の幅と信号伝送線路と信号接地面４２との間隔が決定される。   FIG. 4 shows a structure of a waveguide having a signal transmission line 41 and a signal ground plane 42 on the same plane on the upper surface of a semiconductor substrate 43, unlike FIG. In the coplanar waveguide, the width of the signal transmission line 41 and the distance between the signal transmission line and the signal ground plane 42 are determined by the operating frequency.

マイクロストリップラインまたは同一平面上導波管の信号伝送線路３１，４１の線幅は、特性インピーダンスが５０Ωになるように用いるが、その理由は信号伝送での伝送損失を最小化するからである。従って、使用周波数によって夫々の信号伝送線路３１，４１の幅は５０Ωを有するように設計する。   The line widths of the signal transmission lines 31 and 41 of the microstrip line or the coplanar waveguide are used so that the characteristic impedance is 50Ω because the transmission loss in signal transmission is minimized. Therefore, the width of each signal transmission line 31, 41 is designed to have 50Ω depending on the frequency used.

このような線路の伝送線路と超高周波半導体素子を集積回路の設計に用いる場合、信号の伝送線路はゲート電極とドレイン電極に連結される。   When such a transmission line and an ultrahigh frequency semiconductor device are used for designing an integrated circuit, the signal transmission line is connected to a gate electrode and a drain electrode.

以上のごとき構造の本発明による超高周波半導体素子を用いる場合には、ゲート電極２１およびドレイン電極２２が集積回路の信号伝送線路と同一の線幅を有する夫々の拡張電極２４，２５と連結されており、集積回路の設計時に拡張電極が信号の伝送線路と連結されるため、電極と拡張電極の連結部に対し付加的に特性分析が必要でない。   When the ultrahigh frequency semiconductor device according to the present invention having the above-described structure is used, the gate electrode 21 and the drain electrode 22 are connected to the respective extension electrodes 24 and 25 having the same line width as the signal transmission line of the integrated circuit. In addition, since the extension electrode is connected to the signal transmission line at the time of designing the integrated circuit, no additional characteristic analysis is required for the connection portion between the electrode and the extension electrode.

この理由により本発明による超高周波半導体素子のゲート拡張電極およびドレイン拡張電極の幅は、回路の使用周波数によって信号伝送線路の幅と同一の大きさに決定される。   For this reason, the width of the gate extension electrode and the drain extension electrode of the ultrahigh frequency semiconductor device according to the present invention is determined to be the same as the width of the signal transmission line depending on the frequency of use of the circuit.

また、半導体素子の特性に影響を及ぼさないソース測定用パッド２６に入力および出力測定基準を示す測定浮標２７，２８を構成して、素子測定時に測定プローブ（probe）が測定浮標までのみ接触されるようにする。そうすると、回路に用いられる能動素子の全体大きさが決定され、デ・エンベディング過程が不要な半導体素子の正確なモデリングがなされ、超高周波単一チップ集積回路の設計時に能動素子の入出力部分に対する正確な設計基準になる。   Further, the measurement buoys 27 and 28 indicating the input and output measurement standards are formed on the source measurement pad 26 that does not affect the characteristics of the semiconductor element, and the measurement probe is contacted only to the measurement buoy at the time of element measurement. Like that. As a result, the overall size of the active element used in the circuit is determined, the semiconductor element that does not require the de-embedding process is accurately modeled, and the input / output portion of the active element is accurately determined when designing an ultra-high frequency single-chip integrated circuit. Design standards.

従来の超高周波半導体素子の平面図である。It is a top view of the conventional superhigh frequency semiconductor element. 本発明による超高周波半導体素子の平面図である。It is a top view of the ultrahigh frequency semiconductor device by this invention. 超高周波単一チップ集積回路におけるマイクロストリップラインの構造図である。FIG. 3 is a structural diagram of a microstrip line in an ultra-high frequency single chip integrated circuit. 超高周波単一チップ集積回路における同一平面上導波管の構造図である。FIG. 3 is a structural diagram of a coplanar waveguide in an ultra-high frequency single chip integrated circuit.

符号の説明Explanation of symbols

１１、２１ ゲート電極
１２、２２ ドレイン電極
１３、２３ ソース電極
１４ 測定用ゲートパッド
１５ 測定用ドレインパッド
１６、２６ 測定用ソースパッド
１７ ゲート電極と測定用ゲートパッドとの連結部
１８ ドレイン電極と測定用ドレインパッドとの連結部
２４ ゲート拡張電極
２５ ドレイン拡張電極
２７ 入力（ゲート）端測定浮標
２８ 出力（ドレイン）端測定浮標
３１、４１ 信号の伝送線路
３２、４２ 信号接地面
３３、４３ 半導体基板 DESCRIPTION OF SYMBOLS 11, 21 Gate electrode 12, 22 Drain electrode 13, 23 Source electrode 14 Measurement gate pad 15 Measurement drain pad 16, 26 Measurement source pad 17 Connection part of gate electrode and measurement gate pad 18 Drain electrode and measurement Connection part with drain pad 24 Gate extension electrode 25 Drain extension electrode 27 Input (gate) end measurement buoy 28 Output (drain) end measurement buoy 31, 41 Signal transmission line 32, 42 Signal ground plane 33, 43 Semiconductor substrate

Claims (3)

ゲート電極、ドレイン電極およびソース電極を備えた超高周波単一チップ集積回路の能動素子として用いられる超高周波半導体素子であって、
前記ゲート電極の代わりにゲート拡張電極と、前記ドレイン電極の代わりにドレイン拡張電極と、前記ソース電極の代わりに測定用ソースパッドを備えてなる
ことを特徴とする超高周波半導体素子。 An ultra-high frequency semiconductor element used as an active element of an ultra-high frequency single chip integrated circuit having a gate electrode, a drain electrode and a source electrode,
An ultrahigh frequency semiconductor device comprising: a gate extension electrode instead of the gate electrode; a drain extension electrode instead of the drain electrode; and a measurement source pad instead of the source electrode. 前記能動素子のゲート拡張電極およびドレイン拡張電極の平面的形状と段差形状が、超高周波単一チップ集積回路を構成する複数の能動素子を電気的に連結した場合、各能動素子間において使用周波数帯域の伝送線路インピーダンス整合が取れるように設定されたことを特徴とする請求項１記載の超高周波半導体素子。 When the planar shape and the step shape of the gate extension electrode and the drain extension electrode of the active element electrically connect a plurality of active elements constituting an ultrahigh frequency single-chip integrated circuit, a frequency band used between the active elements 2. The ultrahigh frequency semiconductor device according to claim 1, wherein the transmission line impedance is set to be matched. 前記測定用ソースパッドに入力および出力基準点を示す測定浮標が設けられることを特徴とする請求項１記載の超高周波半導体素子。 2. The ultrahigh frequency semiconductor device according to claim 1, wherein a measurement buoy indicating input and output reference points is provided on the measurement source pad.
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