JP2006092522A - Bus control method and circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a hang-up to the utmost by executing the same access processing as previous one again without immediate initialization even when a ready signal RDY has not become active. <P>SOLUTION: A bus control method that, at a reading operation or writing operation on an external I/O device 20, completes the processing of the bus cycle of the access when a ready signal RDY input from the external I/O device 20 becomes active, if the ready signal RDY has not become active in a prescribed time, aborts the current bus cycle to recover a non-access state and, in the non-access state, executes the bus cycle of the same access as previous one again. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus control method and circuit for exchanging data with an external circuit, and particularly forcibly to a non-access state when a ready signal is not valid and cannot be restored from an access state for some reason. The present invention relates to a bus control method and a circuit that are restored and then accessed again.

  As seen in Patent Document 1, in a microcontroller that has started a read operation or a write operation, in a built-in bus control circuit, a ready signal that is one signal of a handshake signal constituting a bus control signal becomes effective. For the convenience of waiting and completing the process, if the ready signal is not valid for some reason, the process cannot be completed forever and hangs up. The fact that the microcontroller and its central CPU hang up is nothing less than that the entire system hangs up.

Therefore, in order to avoid this problem, in Patent Document 1, when the ready signal does not become effective even after a certain time, the CPU is initialized to avoid the hang-up from continuing for a long time. ing.
Japanese Patent Application Laid-Open No. 07-084835

  However, initializing the CPU means giving up all of the processing executed so far, and it is a last resort. If the ready signal is not valid due to an accidental reason (for example, noise mixing), there is a possibility that no problem will occur if the same processing is executed again. Further, when access is not successful even if the same processing is executed again, it is difficult to specify the access target, reset only the target module, and perform initial setting.

  The present invention has been made paying attention to this point, and even if the ready signal is not valid, the same access processing as the previous time is executed again without being initialized immediately, so as to hang up as much as possible. In addition, if the same access process is executed again and again multiple times, it will be possible to reset only the access target and continue the subsequent processing. It is an object of the present invention to provide a bus control method and a circuit that increase the possibility of such a problem.

  In the invention of the bus control method, when a read operation or a write operation is performed on an external circuit using a CPU, the read or write access is performed based on a ready signal input from the external circuit being valid. In the bus control method that completes the processing of the bus cycle, when the ready signal does not become effective even after a specified time, the current bus cycle is stopped to return to the non-access state, and after entering the non-access state The bus cycle of the same access as the previous time is executed again.

  Here, when the number of executions of the bus cycle of the same access reaches a specified number, it is desirable to end the processing of the bus cycle and output a signal that can be used as an interrupt or reset.

  It is also desirable that when the number of executions of the same access bus cycle reaches a specified number, the processing of the bus cycle is terminated and information related to the access is stored.

  Further, it is desirable to perform data processing for causing the CPU to read the stored access information.

  The invention of the bus control circuit is connected to an external circuit via a bus and a control line, and outputs a read control signal or a write control signal to the external circuit based on a read or write command from the CPU. When reading or writing, in the bus control circuit that completes the processing of the bus cycle of the access based on the ready signal input from the external circuit becoming valid, the external control is performed based on a read or write command from the CPU. A read / write circuit that generates and outputs the read control signal or the write control signal to the circuit, and outputs the read control signal or the write control signal from the read / write circuit to the external circuit Bus cycle measurement circuit that outputs a retry signal when the specified time has passed without the ready signal being valid. And the read / write circuit temporarily cancels the read control signal or the write control signal and generates it again when the retry signal is output from the bus cycle measuring circuit. A bus cycle of the same access is executed.

  Here, when the read control signal or the write control signal is generated, the bus cycle measuring circuit once cancels the time measuring operation and then restarts the measuring operation, and after the retry signal is output. Preferably, the measurement operation is canceled when the read control signal and the write control signal are canceled.

  It is also desirable to provide a retry count measurement circuit that outputs a signal that can be used as an interrupt or reset when the number of retry signals generated by the bus cycle measurement circuit is measured and reaches a specified number.

  Furthermore, it is preferable that the retry count measurement circuit cancels the retry count measurement operation when the ready signal becomes valid before the measured value of the retry count reaches the specified count.

  Furthermore, it is desirable to further include an access content storage circuit that stores information related to the access when the measured value of the retry count measured by the retry count measurement circuit reaches the specified count.

  Further, it is desirable to further include a data processing circuit that performs data processing for causing the CPU to read information related to the access stored in the access content storage circuit.

  According to the present invention, when the ready signal is not valid for some reason, the same access bus cycle as the previous time is executed again to increase the chance of normal completion of the bus access. It can be avoided. In addition, even if the bus access ends abnormally, by storing the access contents to the target device, resetting and setting the target device using an interrupt etc., the subsequent processing The possibility of continuing increases. As a result, the opportunity for resetting (restarting) the entire system can be reduced.

  In this embodiment, the access waits until a ready signal used when performing a read operation or a write operation on an external circuit such as a memory or an I / O device connected to the outside of the microcontroller becomes valid. In the bus control circuit that notifies the CPU of the completion of processing of the bus cycle, when the ready signal is not valid for a long time, it is forcibly viewed from the external bus (= external bus connected to the I / O device or memory). A) Stop the current bus cycle, forcibly return to the non-access state, and execute the same access bus cycle as the previous time after returning. If the ready signal does not become effective even if the same bus cycle is re-executed a specified number of times, a signal that can be used as an interrupt request or reset is output to the CPU, or the signal is further advanced and By storing the access contents to the target device, it is possible to easily perform reset and setting processing from the CPU or the like to the target device using an interrupt or the like.

  FIG. 1 is a block diagram showing a bus control circuit and its peripheral circuit portion according to the first embodiment of the present invention. In FIG. 1, A [15: 0] is a 16-bit address bus, and is connected from the microcontroller 10 to the external I / O device 20. D [7: 0] is an 8-bit data bus, and is bi-directionally connected to the microcontroller 10 and the external I / O device 20.

  CPU_RDN and CPU_WRN are a read control signal and a write control signal (Low Active) that are set to “L” when reading and writing from a CPU (not shown) to the outside, respectively. The CPU receives the read end signal RD_END and the write end signal WR_END “H” from the bus control circuit 11 and ends the read cycle, the write cycle, that is, the bus cycle. The read end signal RD_END and the write end signal WR_END are used when the bus control circuit 11 completes taking in valid data from the external I / O device 20 or when valid data writing to the external I / O device is completed. The signal becomes “H” at (High Active).

  A read control signal RDN and a write control signal WRN from the bus control circuit 11 to the external I / O device 20 are output based on a read control signal CPU_RDN and a write control signal CPU_WRN from the CPU, respectively. However, this is for providing bus timing in consideration of the timing with the effective input of the ready signal RDY used for handshaking with an external circuit such as a memory or an I / O device. Due to the presence of the bus control circuit 11, when it is necessary to connect to various external I / O devices, memories, etc., the bus control circuit 11 which tends to be complicated is separated from the CPU itself, so that the CPU itself There is an advantage that the specifications and design for reading and writing are easy.

  In the first embodiment, an RDN_WRN generation circuit 111 as a read / write circuit, a bus cycle measurement circuit 112, and a retry count measurement circuit 113 are arranged in the bus control circuit 11. The RDN_WRN generation circuit 111 literally generates a read control signal RDN and a write control signal WRN that are output to the external I / O device 20.

  The bus cycle measurement circuit 112 is a circuit that measures how many clock cycles a bus cycle continues in units of system clocks, and outputs a retry signal RETRY when the number of clocks reaches a specified number.

  Upon receiving the retry signal RETRY, the RDN_WRN generation circuit 111 once cancels the read control signal RDN or the write control signal WRN to request the external I / O device 20 to re-execute the read cycle or the write cycle. Generate again.

  The retry count measurement circuit 113 includes an internal counter that receives the retry signal RETRY from the bus cycle measurement circuit 112 and measures how many times the bus cycle having the same access as the previous one has been executed, and the measured value RTRY_CNT reaches the specified number of times. When this occurs, a pulse signal INT_O is generated toward the CPU.

  In addition, the retry count measuring circuit 113 receives the read end signal RD_END output from the RDN_WRN generation circuit 111 or the write end when the ready signal RDY from the external I / O device 20 becomes valid and the bus cycle ends normally. In response to the signal WR_END, the internal counter is reset.

  Further, the retry count measurement circuit 113 sends the measurement value RTRY_CNT of the current retry count to the RDN_WRN generation circuit 111. When the measurement value RTRY_CNT reaches the specified number of times, the read end signal RD_END or the write end is sent from the RDN_WRN generation circuit 111. Since the signal WR_END is output, the internal counter is reset in response to the read end signal RD_END or the write end signal WR_END output from the RDN_WRN generation circuit 111.

  FIG. 2 shows a timing chart of the data read operation (normal time) from the external I / O device 20. The microcontroller 10 outputs the address value held in the internal register to the address bus A [15: 0]. At the same time, the CPU sets the read control signal CPU_RDN to “L”. In response to the read control signal CPU_RDN = “L”, the bus control circuit 11 changes the read control signal RDN from “H” to “L”. The external I / O device 20 outputs the valid output data to the data bus D [7: 0] at the time when the preparation of data in response to the read request from the microcontroller 10 is completed, and at the same time, the ready signal RDY is validated. That is, “L” → “H”. The bus control circuit 11 receives the ready signal RDY from “L” to “H” and sets the read end signal RD_END to “H”. In response to this, the CPU can take in the read data. At the same time, the CPU changes the read control signal CPU_RDN from “L” to “H” to complete the read cycle.

  FIG. 3 shows a timing chart of a data write operation (normal time) to the external I / O device 20. The microcontroller 10 outputs the address value held in the internal register to the address bus A [15: 0]. At the same time, the write control signal CPU_WRN is set to “L”. The data bus D [7: 0] outputs write data, and the bus control circuit 11 receives the write control signal CPU_WRN = “L” and changes the write control signal WRN from “H” to “L”. The external I / O device 20 makes the ready signal RDY valid, that is, changes from “L” to “H” when the preparation for responding to the write request from the microcontroller 10 is completed, and takes in the write data to the inside. . In response to the ready signal RDY “L” → “H”, the bus control circuit 11 changes the write end signal WR_END to “H”, and in response to this, the CPU changes the write control signal CPU_WRN from “L” to “H”. This completes the write cycle.

  FIG. 4 is a block diagram illustrating a configuration example of the bus cycle measurement circuit 112. In the drawing, a 3-bit binary counter 1121 is symbolized and this counter 1121 counts up from “0” to “7”. Counting is performed at the rising edge of the system clock signal CLK. When the enable terminal ENABLE is “H”, the count value is incremented by 1 at the rising edge of the clock signal CLK, and when the enable terminal ENABLE is “L”, the count value is changed. do not do. Further, when the reset terminal RESETN is “L”, the counter value is set to “0” at the rising edge of the clock signal CLK, and when the reset terminal RESETN is “H”, the operation is switched by the enable terminal ENABLE described above. This is a reset priority counter.

  In addition, reference numeral 1122 denotes a selector for switching inputs according to a retry signal RETRY, 1123 denotes a D-type flip-flop, 1124, 1125, 1126 denote AND circuits, 1127 denotes a NOR circuit, and 1128 denotes an inverter. When the D-type flip-flop 1123 and the AND circuit 1124 detect the falling edge of the read control signal RDN or the write control signal WRN, the AND circuit 1124 outputs “H”.

  In the first embodiment, when the read control signal RDN or the write control signal WRN is “L”, the enable terminal ENABLE of the counter 1121 becomes “H”, whereby the read control signal RDN or the write control signal WRN. Is a period “L” for each system clock signal CLK. In addition to the system RESET, the counter 1121 is reset when the retry signal RETRY = "L", the output of the AND circuit 1124 is selected by the selector 1122, and the read control signal RDN or the write control signal WRN changes from "H" to "L". When the retry signal RETRY = “H”, the output of the NOR circuit 1126 is directly selected by the selector 1122 and when the read control signal RDN and the write control signal WRN are both “H”. .

  That is, for example, in the case of a read operation, the counter 1121 is reset when the read control signal RDN changes from “H” to “L”, then counts the clock signal CLK, and the ready signal RDY when the count value = “7” or less. Is reset when the read control signal RDN returns from "L" to "H" due to "H", but when the count value = "7", the retry signal RETRY becomes "H" and the bus cycle ends. It was shown that they did not. When the retry signal RETRY becomes “H”, the read control signal RDN becomes “H” by the RDN_WRN generation circuit 111, the counter 1121 is reset, and the retry signal RETRY becomes “L”. The same applies to the write operation.

  FIG. 5 is a block diagram illustrating a configuration example of the retry count measuring circuit 113. The function of the counter 1131 used in the figure is exactly the same as the counter 1121 used in FIG. Reference numerals 1132 and 1133 denote D-type flip-flops, 1134 to 1136 denote AND circuits, and 1137 denotes a NOR circuit. When the rising edge of the retry signal RETRY is detected by the D flip-flop 1132 and the AND circuit 1134, the AND circuit 1134 outputs “H”. When the rising edge of the AND circuit 1135 is detected by the D-type flip-flop 1133 and the AND circuit 1136, the AND circuit 1136 outputs “H”.

  The counter 1131 measures the number of rising edges of the retry signal RETRY, and outputs a measurement value RTRY_CNT. The counter 1131 is reset when the system RESET signal, the read end signal RD_END, or the write end signal WR_END is “H”. When the count value of the counter 1131 becomes “7”, the AND circuit 1135 outputs a pulse signal INT_O for one clock and can be used as an interrupt request or reset to the CPU.

  FIG. 6 is a timing chart in the case where the ready signal RDY is not enabled in the first read cycle, the retry is performed and the second read cycle is performed, and the ready signal RDY is enabled. The count value COUNT in the figure indicates the value of the counter 1121 in the bus cycle measuring circuit 112 in decimal. The counter 1121 receives the read control signal RDN = “L”, is cleared to the count value COUNT = “0”, and thereafter, since the read control signal RDN is “L”, the counter 1121 counts up in synchronization with the clock signal CLK.

  When the count value COUNT reaches “7” which is the specified value in the first embodiment, the retry signal RETRY changes to “H”, and the read control signal RDN changes from “L” to “H”, thereby causing the external I / O. The apparent bus cycle (first time) seen from the device 20 is completed. At the same time, the measured value RTRY_CNT of the counter 1131 in the retry count measuring circuit 113 is counted up from “0” to “1”. In addition, since the read control signal RDN becomes “H”, the count value COUNT of the counter 1121 is cleared to “0”, and the second bus cycle of the same access as the previous time is started.

  In this example, in the period when the read control signal RDN is “L” in the second bus cycle, the read end signal RD_END is “H” in response to the ready signal RDY becoming “H”, and the read control signal CPU_RDN is “ At this time, the bus cycle relating to the read access ends. During the first and second bus cycles, the read control signal CPU_RDN remains “L”, and the CPU executes one long bus cycle until the read end signal RD_END becomes “H”. It will be understood. The counter 1131 in the retry count measuring circuit 113 is reset when the read end signal RD_END becomes “H”.

  The write processing corresponding to FIG. 6 can be handled by replacing each signal with RDN → WRN, CPU_RDN → CPU_WRN, RD_END → WR_END, as is apparent from the relationship between FIG. 2 and FIG. (The waveform of the data bus D [7: 0] differs between the two, but this is not essential).

  FIG. 7 shows the number of retries, that is, one clock width when the measured value RTRY_CNT of the counter 1131 in the retry number measuring circuit 113 reaches “7” (that is, the number of retries is the eighth) which is the specified number in this embodiment. 6 is a timing chart showing how the pulse signal INT_O is output. By using this pulse signal INT_O as an interrupt request signal, the processing after the detection of the bus cycle error can be handled by software. It is also possible to use this pulse signal INT_O as a reset to initialize the system. As described above, when the measurement value RTRY_CNT reaches “7” which is the prescribed number in the first embodiment, the read end signal RD_END is “H” and the read control signal CPU_RDN is set based on the measurement value RTRY_CNT. At this time, the bus cycle related to the read access ends. The counter 1131 in the retry count measuring circuit 113 is reset when the read end signal RD_END becomes “H”.

  FIG. 8 is a block diagram showing a bus control circuit and its peripheral circuit portion according to the second embodiment of the present invention. The same components as those shown in FIG. Reference numeral 114 denotes an access content storage circuit. When the number of retries reaches a predetermined value “7” and the access ends abnormally, the address bus A [15: 0], which is the access content, is written. The contents of write data DOUT [7: 0], CPU_RDN as a read flag, and CPU_WRN as a write flag are collectively stored as data DO [25: 0] in an internal register.

  Reference numeral 115 denotes a DIN generation circuit as a data processing circuit that generates data to be read by the CPU when access is unsuccessful. When the read access from the CPU is to the IO device 20, the read from the IO device 20 is performed. The contents of the data bus D [7: 0] are output as DIN [7: 0], and in the case of the access content storage circuit 114, the data DO [25: 0] stored in the register of the access content storage circuit 114 is 8 bits. Switch in units and output as DIN [7: 0].

  FIG. 9 is a block diagram showing a configuration example of the access content storage circuit 114. 1141 is a 3-bit D-type flip-flop, 1422 is a 26-bit D-type flip-flop, 1143 to 1145 are AND circuits, 1146 is an OR circuit, and 1147 is a selector.

  The D-type flip-flop 1141 takes in the measured value RTRY_CNT of the counter 1131 in the retry count measuring circuit 113, and when the value reaches “6”, the output of the AND circuit 1143 becomes “H”, and the gate of the AND circuit 1144 is turned on. Therefore, when the next “H” retry signal RETRY (when RTRY_CNT = “7”) is input, the output of the AND circuit 1144 becomes “H”, and the AND circuit 1145 opens the gate.

  As a result, the content of the address bus A [15: 0], which is the content of the access that ended abnormally, the write data bus DOUT [7: 0] in the case of writing, the CPU_RDN as the read flag, and the content of the CPU_WRN as the write flag That is, a total of 26 bits are input to the selector 1147 via the AND circuit 1145.

  At this time, since the read end signal RD_END is “H” based on the measurement value RTRY_CNT becoming “7”, the output of the OR circuit 1146 becomes “H”, and the selector 1147 outputs the output of the AND circuit 1145. The data DO [25: 0] indicating the contents of the access that has been selected and ended abnormally is stored in the flip-flop 1142. Thereafter, the read end signal RD_END becomes “L” and the selector 1147 is switched, so that even if the clock CLK is updated, the stored contents of the flip-flop 1142 are self-held via the selector 1147.

  FIG. 10 is a block diagram illustrating a configuration example of the DIN generation circuit 115. 1151 is a decoding circuit for converting the contents of the address bus A [15: 0] coming from the CPU into a 3-bit code, 1152 is the 26-bit retained data DO [25: 0] of the access content storage circuit 114, and the IO device 20 Is a selector that selects the read data D [7: 0] from the decoding result of the decoding circuit 1151. The stored data DO [25: 0] of the access content storage circuit 114 is in units of 8 bits like DO [7: 0], DO [15: 8], DO [22:16], DO [25:23]. Is selected (the missing bits are optional if less than 8 bits).

  The decode circuit 1151 outputs a code “000” when the content of the address bus A [15: 0] from the CPU indicates the IO device 20. Then, the selector 1152 selects the input data D [7: 0] to the IO device 20 and this is read into the CPU. When the content of the address bus A [15: 0] from the CPU indicates the IO address # 0 assigned to the access content storage circuit 114, a code "001" is output and stored in the access content storage circuit 114. Data DO [7: 0] is selected from the data DO [25: 0] and is read by the CPU. Hereinafter, when the IO addresses # 1, # 2, and # 3 assigned to the access content storage circuit 114 are indicated, by outputting the codes “010”, “011”, and “100”, respectively, the data DO [25: Data DO [15: 8], DO [22:16], and DO [25:23] in [0] are selected and read by the CPU.

  In this way, by switching the contents of the address bus A [15: 0] from the CPU, the DIN generation circuit 115 directly reads the stored data DO [25: 0] of the access content storage circuit 114 or the IO device 20. Data D [7: 0] is sent to the CPU in 8-bit units so that it can be easily read by the CPU.

  As described above, by the interrupt processing by the INT_O signal, the CPU accesses the contents stored in the access content storage circuit 114 by software after data processing by the DIN generation circuit 115, and the user accesses which IO device. It becomes possible to know whether or not an error has occurred. If the specified IO device is an IO device that does not consider the history of processing up to that point, only the specified IO device is reset, and then the IO device is set again. It becomes possible to perform the access again after the last unsuccessful access and continue the process again. This means a reduction in the chance of resetting (restarting) the entire system.

FIG. 2 is a block diagram illustrating a part of a microcontroller including a bus control circuit according to the first embodiment and an external I / O device. 3 is a timing chart of a read operation (normal time) of the bus control circuit of FIG. 1. 2 is a timing chart of a writing operation (normal time) of the bus control circuit of FIG. 1. It is a block diagram which shows the structural example of a bus cycle measurement circuit. It is a block diagram which shows the structural example of a retry frequency measurement circuit. It is a timing chart of a retry operation. 6 is a timing chart when the number of retries reaches a specified number. 10 is a block diagram showing a part of a microcontroller including a bus control circuit according to a second embodiment and an external I / O device. FIG. It is a block diagram which shows the structural example of an access content memory circuit. It is a block diagram which shows the structural example of a DIN production | generation circuit.

Explanation of symbols

10: Microcontroller 11: Bus control circuit 111: RDN_WRN generation circuit (read / write circuit)
112: Bus cycle measurement circuit, 1121: Counter, 1122: Selector, 1123: D-type flip-flop, 1124, 1125, 1126: AND circuit, 1127: NOR circuit, 1128: Inverter 113: Retry count measurement circuit, 1131: Counter, 1132, 1133: D-type flip-flop, 1134 to 1136: AND circuit, 1137: NOR circuit 114: Access content storage circuit, 1141, 1142: D-type flip-flop, 1143 to 1145: AND circuit, 1146: OR circuit, 1147: Selector 115: DIN generation circuit, 1151: decode circuit, 1152: selector 20: external I / O device A [15: 0]: address bus D [7: 0]: data bus CLK: clock signal CPU_RDN: read control signal CPU_WR : Write control signal RDN: read control signal WRN: write control signal RDY: Ready signal RETRY: Retry signal WR_END: write end signal RD_END: read end signal COUNT: count value of the counter 1121 RTRY_CNT: count value of the counter 1131

Claims (10)

When a read operation or a write operation is performed on an external circuit using the CPU, processing of the bus cycle for the read or write access is completed based on the ready signal input from the external circuit being valid. In the bus control method to
When the ready signal does not become effective even after a specified time, the current bus cycle is canceled to return to the non-access state, and after entering the non-access state, the same access bus cycle as before is executed again. A characteristic bus control method. The bus control method according to claim 1,
When the number of executions of the same access bus cycle reaches a specified number, the bus cycle processing is terminated and a signal that can be used as an interrupt or reset is output. The bus control method according to claim 1,
A bus control method characterized in that when the number of executions of the bus cycle of the same access reaches a specified number, the processing of the bus cycle is terminated and information relating to the access is stored. The bus control method according to claim 3,
A bus control circuit that performs data processing for causing the CPU to read information relating to the stored access. When connected to an external circuit via a bus and a control line and reading or writing by outputting a read control signal or a write control signal to the external circuit based on a read or write command from the CPU, In the bus control circuit that completes the processing of the bus cycle of the access based on the ready signal input from the external circuit being valid,
A read / write circuit that generates and outputs the read control signal or the write control signal to the external circuit based on a read or write command from the CPU, and the read control from the read / write circuit A bus cycle measuring circuit that outputs a retry signal when a specified time elapses without the ready signal being effective after the signal or the write control signal is output to the external circuit,
The read / write circuit temporarily cancels the read control signal or the write control signal when the retry signal is output from the bus cycle measuring circuit, and generates the bus control cycle in the same access as the previous time. A bus control circuit characterized in that is executed. The bus control circuit according to claim 5.
When the read control signal or the write control signal is generated, the bus cycle measurement circuit once cancels the time measurement operation and restarts the measurement operation. After the retry signal is output, the bus cycle measurement circuit resumes the read operation. A bus control circuit which releases the measurement operation when a control signal and the write control signal are released. In the bus control circuit according to claim 5 or 6,
A bus control circuit, comprising: a retry count measuring circuit that outputs a signal that can be used as an interrupt or a reset when the number of retry signals generated by the bus cycle measuring circuit is measured and reaches a specified number. The bus control circuit according to claim 7,
The retry count measurement circuit releases the retry count measurement operation when the ready signal becomes valid before the measured value of the retry count reaches the specified count. The bus control circuit according to claim 7,
A bus control circuit comprising: an access content storage circuit for storing information related to the access when a measured value of the retry count measured by the retry count measurement circuit reaches the specified number of times. The bus control circuit according to claim 7,
A bus control circuit comprising a data processing circuit for performing data processing for causing the CPU to read information relating to the access stored in the access content storage circuit.

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