JP2006080795A - Digital pwm means - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a digital PWM (pulse width modulation) means for outputting a PWM signal for reducing spectral intensity of a switching frequency in addition to having high resolution even in a short PWM signal period with a simple configuration. <P>SOLUTION: This digital PWM means outputs a signal having two values or more, wherein the ratio of a period in which one value of the two values or more repeats to a time in which the value continue changes in accordance with an input signal. By changing the period for repeating the value without fixing the value, the PWM means can be realized which outputs the PWM signal having high resolution even in a short PWM signal period with a simple configuration and capable of reducing spectral intensity of a switching frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

    The present invention relates to increasing the accuracy of a switching PWM signal.

FIG. 9 shows a PWM signal using a conventional technique (for example, see Patent Document 1 below). A waveform having a duty ratio corresponding to the numerical value is shown for the input signal Data. In this figure, one period of the waveform is divided into 64, and in this unit, for the input of Data = −31 to 31,
The duty ratio changes. Specifically, the output is such that the minimum duty ratio is output for Data = −31, the duty ratio is 50% for Data = 0, and the maximum duty ratio is for Data = 31.

  In this figure, one period from a portion where the waveform rises from a low level to a high level to the next rising portion is defined as a PWM signal cycle, regardless of the value of Data. Since only the input signal values from Data = −31 to 31 can be handled, the PWM signal output has 6-bit resolution.

JP 2004-88431 A

  Such a conventional method has a problem that the resolution of the PWM signal depends on the minimum resolution of the PWM signal. In order to increase the resolution of the PWM signal, the range of the input signal value that can be expressed as the PWM signal can be expanded by increasing the period of the PWM signal. However, if the period of the PWM signal is increased, the frequency of the original input signal and the PMW signal As a result, the S / N ratio when the PWM signal is passed through the low-pass filter deteriorates and the PWM signal cycle cannot be lengthened. Therefore, the conventional method has a problem that a signal with high resolution cannot be expressed with a short PWM signal period. Further, since the PWM signal cycle is fixed, there is a problem that the spectrum intensity of the switching frequency is strong and the radiated electromagnetic noise is large.

  In order to achieve the above object, the invention according to claim 1 is a signal having two or more values, and the ratio of the time during which one of the values continues and the repetition period of the value depends on the input signal. Since the digital PWM means is a digital PWM means that changes the cycle in which the value repeats, a PWM signal that represents a resolution exceeding the minimum resolution of the conventional PWM signal is obtained. Therefore, high resolution can be expressed even with a PWM signal having a short period.

  With a simple configuration, a high resolution PWM signal can be expressed even with a short PWM signal period. In addition, the spectral intensity of the switching frequency can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment of digital PWM means. An analog signal or a multi-value multi-bit digital signal (hereinafter abbreviated as MBD signal) is input to the ΔΣ modulation means 21 as an input signal. The ΔΣ modulation means 21 outputs, for example, a single bit stream signal (hereinafter abbreviated as an SBS signal) subjected to ΔΣ modulation for every 10 MHz CLOCK signal input. This signal can also be a binary output signal or a multi-value output signal higher than that. This SBS signal is input to the adding means 22, added to the output of the inverting means 25, and output as an MBD signal. This output is input to the integrating means 23 and accumulated for each CLOCK input. The output of the integration means 23 is converted into a PWM signal having a binary value according to the magnitude of the input signal value by the comparison means 24 and output. This PWM signal output is input to the delay means 26 and output to the inversion means 25 with a delay of one CLOCK period. The inverting means 25 inverts the input signal logic and outputs it to the adding means 22.

  Next, FIG. 2 shows details of the integrating means 23. Let the input signal be a (nT). T is the period of the CLOCK signal. n indicates the nth clock signal. Therefore, a (nT) indicates the value of the a signal at time n * T. The input a (nT) of the integration unit 23 is added to the output of the delay unit 32 by the addition unit 31. The output of the adding means 31 is output to the subsequent stage as the output of the integrating means 23, that is, Σa (nT). In addition, it is also input to the delay means 32, stores the output of the addition means 31 for each CLOCK signal input, and outputs the value to the addition means 31. With these operations, FIG. 2 generally integrates the input signal a (nT). If necessary, a limiter may be inserted into the output of the adding means 31 to limit the upper limit value and lower limit value of the integral value.

  FIG. 3 shows operating characteristics of the comparison means 24. The horizontal axis is the input of the comparison means 24, and the vertical axis is the output of the comparison means 24. If the MBD signal is input and the value is H or more, +1 is output, and if the value is -H or less, -1 is output. Since there is a hysteresis characteristic until the input exceeds -H and immediately before + H, two values can be taken. That is, -1 is output when transitioning from a small value to a large value, and +1 is output when transitioning from a large value to the small value.

  Now, referring back to FIG. 1, the adding means 22, integrating means 23, comparing means 24, delay means 26, and inverting means 25 constitute a negative feedback closed loop. The output of the adding means 22 means the difference between the two because it calculates the difference in PWM signal output with respect to the input of the SBS signal. Since this deviation is input to the integrating means 23, when operating as a closed loop, the deviation becomes zero. That is, control is performed such that the input SBS signal and the output PWM signal match. Therefore, the SBS signal, that is, the input signal of the ΔΣ modulation means 21 is modulated to the PWM signal.

  Hereinafter, the closed loop operation will be described in detail. The PWM signal takes values of −1 and +1 as described with reference to FIG. For example, suppose that -1 is currently being output. Further, it is assumed that the input of the ΔΣ modulation means 21 is zero, and the output of the ΔΣ modulation means 21 that is an SBS signal outputs +1 and −1 with equal probability and randomly. At this time, since the input on the inverting means 25 side of the adding means 22 is fixed at +1, the output of the adding means 22, that is, the deviation is generated and output at random with equal probability of +2 or 0. The average is 1. Since this signal is input to the integration means 23, the output of the integration means 23 is generally incremented by +1 for each CLOCK. In the comparison means 24, when the increment value becomes equal to + H, the comparison means output becomes +1. That is, the PWM signal output is inverted from −1 to +1. By becoming +1, this time, the deviation becomes -2 or 0, and becomes -1 on average. The integration means 23 decrements by -1 every CLOCK, and the comparison means 24 returns the comparison means output to -1 when the decremented value becomes equal to -H. That is, the PWM signal returns to -1, and one cycle of the PWM signal ends. When the input signal of ΔΣ modulation means 21 is zero, the output PWM signal is a PWM signal with a duty of 50% with +1 being about 2H CLOCK cycle pulse width and -1 being about 2H clock cycle pulse width. .

  When the input signal of the ΔΣ modulation means 21 changes, the deviation changes, and as a result, the output of the integration means 23 changes, so that the +1 width and -1 width of the PWM output signal change, and the duty 50 Deviation from%. Further, the sum of the width of +1 and the width of −1, that is, one cycle of the PWM signal also changes in accordance with the deviation, and hence the output of the integrating means 23. Therefore, the period of the PWM signal is not fixed as shown in FIG. The center period of the PWM signal is determined by the parameter H in the characteristics of the comparison means 24 in FIG. 3, but there is fluctuation. This is shown in FIG. When a certain H is determined, the PWM signal period varies between ToMAX and ToMIN.

FIG. 5 shows the FFT result of the PWM signal output when a single frequency sine wave is input as the input signal of the ΔΣ modulation means of FIG. The following parameters were used:
・ CLOCK frequency 12.5MHz
・ H = 10
・ Input signal frequency: 1 kHz
It can be seen that the switching frequency component, that is, the PWM signal period component has a width of about 200 kHz and fluctuates. Further, the characteristic curve, that is, the noise component becomes −20 dB / dec and becomes lower as the frequency goes lower. Therefore, it can be seen that a higher S / N ratio can be realized as the distance from the PWM period component increases. In this waveform, since the switching frequency is about 200 kHz for 12.5 MHz CLOCK, the PWM period is only about 62.5 times the CLOCK period. In the conventional example shown in FIG. 9, the resolution is 6 bits and 1/64. However, at the 1 kHz input signal frequency of FIG. 5 of this embodiment, the noise is 100 dB or less with respect to the input signal peak, and the resolution is 1/10000, which is dramatically improved. When a lower frequency, for example, 1 / 10th of 100 Hz is input, the frequency is further improved by 20 dB, that is, a resolution of 1/10000 is obtained.

  As described above, in this embodiment, the PWM signal output resolution is greatly improved by changing the PWM signal period, that is, the period in which, for example, +1 of the two values fluctuates. Further, since the switching frequency fluctuates, there is an effect that the spectrum is diffused and radiated electromagnetic noise can be reduced.

  FIG. 6 is a diagram showing another embodiment of the digital PWM means according to the present invention. The digital PWM means 200 in FIG. 6 is a part of the digital PWM means of the embodiment described with reference to FIG. 1 and includes an adding means 22, an integrating means 23, a comparing means 24, a delay means 26, and an inverting means. 25. In order to simplify the drawing, the CLOCK signal is omitted, but this part has the same configuration as in FIG. In the present embodiment, a negative feedback closed loop with compensation means 47 is provided outside the digital PWM means 200 so that a highly accurate PWM signal can be output.

  FIG. 6 will be described in detail. The adding means 42 has an input signal which is a digital signal and inputs from the inverting means 45, and outputs the addition result. The output of the adding means 42 is input to the compensating means 47, for example, PI (proportional integration) compensated and output. The output of the compensation means 47 is input to the digital PWM means 200, and a PWM signal is output. The PWM signal is delayed by a CLOCK signal period (not shown) by the delay means 46 and input to the inversion means 45. The output of the inverting means 45 is input to the adding means 42 and constitutes a negative feedback closed loop. By performing another closed loop control in addition to the digital PWM means 200 as in the present embodiment, the S / N is improved 10 times.

  In the description of the embodiments so far, −1 and +1 are used as binary values, but the effect does not change even if the level is shifted to 0 and 1.

  FIG. 7 is a diagram showing another embodiment of the digital PWM means according to the present invention. Compared to FIG. 1, a ternary means 58 is added, and the PWM signal output is ternary. For simplification, the CLOCK and ΔΣ modulation means 21 are omitted. The output of the comparison means 24 is a binary value of +1 and −1 as described with reference to FIG. The ternarization means 58 receives the output of the binary comparison means 24 shown in FIG. 8A, and sets a delay time of a fixed time to a value 0 for every change of the comparison means 24 output as shown in FIG. 8B. Insert it. Therefore, it becomes three values. This delay time is set to several hundred ns to several μs assuming the delay time of the load driving switching element connected to the subsequent stage. The switching elements are connected in series up and down, and are controlled to be turned on by the upper ON and lower ON signals in FIGS. 8C and 8D, respectively.

  In FIG. 7, since the closed loop is configured including the ternary means 58 for simulating the delay time of the load driving switching element connected to the subsequent stage, the input signal of the adding means 22 including the error due to the delay time is included. A PWM signal for follow-up control is output. Also in this embodiment with three values, as shown in FIG. 8B, for example, the ratio of the time during which the +1 level appears at almost constant intervals and the +1 level continues and the cycle at which the +1 level repeats is the input signal. It changes according to. Further, since the cycle in which the level of +1 repeats fluctuates similarly to the embodiment of FIG. 1, the effect is equivalent.

  In the description so far, the input of the adding means 22 is described as an SBS signal in order to emphasize the high resolution characteristics of the present invention. However, if the MBD signal is also a multi-bit high resolution signal, the effects of the present invention can be obtained. You can enjoy it.

  Although the embodiments and examples of the invention made by the present inventor have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

It is a block diagram showing the digital PWM means in one Embodiment of this invention. It is a block diagram of the integration means concerning FIG. FIG. 2 is an operation characteristic diagram of the comparison unit according to FIG. 1. FIG. 2 is a relationship diagram between a PWM signal period and a comparison means parameter H according to FIG. 1. It is a PWM signal frequency analysis characteristic view concerning FIG. It is a block diagram showing the digital PWM means in other embodiment of this invention. It is a block diagram showing the digital PWM means in other embodiment of this invention. It is explanatory drawing of the signal concerning FIG. It is a wave form diagram showing the relationship between the input data and output waveform in the conventional PWM means.

Explanation of symbols

21 ΔΣ modulation means 22 addition means 23 integration means 24 comparison means 25 inversion means 26 delay means 31 addition means 32 delay means 42 addition means 45 inversion means 46 delay means 47 compensation means 58 ternarization means

Claims (1)

A means for outputting a signal having two or more values, wherein the ratio of the time during which one of the values lasts and the repetition period of the value changes in accordance with the input signal, Digital PWM means in which the repetition period changes.

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