JP2006074069A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To planarize a step formed accompanied by the growth of an InP layer. <P>SOLUTION: Wet etching is applied to the grown InP layer using an etchant containing at least a hydrochloric acid and an acetic acid. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention generally relates to a compound semiconductor device, and more particularly to a method of manufacturing an optical semiconductor element used for optical communication and optical information processing.

  Compound semiconductors have a direct transition type band structure that interacts with light. Therefore, optical semiconductor devices using compound semiconductors are widely used in the fields of optical communication and optical information processing. Particularly, an InP-based compound semiconductor device, particularly a laser diode, is important because it can form an optical signal having a wavelength of 1.3 or 1.55 μm transmitted through an optical fiber.

In such a laser diode, in order to improve the laser oscillation efficiency, it is essential to provide a current confinement structure that confines injected carriers in a limited region in the axial direction. Further, since laser oscillation occurs by stimulated emission in a laser diode, it is necessary to efficiently confine light in a region where such carriers are confined. In an InP-based laser diode, optical confinement in the horizontal direction is realized by a refractive index difference between an InGaAsP core that guides light and an InP buried layer.
JP 09-283505 A Japanese Patent Laid-Open No. 02-213134 Japanese Patent Laid-Open No. 04-229682 JP 05-021419 A JP 2000-091303 A JP 2000-349395 A

  1A to 1D show a manufacturing process of a laser diode 10 having a buried heterostructure (BH structure) as a current and optical confinement structure.

  Referring to FIG. 1A, a multiple quantum well layer 12 in which an InGaAs layer and an InGaAsP layer are repeatedly stacked is formed on an n-type InP substrate 11, and a p-type InP is further formed on the multiple quantum well layer 12. A clad layer 13 and a p-type InGaAs contact layer 14 are sequentially formed.

Next, in the step of FIG. 1B, an SiO ₂ film 15 is formed on the contact layer 14 as an etching protective film, and an active layer mesa stripe is formed by performing dry etching on the structure. In the illustrated example, the mesa stripe extends in the <011> direction.

Next, in the step of FIG. 1C, the SiO ₂ film 15 is used as a selective growth mask, and Fe-doped high resistance InP buried layers 16A and 16B are formed by metal organic vapor phase epitaxy (MOVPE). In the regrowth process of the InP buried layers 16A and 16B, a (111) B plane that is a growth stop surface is developed, and as a result, the buried layer has a reference numeral 16a at the mask edge. Or the growth shape which rises as shown by 16b is obtained.

Finally, in the step of FIG. 1D, the SiO ₂ film 15 is removed, and a p-side electrode 17 is formed on the contact layer 14 and an n-side electrode 18 is formed on the lower surface of the substrate 11.

Thus, in the buried growth of the InP layers 16A and 16B using the SiO ₂ film 15 as a selective growth mask, the InP layer is formed in the regions 16a and 16b corresponding to the edges of the SiO ₂ film 15 as described above. It is inevitable that 16A and 16B rise. This is because the crystal growth does not occur on the SiO ₂ mask 15 and the concentration of the raw material locally increases on the SiO ₂ film 15 so that the InP layer 16A grown on both sides of the mesa region or This is because the raw material is excessively supplied to the surface of 16B. For example, in the process of FIG. 1C, when the height of the measto life is about 1.5 μm, the InP buried layers 16A and 16B swell about 0.7 μm in the mask edge regions 16a and 16b.

  As described above, in the step of FIG. 1D, the p-side electrode 17 is formed on the stepped surface, but the p-side electrode 17 is sequentially formed by sputtering of a Ti film, a Pt film, and an Au film. In this case, since each of the Ti film and the Pt film has a thickness of only about 0.1 μm, there arises a problem that the electrode layer is interrupted at the concavo-convex portion 17a as shown in FIG. When such an electrode break occurs, current injection becomes non-uniform, causing electrical degradation of the device.

In recent years, an optical integrated circuit element in which a laser diode, a waveguide, a light receiving element, and an optical functional element are integrated in the element has attracted attention as an important optical semiconductor device. In such an optical integrated circuit element, a mesa stripe is < In some cases, the stripe extends in a direction other than 011> or a branch point exists in the stripe. When the embedded growth of the stripe in the <011> direction is performed as shown in FIG. 1C, the (111) B plane develops as a growth stop surface. Due to the absence of the growth stop surface, as shown in FIGS. 3A to 3C, an over-hang in which the buried layer extends on the SiO ₂ mask film may occur. 3A is a perspective view of the optical waveguide, FIG. 3B is a cross-sectional view, and FIG. 3C is a partially enlarged view.

Referring to FIGS. 3A to 3C, an SiO ₂ pattern 22 having an opening exposing the substrate 21 is formed on the InP substrate 21, and the SiO ₂ pattern 22 is used as a mask. An InP buried layer 23 is formed by regrowth on the exposed surface of the InP substrate 21. At this time, since the InP buried layer 23 does not have a growth stop surface like the previous (111) B surface, an opening in the SiO ₂ pattern 22 is formed as shown in the enlarged view of FIG. As a result, the overhang 23A is formed.

3A to 3C, when the InP layer 24 is grown again after removing the SiO ₂ mask 22, the source gas does not reach the portion immediately below the overhang portion 23A. As a result, the structure shown in FIG. Thus, the cavity 23B may be generated. Since such a cavity 23B has an extremely different refractive index from that of the InP layer 23, the light guided in the waveguide is scattered, resulting in light loss.

5A to 5D show laser diodes in which a mesa stripe 31M extends in a direction other than the <011> direction on a substrate 31, and InP buried layers 32A and 32B on both sides of the mesa stripe 31M. FIG. 6 is a diagram for explaining a problem when the SiO ₂ film 33 formed on the mesa stripe 31M is grown as a selective growth mask.

In the example of FIG. 5A, the mesa stripe 31M extends in a direction offset by 10 ° from the <011> direction to the <010> direction. As shown in the enlarged view of FIG. Since the buried layers 32A and 32B have no growth stop surface, they protrude to the SiO ₂ mask 33 to form an overhang.

In such a structure, when the SiO ₂ mask 33 is removed by etching and an InP layer 34 is deposited so as to cover the InP buried layers 32A and 32B and the mesa stripe 31M as shown in FIG. As shown in FIG. 5D, the gas phase raw material may not be sufficiently supplied to the region immediately below the overhang of the InP buried layers 32A and 32B, and cavities 32a and 32b may be formed.

  Accordingly, it is a general object of the present invention to provide a novel and useful method for manufacturing a semiconductor device that solves the above problems.

  A more specific object of the present invention is to provide a method of manufacturing a semiconductor device that can planarize an InP layer having a step shape after growth.

The present invention solves the above problems.
As described in claim 1,
Crystal growth of an InP buried layer having a step shape on a growth start surface having a step, wet etching using an etchant containing hydrochloric acid and acetic acid is performed on the InP buried layer, and the InP A step of flattening the step shape of the buried layer, or a method of manufacturing a semiconductor device, or as described in claim 2,
4. The semiconductor device manufacturing method according to claim 1, wherein the growth step is performed so that the step shape is generated corresponding to an initial step of the growth start surface. 5. like,
The method according to claim 2, wherein the initial step of the growth start surface is a mesa shape, or as described in claim 4.
The initial step of the growth start surface is a step shape, or by the method for manufacturing a semiconductor device according to claim 2, or as described in claim 5.
The method for manufacturing a semiconductor device according to claim 1, wherein the growth start surface is a flat surface and partially has a selective growth mask, and the step shape is formed corresponding to the selective growth mask. Or as described in claim 6
The planarization step is performed such that the InP layer has a planarization surface composed of any one of the (100) plane, the (011) plane, and the (0-1-1) plane as a result of the planarization process. The semiconductor device manufacturing method according to any one of claims 1 to 5, or as described in claim 7,
In the planarization step, the InP layer is closer to one of the (100) plane, the (011) plane, and the (0-1-1) plane as a result of the planarization step than before the planarization step. The semiconductor device manufacturing method according to any one of claims 1 to 5, or as described in claim 8, wherein the semiconductor device manufacturing method is performed so as to have a planarized surface.
The growth step is performed such that the InP layer surface is lower than the highest position of the growth start surface, and the planarization step is performed by measuring the InP layer from the substrate surface after the planarization step. The semiconductor device manufacturing method according to claim 1, wherein the method is performed so as to have a planarized surface having a height corresponding to the lowest position of the InP layer. As described in item 9,
The growth process is performed such that the InP layer surface is equal to or higher than the highest position of the growth start surface, and the planarization process is performed after the planarization process. The semiconductor device according to claim 1, wherein the semiconductor device is executed so as to have a planarized surface having a height equal to or higher than the height corresponding to the highest position of the growth start surface. By the manufacturing method or as described in claim 10,
The growth start surface has a selective growth mask in a part of the initial step, and the step of growing the InP layer is such that the step shape of the InP layer is formed corresponding to the edge of the selective growth mask. The semiconductor device manufacturing method according to claim 2, or as described in claim 11,
The step of growing the InP layer is performed such that a step shape of the InP layer forms a slope region along a side surface of the initial step on the growth start surface. Or a semiconductor device manufacturing method according to claim 12, or
The step of growing the InP layer is performed such that the step shape of the InP layer is formed so that the InP layer covers the initial step on the growth start surface. According to a manufacturing method of a semiconductor device or as described in claim 13,
13. The method of manufacturing a semiconductor device according to claim 1, wherein the etchant contains hydrochloric acid and acetic acid so that the concentration of acetic acid is 20 times or less that of hydrochloric acid. Or as described in claim 14,
The method of manufacturing a semiconductor device according to any one of claims 1 to 13, wherein the etchant further includes an additional agent comprising at least one of water and hydrogen peroxide. As described in 15,
15. The semiconductor device manufacturing method according to claim 14, wherein the additional agent adds hydrogen peroxide water to the etchant at a concentration of 30% or less of hydrochloric acid with respect to hydrochloric acid and acetic acid. As described in item 16,
The method for manufacturing a semiconductor device according to claim 14, wherein the additive is made of water, or as described in claim 17.
The method for manufacturing a semiconductor device according to claim 14, wherein the additive comprises water and hydrogen peroxide water, or as described in claim 18.
A region under the selective etching mask is formed by carrying an etching with an etchant containing hydrochloric acid and acetic acid on the InP layer having a selective etching mask and having a surface region lower than the selective etching mask and having a stepped portion on the surface. The method of manufacturing a semiconductor device, wherein the surface of the InP layer is planarized, or as described in claim 19,
The method of manufacturing a semiconductor device according to claim 18, wherein the step shape of the InP layer is formed corresponding to an initial step portion on a growth start surface, or as described in claim 20.
The method according to claim 19, wherein the selective etching mask is provided on an upper portion of the initial step portion, or as described in claim 21.
The method according to claim 18, wherein the selective etching mask is provided on a surface of a step portion on the InP layer, or as described in claim 22.
The method according to claim 18, wherein the selective etching mask is selected from the group consisting of a compound semiconductor excluding an insulating material and InP, or as described in claim 23.
25. The method according to claim 22, wherein the selective etching mask is made of any one of silicon oxide, silicon nitride, InGaAs, InGaAsP, AlGaInP, AlGaAs, and GaInNAs. like,
24. The method of manufacturing a semiconductor device according to claim 18, wherein the etchant contains hydrochloric acid and acetic acid so that the concentration of acetic acid is 20 times or less that of hydrochloric acid. Or as described in claim 25,
25. The method for manufacturing a semiconductor device according to claim 18, wherein the etchant further includes an additional agent comprising at least one of water and hydrogen peroxide. 26. The method of manufacturing a semiconductor device according to claim 25, wherein the additional agent is a hydrogen peroxide solution added to hydrochloric acid and acetic acid at a concentration of 30% or less of hydrochloric acid. Or as described in claim 27,
26. The semiconductor device manufacturing method according to claim 25, wherein the additional agent is made of water.
[Action]
The present invention solves the above problem by flattening the step shape generated on the surface by InP crystal growth by wet etching. In particular, the present invention uses a mixed solution containing hydrochloric acid and acetic acid as an etchant.

  FIG. 6 shows a <100> direction in an experiment conducted by the inventors of the present invention in etching a stepped InP layer using a mixed solution having a mixture ratio of hydrochloric acid: acetic acid: water of 1: 5: 1. The correlation between the etching amount and the etching time in the 0-11> direction and the <011> direction is shown.

  Referring to FIG. 6, the etching rate in the <100> direction and the <011> direction is about 0.05 to 0.7 μm / min, whereas the etching rate in the <0-11> direction is 5 to 30 μm. It can be seen that / min is about 100 times faster. Therefore, when the step shape is etched with the mixed solution, the step in the <0-11> direction is retreated at a very high speed, and as a result, the (100) plane, the (011) plane, and the equivalent (0-1-1) ) Only the surface remains as a development surface and the other surfaces disappear. That is, it has been found that only the (100) plane, the (011) plane, or the (0-1-1) plane appears as a flat surface on the InP layer by wet etching using the above etching solution.

  When the mixing ratio of each component in the etchant is changed, the absolute value of the etching rate and the relative velocity with respect to each plane orientation change.

  FIG. 7 shows the etching rate ratio in the <0-11> direction to the <100> direction when the concentration ratio X of acetic acid to hydrochloric acid in the etchant is changed. That is, in FIG. 7, in the etchant, the concentration ratio of hydrochloric acid: acetic acid: water is expressed as 1: X: 1.

  Referring to FIG. 7, it can be seen that in any acetic acid concentration range X, the etching rate in the <0-11> direction is 30 to 100 times larger than that in the <100> direction. This etching anisotropy is obtained by the inclusion of hydrochloric acid and acetic acid in the etchant, and it can be seen that an etching rate ratio of 30 or more can be obtained particularly when the concentration ratio X of hydrochloric acid and acetic acid is in the range of 1-10. In this way, by setting the concentration of acetic acid in the etchant within the above range, the remarkable planarization effect of the InP layer, which is the object of this patent, can be obtained.

  When the concentration ratio of water in the etchant changes, the (hydrochloric acid + acetic acid) concentration changes, so the absolute value of the etching rate changes, but the etching anisotropy itself shown in FIGS. 6 and 7 does not change. The flattening effect is not affected.

  Etching anisotropy by the etchant of the present invention can also be obtained by adding hydrogen peroxide water to the above etchant mixture.

  FIG. 8 shows the etching rate in the <0-11> direction with respect to the <100> direction when the InP step shape is etched with an etchant in which hydrogen peroxide is further added to the mixed solution of hydrochloric acid, acetic acid and water. Indicates the ratio.

  Referring to FIG. 8, when the composition ratio of hydrochloric acid, acetic acid, hydrogen peroxide solution, and water in the etchant is expressed as 1: 1: Y: 1, the value of the hydrogen peroxide solution composition Y is 0 to 0. It can be seen that anisotropy of 30 or more is obtained in the range of 0.3.

The etchant containing hydrochloric acid and acetic acid according to the present invention is applied to the structure in which the SiO ₂ etching mask shown in FIG. 9A is formed on the surface of the stepped shape of InP, and is planarized as shown in FIG. 9B. It has been found that side etching does not proceed under the etching mask when performing.

Referring to FIG. 9A, a mesa stripe 41M is formed in the [011] direction on the InP substrate 41 using the SiO ₂ pattern 42 as an etching mask, and the mesa stripe 41M is formed on both sides of the mesa stripe 41M. InP buried layers 43A and 43B are formed using the SiO2 pattern 42 on 41M as a selective growth mask.

In the step of FIG. 9B, the InP buried layers 43A and 43B are etched with the etchant containing hydrochloric acid and acetic acid according to the present invention using the SiO ₂ pattern 42 as an etching mask again, and a flat (100) plane is formed. Form a chemical surface.

9B, even if the side wall surface of the mesa stripe 41M is the (0-11) plane of InP that is selectively etched by the etchant, the SiO ₂ pattern 42 is formed on the mesa stripe 41M. As long as this is formed, no substantial side etching occurs in the mesa stripe 41M, and therefore the mesa stripe 41M remains substantially completely even after the planarization step of FIG. It was found.

  That is, in the step of planarizing the step structure of InP using the etchant containing hydrochloric acid and acetic acid according to the present invention, the step of the surface of the InP step structure is covered with a mask to intentionally leave this step. It can be seen that the region not covered with the mask can be selectively planarized to any one of the (100) plane, (011) plane and (0-1-1) plane by etching using the etchant. It was issued.

  On the other hand, even if an etching mask is formed on the (100) plane, the (011) plane, or the (0-1-1) plane that originally has no step, and this structure is etched with the mixed liquid of the present invention, the object of the present invention is achieved. Is not achieved. In order for the selective planarization of the present invention to be effective, at least a portion of the region not covered with the mask must be present at a lower position than the region where the etching mask is formed.

Note that, in a compound semiconductor layer containing Ga or As such as InGaAsP and InGaAs, the etching rate by an etchant containing hydrochloric acid and acetic acid according to the present invention is very slow compared to InP. In particular, when the etchant does not contain hydrogen peroxide, these semiconductor layers are not substantially etched. Therefore, a compound semiconductor layer containing Ga or As, such as InGaAsP or InGaAs, can be used as the etching mask for the selective planarization described above, in addition to SiO ₂ and SiN.

Therefore, when the step shape that can effectively apply the above-described planarization effect by the etchant of the present invention is formed, the following is obtained.

A. 10A and 10B, an InP layer 53 is grown using the SiO ₂ pattern 52 formed on the n-type InP substrate 51 as a selective growth mask. The case where the InP layer 53 is planarized with an etchant containing hydrochloric acid and acetic acid is shown.

  When the semiconductor layer is vapor-grown on the substrate using the selective growth mask 52, the vapor-phase raw material is not consumed on the mask 52 and the raw material concentration increases, so that the raw material is excessively supplied to the edge of the mask 52. As a result, the growth rate of the formed semiconductor layer is increased.

11A and 11B, the SiO ₂ pattern 52 is formed on a convex portion such as a mesa stripe formed on the InP substrate 51, and the convex portion is formed using the SiO ₂ pattern 52 as a selective growth mask. The case where InP buried layers 53A and 53B are grown on both sides of the substrate is shown. In this case, as described above, the InP buried layers 53A and 53B rise on both sides of the mask 52 as a result of the increase in the source concentration on the selective growth mask 52.

Therefore, a wet etching process using an etchant containing hydrochloric acid and acetic acid according to the present invention is applied to the structure of FIG. 11A in the process of FIG. 11B to planarize the InP buried layers 53A and 53B. . In the steps of FIGS. 11A and 11B, the selective growth mask 52 is used as an etching mask. However, as shown in FIGS. 12A and 12B, it takes place before the planarization step. Even if the selective growth mask 52 is removed by etching, the same planarization effect is achieved.

B. FIGS. 13A and 13B show a step of flattening unevenness generated on the surface of an InP layer when an InP layer is grown on the structure having the step shape. Show.

  Referring to FIG. 13A, a mesa structure 61M is formed on an n-type InP substrate 61, and an InP layer 62 is deposited on the substrate 61 so as to cover the mesa structure 61M. . As a result, a convex portion corresponding to the mesa structure 61M is formed on the surface of the InP layer 62.

Therefore, in the step shown in FIG. 13B, the InP layer 62 is wet etched with an etchant containing hydrochloric acid and acetic acid to flatten the surface of the InP layer 62.

C. FIGS. 14A and 14B are diagrams illustrating a case where a buried InP layer is crystal-grown using a selective growth mask on a substrate on which a convex portion is formed. 2 shows a case where a slope surface formed on the surface of the buried InP layer adjacent to the convex portion is planarized by the wet etching of the present invention. Such a slope surface occurs when the buried InP layer is formed at a position lower than the height of the selective growth mask.

Referring to FIG. 14A, a mesa structure 71M is formed on an n-type InP substrate 71 using an SiO ₂ pattern 72 as an etching mask, and the mesa structure using the SiO ₂ pattern 72 as a selective growth mask. InP buried layers 73A and 73B are formed on both sides of 71M. At this time, the InP buried layers 73A and 73B are formed at a height not exceeding the mesa structure 71M, and the surface of the buried layers 73A and 73B is formed on the selective growth mask 72. A slope surface descending laterally from the mesa structure 71M is formed due to the excess of the vapor phase material during selective growth of the buried layers 73A and 73B.

14B, a wet etching process using an etchant containing hydrochloric acid and acetic acid according to the present invention is applied to the structure of FIG. 14A to planarize the buried layers 73A and 73B. .

D. As described above, InGaAsP or In wet etching is a semiconductor containing As, and the etching rate in wet etching using the etchant containing hydrochloric acid and acetic acid according to the present invention is as described above. Is very slow compared to InP. Therefore, when the InP layer is planarized using the etchant of the present invention, such an InGaAsP or InGaAs semiconductor film can be used as an etching mask.

  FIG. 15A shows a case where a mesa structure 81M supporting an InGaAsP pattern 82 is formed on an n-type InP substrate 81, and an InP buried layer 83 is deposited so as to cover the mesa structure 81M and the InGaAsP pattern 82. .

  By applying a wet etching process using an etchant containing hydrochloric acid and acetic acid according to the present invention to the structure of FIG. 15A, the InGaAsP pattern 82 acts as an etching mask as shown in FIG. The InP buried layer 83 can be planarized so as to have a surface coinciding with the surface of the InGaAsP pattern 82.

  Alternatively, as shown in FIGS. 16A and 16B, the InP buried layer 83 can be etched to a position below the InGaAsP pattern 82.

  By the way, in the description so far, flattening is performed by applying wet etching using an etchant containing hydrochloric acid and acetic acid to the stepped shape formed with the growth of the InP layer. As a result, (100) plane or (011) ) Plane or (0-1-1) plane has been defined as developing in the InP layer. However, in the initial stage of etching, a slope surface having a surface orientation in the middle of changing from the step slope to the (100) plane, (011) plane, or (0-1-1) plane has appeared. Gradually changes to one of the crystal planes as the etching progresses. Therefore, the planarization of the present invention is not only performed when the step surface is changed to the (100) plane, the (011) plane, or the (0-1-1) plane in the actual manufacturing process of the semiconductor device, but also in the etching process. It is effective even when it is cut off in the middle. That is, the planarization of the present invention is not only when the InP step surface changes to the (100) plane, the (011) plane or the (0-1-1) plane after etching, but also when it becomes an intermediate slope plane or slope. Is also included.

  By the way, an etchant itself containing hydrochloric acid, acetic acid and hydrogen peroxide is known. For example, Japanese Patent Application Laid-Open No. 10-65201 describes an example in which an etchant containing hydrochloric acid, acetic acid, and hydrogen peroxide is used in the mesa stripe forming process. However, the above-mentioned known example uses an etchant to align the side wall surface of the convex part before crystal growth with a specific slope, and has a stepped shape formed with crystal growth which is an effect of the present invention. It cannot be inferred from this known example that the etchant can be used for planarization.

  Japanese Patent Application Laid-Open No. 2000-91303 describes an example in which a side wall surface of a mesa stripe formed by dry etching is etched with an etchant containing hydrochloric acid, acetic acid, and hydrogen peroxide. However, since the above-mentioned known example aims to remove the mesa surface damage caused by dry etching, the flattening of the step shape intended by the present invention cannot be analogized.

  According to the present invention, the step shape generated in the InP layer with crystal growth can be planarized by wet etching using an etchant containing hydrochloric acid and acetic acid, and the position of the planarized surface to be formed Can be matched with the lowest surface portion of the step shape.

[Example 1]
Hereinafter, a manufacturing process of the laser diode having the BH structure according to the first embodiment of the present invention will be described with reference to FIGS. 17 (A) to 18 (E).

  Referring to FIG. 17A, an InGaAsP / InGaAsP multiple quantum well active layer 102, a p-type InP cladding layer 103, and a p-type InGaAs contact layer 104 are sequentially stacked on an n-type InP substrate 101.

Next, in the step of FIG. 17B, the active layer mesa stripe 101M is formed by performing dry etching using the SiO ₂ film 105 as an etching mask. In the illustrated example, the active layer mesa stripe 101M extends in the <011> direction.

Next, in the step of FIG. 17C, using the SiO ₂ film 105 as a selective growth mask, Fe-doped InP buried layers 106 ₁ and 106 ₂ are grown on the substrate 101 on both sides of the mesa stripe 101M by the MOVPE method. To do. The MOVPE process is performed, for example, by setting the growth temperature to 630 ° C. and the growth pressure to 0.1 atm. Using TMIn, PH ₃ and Cp ₂ Fe as raw materials for the group III element, group V element and Fe dopant To do. In this embodiment, the thickness of the InP buried layers 106A and 106B is set so that the lowest part of the InP buried layers 106 ₁ and 106 ₂ is higher than the p-type InGaAs contact layer 104 in the mesa stripe 101M. Is set. As a result, raised portions 106a and 106b are formed in the InP buried layers 106 ₁ and 106 ₂ adjacent to the SiO ₂ film 105 on the mesa stripe 101M.

  Next, in the step of FIG. 18D, the structure of FIG. 17C is wet-etched with an etchant made of a mixture of hydrochloric acid, acetic acid, and water.

  In the step of FIG. 18D, the mixing ratio of hydrochloric acid, acetic acid and water in the etchant is set to 1: 5: 1, and etching is typically performed at a liquid temperature of 2.3 ° C. for 3 minutes. As a result of this etching, the surfaces of the InP buried layers 106A and 106B become (100) planes as shown in FIG. 18D, and are flattened at the height of the p-type InGaAs layer 104.

Finally, in the step of FIG. 18E, the structure of FIG. 18D is immersed in hydrofluoric acid for 1 minute to remove the SiO ₂ film 105 by etching, and then the p-side electrode 107 is formed on the p-type InGaAs layer 104. In addition, an n-side electrode 108 is formed on the lower surface of the substrate 101.

In this embodiment, since the buried layers 106 ₁ and 106 ₂ are flat surfaces in the step of FIG. 18E, the p-side electrode 107 is laminated on a plane. The problem of electrode breakage does not occur.

[Example 2]
Next, a manufacturing process of the laser diode having the BH structure according to the second embodiment of the present invention will be described with reference to FIGS. However, in FIGS. 19A to 19C, the same reference numerals are given to the portions described above, and the description thereof is omitted.

In this embodiment, a mesa stripe 101M is formed on the InP substrate 101 in the step of FIG. 19A in the same step as in FIGS. 17A and 17B, and the SiO ₂ layer 105 is further converted to hydrofluoric acid. Etch away.

  Next, in the step of FIG. 19B, an Fe-doped InP buried layer 106 is grown on the structure of FIG. 19A by the MOVPE method. The InP buried layer 106 formed in this way has a slope surface in which a portion corresponding to a mesa stripe is raised reflecting the step shape of the base. In the step of FIG. 19B, the Fe-doped InP buried layer is formed so as to be higher than the InGaAs contact layer at the lowest thickness portion.

  Finally, in the step of FIG. 19C, the structure of FIG. 19B is etched with an etchant made of a mixture of hydrochloric acid, acetic acid and water. As a result of this etching, the slope slope of the Fe-doped InP buried layer 106 is flattened, and a surface closer to the (100) plane appears.

In the step of FIG. 19C, the InP buried layer 106 is etched, and InP buried layers 106 ₁ and 106 ₂ are formed on both sides of the mesa stripe 101M. When the p-type InGaAs layer contact layer 104 is exposed on the surface as a result of the etching, the exposed contact layer 104 acts as an etching mask layer, and a flat (100) plane aligned with the height of the p-InGaAs layer 104 is formed. It appears as the main surface of the InP buried layers 106 ₁ and 106 ₂ .

[Example 3]
Next, a method of manufacturing a laser diode having a pn buried structure according to the third embodiment of the present invention will be described with reference to FIGS. 20 (A) to 21 (F).

Referring to FIG. 20A, a semiconductor stacked structure in which an InGaAs / InGaAsP multiple quantum well active layer 112, a p-type InP cladding layer 113, and a SiO ₂ film 115 are sequentially stacked on an n-type InP substrate 111. The active layer mesa stripe 111M is formed by patterning this by dry etching.

Next, in the step of FIG. 20B, p-type InP layers 116 ₁ and 116 ₂ are formed on the InP substrate 111 and on both sides of the mesa region 111M by the MOVPE method using the SiO ₂ film 115 as a selective growth mask. ,grow up. DMZn may be used as a p-doping raw material. At this time, the growth of the p-type InP layers 116 ₁ and 116 ₂ is such that the lowest part of the surfaces of the InP layers 116 ₁ and 116 ₂ is higher than the upper surface of the InGaAsP / InGaAsP multi- _double well layer. This is performed so as to be lower than the upper surface of the p-InP clad layer 113 in the stripe 111M.

Next, in the step of FIG. 20C, wet etching is performed on the structure of FIG. 20B using an etchant made of a mixture of hydrochloric acid, acetic acid, and water. As a result of the wet etching, the p-type InP layers 116 ₁ and 116 ₂ become flat, and the surfaces thereof correspond to the lowest regions of the initial surfaces of the InP layers 116 ₁ and 116 ₂ , and the InGaAsP / InGaAsP multiple quantum well layers 112. The p-type InP cladding layer 113 in the mesa stripe 111M is formed at a position lower than the upper surface of the p-type InP cladding layer 113.

  Next, in the step of FIG. 21D, an n-type InP layer 117 and a p-InP layer 118 are sequentially grown on the structure of FIG. 20C by MOVPE.

Further, in the step of FIG. 21E, the SiO ₂ film 115 is etched away with hydrofluoric acid. Finally, in the step of FIG. 21F, the p-type InP cladding layer 119 and the structure of FIG. A p-type InGaAs contact layer 120 is sequentially grown by the MOVPE method.

In general, in the pn buried structure, the position of the n-type InP buried layer 117 must be accurately controlled for current confinement. When the interval between the n-type InP buried layer 117 and the active layer 112 is wide, a current leak path is formed between them, and current injection efficiency is lowered. On the other hand, if the distance between the n-type InP buried layer 117 and the active layer 112 is too narrow, the n-type InP buried layer 117 and the n-type InP layer 111 below the active layer cannot be electrically insulated, Becomes a current leak path. On the other hand, according to the method of this embodiment, the lower surface position of the n-type InP buried layer 117 is determined only by the initial layer thickness of the p-type InP layers 116 ₁ and 116 ₂ in FIG. It is not affected by the index of the crystal growth surface generated by the MOVPE method. Since the growth crystal plane easily changes depending on the growth conditions such as the growth temperature and pressure in the MOVPE process, the position control is difficult. Further, since the n-type InP buried layer 117 is grown on the p-type InP layers 116 ₁ and 116 ₂ having the (100) plane, the n-type InP buried layer 117 is affected by the plane orientation dependence of the n-type dopant incorporation efficiency into the InP layer. Instead, an n-type InP layer 117 having a uniform concentration is formed on the entire surface.

[Example 4]
Next, a method of manufacturing a laser diode having a pn buried structure according to the fourth embodiment of the present invention will be described with reference to FIGS. 22 (A) to 23 (G). However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

Referring to FIG. 22A, an InGaAsP / InGaAsP multiple quantum well active layer 112, a p-type InP cladding layer 113, and a p-type InGaAs contact layer 114 are stacked on the n-type InP substrate 111, and the InGaAs contact is further formed. A mesa stripe 111M is formed on the substrate 111 by dry etching using the SiO ₂ film 105 formed on the layer 114 as a mask. In FIG. 22A, the SiO ₂ film 115 is further etched away with hydrofluoric acid.

  Next, in the step of FIG. 22B, a p-type InP layer 116 is crystal-grown on the structure of FIG. 22A by the MOVPE method. At this time, the p-type InP layer 116 is so formed that the lowest portion of the surface of the p-type InP layer 116 is higher than the upper surface of the InGaAsP / InGaAsP multiple quantum well layer 112 and lower than the lower surface of the p-InGaAs contact layer 114. Set the thickness.

Next, in the step of FIG. 22C, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water is applied to the structure of FIG. 22B to planarize the p-type InP layer 116. At that time, the surface of the planarized InP layer 116 corresponds to the lowest region of the initial surface of the InP layer 116 and is higher than the InGaAsP / InGaAsP multiple quantum well layer 112 and lower than the p-type InGaAs layer 114. . As a result of the planarization process of FIG. 22C, the InP layer 116 is divided into an InP region 116 ₁ and an InP region 116 ₂ across the mesa stripe 111M.

  Next, in the step of FIG. 22D, an n-type InP buried layer 117A is grown on the structure of FIG. 22C by MOVPE. At this time, the thickness of the n-type InP layer 117A is determined so that the lowest part of the surface of the InP layer 117A is lower than the lower surface of the InGaAs contact layer 114.

  Next, in the step of FIG. 23E, the n-type InP buried layer 117A is etched by wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water. As a result, the n-type InP layer 117A is planarized at a position where the surface is lower than the InGaAs contact layer 114.

  Next, in the step of FIG. 23F, a p-type InP buried layer 118A is grown on the structure of FIG. 23E so as to cover the InGaAs contact layer 114 by MOVPE.

  Finally, in the step of FIG. 23G, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water is applied to the p-type InP buried layer 118A of FIG. The upper surface of the buried layer 118A is made to coincide with the upper surface of the InGaAs contact layer 114.

According to the present embodiment, by controlling the thickness of the p-type InP buried layer 116A in the step of FIG. 22B, the bottom surface of the n-type InP buried layer 117A as shown in FIG. The position of the upper surface of the n-type InP layer 117A can be controlled by controlling the initial thickness of the n-type InP buried layer 117A in the step of FIG. Can be manufactured with high accuracy.

[Example 5]
Next, a method for manufacturing a laser diode having a pn buried structure according to the fifth embodiment of the present invention will be described with reference to FIGS. 24 (A) to 26 (G). However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

Referring to FIG. 24A, the InGaAsP / InGaAsP multiple quantum well active layer 112, the p-type InP clad layer 113, and the p-type InGaAs contact are formed on the n-type InP substrate 111 in the same manner as in the step of FIG. A mesa stripe 111M including the layer 114 is formed by dry etching using the SiO ₂ film 115 as a mask, and the SiO ₂ film 115 is removed by etching with hydrofluoric acid.

  Next, in the step of FIG. 24B, a p-type InP layer 116 is grown on the structure of FIG. 24A by the MOVPE method. At that time, the p-type InP layer 116 is so formed that the lowest part of the surface of the p-type InP layer 116 is higher than the upper surface of the InGaAsP / InGaAsP multiple quantum well layer 112 and lower than the lower surface of the p-type InGaAs contact layer 114. Set the thickness.

Next, in the process of FIG. 24C, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water is applied to the structure of FIG. 24B to planarize the p-type InP layer 116. At that time, the surface of the planarized InP layer 116 corresponds to the lowest region of the initial surface of the InP layer 116 and is higher than the InGaAsP / InGaAsP multiple quantum well layer 112 and lower than the p-type InGaAs layer 114. . As a result of the planarization step of FIG. 24C, the InP layer 116 is divided into an InP region 116 ₁ and an InP region 116 ₂ with the mesa stripe 111M interposed therebetween. As described above, the steps of FIGS. 24A to 24C correspond to the steps of FIGS. 22A to 22C, respectively.

  Next, in the step of FIG. 25D, an n-type InP layer 117B and a p-type InP buried layer 118B are sequentially grown on the composition of FIG. 24C by the MOVPE method. At this time, the lowest part of the n-type InP layer 117B is lower than the lower surface of the p-type InGaAs layer 114, and the lowest part of the p-type InP layer 118B is higher than the InGaAs layer 114. The thickness of layers 117B and 118B is set.

  Next, in the step of FIG. 25E, the InP layers 118B and 117B are etched by wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water. In the wet etching process, the InGaAs layer 114 functions as an etching mask, and the surfaces of the p-type InP layer 118B and the n-type InP layer 117B are planarized.

  Next, in the step of FIG. 25 (F), the InGaAs layer 114 is removed by etching with a mixed solution of hydrofluoric acid and nitric acid. Finally, in the step of FIG. 26 (G), the MOVPE is formed on the structure of FIG. 25 (F). The p-type InP cladding layer 119 and the p-type InGaAs contact layer 120 are successively grown by the method.

Also in the method of this embodiment, the position of the lower surface of the n-type InP buried layer 117 can be controlled by controlling the thickness of the n-type InP buried layer 116 in the step of FIG.

[Example 6]
Next, a method of manufacturing a laser diode having a pn buried structure according to the sixth embodiment of the present invention will be described with reference to FIGS. 27 (A) to (C) and FIG. 28 (D). However, in the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIG. 27A, an InGaAsP / InGaAsP multiple quantum well active layer 112, a p-type InP cladding layer 113, and a p-type InGaAs contact are formed on the n-type InP substrate 111 in the same manner as in the step of FIG. A mesa stripe 111M including the layer 114 is formed by dry etching using the SiO ₂ film 115 as a mask.

Next, in the step of FIG. 27B, the p-type InP buried layer 116, the n-type InP buried layer 117, and the p-type InP are formed by the MOVPE method with the SiO ₂ film 115 left on the mesa stripe 111M. Layer 118 is grown sequentially. In the MOVPE process of FIG. 27B, typically, the growth temperature is set to 550 ° C. and the growth pressure is set to 0.1 atm. As a group III source material, a group V source material, and a p-type and n-type dopant source, respectively. TMIn, PH ₃ , DMZn, SiH ₄ are used and 10 CCM of methyl chloride CH ₃ Cl is added. By combining such low-temperature growth and addition of chlorine-based gas, each buried layer is suppressed from growing on the side surface of the mesa and grows in the <100> direction from the bottom surface of the mesa.

  In the step of FIG. 27B, each buried layer is formed such that the lower surface of the n-type InP layer 117 is higher than the upper surface of the active layer 112 at a position in contact with the mesa stripe 111M. The thicknesses of the p-type InP layer 116 and the n-type InP layer 117 are controlled so that the top surface of the p-type InGaAs layer 111M is lower than the bottom surface of the p-type InGaAs contact layer 114 at a position where it contacts the mesa stripe 111M.

Next, in the step of FIG. 27C, the structure of FIG. 27B is etched by wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid, and water using the SiO ₂ film 115 as a mask. As a result, the p-type InP layer 118 is planarized, and a planarized surface coinciding with the upper surface of the InGaAs cladding layer 114 is obtained.

Next, in the step of FIG. 28D, the SiO ₂ film 115 is removed by etching with a mixed solution of hydrofluoric acid and hydrogen peroxide.

In this embodiment, a flat growth surface can be obtained by a single buried growth, and the manufacturing process of the laser diode can be greatly simplified.

[Example 7]
Next, a method for manufacturing a laser diode having a ridge structure according to the seventh embodiment of the present invention will be described with reference to FIGS. 29 (A) to 30 (E).

Referring to FIG. 29A, on an n-type InP substrate 121, an InGaAs / InGaAsP multiple quantum well active layer 122, a p-type InP cladding layer 123, a p-type InGaAs contact layer 124, an SiO ₂ film 125, A semiconductor laminated structure is formed by sequentially laminating the layers, and is further patterned by dry etching using the SiO ₂ film 125 as a mask, thereby forming a ridge stripe 123M on the cladding layer 123. Further, in the step of FIG. 29A, the SiO ₂ film 125 is removed by etching with hydrofluoric acid.

  Next, in the step of FIG. 29B, the n-type InP layer 126 is crystal-grown on the structure of FIG. 29A by the MOVPE method. At this time, the thickness of the n-type InP layer 126 is set so that the upper surface of the InP layer 126 is lower than the lower surface of the p-type InGaAs layer 124.

  Next, in the step of FIG. 29C, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water is performed on the structure of FIG. 29B using the InGaAs contact layer 124 as a mask. The surface of the n-type InP layer 126 is planarized. As a result of the planarization, the position of the upper surface of the n-type InP layer 126 is lower than the position of the lower surface of the p-type InGaAs layer 124.

  Next, in the step of FIG. 30D, the p-type InP layer 127 is formed on the structure of FIG. 29C by the MOVPE method, and the p-type InGaAs layer 124 is also formed on the upper surface of the p-type InP layer 127. The thickness is higher than the upper surface.

  Finally, in the step of FIG. 30E, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water is performed on the structure of FIG. 30D using the InGaAs contact layer 124 as a mask. The InP layer 127 is planarized. As a result of the planarization, the p-type InP layer 127 has a surface that matches the surface of the InGsAs contact layer 124.

Even in a laser diode having such a ridge structure, the surface position of the n-type InP buried layer 126 must be carefully controlled in order to achieve effective current confinement. For example, when the interval between the n-type InP layer 126 and the p-type InGaAs contact layer 124 is wide, this interval acts as a current leak path. In the method of this embodiment, a desired effective current squeezing can be realized only by controlling the thickness of the n-type InP buried layer 126 in the step of FIG.

[Example 8]
Next, a method for manufacturing a laser diode having a ridge structure according to an eighth embodiment of the present invention will be described with reference to FIGS. 31 (A) to 32 (F). However, in the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIG. 31A, on the n-type InP substrate 121, an InGaAs / InGaAsP multiple quantum well active layer 122, a p-type InP cladding layer 123, and the like in the previous step of FIG. A semiconductor multilayer structure in which a p-type InGaAs contact layer 124 and an SiO ₂ film 125 are sequentially laminated is formed, and further patterned by dry etching using the SiO ₂ film 125 as a mask, thereby forming a layer on the cladding layer 123. A ridge stripe 123M is formed.

Next, in the step of FIG. 31B, the n-type InP layer 126 is formed on the structure of FIG. 31A by the MOVPE method with the SiO ₂ film 125 left as a selective growth mask. The upper surface of 126 is formed so as to be lower than the lower surface of the p-type InGaAs contact layer 124.

  Next, in the step of FIG. 31C, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid, and water is performed on the structure of FIG. 31B to planarize the InP layer 126. The InP layer 126 thus planarized has a planarized surface at a position lower than the p-type InGaAs layer 124.

Next, in the step of FIG. 32D, the p-type InP layer 127 is formed on the structure of FIG. 31C by the MOVPE method while leaving the SiO ₂ film 125 as a selective growth mask. Even in a region where the upper surface of 127 is the lowest, it grows with such a thickness as to be higher than the height of the p-type InGaAs contact layer 124.

Next, in the step of FIG. 32E, wet etching is performed on the structure of FIG. 32D using an etchant made of a mixed solution of hydrochloric acid, acetic acid and water, and the p-type InP layer 127 is planarized. . The planarization step of FIG. 32E is performed with the SiO ₂ film 125 left on the contact layer 124. As a result, the height of the planarization surface of the p-type InP layer 127 is the contact layer. It corresponds to the height of the upper surface of 124.

Finally, in the step of FIG. 32F, the SiO ₂ film 125 is removed by etching with a mixed solution of hydrofluoric acid and hydrogen peroxide.

[Example 9]
Next, a method for manufacturing a branched optical waveguide according to the ninth embodiment of the present invention will be described with reference to FIGS. 33 (A) to 34 (E).

Referring to FIG. 33A, an InGaAsP / InGaAsP multiple quantum well layer 202 and an InP cladding layer 203 are stacked on an n-type InP substrate 201, and a SiO ₂ pattern 205 branched into a Y-shape is masked. Further, by performing dry etching reaching the InP substrate 201, a Y-shaped mesa stripe 201M corresponding to the SiO ₂ pattern 205 is formed on the substrate 201.

Next, in the step of FIG. 33B, the Fe-doped InP buried layer 206 is replaced with the Fe-doped InP layer 206 with the SiO ₂ pattern 205 left as a selective growth mask on the structure of FIG. Is formed by the MOVPE method so that the lowest surface portion is higher than the upper surface of the clad layer 203 in the mesa stripe 201M. As a result of the process of FIG. 33B, the Fe-doped InP buried layer 206 is formed on the InP substrate 201 so as to sandwich the Y-shaped mesa stripe 201M from the side.

  Next, in the step of FIG. 33C, the structure of FIG. 33B is etched by wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water, and the surface of the Fe-doped InP buried layer 206 is etched. And flattening so as to coincide with the upper surface of the uppermost InP cladding layer 203 of the mesa stripe 201M.

Next, in the step of FIG. 34D, the SiO ₂ film 205 is removed by etching with a mixed solution of hydrofluoric acid and hydrogen peroxide. Finally, in the step of FIG. 34E, the SiO ₂ film 205 of FIG. An Fe-doped InP layer 207 is grown on the structure by MOVPE. At this time, since the InP clad layer 203 and the Fe-doped InP layer 206 form a flat surface made of (100) plane in the step of FIG. 34D, the surface of the Fe-doped InP layer 207 is also planarized. ing.

As described above with reference to FIG. 3, in the conventional process, when an InP buried layer is grown around a stripe having a branch point, the buried InP layer may overhang on the mask at the branch portion. . On the other hand, in this embodiment, the overhanging portion can be removed by wet etching the InP buried layer 206 in the step of FIG. 33C. As a result, in the step of FIG. Even if the InP layer 207 is deposited, no cavity is formed.

[Example 10]
Next, a manufacturing process of an optical waveguide having a branch point and a BH buried structure according to the tenth embodiment of the present invention will be described with reference to FIGS. However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

Referring to FIG. 35A, the InGaAsP / InGaAsP multiple quantum well layer 202, the InP clad layer 203, and the InGaAs layer 204 are sequentially stacked on the n-type InP substrate 201, and SiO _{2 (} not shown) is further illustrated. By performing dry etching using the pattern 205, a Y-type mesa stripe 201M is formed. In the step of FIG. 35A, after the formation of the mesa stripe, the SiO ₂ film 205 is etched away with hydrofluoric acid.

  Next, in the step of FIG. 35B, the Fe-doped InP buried layer 206 is formed on the structure of FIG. 35A by the MOVPE method, and the lowest surface portion of the Fe-doped InP layer 206 is the p-type InGaAs. The layer 204 is formed to a thickness that is higher than the upper surface of the layer 204. The InP buried layer 206 formed in this way has irregularities reflecting the shape of the Y-shaped stripe pattern 201M serving as a base on the surface thereof.

  Finally, in the step of FIG. 35C, wet etching is performed on the structure of FIG. 35B using an etchant made of a mixture of hydrochloric acid, acetic acid and water, and the InP buried layer 206 is planarized. .

In the planarization step of FIG. 35C, the p-type InGaAs layer 204 acts as an etching mask, and as a result, the Fe-doped InP 206 has a surface that substantially matches the surface of the InGaAs layer 204. Accordingly, even when another semiconductor layer or an electrode pattern is formed on the structure of FIG. 35C in the steps after FIG. 35C, there is no problem because it is formed on a flat surface.

[Example 11]
Next, a method for fabricating a semiconductor device including an active layer selective growth step according to an eleventh embodiment of the present invention will be described with reference to FIGS. 36 (A) to 36 (C).

Referring to FIG. 36A, the SiO ₂ film pattern 212 exposing the substrate region extending in the <0-11> direction on the surface of the n-type InP substrate 211 is along the <0-11> direction. The width is changed.

36B, the n-type InP layer 213, the InGaAsP / InGaAsP multiple quantum well layer 214, and the p-type InP cladding layer 215 are formed on the InP substrate 211 by the MOVPE method using the SiO ₂ film pattern 212 as a mask. Are sequentially deposited. In the vapor phase growth using the SiO ₂ film pattern 212 as a mask, the raw material concentration is increased on the SiO ₂ film pattern 212 where no growth of the semiconductor layer occurs. As a result, the SiO ₂ film pattern 212 is interrupted <0− The material is excessively supplied to the substrate region extending in the 11> direction. Oversupply of such raw materials, the coverage of the SiO ₂ film, that depends on the width of the SiO ₂ film pattern 212, or increased raw material the width is excessively supplied the wider, the thickness of the semiconductor layer 213 215 To increase. Since the width of the SiO ₂ film pattern 212 changes along the <0-11> direction, the thickness of the semiconductor layers 213 to 215 changes in the <0-11> direction.

  Finally, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water in the step of FIG. 36C is applied to the step of FIG. 36B, thereby flattening the p-type InP layer 215. Turn into. At this time, the p-type InP layer 215 is planarized at a height corresponding to the lowest surface portion of the upper surface thereof.

When the step structure is generated by such selective growth including the active layer 214, a problem occurs in the current confinement embedding growth process or the electrode forming process in the subsequent process. However, according to the present embodiment, the step structure is easily flattened. Therefore, such inconvenience can be avoided.

[Example 12]
Next, a manufacturing process of the semiconductor device according to the twelfth embodiment of the present invention including the selective growth process of the active layer will be described with reference to FIGS. 37 (A) to 38 (E). However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

Referring to FIG. 37A, in this embodiment, the SiO ₂ film pattern 212 is formed on the InP substrate 211 in the same manner as the process of FIG. Next, in the step of FIG. 37B, the InP substrate 211 is dry-etched using the SiO ₂ film pattern 212 as a mask in the step of FIG. 37B, and a groove 211A having a depth of about 1 μm is formed on the surface of the InP substrate 211. Form.

Next, in the step of FIG. 37C, the InGaAsP / InGaAsP multiple quantum well layer 213 and the p-type InP cladding layer 215 are formed on the structure of FIG. 37B by MOVPE so as to fill the trench 211A. . At this time, the thickness of the p-type InP cladding layer 215 is set so that the lowest surface portion of the upper surface of the InP cladding layer 215 is higher than the surface of the n-InP substrate 211. Since the SiO ₂ mask 212 changes its width along the <0-11> direction, the thickness of the InP cladding layer 215 is modulated in the <0-11> direction.

Next, in the step of FIG. 38D, the SiO ₂ film pattern 212 is removed by etching with a mixed solution of hydrofluoric acid and hydrogen peroxide solution. Finally, in the step of FIG. 38E, the SiO ₂ film pattern 212 of FIG. Wet etching is performed on the structure using an etchant made of a mixture of hydrochloric acid, acetic acid and water.

As a result of the wet etching, the InP cladding layer 215 is planarized, and a flat surface matching the InP substrate 211 is obtained as the upper surface of the cladding layer 215.

[Example 13]
Next, a multilayer optical waveguide manufacturing method according to a thirteenth embodiment of the present invention will be described with reference to FIGS. 39 (A) to 41 (G). However, in FIGS. 39A to 41G, the same reference numerals are given to the portions described above, and the description thereof is omitted.

Referring to FIG. 39A, after an InGaAsP / InGaAsP multiple quantum well layer 222 and an InP cladding layer 223 are sequentially stacked on an n-type InP substrate 221, first etching is performed by dry etching using the SiO ₂ film pattern 225 as a mask. The waveguide mesa stripe pattern 221M is formed. In the example of FIG. 39A, the first waveguide mesa stripe pattern 212M has a shape branched in a Y shape.

Next, in the step of FIG. 39B, the first waveguide is formed on the structure of FIG. 39A by using the Fe-doped InP buried layer 226 by the MOVPE method and the SiO ₂ film pattern 225 as the selective growth mask. The mesa stripe pattern 221M is grown so as to be embedded. In the step of FIG. 39B, the thickness of the Fe-doped InP layer 226 is set so that the lowest surface portion is higher than the upper portion of the first waveguide mesa stripe pattern 221M.

  Next, in the step of FIG. 39C, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water is applied to the structure of FIG. 39B to planarize the surface of the InP layer 226. To do.

Further, in the step of FIG. 40D, the SiO ₂ film 225 is removed by etching with a mixed solution of hydrofluoric acid and hydrogen peroxide, and in the step of FIG. 40E, the structure shown in FIG. An InP cladding layer 227, an InGaAsP / InGaAsP multiple quantum well layer 228, and an InP cladding layer 229 are sequentially stacked. Further, a _second waveguide mesa stripe 227M is formed on the InP layer 226 by dry etching using the SiO ₂ film pattern 230 formed on the InP cladding layer 229 as a mask.

Next, in the step of FIG. 41F, an Fe-doped InP buried layer 231 is formed on the structure of FIG. 40E by the MOVPE method using the SiO ₂ pattern 230 as a selective growth mask. At this time, the Fe-doped InP layer 231 is formed to have a thickness that is higher than the upper portion of the waveguide mesa stripe pattern 227M even at the lowest surface portion.

Further, in the step of FIG. 41G, wet etching using an etchant made of a mixture of hydrochloric acid, acetic acid and water is applied to the structure of FIG. 41F to planarize the Fe-doped InP layer 231. Finally, the SiO ₂ film pattern 230 is removed by etching with a mixture of hydrofluoric acid and harsh hydrogenated water to obtain a two-layered optical waveguide.

  When optical waveguides are stacked in multiple layers, the surface must be flat after each layer is formed. In this embodiment, the thickness of the InP layer 226 or 231 is controlled, and the lowest surface of these layers is used. Flatten according to the part. Such flattening by polishing cannot control the layer thickness.

  In each of the embodiments described above, an example in which a mixed solution of hydrochloric acid, acetic acid and water is used as an etchant has been described. The planarization by the etchant of the present invention is effective when the composition of the etchant is expressed as hydrochloric acid: acetic acid: water = 1: X: Y, and the concentration parameter X is in the range of 0 to 20 and the concentration parameter Y is in an arbitrary range. It is. Further, when a mixed solution of hydrochloric acid, acetic acid, hydrogen peroxide water and water is used as the etchant of the present invention, the etchant composition is represented by hydrochloric acid: acetic acid: hydrogen peroxide water: water = 1: X: Y: Z. The same effect is obtained when the density parameter X is in the range of 0 to 20, the density parameter Y is in the range of 0 to 0.3, and the density parameter Z is in the arbitrary range.

  Since the present invention is based on the principle of planarization by anisotropic etching with respect to the step shape of the grown InP layer, the scope of the present invention is not limited to optical semiconductor devices but also to all semiconductor devices using InP as a material. Applicable.

(A)-(D) are figures which show the manufacturing process of the laser diode which has a buried heterostructure by related technology. It is a figure explaining the problem accompanying the process of FIG. (A)-(C) are figures which show the formation process of the optical waveguide by related technology. It is a figure explaining the problem of FIG. (A)-(D) is a figure explaining the manufacturing process of the laser diode by another related technique, and its problem. It is a figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the laser diode by 1st Example of this invention. (D)-(E) is a figure (the 2) which shows the manufacturing process of the laser diode by 1st Example of this invention. (A)-(C) is a figure which shows the manufacturing process of the laser diode by 2nd Example of this invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the laser diode by 3rd Example of this invention. (D)-(F) is a figure (the 2) which shows the manufacturing process of the laser diode by 3rd Example of this invention. (A)-(D) are figures (the 1) which show the manufacturing process of the laser diode by 4th Example of this invention. (E)-(G) is a figure (the 2) which shows the manufacturing process of the laser diode by 4th Example of this invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the laser diode by 5th Example of this invention. (D)-(F) is a figure (the 2) which shows the manufacturing process of the laser diode by 5th Example of this invention. (G) is a figure (the 3) which shows the manufacturing process of the laser diode by 5th Example of this invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the laser diode by 6th Example of this invention. (D) is a figure (the 2) which shows the manufacturing process of the laser diode by 6th Example of this invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the laser diode by 7th Example of this invention. (D)-(E) is a figure (the 2) which shows the manufacturing process of the laser diode by 7th Example of this invention. (A)-(C) are figures (the 1) which show the manufacturing process of the laser diode by 8th Example of this invention. (D)-(F) is a figure (the 2) which shows the manufacturing process of the laser diode by 8th Example of this invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the optical waveguide by 9th Example of this invention. (D)-(E) is a figure (the 2) which shows the manufacturing process of the optical waveguide by 9th Example of this invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the optical waveguide by 10th Example of this invention. (A)-(C) are diagrams showing a manufacturing process of a semiconductor device according to an eleventh embodiment of the present invention. (A)-(C) is a figure (the 1) which shows the manufacturing process of the semiconductor device by 12th Example of this invention. (D)-(E) is a figure (the 2) which shows the manufacturing process of the semiconductor device by 12th Example of this invention. (A)-(C) are figures (the 1) which show the manufacturing process of the multilayer optical waveguide by 13th Example of this invention. (D)-(E) is a figure (the 2) which shows the manufacturing process of the multilayer optical waveguide by 13th Example of this invention. (F)-(G) is a figure (the 3) which shows the manufacturing process of the multilayer optical waveguide by 13th Example of this invention.

Explanation of symbols

10 laser diode 11,21,31,41,51,61,71,81 InP substrate 12 multiple quantum well active layer 13 InP cladding layer 14 InGaAs contact layer 15,22,33,42,52,72,82 SiO ₂ mask 16A, 16B, 23, 32A, 32B, 43A, 43B, 53A, 53B, 73A, 73B InP buried layer 16a, 16b Swelling portion 17, 18 Electrode 17a Electrode disconnection 23A Overhang portion 23B, 32a, 32b Cavity 24, 34 , 53, 62, 83 InP regrowth layer 31M, 41M, 51M, 61M, 71M, 81M Mesa structure 101, 111, 121 InP substrate 101M, 111M, 123M Mesa stripe 102, 112, 122 Multiple quantum well layers 103, 113, 123 InP clad layer 104, 114, 124 InGaAs contact layer 105, 115, 125 SiO ₂ mask 106, 106 ₁ , 106 ₂ , 116 ₁ , 116 ₂ InP buried layer 106a, 106b Swell 107, 108 Electrode 117, 117A, 117B, 126 n-type InP layer 118, 118A, 118B, 127 p-type InP layer 119 InP clad layer 120, 124 InGaAs contact layer 123M ridge stripe 201 InP substrate 201M mesa stripe 202 multiple quantum well layer 203 InP clad layer 204 InGaAs layer 205 SiO ₂ mask 206, 226,231 InP buried layer 207 InP regrowth layer 211 and 221 InP substrate 221M first-layer light guide pattern 212,225,230 SiO ₂ film 213,215,2 3,227,229 InP cladding layer 214,222,228 multi-quantum well layer 224 GaInAs layer

Claims (27)

A step of crystal-growing an InP buried layer on the growth start surface having a step so as to have a step shape;
And a step of performing wet etching using an etchant containing hydrochloric acid and acetic acid on the InP buried layer to flatten the step shape of the InP buried layer.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the growth step is performed so that the step shape is generated corresponding to an initial step of the growth start surface.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the initial step on the growth start surface has a mesa shape.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the initial step on the growth start surface has a step shape.   2. The growth start surface according to claim 1, wherein the growth start surface is a flat surface and partially has a selective growth mask, and the step of forming the step corresponds to the selective growth mask. A method for manufacturing a semiconductor device.   The planarization step is performed such that the InP layer has a planarization surface composed of any one of the (100) plane, the (011) plane, and the (0-1-1) plane as a result of the planarization process. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method.   In the planarization step, the InP layer is closer to one of the (100) plane, the (011) plane, and the (0-1-1) plane as a result of the planarization step than before the planarization step. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed so as to have a planarized surface.   The growth step is performed such that the InP layer surface is lower than the highest position of the growth start surface, and the planarization step is performed by measuring the InP layer from the substrate surface after the planarization step. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed so as to have a planarized surface having a height corresponding to the lowest position of the InP layer.   The growth step is performed such that the surface of the InP layer is equal to or higher than the highest position of the growth start surface, and the planarization step is performed after the planarization step. The semiconductor device according to claim 1, wherein the semiconductor device is executed so as to have a planarized surface having a height corresponding to the highest position of the growth start surface as measured from the surface. Production method.   The growth start surface has a selective growth mask at a part of the initial step, and the step of growing the InP layer is formed such that the step shape of the InP layer corresponds to an edge of the selective growth mask. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the method is performed as follows.   The step of growing the InP layer is performed such that a step shape of the InP layer forms a slope region along a side surface of the initial step on the growth start surface. Semiconductor device manufacturing method.   The step of growing the InP layer is performed such that the step shape of the InP layer is formed so that the InP layer covers the initial step on the growth start surface. A method for manufacturing a semiconductor device.   13. The method of manufacturing a semiconductor device according to claim 1, wherein the etchant contains hydrochloric acid and acetic acid so that the concentration of acetic acid is 20 times or less that of hydrochloric acid.   The method of manufacturing a semiconductor device according to claim 1, wherein the etchant further includes an additional agent including at least one of water and hydrogen peroxide.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the additional agent adds hydrogen peroxide water to the etchant at a concentration of 30% or less of hydrochloric acid with respect to hydrochloric acid and acetic acid.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the additional agent is made of water.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the additional agent comprises water and hydrogen peroxide water.   A region under the selective etching mask, which carries a selective etching mask, has a surface region lower than the selective etching mask, and etches an InP layer having a stepped portion on the surface with an etchant containing hydrochloric acid and acetic acid. A method of manufacturing a semiconductor device, wherein the surface of the InP layer is flattened except for.   19. The method of manufacturing a semiconductor device according to claim 18, wherein the step shape of the InP layer is formed corresponding to an initial step portion on a growth start surface.   20. The method of manufacturing a semiconductor device according to claim 19, wherein the selective etching mask is provided above the initial stepped portion.   19. The method of manufacturing a semiconductor device according to claim 18, wherein the selective etching mask is provided on a surface of a step portion on the InP layer.   22. The method of manufacturing a semiconductor device according to claim 18, wherein the selective etching mask is selected from the group consisting of an insulating material and a compound semiconductor excluding InP.   23. The method of manufacturing a semiconductor device according to claim 22, wherein the selective etching mask is made of any one of silicon oxide, silicon nitride, InGaAs, InGaAsP, AlGaInP, AlGaAs, and GaInNAs.   The method for manufacturing a semiconductor device according to any one of claims 18 to 23, wherein the etchant contains hydrochloric acid and acetic acid so that the concentration of acetic acid is 20 times or less that of hydrochloric acid.   25. The method of manufacturing a semiconductor device according to claim 18, wherein the etchant further includes an additional agent comprising at least one of water and hydrogen peroxide water.   26. The method of manufacturing a semiconductor device according to claim 25, wherein the additional agent is a hydrogen peroxide solution added to hydrochloric acid and acetic acid at a concentration of 30% or less of hydrochloric acid.   26. The method of manufacturing a semiconductor device according to claim 25, wherein the additional agent is made of water.

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