JP2006073806A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2006073806A
JP2006073806A JP2004255543A JP2004255543A JP2006073806A JP 2006073806 A JP2006073806 A JP 2006073806A JP 2004255543 A JP2004255543 A JP 2004255543A JP 2004255543 A JP2004255543 A JP 2004255543A JP 2006073806 A JP2006073806 A JP 2006073806A
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polishing
semiconductor substrate
polishing pad
slurry
pad
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Shinji Hirano
伸治 平野
Koichi Yamagata
恒一 山形
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Kawasaki Microelectronics Inc
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<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of reducing occurrence of flaws on the surface of a semiconductor substrate in its polishing process. <P>SOLUTION: The surface of the semiconductor substrate is polished by pressing the surface of the semiconductor substrate on a polishing pad at a prescribed pressure, and moving the surface of the semiconductor substrate at a prescribed relative speed with respect to the polishing pad. Then the semiconductor substrate is left from the polishing pad after a buffering step. The relative speed is reduced more than the speed at polishing while the pressing pressure of the surface of the semiconductor substrate onto the polishing pad is kept within a range between the pressing pressure at polishing or below and a pressure of 60% thereof or over. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置の製造方法、さらに詳しくは、半導体基板上に堆積された絶縁膜等の表面を研磨するCMP(化学機械研磨)技術に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a CMP (Chemical Mechanical Polishing) technique for polishing a surface of an insulating film or the like deposited on a semiconductor substrate.

半導体装置の製造において、配線等による段差が形成された半導体基板上に堆積された絶縁膜の表面を平坦化する、もしくは、溝が形成された半導体基板上に絶縁膜を堆積し、溝外の部分を除去して溝内に埋め込まれた部分を残す(STI(シャロー・トレンチ・アイソレーション工程))、等の目的で、絶縁膜の表面を研磨するCMP法が広く利用されている。CMP法はまた、半導体基板上の絶縁膜に溝やホールを形成し、その上に堆積したタングステンや銅などの金属材料の、溝もしくはホール外の部分を除去し、溝もしくはホール内に金属材料を埋め込む(ダマシンもしくはプラグ形成工程)目的でも使用されている。   In manufacturing a semiconductor device, the surface of an insulating film deposited on a semiconductor substrate on which a step due to wiring or the like is formed is planarized, or an insulating film is deposited on a semiconductor substrate on which a groove is formed, A CMP method for polishing the surface of an insulating film is widely used for the purpose of removing the portion and leaving a portion embedded in the trench (STI (shallow trench isolation process)). The CMP method also forms a groove or a hole in an insulating film on a semiconductor substrate, removes a portion of the metal material such as tungsten or copper deposited thereon, and removes a portion outside the groove or the hole, and a metal material in the groove or hole. It is also used for the purpose of embedding (damascene or plug forming process).

CMPでは、研磨すべき材料が表面に形成された半導体基板を、研磨パッドを表面に有する定盤に、一定の圧力で押しつけ、研磨パッドに対して一定の相対速度で移動させながら、研磨パッドの表面に固定された、もしくは、スラリー(研磨液)に含有されて研磨パッド上に供給された、砥粒の作用によって、基板表面の被研磨材料の研磨が行われる。   In CMP, a semiconductor substrate on which a material to be polished is formed is pressed against a surface plate having a polishing pad on the surface with a constant pressure and moved at a constant relative speed with respect to the polishing pad. The material to be polished on the surface of the substrate is polished by the action of the abrasive grains fixed on the surface or contained in the slurry (polishing liquid) and supplied onto the polishing pad.

しかし、研磨によって、被研磨材料(絶縁膜平坦化の場合)、もしくは、被研磨材料が除去された後に露出する下地材料(STI、プラグ、ダマシンの場合)の表面に傷(スクラッチ等)が発生する場合があることが知られている。特に、研磨速度を高くして処理能力を向上させるために、押しつけ圧力および相対速度を大きくした場合には、傷の発生が顕著になる。   However, scratches (scratches, etc.) occur on the surface of the material to be polished (in the case of planarizing the insulating film) or the underlying material (in the case of STI, plug, damascene) that is exposed after the material to be polished is removed by polishing. It is known that there may be. In particular, when the pressing pressure and the relative speed are increased in order to increase the polishing rate and improve the processing capability, the occurrence of scratches becomes significant.

このような傷発生を防止もしくは削減するために、加工終了時に、定盤の回転速度を低速にするとともに、圧力を低く制御することが提案されている(特許文献1)。   In order to prevent or reduce the occurrence of such scratches, it has been proposed to reduce the rotation speed of the surface plate and control the pressure to be low at the end of machining (Patent Document 1).

また、研磨後の表面粗度を減少させるために、研磨のための研磨パッドとは別の補助パッドに半導体基板を移し、研磨パッド上にスラリーを供給してスラリーバフミガキ(タッチ−アップ工程)を行うことが提案されている(特許文献2)。   Further, in order to reduce the surface roughness after polishing, the semiconductor substrate is transferred to an auxiliary pad different from the polishing pad for polishing, slurry is supplied onto the polishing pad, and slurry buffing (touch-up process) Has been proposed (Patent Document 2).

さらに、純水との混合によるpH値の変化(pHショック)によってスラリーに含まれる砥粒が凝集し、傷が発生することを防止するため、スラリーのpH値を調整する手段を設けることが提案されている(特許文献3)。   Furthermore, in order to prevent the abrasive grains contained in the slurry from aggregating due to a change in pH value (pH shock) due to mixing with pure water and causing scratches, it is proposed to provide means for adjusting the pH value of the slurry. (Patent Document 3).

特開昭62−162464号公報JP 62-162464 A 特開平10−202507号公報JP-A-10-202507 特開2000−326211号公報JP 2000-326211 A

しかし、研磨に使用したパッド表面には、スラリーに含有させて供給した砥粒が凝集した大粒径の砥粒や、被研磨材料の破片等が存在しており、その表面に被加工基板を押しつけて研磨を行う限り、特許文献1で提案されたように終了時の速度や圧力を低くしたとしても、傷の発生は避けられない。   However, the pad surface used for polishing contains large-diameter abrasive grains in which the abrasive grains supplied in the slurry are aggregated, debris of the material to be polished, etc., and the substrate to be processed is on the surface. As long as it is pressed and polished, even if the speed and pressure at the end are lowered as proposed in Patent Document 1, the occurrence of scratches is inevitable.

また、特許文献2では、研磨パッドとは別の補助パッドに半導体基板を移してタッチ−アップ工程を行うことが提案されているが、具体的に、どのようなシーケンスおよび条件で行うべきかについての記載は無い。   Further, in Patent Document 2, it is proposed to perform a touch-up process by transferring a semiconductor substrate to an auxiliary pad different from the polishing pad. Specifically, what sequence and conditions should be used. There is no description.

さらに、本発明者による検討によって、研磨パッドから半導体ウエハを脱離するタイミングで傷が発生する場合があることが明らかになった。すなわち、半導体ウエハと研磨パッドとの密着性が高いため、半導体ウエハを研磨パッドから脱離する時に、研磨パッドが撓み、研磨パッドが半導体ウエハ表面に接触することによって、半導体ウエハ表面に傷が発生する場合がある。このような脱離時の傷発生を抑制する方法は、上記の従来技術には示されていない。   Further, as a result of studies by the present inventors, it has been clarified that scratches may occur at the timing when the semiconductor wafer is detached from the polishing pad. That is, since the adhesion between the semiconductor wafer and the polishing pad is high, when the semiconductor wafer is detached from the polishing pad, the polishing pad bends and the polishing pad comes into contact with the semiconductor wafer surface, so that the semiconductor wafer surface is scratched. There is a case. Such a method for suppressing the occurrence of scratches at the time of detachment is not shown in the above-described prior art.

本発明の目的は、前記従来技術に基づく問題点を解消し、研磨処理の時に、半導体基板表面に傷が発生することを低減することができる半導体装置の製造方法を提供することにある。   An object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the problems based on the conventional technology and reduce the occurrence of scratches on the surface of a semiconductor substrate during polishing.

上記目的を達成するために、本発明は、半導体基板表面を研磨パッドに所定の圧力で押しつけ、かつ、該半導体基板表面を該研磨パッドに対して所定の相対速度で移動させることによって、該半導体基板表面を研磨した後に、該半導体基板を該研磨パッドから脱離するにあたって、
前記研磨パッドに対する押しつけ圧力を前記研磨時以下でかつ60%以上の範囲に保って、前記相対速度を前記研磨時に比較して減少させる緩衝ステップを行ってから、前記半導体基板を脱離することを特徴とする半導体装置の製造方法を提供するものである。
In order to achieve the above object, the present invention provides a method for pressing a semiconductor substrate surface against a polishing pad with a predetermined pressure and moving the semiconductor substrate surface with respect to the polishing pad at a predetermined relative speed. In removing the semiconductor substrate from the polishing pad after polishing the substrate surface,
Removing the semiconductor substrate after performing a buffering step in which the pressing pressure against the polishing pad is kept within the range of 60% or more during the polishing and the relative speed is decreased as compared with the polishing. A feature of the present invention is to provide a method for manufacturing a semiconductor device.

ここで、前記緩衝ステップにおける相対速度を前記研磨時の相対速度の2/3ないし1/3に減少させることが好ましい。   Here, it is preferable that the relative speed in the buffering step is reduced to 2/3 to 1/3 of the relative speed during the polishing.

また、本発明は、半導体基板を研磨パッドを有する定盤に装着し、該半導体基板の表面を研磨した後に、前記研磨パッドとは別個に設けられたバフ研磨パッドを有する定盤に装着してバフ研磨を行うにあたって、
前記バフ研磨パッドを有する定盤に純水を供給しながら前記半導体基板を装着し、続いて、砥粒を含んだスラリーを供給してスラリーバフ研磨を行い、さらに、純水を供給してバフ研磨を行うことを特徴とする半導体装置の製造方法を提供する。
Further, the present invention attaches a semiconductor substrate to a surface plate having a polishing pad, polishes the surface of the semiconductor substrate, and then attaches it to a surface plate having a buff polishing pad provided separately from the polishing pad. In performing buffing,
The semiconductor substrate is mounted while supplying pure water to the surface plate having the buffing pad, and then slurry buffing is performed by supplying slurry containing abrasive grains, and then buffing is performed by supplying pure water. A method for manufacturing a semiconductor device is provided.

ここで、前記研磨パッドに装着して行う研磨を、該研磨パッドに砥粒を含んだスラリーを供給して行い、
前記スラリーバフ研磨を、前記研磨パッドに供給するものと同一のスラリーを、該研磨パッドへの供給量の±25%の範囲の供給量で供給して行うことが好ましい。
Here, polishing performed by attaching to the polishing pad is performed by supplying slurry containing abrasive grains to the polishing pad,
The slurry buffing is preferably performed by supplying the same slurry as that supplied to the polishing pad at a supply amount in a range of ± 25% of the supply amount to the polishing pad.

また、前記研磨パッドが前記半導体基板に比較して大きな寸法を有し、該研磨パッドおよび半導体基板のそれぞれを、互いに異なる軸を中心として自転させることにより前記半導体基板表面の研磨を行うことが好ましい。   Preferably, the polishing pad has a size larger than that of the semiconductor substrate, and the surface of the semiconductor substrate is polished by rotating each of the polishing pad and the semiconductor substrate about different axes. .

また、前記半導体基板表面の研磨は、該半導体基板表面の全面に形成された絶縁膜の表面層の研磨であることが好ましい。   The polishing of the surface of the semiconductor substrate is preferably polishing of a surface layer of an insulating film formed on the entire surface of the semiconductor substrate.

本発明によれば、緩衝ステップを行ってから、半導体基板を研磨パッドから脱離することによって、半導体基板表面に傷が発生するのを大幅に低減することができる。また、本発明によれば、定盤に純水を供給しながら、バフ研磨パッドを有する定盤に半導体基板を装着することによって、メイン研磨中に半導体基板表面に付着した、凝集した砥粒や被研磨材料の破片や、もしくは、バフ研磨パッドに付着した粒子等を除去することができる。続いて、砥流を含んだスラリーを供給してスラリーバフ研磨を行うことによって、メイン研磨時に半導体基板表面に発生した傷を除去し、製造される半導体装置の歩留まりを向上させることができる。   According to the present invention, it is possible to greatly reduce the occurrence of scratches on the surface of the semiconductor substrate by detaching the semiconductor substrate from the polishing pad after performing the buffering step. Further, according to the present invention, while supplying pure water to the surface plate, by attaching the semiconductor substrate to the surface plate having a buffing pad, the agglomerated abrasive grains adhering to the surface of the semiconductor substrate during the main polishing or Debris of the material to be polished or particles adhering to the buffing pad can be removed. Subsequently, by supplying slurry containing an abrasive flow and performing slurry buff polishing, scratches generated on the surface of the semiconductor substrate during main polishing can be removed, and the yield of manufactured semiconductor devices can be improved.

以下に、添付の図面に示す好適実施形態に基づいて、本発明の半導体装置の製造方法を詳細に説明する。   Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

図1は、本発明の半導体装置の製造方法を適用して半導体ウエハの表面を研磨する工程を表す概略図である。同図に示すように、本発明の半導体装置の製造方法を適用するためのCMP装置11は、ウエハローダ部12、研磨ヘッド24、メイン研磨用研磨ユニット14、バフ研磨用研磨ユニット16、およびウエハアンローダ部18を備えている。メイン研磨用研磨ユニット14は、その上面にメイン研磨用の研磨パッド20が装着された研磨定盤22と、純水供給管26およびスラリー供給管28とを備えている。バフ研磨用研磨ユニット16は、バフ研磨用の研磨パッド30が装着された研磨定盤32と、純水供給管36およびスラリー供給管38とを備えている。   FIG. 1 is a schematic view showing a step of polishing the surface of a semiconductor wafer by applying the method for manufacturing a semiconductor device of the present invention. As shown in the figure, a CMP apparatus 11 for applying the semiconductor device manufacturing method of the present invention includes a wafer loader unit 12, a polishing head 24, a main polishing unit 14, a buff polishing unit 16, and a wafer unloader. A portion 18 is provided. The main polishing polishing unit 14 includes a polishing surface plate 22 having a main polishing pad 20 mounted on the upper surface thereof, a pure water supply pipe 26 and a slurry supply pipe 28. The buffing polishing unit 16 includes a polishing surface plate 32 on which a buffing polishing pad 30 is mounted, a pure water supply pipe 36 and a slurry supply pipe 38.

半導体ウエハ10の表面(被研磨面となる半導体基板表面)を研磨する場合、半導体ウエハ10は、ウエハローダー部12を介してCMP装置11に搬入され、研磨ヘッド(半導体ウエハ吸着機構)24の下部に、その被研磨面を下側に向けて(メイン研磨用研磨ユニット14、バフ研磨用研磨ユニット16のそれぞれにおいて、被研磨面が研磨定盤22および32に向かうように)吸着される。そして、研磨ヘッド24に吸着された状態で、メイン研磨用の研磨ユニット14に装着され、そこでメイン研磨が施される。   When polishing the surface of the semiconductor wafer 10 (the surface of the semiconductor substrate that is the surface to be polished), the semiconductor wafer 10 is carried into the CMP apparatus 11 via the wafer loader unit 12, and below the polishing head (semiconductor wafer suction mechanism) 24. Then, the surface to be polished is attracted downward (in the main polishing polishing unit 14 and the buffing polishing unit 16, the surfaces to be polished are directed to the polishing surface plates 22 and 32). Then, it is attached to the main polishing unit 14 while being adsorbed by the polishing head 24, and main polishing is performed there.

メイン研磨用の研磨ユニット14において、半導体ウエハ10を、その被研磨面を研磨パッド20に所定圧力で押しつけ、スラリー供給管28から砥粒を含んだスラリーを所定流量で供給しながら、研磨定盤22および研磨ヘッド24を各々所定速度で所定時間回転させる。すなわち半導体基板表面を研磨パッド20に対して所定の相対速度で移動させる。これによって、半導体基板表面を研磨する。   In the polishing unit 14 for main polishing, the polishing surface plate of the semiconductor wafer 10 is pressed while the surface to be polished is pressed against the polishing pad 20 with a predetermined pressure, and slurry containing abrasive grains is supplied from the slurry supply pipe 28 at a predetermined flow rate. 22 and the polishing head 24 are each rotated at a predetermined speed for a predetermined time. That is, the surface of the semiconductor substrate is moved with respect to the polishing pad 20 at a predetermined relative speed. Thereby, the surface of the semiconductor substrate is polished.

その後、半導体基板(すなわち、半導体ウエハ10)を研磨パッド20から脱離するにあたって、研磨パッド20に対する押しつけ圧力を研磨時以下でかつ60%以上の範囲に保ち、かつ相対速度を研磨時の速度に比較して減少させて、スラリー供給管28からスラリーを所定流量で供給しながら、研磨定盤22および研磨ヘッド24を各々所定速度で所定時間回転させることによって半導体基板表面を研磨する緩衝ステップを行ってから、半導体基板を研磨パッド20から脱離する。   Thereafter, when the semiconductor substrate (that is, the semiconductor wafer 10) is detached from the polishing pad 20, the pressing pressure against the polishing pad 20 is kept within the range of 60% or more during polishing and the relative speed is set to the speed during polishing. A buffering step for polishing the surface of the semiconductor substrate is performed by rotating the polishing surface plate 22 and the polishing head 24 at a predetermined speed for a predetermined time while supplying the slurry from the slurry supply pipe 28 at a predetermined flow rate. After that, the semiconductor substrate is detached from the polishing pad 20.

なお、メイン研磨の処理時間は、被研磨面の材質および必要な研磨量に応じて適宜設定すればよい。また、緩衝ステップの処理時間は、メイン研磨の処理時間と比べて、極めて短い時間とするのが好ましい。緩衝ステップの目的は、その後に半導体ウエハを研磨パッドから脱離するときの、研磨パッドの撓みを低減することであるので、研磨定盤22および研磨ヘッド24の回転が、研磨時に比較して減少させた速度で安定するだけの時間だけ行えば十分である。具体的に必要な速度は、研磨定盤22および研磨ヘッド24の応答速度によって異なるが、通常、5ないし10秒程度にすることが好ましい。   The main polishing processing time may be set as appropriate according to the material of the surface to be polished and the required polishing amount. Further, it is preferable that the processing time of the buffering step is extremely short compared with the processing time of the main polishing. Since the purpose of the buffering step is to reduce the deflection of the polishing pad when the semiconductor wafer is subsequently detached from the polishing pad, the rotation of the polishing surface plate 22 and the polishing head 24 is reduced as compared with the polishing. It suffices to go for a period of time to stabilize at the set speed. The specific required speed varies depending on the response speeds of the polishing surface plate 22 and the polishing head 24, but is usually preferably about 5 to 10 seconds.

上記のように、メイン研磨の後、半導体ウエハ10を研磨パッド20から脱離する時に、緩衝ステップを行ってから、半導体基板を研磨パッド20から脱離することによって、脱離時に半導体基板表面に傷が発生するのを低減することができる。   As described above, after the main polishing, when the semiconductor wafer 10 is detached from the polishing pad 20, a buffering step is performed, and then the semiconductor substrate is detached from the polishing pad 20. The occurrence of scratches can be reduced.

なお、緩衝ステップによる十分な傷減少効果を得るためには、研磨パッド20と半導体ウエハ10との間の相対速度が、研磨時の相対速度の2/3程度以下になるように、研磨定盤22および研磨ヘッド24の回転速度を減少させることが好ましい。一方、相対速度を減少させすぎると、スラリーの供給が不均一になり、かえって傷が増大する場合もある。従って、通常は、研磨時の相対速度の2/3〜1/3の範囲、例えば、1/2程度に減少させることが好ましい。   In order to obtain a sufficient scratch reduction effect by the buffering step, the polishing surface plate is set so that the relative speed between the polishing pad 20 and the semiconductor wafer 10 is about 2/3 or less of the relative speed during polishing. It is preferable to reduce the rotational speed of the polishing head 22 and the polishing head 24. On the other hand, if the relative speed is decreased too much, the supply of slurry becomes non-uniform and the scratches may increase. Therefore, it is usually preferable to reduce the relative speed during polishing to a range of 2/3 to 1/3, for example, about 1/2.

メイン研磨が終了した後の半導体ウエハ10は研磨ヘッド24に吸着されたままの状態で、バフ研磨用の研磨ユニット16に移送され、そこでバフ研磨が施される。   The semiconductor wafer 10 after the main polishing is finished is transferred to the polishing unit 16 for buff polishing while being adsorbed by the polishing head 24, where buff polishing is performed.

バフ研磨用の研磨ユニット16において、バフ研磨パッド30を有する研磨定盤32に、純水供給管36から純水を供給しながら、研磨ヘッド24に吸着した半導体ウエハ10を装着する。この時、半導体ウエハ10をバフ研磨パッド30に押しつけるのではなく、バフ研磨パッド30の表面に純水を介して浮いている状態とする。   In the polishing unit 16 for buff polishing, the semiconductor wafer 10 adsorbed by the polishing head 24 is mounted on the polishing surface plate 32 having the buff polishing pad 30 while supplying pure water from the pure water supply pipe 36. At this time, the semiconductor wafer 10 is not pressed against the buffing pad 30, but is floated on the surface of the buffing pad 30 through pure water.

研磨定盤32に純水を供給しながら半導体ウエハ10を装着することによって、メイン研磨中に半導体基板表面に付着した、凝集した砥粒や被研磨材料の破片や、もしくは、バフ研磨パッド30に付着した粒子等を除去することができる。   By attaching the semiconductor wafer 10 while supplying pure water to the polishing surface plate 32, the agglomerated abrasive grains or fragments of the material to be polished adhered to the surface of the semiconductor substrate during the main polishing, or the buffing pad 30 are applied. Adhering particles and the like can be removed.

続いて、半導体基板表面をバフ研磨パッド30に所定圧力で押しつけ、スラリー供給管38から砥粒を含んだスラリーを所定流量で供給し、研磨定盤32および研磨ヘッド24を所定速度で所定時間回転させることによってスラリーバフ研磨を行う。そして最後に、純水供給管36から純水を所定流量で供給し、同様に研磨定盤32および研磨ヘッド24を所定速度で所定時間回転させることによってバフ研磨を行う。   Subsequently, the surface of the semiconductor substrate is pressed against the buffing pad 30 at a predetermined pressure, slurry containing abrasive grains is supplied from the slurry supply pipe 38 at a predetermined flow rate, and the polishing surface plate 32 and the polishing head 24 are rotated at a predetermined speed for a predetermined time. Slurry buffing is performed. Finally, pure water is supplied from the pure water supply pipe 36 at a predetermined flow rate, and buffing is similarly performed by rotating the polishing surface plate 32 and the polishing head 24 at a predetermined speed for a predetermined time.

スラリーバフ研磨を行うことによって、メイン研磨時に半導体基板表面に発生した傷を除去し、製造される半導体装置の歩留まりを向上させることができる。その後の純水によるバフ研磨によって、半導体基板表面を洗浄してスラリーを除去することができる。   By performing slurry buff polishing, scratches generated on the surface of the semiconductor substrate during the main polishing can be removed, and the yield of the manufactured semiconductor device can be improved. By subsequent buffing with pure water, the surface of the semiconductor substrate can be washed to remove the slurry.

そして最後に、バフ研磨が終了した後の半導体ウエハ10は、ウエハアンローダー部18を介して搬出される。   Finally, the semiconductor wafer 10 after the buffing is finished is unloaded via the wafer unloader unit 18.

なお、バフ研磨を行う場合、メイン研磨後に緩衝ステップを行わず、バフ研磨時に、純水を供給しながら半導体ウエハを研磨定盤32に装着し、スラリーバフ研磨を行ってからバフ研磨を行うようにしてもよい。また、バフ研磨時に、半導体基板をバフ研磨パッド30から脱離するにあたって、メイン研磨時と同様に緩衝ステップを行うようにしてもよい。   When buffing is performed, the buffer step is not performed after the main polishing. At the time of buffing, the semiconductor wafer is mounted on the polishing surface plate 32 while supplying pure water, and the buffing is performed after the slurry buffing is performed. May be. Further, when the semiconductor substrate is detached from the buff polishing pad 30 during the buff polishing, a buffering step may be performed as in the main polishing.

上記実施形態の場合のように、メイン研磨時にスラリーを使用する場合、バフ研磨時にも、メイン研磨時と同じスラリーを利用することができる。スラリーバフ研磨時のスラリー供給量が少なすぎると、傷を除去する効果が得られず、多すぎると、スラリーバフ研磨時のスラリーが半導体基板表面に残留して、半導体装置の歩留まりを低下させる原因となる。従って、スラリーバフ研磨時のスラリー供給量は、メイン研磨時と同等の量、具体的には、メイン研磨時の±25%程度が好ましい。   When the slurry is used at the time of main polishing as in the case of the above embodiment, the same slurry as at the time of main polishing can be used also at the time of buff polishing. If the amount of slurry supplied at the time of slurry buff polishing is too small, the effect of removing scratches cannot be obtained, and if too large, the slurry at the time of slurry buff polishing remains on the surface of the semiconductor substrate, causing a decrease in the yield of the semiconductor device. . Therefore, the amount of slurry supplied at the time of slurry buff polishing is preferably the same amount as at the time of main polishing, specifically, about ± 25% of that at the time of main polishing.

特許文献3にも記載されているように、従来は、スラリーと純水が混合されてpHが変化すると、砥粒の凝集が発生し、傷発生の原因になることが危惧されていた。しかし現実には、同一のバフ研磨パッドに半導体基板表面を装着したままの状態で、純水、スラリー、純水と切り替えて供給しても、すなわち、切替のタイミングで純水とスラリーとが混合される状態になっても、傷を増大させることはなく、むしろ、メイン研磨によって発生された傷を減少させ、製造される半導体装置の歩留まりを向上させることができることが明らかとなった。   As described in Patent Document 3, conventionally, when the slurry and pure water are mixed and the pH is changed, the agglomeration of abrasive grains occurs, which may cause scratches. However, in reality, even if the semiconductor substrate surface is mounted on the same buffing pad, it can be switched to pure water, slurry, or pure water, that is, the pure water and slurry are mixed at the timing of switching. It has been clarified that even if the state is changed, the scratches are not increased, but rather, the scratches generated by the main polishing can be reduced and the yield of the manufactured semiconductor device can be improved.

また、半導体基板表面の具体的な研磨方法は何ら限定されないが、好ましい例として、図1に示す例のように、研磨パッド20が半導体基板に比較して大きな寸法を有し、研磨パッド20および半導体基板のそれぞれを、互いに異なる軸を中心として自転させることにより半導体基板表面の研磨を行うことを挙げることができる。また、研磨される半導体基板の表面層も何ら限定されないが、一例として、半導体基板表面の全面に形成された絶縁膜の表面層を挙げることができる。   Further, the specific polishing method of the surface of the semiconductor substrate is not limited at all. However, as a preferable example, the polishing pad 20 has a larger size than the semiconductor substrate as shown in FIG. The semiconductor substrate surface can be polished by rotating each of the semiconductor substrates around different axes. Further, the surface layer of the semiconductor substrate to be polished is not limited in any way, but as an example, a surface layer of an insulating film formed on the entire surface of the semiconductor substrate can be mentioned.

CMP装置として、IPEC/WESTECH社製 AVANTI472を使用し、メイン研磨用の研磨パッドとして、IC1000/Suba−4の2層パッド、バフ研磨用のバフ研磨パッドとして、Supreme RN−Hを使用して、PSG膜が堆積された半導体基板表面の研磨を行った後、表面欠陥検出装置として、KLA−Tencor社製 AIT−IIを使用して、研磨後の半導体基板表面の欠陥数(欠陥検査装置によって観察される傷の個数)を測定した。   As a CMP apparatus, AVECTI 472 manufactured by IPEC / WESTEC is used, as a polishing pad for main polishing, a two-layer pad of IC1000 / Suba-4, and as a buff polishing pad for buff polishing, Supreme RN-H is used. After polishing the surface of the semiconductor substrate on which the PSG film is deposited, use AIT-II manufactured by KLA-Tencor as a surface defect detection device, and the number of defects on the surface of the semiconductor substrate after polishing (observed by a defect inspection device). The number of scratches made was measured.

本実施例では、図2のグラフに示すように、本発明を適用して、メイン研磨の後、緩衝ステップを行ってから、半導体ウエハを研磨パッドから脱離し、さらに純水のみを供給してバフ研磨を行った。図2のグラフの縦軸は半導体ウエハを研磨パッドに押しつける圧力(psi)、横軸は処理時間(sec)を表す。また、T1,T2,Tt,Tbは、それぞれメイン研磨の処理時間、緩衝ステップの処理時間、半導体ウエハの移送時間、バフ研磨の処理時間を表す。   In this embodiment, as shown in the graph of FIG. 2, the present invention is applied, a buffer step is performed after the main polishing, the semiconductor wafer is detached from the polishing pad, and only pure water is supplied. Buffing was performed. The vertical axis of the graph in FIG. 2 represents the pressure (psi) for pressing the semiconductor wafer against the polishing pad, and the horizontal axis represents the processing time (sec). T1, T2, Tt, and Tb represent a main polishing processing time, a buffer step processing time, a semiconductor wafer transfer time, and a buff polishing processing time, respectively.

また、緩衝ステップの効果を確認するために、従来通り、メイン研磨の後、緩衝ステップを行わずに、そのまま半導体ウエハを研磨パッドから脱離し、さらに純水のみを供給してバフ研磨を行った。   In addition, in order to confirm the effect of the buffer step, as before, after the main polishing, without performing the buffer step, the semiconductor wafer was detached from the polishing pad as it was, and buff polishing was performed by supplying only pure water. .

メイン研磨時の処理条件は以下の通りとした。
研磨定盤回転速数:50rpm
研磨ヘッド回転数:30rpm
圧力:7psi(4.8×104Pa)
時間は、緩衝ステップを行わない場合は60秒とし、緩衝ステップを行う場合には55秒とした。
The processing conditions during main polishing were as follows.
Polishing platen rotational speed: 50 rpm
Polishing head rotation speed: 30 rpm
Pressure: 7 psi (4.8 × 10 4 Pa)
The time was 60 seconds when the buffer step was not performed, and 55 seconds when the buffer step was performed.

バフ研磨時の条件は以下の通りとした。
研磨定盤回転速数:50rpm
研磨ヘッド回転数:50rpm
圧力:2psi(1.4×104Pa)
時間:30秒
The conditions during buffing were as follows.
Polishing platen rotational speed: 50 rpm
Polishing head rotation speed: 50 rpm
Pressure: 2 psi (1.4 × 10 4 Pa)
Time: 30 seconds

緩衝ステップ時の処理条件は、下記表1の通りとした。すなわち、緩衝ステップ時の研磨定盤/研磨ヘッドの回転数(半導体ウエハと研磨パッドとの間の相対速度)は、メイン研磨時の研磨定盤/研磨ヘッドの回転数の1/2とした。また、緩衝ステップ時の圧力は、メイン研磨時の圧力以下の値で変化させた。すなわち、7psi(4.8×104Pa)から1psi(6.9×103Pa)の範囲で変化させた。時間は、この実験においては、緩衝ステップにおける研磨量を同一にして比較するために、圧力に応じて変化させた。なお、表1には、6インチウエハ全面の欠陥数(個)を研磨量(nm)で規格化した数値を示してある(以下、単に欠陥数の規格値という)。 The processing conditions during the buffering step were as shown in Table 1 below. That is, the rotation speed of the polishing platen / polishing head at the buffer step (relative speed between the semiconductor wafer and the polishing pad) was set to ½ of the rotation speed of the polishing platen / polishing head at the main polishing. The pressure at the buffering step was changed to a value equal to or lower than the pressure at the main polishing. That is, it was changed in the range of 7 psi (4.8 × 10 4 Pa) to 1 psi (6.9 × 10 3 Pa). In this experiment, the time was changed according to the pressure in order to compare with the same polishing amount in the buffer step. Table 1 shows numerical values obtained by normalizing the number of defects (pieces) on the entire surface of the 6-inch wafer by the polishing amount (nm) (hereinafter simply referred to as a standard value of the number of defects).

Figure 2006073806
Figure 2006073806

表1に示す通り、緩衝ステップを行わずに半導体ウエハを脱離した場合、欠陥数の規格値は0.63(個/nm)であった。一方、緩衝ステップを行ってから半導体ウエハを脱離した場合、半導体基板表面と研磨パッドとの間の相対速度を1/2にしても、圧力を1/2以下に下げてから脱離した場合(圧力が3psiおよび1psiの場合)、かえって欠陥数の規格値が増加する結果となった。これに対して、圧力を60%以上に保った状態で、相対速度を1/2に低下させてから脱離した場合(圧力が7psiおよび5psiの場合)、欠陥数の規格値を低下させることができた。   As shown in Table 1, when the semiconductor wafer was detached without performing the buffering step, the standard value of the number of defects was 0.63 (pieces / nm). On the other hand, when the semiconductor wafer is detached after performing the buffering step, when the relative speed between the semiconductor substrate surface and the polishing pad is halved, the pressure is lowered to ½ or less and then detached (When the pressure was 3 psi and 1 psi), the standard value of the number of defects was increased. On the other hand, when the pressure is kept at 60% or higher and the relative speed is reduced to 1/2 and then desorption (when the pressure is 7 psi and 5 psi), the standard value of the number of defects is reduced. I was able to.

図3は、メイン研磨時の圧力P1と緩衝ステップ時の圧力P2との比P2/P1と、欠陥数の規格値との間の関係を表すグラフであって、その縦軸は欠陥数の規格値(個/nm)、横軸は研磨圧力比P2/P1を示す。このグラフから、緩衝ステップを行わない場合の欠陥数の規格値0.63を上限として、これよりも低い数値、例えば0.5を欠陥数の規格値の目標値とすると、この目標値0.5よりも欠陥数の規格値が小さくなる範囲は、研磨圧力比P2/P1を0.60程度以上とした場合であることが分かる。   FIG. 3 is a graph showing the relationship between the ratio P2 / P1 between the pressure P1 during main polishing and the pressure P2 during the buffering step, and the standard value for the number of defects, and the vertical axis indicates the standard for the number of defects. The value (pieces / nm) and the horizontal axis indicate the polishing pressure ratio P2 / P1. From this graph, if the standard value 0.63 of the number of defects when the buffering step is not performed is set as an upper limit, and a numerical value lower than this, for example, 0.5 is set as the target value of the standard value of the number of defects, this target value 0. It can be seen that the range in which the standard value of the number of defects is smaller than 5 is when the polishing pressure ratio P2 / P1 is about 0.60 or more.

実施例1と同じ装置を使用して、PSG膜が堆積された半導体基板表面の研磨を行い、研磨後の半導体基板表面の欠陥数を測定した。本実施例では、図4のグラフに示すように、本発明を適用して、メイン研磨の後、緩衝ステップを行わずに半導体ウエハを研磨パッドから脱離し、さらに純水を供給しながら半導体ウエハをバフ研磨パッドを有する研磨定盤に装着(洗浄工程)し、続いてスラリーバフ研磨を行い、最後に純水を供給してバフ研磨を行った。図4のグラフにおいて、Tsは、スラリーバフ研磨の処理時間を表す。   Using the same apparatus as in Example 1, the surface of the semiconductor substrate on which the PSG film was deposited was polished, and the number of defects on the surface of the semiconductor substrate after polishing was measured. In this embodiment, as shown in the graph of FIG. 4, the present invention is applied, and after the main polishing, the semiconductor wafer is detached from the polishing pad without performing a buffering step, and further supplied with pure water while supplying pure water. Was mounted on a polishing surface plate having a buffing pad (cleaning step), followed by slurry buffing, and finally boiled by supplying pure water. In the graph of FIG. 4, Ts represents the processing time of slurry buffing.

また、スラリーバフ研磨の効果を確認するために、従来通り、メイン研磨の後、緩衝ステップを行わずに、そのまま半導体ウエハを研磨パッドから脱離した後、純水のみを供給してバフ研磨を行った。バフ研磨の条件は、スラリーバフ研磨を行った場合も行わなかった場合も、実施例1と同一である。メイン研磨の条件も、スラリーバフ研磨の有無によらず、実施例1において緩衝ステップを行わなかった場合と同一である。   In order to confirm the effect of slurry buff polishing, as before, after the main polishing, without performing the buffer step, the semiconductor wafer is detached from the polishing pad as it is, and then only pure water is supplied to perform buff polishing. It was. The buffing conditions are the same as in Example 1 whether or not slurry buffing is performed. The conditions for the main polishing are the same as in the case where the buffering step was not performed in Example 1 regardless of the presence or absence of slurry buffing.

スラリーバフ研磨時の処理条件は、下記表2の通りとした。また、表2には、スラリーバフ研磨時の研磨量、すなわち、スラリーバフ研磨およびバフ研磨を行った場合の研磨量と、バフ研磨のみを行った場合の研磨量との差も併せて示してある。   The processing conditions at the time of slurry buffing were as shown in Table 2 below. Table 2 also shows the difference between the polishing amount during slurry buff polishing, that is, the polishing amount when slurry buff polishing and buff polishing are performed, and the polishing amount when only buff polishing is performed.

Figure 2006073806
Figure 2006073806

表2に示す通り、バフ研磨のみを行った場合、欠陥数は38個であった。一方、スラリーバフ研磨を行った場合、欠陥数は、15秒、30秒、60秒のスラリーバフ研磨でそれぞれ32個、3個、0個となり、スラリーバフ研磨を行うことによって確実に欠陥数を減少させることができた。また、この時の研磨量は、それぞれ45nm、109nm、261nmであり、約100nm程度のスラリーバフ研磨によって欠陥数を大幅に削減できることが分かった。   As shown in Table 2, when only buffing was performed, the number of defects was 38. On the other hand, when slurry buffing is performed, the number of defects is 32, 3, and 0 by slurry buffing for 15 seconds, 30 seconds, and 60 seconds, respectively, and the number of defects can be reliably reduced by slurry buffing. I was able to. Further, the polishing amounts at this time are 45 nm, 109 nm, and 261 nm, respectively, and it was found that the number of defects can be greatly reduced by slurry buffing of about 100 nm.

CMP装置として、APPLIED MATERIALS社製 MIRRAを使用し、メイン研磨用の研磨パッドとして、IC1000/Suba−4の2層パッド、バフ研磨用のバフ研磨パッドとして、Supreme RN−Hを使用して、BPSG膜が堆積された半導体基板表面の研磨を行った。   Uses MIRRA manufactured by APPLIED MATERIALS as the CMP apparatus, uses IC1000 / Suba-4 two-layer pad as the polishing pad for main polishing, and Supply RN-H as the buff polishing pad for buff polishing, using BPSG The semiconductor substrate surface on which the film was deposited was polished.

本実施例では、図5のグラフに示すように、本発明を適用して、メイン研磨の後、半導体ウエハを研磨パッドから脱離し、次に、バフ研磨パッドを有する研磨定盤に純水を供給しながら半導体ウエハを装着(洗浄工程)し、続いてスラリーバフ研磨を行い、さらに純水を供給してバフ研磨を行った。   In this embodiment, as shown in the graph of FIG. 5, the present invention is applied, and after the main polishing, the semiconductor wafer is detached from the polishing pad, and then pure water is supplied to the polishing surface plate having the buff polishing pad. The semiconductor wafer was mounted (cleaning step) while being supplied, followed by slurry buff polishing, and further supplied with pure water for buff polishing.

また、スラリーバフ研磨の有無による製品歩留まりの差を調べるために、従来通り、メイン研磨の後、純水のみを供給してバフ研磨を行った。   Further, in order to examine the difference in product yield depending on the presence or absence of slurry buffing, buffing was performed by supplying only pure water after main polishing as usual.

各処理における処理条件は、下記表3の通りとした。スラリーバフ研磨時のスラリー流量は、メイン研磨時のスラリー流量の80%とした。   The processing conditions in each processing were as shown in Table 3 below. The slurry flow rate during slurry buff polishing was 80% of the slurry flow rate during main polishing.

Figure 2006073806
Figure 2006073806

その結果、スラリーバフ研磨を行わず、従来通り、純水によるバフ研磨のみを行った場合の製品歩留まりは82%であった。これに対して、本発明を適用してスラリーバフ研磨を行った場合の製品歩留まりは87%に向上することを確認した。   As a result, the product yield was 82% when slurry buffing was not performed and only buffing with pure water was performed as usual. On the other hand, it was confirmed that the product yield improved to 87% when slurry buffing was performed by applying the present invention.

本発明は、基本的に以上のようなものである。
以上、本発明の半導体装置の製造方法について詳細に説明したが、本発明は上記実施形態に限定されず、本発明の主旨を逸脱しない範囲において、種々の改良や変更をしてもよいのはもちろんである。
The present invention is basically as described above.
As mentioned above, although the manufacturing method of the semiconductor device of this invention was demonstrated in detail, this invention is not limited to the said embodiment, In the range which does not deviate from the main point of this invention, you may make various improvement and a change. Of course.

本発明の半導体装置の製造方法を適用して半導体ウエハの表面を研磨する工程を表す概略図である。It is the schematic showing the process of grind | polishing the surface of a semiconductor wafer by applying the manufacturing method of the semiconductor device of this invention. 実施例1に係る研磨工程を表す概念図である。3 is a conceptual diagram illustrating a polishing process according to Example 1. FIG. 欠陥数の規格値と研磨圧力比との間の関係を表すグラフである。It is a graph showing the relationship between the standard value of the number of defects, and polishing pressure ratio. 実施例2に係る研磨工程を表す概念図である。6 is a conceptual diagram illustrating a polishing process according to Example 2. FIG. 実施例3に係る研磨工程を表す概念図である。10 is a conceptual diagram illustrating a polishing process according to Example 3. FIG.

符号の説明Explanation of symbols

10 半導体ウエハ
11 CMP装置
12 ウエハローダー部
14 メイン研磨用研磨ユニット
16 バフ研磨用研磨ユニット
18 ウエハアンローダー部
20,30 研磨パッド
22,32 研磨定盤
24 研磨ヘッド
26,36 純水供給管
28,38 スラリー供給管
DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 11 CMP apparatus 12 Wafer loader part 14 Main polishing polishing unit 16 Buff polishing polishing unit 18 Wafer unloader part 20, 30 Polishing pad 22, 32 Polishing surface plate 24 Polishing head 26, 36 Pure water supply pipe 28, 38 Slurry supply pipe

Claims (6)

半導体基板表面を研磨パッドに所定の圧力で押しつけ、かつ、該半導体基板表面を該研磨パッドに対して所定の相対速度で移動させることによって、該半導体基板表面を研磨した後に、該半導体基板を該研磨パッドから脱離するにあたって、
前記研磨パッドに対する押しつけ圧力を前記研磨時以下でかつ60%以上の範囲に保って、前記相対速度を前記研磨時に比較して減少させる緩衝ステップを行ってから、前記半導体基板を脱離することを特徴とする半導体装置の製造方法。
After polishing the semiconductor substrate surface by pressing the semiconductor substrate surface against the polishing pad with a predetermined pressure and moving the semiconductor substrate surface with respect to the polishing pad at a predetermined relative speed, the semiconductor substrate is When detaching from the polishing pad,
Removing the semiconductor substrate after performing a buffering step in which the pressing pressure against the polishing pad is kept within the range of 60% or more during the polishing and the relative speed is decreased as compared with the polishing. A method of manufacturing a semiconductor device.
前記緩衝ステップにおける相対速度を前記研磨時の相対速度の2/3ないし1/3に減少させることを特徴とする請求項1記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the relative speed in the buffering step is reduced to 2/3 to 1/3 of the relative speed during the polishing. 半導体基板を研磨パッドを有する定盤に装着し、該半導体基板の表面を研磨した後に、前記研磨パッドとは別個に設けられたバフ研磨パッドを有する定盤に装着してバフ研磨を行うにあたって、
前記バフ研磨パッドを有する定盤に純水を供給しながら前記半導体基板を装着し、続いて、砥粒を含んだスラリーを供給してスラリーバフ研磨を行い、さらに、純水を供給してバフ研磨を行うことを特徴とする半導体装置の製造方法。
After mounting the semiconductor substrate on a surface plate having a polishing pad and polishing the surface of the semiconductor substrate, when performing buffing by mounting on a surface plate having a buff polishing pad provided separately from the polishing pad,
The semiconductor substrate is mounted while supplying pure water to the surface plate having the buffing pad, and then slurry buffing is performed by supplying slurry containing abrasive grains, and then buffing is performed by supplying pure water. A method for manufacturing a semiconductor device, comprising:
前記研磨パッドに装着して行う研磨を、該研磨パッドに砥粒を含んだスラリーを供給して行い、
前記スラリーバフ研磨を、前記研磨パッドに供給するものと同一のスラリーを、該研磨パッドへの供給量の±25%の範囲の供給量で供給して行うことを特徴とする請求項3記載の半導体装置の製造方法。
Polishing performed by attaching to the polishing pad is performed by supplying slurry containing abrasive grains to the polishing pad,
4. The semiconductor according to claim 3, wherein the slurry buff polishing is performed by supplying the same slurry as that supplied to the polishing pad at a supply rate in a range of ± 25% of the supply amount to the polishing pad. Device manufacturing method.
前記研磨パッドが前記半導体基板に比較して大きな寸法を有し、該研磨パッドおよび半導体基板のそれぞれを、互いに異なる軸を中心として自転させることにより前記半導体基板表面の研磨を行うことを特徴とする請求項1ないし4のいずれかに記載の半導体装置の製造方法。   The polishing pad has a size larger than that of the semiconductor substrate, and the polishing surface of the semiconductor substrate is polished by rotating each of the polishing pad and the semiconductor substrate around different axes. The method for manufacturing a semiconductor device according to claim 1. 前記半導体基板表面の研磨は、該半導体基板表面の全面に形成された絶縁膜の表面層の研磨であることを特徴とする請求項1ないし5のいずれかに記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 1, wherein the polishing of the surface of the semiconductor substrate is polishing of a surface layer of an insulating film formed on the entire surface of the semiconductor substrate.
JP2004255543A 2004-09-02 2004-09-02 Manufacturing method of semiconductor device Pending JP2006073806A (en)

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