JP2006073108A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a soft error rate in a latch circuit mounted in a semiconductor integrated circuit, and relieve an error recognized as a hard error when relief information is latched. <P>SOLUTION: The semiconductor integrated circuit has a plurality of fuse elements 10 that store information such as defective addresses, a plurality of first latch circuits 11 that latch a plurality of information transferred in parallel from the plurality of fuse elements 10, a plurality of second latch circuits 12 that latch a plurality of information transferred in parallel or in serial from the plurality of first latch circuits, and a transfer control circuit 13 that controls the transfer of information inputted into each of the latch circuits, wherein the latch circuits have a refresh function. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a latch circuit, and is applied to, for example, a semiconductor memory having a redundancy circuit for repairing a defect.

  Conventionally, in a latch circuit that latches failure relief information (address) of a semiconductor memory having redundant memory cells, relief information stored in a nonvolatile element is transferred when the memory power is turned on. After transferring the relief information in this way, the relief information latched in the latch circuit is compared with the input information for each address input, and access to the regular memory cell or redundant memory cell is controlled based on the result. Yes. If the relief information is transferred to the latch circuit in this way, the relief information can be read from the latch circuit at a higher speed than the relief information of the nonvolatile element is read every address input.

  In recent years, in semiconductor memories, miniaturization of elements has progressed, and a decrease in soft error resistance (an increase in soft error rate) of a latch circuit has been regarded as a problem. In particular, in the case of a latch circuit that latches relief information, if a soft error occurs, the relief information is rewritten, and a hard error occurs in the memory cell.

In the conventional SRAM or DRAM, there are many circuit / element countermeasures for memory cells, but two latch circuits are connected in parallel to double the circuit as a countermeasure for soft errors in the latch circuit that latches relief information. A double latch circuit is disclosed in Patent Document 1.
JP-A-6-237151

  An object of the present invention is to provide a semiconductor integrated circuit equipped with a latch circuit with a refresh function that can reduce a soft error rate and can repair an error that is recognized as a hard error when relief information is latched. And

  The semiconductor integrated circuit of the present invention includes a plurality of nonvolatile memory elements that store information, a plurality of first latch circuits that latch a plurality of information transferred in parallel from the plurality of nonvolatile memory elements, and the plurality A plurality of second latch circuits that latch a plurality of pieces of information transferred in parallel or serially from the first latch circuit, information transfer to the first latch circuit, and information transferred to the second latch circuit And a transfer control circuit for controlling the transfer.

  The nonvolatile memory element, the first latch circuit, the second latch circuit, and the transfer control circuit mounted on the semiconductor integrated circuit of the present invention form a latch circuit with a refresh function capable of refreshing latch data. is doing. According to such a latch circuit with a refresh function, it is possible to reduce the influence of a soft error (such as an increase in the soft error rate and the occurrence of a hard error due to a soft error), and the area of the circuit pattern. Is relatively small. In addition, by adding an error detection circuit, it is possible to perform a repair when a soft error occurs (self-repair of a hard error caused by a soft error).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a first embodiment of a latch circuit with a refresh function (latch circuit block) mounted on a semiconductor integrated circuit according to the present invention. This example shows an example applied to a latch circuit block that is mounted on a semiconductor memory having redundant memory cells and latches information for defect relief. For example, a DRAM has many latch circuit blocks such as this example. Provided.

  In FIG. 1, reference numeral 10 denotes a plurality of nonvolatile memory elements that store predetermined information, and in this example, a plurality of existing fuse elements that store a defective address in a nonvolatile manner. Reference numeral 11 denotes a plurality of first latch circuits that latch a plurality of pieces of information transferred in parallel from the plurality of nonvolatile memory elements 10. Reference numeral 12 denotes a plurality of second latch circuits that latch a plurality of pieces of information transferred in parallel from the plurality of first latch circuits 11. A transfer control circuit 13 controls information transfer from the plurality of fuse elements 10 to the first latch circuit 11 and information transfer from the plurality of first latch circuits 11 to the plurality of second latch circuits 12, for example, A transfer control operation is performed based on a control input instruction. The information latched by the plurality of second latch circuits 12 is output to a comparison circuit (not shown) for comparison with the address input.

  FIG. 2 is a circuit diagram showing a specific example of representatively taking out two sets of the plurality of fuse elements 10 and the plurality of first latch circuits 11 in the latch circuit block shown in FIG.

  Each set of latch circuits 11 includes a CMOS inverter circuit 21 for reading fuse data and an F / F (flip-flop) circuit 22 that latches the potential of the output node of the CMOS inverter circuit 21. Each F / F circuit 22 includes two CMOS inverter circuits 23 connected in anti-parallel, and each output can be taken out in parallel. Further, as will be described later, the F / F circuits 22 are serially connected in order to serially output the outputs of the plurality of first latch circuits 11.

  In the CMOS inverter circuit 21 for reading fuse data, a high power supply potential side node is connected to a power supply node, and a low power supply potential side node is connected to a ground node via a fuse (FUSE) element 10.

  According to the latch circuit block having the configuration shown in FIG. 1, a plurality of pieces of information transferred in parallel from a plurality of fuse elements 10 are latched by a plurality of first latch circuits 11, and a plurality of first latch circuits It is possible to perform transfer control so that a plurality of pieces of information transferred in parallel from 11 are latched by a plurality of second latch circuits 12. For example, by periodically performing transfer control, the latch information of the plurality of first latch circuits 11 can be refreshed, and further, the latch information (output data) of the plurality of second latch circuits 12 can be refreshed. Is possible. Therefore, it is possible to reduce the influence of soft errors and the occurrence of hard errors due to soft errors. In addition, a plurality of first latch circuits 11, a plurality of second latch circuits 12, and a transfer control circuit 13 are added to the existing plurality of fuse elements 10, and the circuit pattern area can be reduced. .

  The above-mentioned latch circuit with a refresh function according to the first embodiment can be applied to all latch circuits mounted on a semiconductor integrated circuit, but is applied when the probability of occurrence of a soft error is high and the influence of the soft error is large. And effective. For example, the present invention is effective when applied to a latch circuit that latches failure relief information in a semiconductor memory having redundant memory cells. At this time, when applied to a general semiconductor memory having a fuse element as a storage element for storing relief information in a non-volatile manner, by effectively using the storage information of the fuse element, the area is not particularly increased. Can be realized.

  The above-mentioned latch circuit with a refresh function is also effective when applied to a latch circuit that latches information of a small number of bits (for example, information for mode selection consisting of 4 bits, 8 bits, etc.) in a semiconductor integrated circuit. It is.

<Second Embodiment>
FIG. 3 is a block diagram showing a second embodiment of a latch circuit with a refresh function (latch circuit block) mounted on the semiconductor integrated circuit of the present invention.

  The latch circuit with a refresh function shown in FIG. 3 is (1) a plurality of first latch circuits 11a to a plurality of second latch circuits as compared with the latch circuit with a refresh function described above with reference to FIG. A plurality of first latch circuits 11a and a plurality of second latch circuits 12a are connected in series so that data to 12a can be serially transferred. (2) The transfer control circuit 13a includes a plurality of second latch circuits 12a. Control is performed so that data is transferred serially from one latch circuit 11a to a plurality of second latch circuits 12a. (3) Number of serial transfers from the first latch circuit 11a to the second latch circuit 12a For determining the completion of serial transfer from the first latch circuit 11a to the second latch circuit 12a, and controlling the information latched in the second latch circuit 12a so that it can be output. Except that it has a counter 21, the others are the same.

  According to the latch circuit block having the configuration shown in FIG. 3, as in the latch circuit block having the configuration shown in FIG. 1, for example, by periodically performing transfer control, the latch information of the plurality of first latch circuits 11a is controlled. In addition, the latch information (output data) of the plurality of second latch circuits 12a can be refreshed. Therefore, similarly to the latch circuit block having the configuration shown in FIG. 1, it is possible to reduce the influence of a soft error and the occurrence of a hard error due to the soft error.

  In addition, a plurality of first latch circuits 11a, a plurality of second latch circuits 12a, and a transfer control circuit 13 are added to the existing plurality of fuse elements 10, and the area of the circuit pattern is relatively small. I'll do it. Further, by serially transferring information from the first latch circuit 11a to the second latch circuit 12a, the number of wiring lines for information transfer can be reduced, and area efficiency can be increased.

  The latch circuit block shown in FIG. 3 involves a serial transfer operation and a count operation of the number of serial transfers. Therefore, compared with the latch circuit block shown in FIG. 1, the refresh operation speed is reduced and the power consumption is increased. Therefore, it is desirable to apply to the case where such a fear hardly causes a problem (for example, when a small number of bits of information for mode selection are latched).

<Third Embodiment>
FIG. 4 is a block diagram showing a third embodiment of a latch circuit (latch circuit block) with a refresh function mounted on a semiconductor integrated circuit according to the present invention.

  The latch circuit with a refresh function shown in FIG. 4 has (1) an error detection circuit 31 as compared with the latch circuit with a refresh function described above with reference to FIG. The difference is that control is performed so that information is re-transferred to the plurality of first latch circuits 11 in response to the error detection output of the error detection circuit 31 and further re-transferred to the plurality of second latch circuits 12b. Are the same.

  According to the above configuration, only when the error of the storage information in the second latch circuit 12b is detected by the error detection circuit 31, the information is retransferred to the first latch circuit 11, and further to the second latch circuit 12b. It is possible to perform refresh by controlling the information to be re-transferred.

  Therefore, according to the latch circuit block having the configuration shown in FIG. 4, an error of data latched in the plurality of second latch circuits 12b is periodically detected by the error detection circuit 31, for example, and refreshed when an error is detected. It is possible to correct the error information by performing the operation. That is, error correction is possible by internal control. In this example, the error detection is to read the data of the plurality of second latch circuits 12b serially and detect a 1-bit inversion error by, for example, a parity check.

  Such a latch circuit block having an error detection / correction function is effective when applied to a latch circuit that latches information for mode selection in a semiconductor integrated circuit.

<Modification of Third Embodiment>
By using an error detection / correction circuit instead of the error detection circuit 31 of the third embodiment, the error detection / error correction operation of the data itself latched in the plurality of second latch circuits 12b can be performed periodically, for example. By doing so, it is possible to provide a refresh function with higher accuracy than in the third embodiment. However, as compared with the third embodiment, there are cases where an increase in current consumption and external control are required with an error correction operation.

<Application example>
FIG. 5 is a block diagram showing a part of a DRAM using a latch circuit with a refresh function for latching data of a plurality of fuse elements storing defective address information as an example of the present invention.

  In FIG. 5, reference numeral 50 denotes a fuse box (FUSE BOX) in which a plurality of fuse elements in which defective address information is stored in a nonvolatile manner are arranged. It is. Reference numeral 51 denotes a plurality of first latch circuits that serially transfer data read from a plurality of fuse elements of the fuse box 50 and latch the data. In the plurality of first latch circuits 51, for example, as described above with reference to FIG. 2, a plurality of F / F circuits are serially connected, and outputs of the respective F / F circuits can be output in parallel. It is possible. A plurality of second latch circuits 52 latch a plurality of pieces of information transferred in parallel from the plurality of first latch circuits 51. 53 counts the number of serial transfers from the fuse box 50 to the first latch circuit 51, determines the completion of the serial transfer from the fuse box 50 to the first latch circuit 51, and the plurality of first latch circuits 51. Is a counter for controlling the information latched in the second latch circuit 52 so that the information can be output to the plurality of second latch circuits 52, and operates based on a control input instruction. A command decoder (command buffer) 54 receives a command signal from the outside, decodes the command signal, generates various control signals, and outputs a plurality of fuse elements from the fuse box 50 to the plurality of first latch circuits 51. And the operation of the counter 53 is controlled.

  Reference numeral 55 denotes an address buffer to which an address signal is input from the outside. Reference numeral 56 denotes whether the internal address signal output from the address buffer 55 matches the address information latched in the second latch circuit 52. This is a predecoder that outputs a desired address signal for selecting and designating a normal DRAM cell or a redundant cell for defect relief according to the result.

  Reference numeral 57 denotes an address decoder for decoding a predecode signal output from the predecoder 56. Reference numeral 58 denotes a DRAM cell array (memory cell array) in which address selection is performed by the decode signal output from the address decoder 57. Have redundant cells.

  According to the DRAM having the above configuration, as a latch circuit for latching data of a plurality of fuse elements storing defective address information, a refresh function capable of performing the same operation as the latch circuit with the refresh function described above with reference to FIG. Is used. Therefore, similarly to the latch circuit with the refresh function described above with reference to FIG. 2, it is possible to reduce the influence of the soft error and the occurrence of the hard error due to the soft error.

The block diagram which shows 1st Embodiment of the latch circuit with a refresh function mounted in the semiconductor integrated circuit of this invention. FIG. 2 is a circuit diagram showing a specific example of representatively taking out two sets from a plurality of fuse elements and a plurality of first latch circuits in FIG. 1. The block diagram which shows 2nd Embodiment of the latch circuit with a refresh function mounted in the semiconductor integrated circuit of this invention. The block diagram which shows 3rd Embodiment of the latch circuit with a refresh function mounted in the semiconductor integrated circuit of this invention. 1 is a block diagram showing a part of a DRAM using a latch circuit with a refresh function for latching data of a plurality of fuse elements storing defective address information as an example of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Nonvolatile memory element, 11 ... 1st latch circuit, 12 ... 2nd latch circuit, 13 ... Transfer control circuit.

Claims (5)

A plurality of nonvolatile storage elements storing information;
A plurality of first latch circuits for latching a plurality of pieces of information transferred in parallel from the plurality of nonvolatile memory elements;
A plurality of second latch circuits for latching a plurality of pieces of information transferred in parallel or serial from the plurality of first latch circuits;
A semiconductor integrated circuit comprising: a transfer control circuit that controls information transfer to the first latch circuit and information transfer to the second latch circuit. The semiconductor integrated circuit according to claim 1, wherein the nonvolatile element is a fuse element. 2. The semiconductor integrated circuit according to claim 1, wherein the nonvolatile element is a fuse element for storing redundant cell repair information in a semiconductor memory. The plurality of first latch circuits and the plurality of second latch circuits are connected in series so as to enable serial transfer of information transfer from the plurality of first latch circuits to the plurality of second latch circuits. 4. The semiconductor integrated circuit according to claim 1, further comprising a counter that counts the number of times of serial transfer and determines completion of serial transfer. 5. An error detection circuit for detecting an error in the information latched in the plurality of second latch circuits; and the transfer control circuit receives the error detection output of the error detection circuit and receives the error detection output from the plurality of first latch circuits. 4. The semiconductor integrated circuit according to claim 1, wherein control is performed such that information is re-transferred to the plurality of latch circuits and information is re-transferred to the plurality of second latch circuits. 5.

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