JP2006066771A - Substrate for stencil mask and stencil mask, and exposing method using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a two-layer structured substrate for a stencil mask with a thin film being an independent film having a function as an etching stopper layer to a supporting substrate and with the stress of the thin film adjusted, in a method for manufacturing a stencil mask using a substrate having the thin film being the etching stopper layer, and to provide the stencil mask and a method for exposing using it. <P>SOLUTION: The method for obtaining the stencil mask 100 comprises steps of forming an indium oxide thin film 11 on the supporting substrate 1 comprising a silicon wafer to manufacture the substrate 10 for the stencil mask, forming an opening 31 in the supporting substrate 1 by pattern-processing the supporting substrate 1 and the indium oxide thin film 11, and forming a charged beam transmitting hole 12 in the indium oxide thin film 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a stencil mask used for manufacturing a semiconductor element, and more particularly, to a material for a thin film formed on a support substrate and a method for manufacturing the same, and the formed thin film is used as an etching stopper layer or a conductor during charged particle beam exposure. The present invention relates to a stencil mask substrate, a stencil mask, and an exposure method using the same.

  In recent years, along with the miniaturization of semiconductor integrated circuits, research and development such as electron beam lithography and ion beam lithography have been actively conducted as manufacturing techniques thereof. Specifically, among the lithography techniques, a method corresponding to the miniaturization of semiconductors. As a method called a cell projection exposure method or a block exposure method using an electron beam, an EPL (Electron Projection Lithography) method capable of further increasing the throughput, or a LEEPL (Low Energy E-beam Proximity Projection Lithography) method. Projection exposure methods have been developed. A stencil mask used for EPL or LEEPL is formed by forming a transfer penetrating pattern on a free-standing silicon thin film (membrane) having a thickness of 2 μm or less.

  An SOI (Silicon On Insulator) substrate 200 as shown in FIG. 5 is used as a stencil mask substrate used when manufacturing a stencil mask used in these lithography because of the ease of fine processing. . The silicon thin film 131 is a portion that becomes a self-supporting membrane, and a single crystal silicon substrate is polished to a predetermined thickness, and then a pattern is formed to form a mask pattern in this portion. In order to support this and maintain the flatness of the mask, a silicon substrate 111 as a support substrate is necessary. As the support substrate 111, single crystal silicon is used from the viewpoint of processability and availability. In order to finely process the thin film by etching, a laminated structure using the silicon oxide thin film 121 as an intermediate layer is taken. At this time, the silicon oxide thin film 121 functions as an etching stopper when the mask pattern is processed. This is because the etching selectivity with respect to single crystal silicon is relatively high, and the thickness of the silicon oxide thin film 121 can be reduced (see, for example, Patent Document 1).

  However, in a general SOI substrate, a pattern formed on a free-standing membrane made of a single crystal silicon thin film is warped in a stencil mask manufacturing process, or a crack is caused by stress concentration depending on the pattern.

In such an SOI substrate, the single crystal silicon thin film 131 has a slight tensile stress (preferably 0 MPa or more and 20 MPa or less), that is, phosphorus or boron having an atomic radius smaller than that of silicon so that the self-supporting membrane is stretched without slack. It has been dealt with by introducing a process of adjusting the stress such as doping of the above (for example, see Patent Document 2).
Japanese Patent Laid-Open No. 11-54409 Japanese Patent Laid-Open No. 11-162823

  However, the silicon oxide thin film 121 as the intermediate layer has a high stress. In addition, the silicon oxide thin film 121 serves as an etching stopper layer as described above, and since it is exposed to a plurality of chemicals in processes such as cleaning, development, and resist stripping, it does not have sufficient resistance to these chemicals. In the past, it was difficult to change the material because no suitable alternative material could be found. In addition, since this intermediate layer has no conductivity, the mask is charged when exposed using the produced stencil mask, the charged particle beam is deflected, and the membrane is destroyed when the sample substrate is replaced depending on the degree of charging. That was also a problem.

  The present invention has been made in view of the related problems, and in the manufacture of a stencil mask using a substrate having a thin film serving as an etching stopper layer, the thin film serving as a self-supporting membrane also has a function as an etching stopper layer for a support substrate, It is another object of the present invention to provide a stencil mask substrate having a two-layer structure in which the stress of the thin film is adjusted, a stencil mask, and an exposure method using the stencil mask.

  In order to achieve the above object in the present invention, first, in claim 1, a stencil mask substrate comprising a support substrate and an indium oxide thin film is used. By using indium oxide having high resistance to alkali, the workability of the support substrate can be expected to be improved.

  Further, in claim 2, the support substrate is a silicon wafer. The stencil mask substrate according to claim 1, wherein the support substrate is etched by using a silicon wafer as the support substrate. In addition, a high selection ratio of 43,000 or more can be secured with the indium oxide film as an etching stopper layer, and even when there is in-plane variation in the etching rate, etching can be performed uniformly without penetrating the etching stopper layer. The thickness of the etching stopper layer can be reduced. This also contributes to reducing the amount of material used.

  According to a third aspect of the present invention, the indium oxide thin film has at least one element selected from tin, titanium, zirconium, hafnium, niobium, tantalum, tungsten, germanium, tellurium, zinc, and fluorine as an element other than oxygen and indium. The stencil mask substrate according to claim 2, wherein the stencil mask substrate contains two or more elements, and the conductivity of the indium oxide thin film can be increased by using such a configuration. In addition, it is easy to remove charges accumulated on the indium oxide thin film side or the supporting substrate substrate side when the substrate is irradiated with a charged particle beam.

  According to a fourth aspect of the present invention, there is provided a stencil mask, wherein a transfer pattern is formed on the indium oxide thin film using the stencil mask substrate according to any one of the first to third aspects. Since the warp does not occur in the stencil mask substrate, the positional accuracy when forming the transfer pattern is good, and the manufactured mask becomes a good stencil mask without warp.

  Furthermore, in claim 5, the charged particle beam is formed by irradiating the stencil mask with a charged particle beam, forming the charged particle beam into the shape of the transfer pattern, and forming a transfer pattern on the transfer substrate. According to the exposure method, the resist formed on the sample substrate can be exposed with high accuracy, and as a result, the pattern formation in the semiconductor device or the like can be performed with a high yield. Can do.

  According to the stencil mask substrate and the stencil mask of the present invention, since the stress is adjusted with the support substrate, it is possible to prevent the warp of the entire mask, and the deformation and displacement of the fine pattern are prevented. Hard to happen.

Further, in the process of producing the stencil mask of the present invention, the indium oxide thin film can be used as an etching stopper layer of the support substrate because it can ensure a high etching selectivity with the support substrate.
In addition, since the indium oxide thin film can be used as a stencil mask membrane, the number of manufacturing steps can be reduced.

  In addition, according to the exposure method using the stencil mask of the present invention, it is possible to perform pattern exposure with high accuracy on the resist formed on the sample substrate, and as a result, patterns such as semiconductor circuits are manufactured with high yield. be able to.

Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a schematic sectional view showing an embodiment of the stencil mask substrate of the present invention, and FIG. 2 is a schematic sectional view showing an embodiment of the stencil mask of the present invention.
The stencil mask substrate 10 of the present invention is a substrate in which an indium oxide thin film 11 is formed on a support substrate 1 and is supported by using an indium oxide thin film having high resistance to general acids and alkalis other than halogen-based acids. This improves the workability of the substrate 1.
The material used for the support substrate 1 is preferably one that has a particularly high etching selectivity with the indium oxide thin film 11, and examples thereof include a silicon wafer made of single crystal silicon, polycrystalline silicon, amorphous silicon, or the like. In order to increase conductivity, it is preferable to dope phosphorus, boron or the like to lower the specific resistance.

3A to 3G are schematic cross-sectional views showing an example of a method for producing a stencil mask substrate and a stencil mask according to the present invention in the order of steps.
First, an indium oxide thin film 11 is formed on a support substrate 1 made of a silicon wafer by reactive sputtering or the like (see FIG. 3A).
The indium oxide thin film 11 is warped in the support substrate 1 due to the influence of the difference in thermal expansion coefficient or the influence of impurities incorporated into the film depending on the film forming conditions (see FIGS. 4A and 4B). .

In the present invention, it is preferable to control the stress of the indium oxide thin film 11 in order to prevent the support substrate 1 from warping.
Specifically, the stress of the indium oxide thin film 11 at this time is adjusted so as to be a tension of 100 MPa or less. If the film has a compressive stress, the support substrate warps as shown in FIG. 4A, or the membrane bends when the opening 31 is formed in the support substrate 1. If the stress of the indium oxide thin film 11 exceeds 100 MPa, the substrate warps as shown in FIG. 4B, the membrane cracks when the opening 31 is formed in the support substrate 1, or a transfer pattern is formed on the membrane. In this case, depending on the shape of the pattern, a phenomenon that the pattern position is shifted becomes noticeable.

The indium oxide thin film 11 is preferably formed by a sputtering method that can be uniformly coated and has high adhesion. The stress adjustment method can be any method such as a method for controlling the total pressure during sputtering, a method for controlling the substrate temperature during film formation, or a method for controlling the baking temperature after film formation. Pure indium oxide is an insulator, but it is preferable to adjust the film forming conditions so that oxygen vacancies are generated in the crystal in order to provide conductivity. Specifically, this can be dealt with by changing the flow rate ratio of Ar and O ₂ during sputtering film formation according to the process. In order to further increase the conductivity, one or more elements selected from tin, titanium, zirconium, hafnium, niobium, tantalum, tungsten, germanium, tellurium, zinc, fluorine, and the like may be added as impurities to the indium oxide thin film. Among these, it is preferable to use tin from the viewpoint that high conductivity can be expected.

Next, a resist is applied on the support substrate 1 to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed by ordinary photolithography to create a resist pattern 21 (see FIG. 3B). ).
Further, the support substrate 1 is dry-etched using the resist pattern 21 as a mask in a dry etching apparatus to form an opening 31 (see FIG. 3C).
Examples of the dry etching apparatus include those using a known discharge method such as RIE, ECR, ICP, microwave, helicon wave, and NLD. As an etching gas for dry etching, when a silicon wafer is used as the support substrate 1, a mixed gas mainly composed of fluorine-based gas (CF ₄ , C ₄ F ₈ , SF _6, etc.) can be used. At this time, the indium oxide thin film 11 functions as an etching stopper layer, and the selectivity can be expected to be 43,000 or more with respect to silicon. Here, when conventional silicon oxide is used as the etching stopper layer, the selection ratio is about 400.
Further, the resist pattern 21 is removed by a resist stripping solution or ashing to obtain a stencil mask blank 20 (see FIG. 3D).

Next, a resist is applied on the indium oxide thin film 11 of the stencil mask blank 20 to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed by ordinary photolithography or EB lithography to form a resist pattern 22. It forms (refer FIG.3 (e)).
Further, the indium oxide thin film 11 is dry etched using the resist pattern 22 as a mask in a dry etching apparatus to form a charged beam transmission hole 12 (see FIG. 3F).
Examples of the dry etching apparatus include dry etching apparatuses using discharge methods such as RIE, magnetron RIE, ECR, ICP, microwave, helicon wave, and NLD.
Examples of the etching gas for dry etching include CH ₄ gas, halogen gas such as HCl gas and HBr gas, or a mixed gas thereof.

Finally, the resist pattern 22 is removed by a resist stripping solution or ashing to obtain a stencil mask 100 in which the charged beam transmission hole 12 is formed in the indium oxide thin film 11 (see FIG. 3G).
Here, the resist pattern 21 after etching the support substrate 1 may be performed simultaneously with the removal of the resist pattern 22.

First, a sputtering gas pressure of 0.5 Pa, Ar using a tin-doped indium oxide (ITO) target on a support substrate 1 composed of a low resistivity single crystal silicon wafer doped with phosphorus heated to 250 ° C. An indium oxide thin film 11 having a thickness of 2 μm was formed by a DC magnetron sputtering apparatus at an O ₂ flow rate ratio of 3.0% and an input power of 300 W (see FIG. 3A). At this time, the warpage of the substrate was less than 1 μm.

Next, a photoresist was applied on the support substrate 1 using a spin coater to form a photosensitive layer. Subsequently, pattern exposure was performed by contact exposure using a photomask, and development was performed with an alkaline developer to form a resist pattern 21 (see FIG. 3B).
Further, using the resist pattern 21 as a mask, etching is performed by a dry etching apparatus using SF ₆ gas (see FIG. 3C), the resist pattern 21 is removed by an oxygen plasma ashing apparatus, and an opening is formed in the support substrate 1. A stencil mask blank 20 having 31 formed thereon was obtained (see FIG. 3D).

  Next, an electron beam resist is applied on the indium oxide thin film 11 of the stencil mask blank 20 by a spin coater to form a photosensitive layer, and a series of patterning processes such as pattern drawing and development are performed by an electron beam drawing machine. A resist pattern 22 was formed (see FIG. 3E). Further, the indium oxide thin film 11 is etched by a dry etching apparatus using a fluorocarbon-based mixed gas with the resist pattern 22 as a mask to form a charged beam transmission hole 12 (see FIG. 3F), and the resist pattern 22 is formed with an organic solvent. The stencil mask 100 of the present invention in which the charged beam transmission hole 12 was formed in the indium oxide thin film 11 was obtained (see FIG. 3G).

  As described above, the manufactured stencil mask can suppress in-plane pattern deformation even after the transfer pattern is formed, and a good stencil mask can be obtained.

  The stencil mask 100 produced as described above was mounted on a charged particle beam exposure apparatus for exposure. An electron beam was used as the charged particle beam here. An electron beam emitted from an electron gun is irradiated onto a stencil mask on a stage placed at a predetermined position to form an electron beam in the shape of a transfer pattern, and this electron beam is reduced by an electron lens as a sample. A transfer pattern was projected and imaged at a desired position on a sensitive substrate on a stage coated with a resist in advance, and electron beam exposure was performed. As a result, it was confirmed that the pattern on the sample was subjected to high-accuracy pattern exposure as designed.

It is a schematic structure sectional view showing one example of a substrate for stencil masks of the present invention. It is a typical composition sectional view showing one example of the stencil mask of the present invention. (A)-(g) is explanatory drawing which shows an example of the manufacturing method of the board | substrate for stencil masks of this invention, and a stencil mask in order of a process. (A) And (b) is explanatory drawing which shows the state of the curvature of the board | substrate for stencil masks. It is a schematic cross section showing an example of an SOI substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support substrate 10, 10a, 10b ... Stencil mask substrate 11 ... Indium oxide thin film 12 ... Charge beam transmission hole 20 ... Stencil mask blank 21, 22 ... Resist pattern 31 ... Opening 100 ... Stencil mask 111 ... Silicon substrate 121 ... Silicon oxide thin film 131 ... Silicon thin film 200 ... SOI substrate

Claims (5)

  A stencil mask substrate comprising a support substrate and an indium oxide thin film.   The stencil mask substrate according to claim 1, wherein the support substrate is a silicon wafer.   The indium oxide thin film contains at least one element selected from tin, titanium, zirconium, hafnium, niobium, tantalum, tungsten, germanium, tellurium, zinc, and fluorine as elements other than oxygen and indium. The stencil mask substrate according to claim 1, wherein the stencil mask substrate is provided.   A stencil mask, wherein a transfer pattern is formed on the indium oxide thin film using the stencil mask substrate according to any one of claims 1 to 3.   A charged particle beam exposure method comprising: irradiating a stencil mask according to claim 4 with a charged particle beam, forming the charged particle beam into a transfer pattern shape, and forming a transfer pattern on a substrate to be transferred. .

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