JP2006066635A - Integrated circuit, and method and program for analyzing consumed current - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make effective the evaluation of a consumed current of an integrated circuit such as a digital LSi, and improve the accuracy of the same in relation to the evaluation. <P>SOLUTION: The integrated circuit(digital LSi2) with a function circuit operated by a single or a plurality of clock signals with different frequencies mounted thereon comprises a plurality of function blocks (logic blocks 4A, 4B, 4C), which are set to the function circuit and are capable of starting and stopping the clock signal independently; and a recording part (operation hysteresis storage blocks 20A, 20B, 20C) for recording operation details based on the clock signal for every function block. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to an evaluation of current consumption of an integrated circuit such as digital LSi (Large Scale integration), and in particular to analysis of complex control contents for the purpose of reducing power consumption and measurement results of current consumption based on the control. The present invention relates to an integrated circuit to be used, a consumption current analysis method thereof, and a consumption current analysis program.

  Regarding the digital LSi, the validity of the current consumption can be evaluated by comparing the measurement result of the current consumption of the whole chip with the result of the current simulation. If the circuit scale of LSi is relatively small and the circuit configuration and control for low power consumption are not complicated, there is no problem in applying such a method, and the evaluation will be highly valid.

Regarding the power consumption of such digital LSi, Patent Document 1 discloses an apparatus and method relating to self-audit control of power consumption in a functional unit of a microprocessor. Patent Document 2 discloses a data processor that outputs a trace information for monitoring internal information and its attribute information to the outside corresponding to the complexity of a plurality of circuit modules and internal buses mounted on the semiconductor chip. It is disclosed.
JP-A-10-91298 JP 2002-149442 A

  In digital LSi with an expanded circuit scale, the logic circuit to be mounted is also complicated. In particular, in LSi applied to a mobile terminal of W-CDMA (Wideband Code Division Multiple Access), etc., in order to reduce current consumption. Therefore, it is difficult to evaluate the validity of the current consumption measurement results. It is possible to divide LSi into a plurality of blocks and measure the average current consumption of each block individually, and compare the current consumption value measured with an ammeter etc. with the result of current consumption simulation. It is also possible to confirm the validity.

  By the way, the start / stop control of each logical block is complicated by the control of hardware and firmware to reduce power consumption, and especially in the LSi configured to frequently start / stop, the logic to start When a block is congested, measuring and evaluating its current consumption value is cumbersome. In such LSi, it is essential to determine the relationship between current consumption and operation. Therefore, it is necessary to measure the current consumption transition within a certain arbitrary time and check whether it is operating according to the control specifications, but it cannot be said that the current consumption transition is as expected. In that case, it is very difficult to determine whether or not the logic circuit is operating as intended only by the transition of the measured current consumption value. Even if the result is as expected, it takes time and effort to determine the validity of the result. Patent Documents 1 and 2 do not disclose such problems, and there is no suggestion or disclosure of means for solving the problems.

SUMMARY OF THE INVENTION The present invention relates to evaluation of current consumption of an integrated circuit such as digital LSi, and aims to improve efficiency and accuracy.

  In order to achieve the above object, the present invention relates to an integrated circuit such as a digital LSi, and pays attention to supply and stop of a clock signal used for the operation of each logic block, and records the operation contents of each logic block, thereby reducing current consumption. This is an improved evaluation function for actual measured values.

  In order to achieve the above object, an integrated circuit of the present invention is an integrated circuit on which a functional circuit that operates by a single or a plurality of clock signals having different frequencies is mounted, and is set in the functional circuit and independently A plurality of functional blocks capable of starting and stopping the clock signal, and a recording unit for recording the operation content based on the clock signal for each functional block.

  In such a configuration, when a functional circuit that operates by a single or a plurality of clock signals having different frequencies is mounted on the integrated circuit, the functional circuit is provided in a plurality of functional blocks that can start and stop the clock signal independently. It can be divided. The operation content based on the clock signal differs for each divided functional block. Therefore, the operation content for each functional block is recorded in the recording unit. This operation content is taken out of the integrated circuit from the recording unit, and can be used for evaluation information such as current consumption.

  In order to achieve the above object, in the integrated circuit of the present invention, the recording unit may be configured to set a period for recording the operation content. With such a configuration, the operation content can correspond to the period.

  To achieve the above object, in the integrated circuit of the present invention, the integrated circuit includes a determination unit that determines the frequency of the clock signal based on a set value of the frequency division number, and causes the recording unit to record the operating frequency information of the functional block. It is good also as a structure. With such a configuration, since the recording unit includes the determination unit that determines the frequency of the clock signal based on the set value of the frequency division number, the recording unit records the operating frequency information in addition to the operation content of the functional block. This operating frequency information can be used for current consumption evaluation.

  In order to achieve the above object, a method of analyzing current consumption of an integrated circuit according to the present invention is a method of analyzing current consumption of an integrated circuit on which a functional circuit operating with a single or a plurality of clock signals having different frequencies is mounted. A process of recording a current value based on the clock signal for each of a plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently; a process of obtaining a current value of the functional block by simulation; In this configuration, the current consumption of the integrated circuit is analyzed including a process of comparing the current value obtained by the simulation with the current value obtained by the operation of the functional block.

  As described above, when the integrated circuit is equipped with a functional circuit that operates with a single or a plurality of clock signals having different frequencies, the functional circuit is divided into a plurality of functional blocks that can start and stop the clock signal independently. The operation can be divided, and the operation content based on the clock signal is different for each functional block. Therefore, it is possible to analyze the current consumption of the integrated circuit by recording the current value based on the clock signal for each functional block, obtaining the current value of each functional block by simulation, and comparing these current values. . In other words, the current consumption value is measured for each functional block and for each clock signal with a different frequency, and by comparing the current consumption value by simulation, the validity of the measurement result can be judged, and the current consumption evaluation accuracy Is increased.

  In order to achieve the above object, an integrated circuit consumption current analysis program according to the present invention is an integrated circuit consumption current analysis program in which functional circuits that operate according to single or plural clock signals having different frequencies are mounted. Recording a current value based on the clock signal for each of a plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently; obtaining a current value of the functional block by simulation; In this configuration, the current consumption of the integrated circuit is analyzed by causing a computer to execute a step of comparing the current value obtained by the simulation with the current value obtained by the operation of the functional block.

By executing such a program, the current consumption analysis of the integrated circuit described above can be executed by a computer, and the current consumption value that is an actual measurement value measured for each clock signal having a different frequency is obtained by simulation. By comparing with the current consumption value, the validity of the measurement result can be judged, and the evaluation accuracy of the current consumption can be improved.

  As described above, according to the present invention, the following effects can be obtained.

  According to the integrated circuit of the present invention, when a functional circuit that operates with a single or a plurality of clock signals having different frequencies is mounted on the integrated circuit, the functional circuit can be started and stopped independently. Divided into a plurality of functional blocks, and the operation content is stored in a recording unit mounted in the integrated circuit for each logical block, so that information representing the operation content of each functional block of the integrated circuit is integrated from the recording unit It can be taken out of the circuit, its operation content can be confirmed, and it can be used to judge the validity of the current consumption value of the integrated circuit, which can contribute to the improvement of the current consumption evaluation accuracy.

  Further, in this integrated circuit, if the recording unit mounted on the integrated circuit is configured to set a period for recording the operation content of each functional block, the operation content of the logic block can be made to correspond to the period, It is possible to judge the validity of the current consumption for each period and contribute to the improvement of the accuracy of current consumption evaluation.

    The integrated circuit further includes a determination unit that determines the frequency of the clock signal based on the setting value of the frequency division number, and the operation frequency information of the functional block is stored in the recording unit. Since the frequency of the clock signal is determined by the determination unit, the operation frequency information can be stored in addition to the operation content of the functional block, and the operation frequency information can be used for the consumption current evaluation. For example, it is possible to contribute to the improvement of the evaluation accuracy of current consumption.

  According to the integrated circuit current consumption analysis method of the present invention, the current value based on the clock signal is recorded in the recording unit for each functional block, the current value of each functional block is obtained by simulation, and the current values are compared. Therefore, the validity of the measurement result can be determined, and the evaluation accuracy of the current consumption can be improved.

According to the integrated circuit consumption current analysis program of the present invention, the consumption current analysis of the integrated circuit can be executed by a computer, and a current consumption value that is an actual measurement value measured for each clock signal having a different frequency and a simulation. By comparing with the obtained current consumption value, the validity of the measurement result can be judged, and the evaluation accuracy of the current consumption can be improved.

First Embodiment A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a configuration example of the digital LSi according to the first embodiment.

  The digital LSi2 is an example of an integrated circuit on which a functional circuit that operates by a single or a plurality of clock signals having different frequencies is mounted. This digital LSi2 is, for example, a digital LSi that is mounted on a W-CDMA terminal for the purpose of reducing power consumption. Each logical block 4A, 4B, 4C is independent of a logical circuit mounted on the digital LSi2. Grouped and divided into a plurality of functional blocks capable of starting and stopping the clock signal. Therefore, each of the logical blocks 4A, 4B, and 4C can be controlled to start and stop by the common block start control circuit 6, and when the start signal is disabled, the clock supplied to the inside of the block It is possible to stop the signal.

  The logic block 4A operates according to the clock signal supplied from the clock generator 8, but the clock control block 10 can stop the clock operation. The logic block 4B divides the clock signal supplied from the clock generator 8 by the internal clock generation circuit 12 to generate a plurality of clock signals having different frequencies, and the operation clock selection circuit 14 generates the clock signal. By selecting based on the selection information, the operation clock signal can be operated with a reduced frequency. This corresponds to a gear-down function of a processor or the like, and has a function of reducing the operating speed and reducing the current consumption when processing is not particularly urgent. The logic block 4C operates with the external clock signal CK1 and generates an clock signal in the same manner as the logic block 4B, or an operation clock selection for selecting an operation clock signal based on clock selection information. A circuit 18 and the like are provided.

  Further, as a recording unit that records the operation contents of the logical blocks 4A, 4B, and 4C, and as a determination unit that determines the frequency of the clock signal based on the set value of the frequency division number, each of the logical blocks 4A, 4B, and 4C corresponds. Operation history storage blocks 20A, 20B, and 20C are installed. In this embodiment, an operation history storage block 20A that records the operation history in the logical block 4A, and an operation history storage block 20B that records the operation history in the logical block 4B. An operation history storage block 20C for recording the operation history is installed in the logical block 4C. In addition, an external clock signal CK2 is applied to each of the operation history storage blocks 20A, 20B, and 20C, and a timer signal is applied from a commonly connected timer circuit 22. In each of the operation history storage blocks 20A, 20B, and 20C, the operation frequency information of the logical blocks 4A, 4B, and 4C is recorded. In this embodiment, clock selection information as the operation frequency information is stored in the operation history storage blocks 20B and 20C. It has been captured.

  These operation history storage blocks 20A, 20B, and 20C are connected to an operation recording unit 24 installed outside the digital LSi 2 through a recording / collecting bus 26, and condition setting writing or operation history reading is executed. The operation recording unit 24 includes an operation history collection circuit 28, a collection condition setting circuit 30, and the like.

  A personal computer (PC) 34 is connected to the operation recording unit 24 via an ICE (Incircuit Emulator) device 32, and each of the operation history storage blocks 20A, 20B, and 20C to the logic blocks 4A, 4B, and 4C is connected to the PC 34. Operation history data is captured. The PC 34 constitutes a consumption current evaluation unit for the digital LSi2 and also constitutes a current simulation unit.

  For example, as shown in FIG. 2, the PC 34 is provided with a CPU (Central Processing Unit) 36 for executing program execution processing, a ROM (Read-Only Memory) 38 and a RAM (Random-Access Memory) 40 as recording media. And an input unit 42 used for data input, an output unit 44 used for data output, a display unit 46 used for data presentation, and the like. The ROM 38 stores various programs such as a current consumption analysis program and a current consumption simulation program.

  Next, operation control specifications of the digital LSi2 will be described with reference to FIG. FIG. 3 shows operation control specifications of the logic blocks 4A, 4B, and 4C of the digital LSi2.

  In this digital LSi2, a control pattern of control 1, control 2, control 3... Control 10 is set, and logical blocks 4A, 4B, 4C are alternatives corresponding to controls 1, 2, 3,. Selected. Corresponding to the selection of the logic blocks 4A, 4B, and 4C, the frequency f1 or the frequency f2 is selected corresponding to the control content as the frequency of the set clock signal, and the control content is either activated or stopped Is selected. Corresponding to such control contents, a transition of operating current, that is, a transition of current consumption occurs.

  Next, a method for analyzing current consumption of an integrated circuit will be described with reference to FIGS. 4, 5, 6, and 7. FIG. 4, 5, 6, and 7 show an example of a current consumption analysis method for an integrated circuit. FIG. 4 shows a current simulation result of each logic block, and FIG. 5 shows a current consumption transition diagram. 6 shows an operation history storage example of each logical block, and FIG. 7 shows an operation history collection example of each logical block.

  As shown in FIG. 4, each logic block 4A, 4B, 4C obtains an average consumption current value calculation result by consumption current simulation. In this calculation result, the logic block 4A has a frequency f1 and the average current value is A [mA], the logic block 4B has the frequency f1 and the average current value is B1 [mA], the frequency f2 and the average current value is B2 [mA], and In the logic block 4C, the average current value is C1 [mA] at the frequency f1, and the average current value is C2 [mA] at the frequency f2. On the other hand, FIG. 5 shows a transition diagram of actual consumption current. In the actual current consumption, as shown in FIG. 5, the operation history collection time (A to I), the operating logic blocks 4A, 4B, and 4C and the frequencies f1 and f2 are taken on the horizontal axis, and the vertical axis Current consumption (A [mA], B1 [mA], B2 [mA], C1 [mA], C2 [mA]). In FIG. 5, for example, at time G, the integrated value of current consumption becomes A + B2 + C2 [mA] due to the operation of the logic blocks 4A, 4B, and 4C.

  In the operation history storage information stored in each of the operation history storage blocks 20A, 20B, and 20C, as shown in FIG. 6, the start time, completion time, and frequency setting are set, and the start time of the logic block 4A includes Times B and F are set as the time C and the start time of the logical block 4B, and times A and D are set as the start time of the logical block 4C. The time I is set as the completion time of the logical block 4A, and the completion time of the logical block 4B. Are time E and H, time C and G are set for the completion time of the logical block 4C, frequency f1 is set for the frequency setting of the logical block 4A, and frequency f1 and f2 are set for the frequency setting of the logical block 4B. The frequencies f1 and f2 are stored in the 4C frequency setting.

  The information recorded in the operation history storage blocks 20A, 20B, and 20C of the logical blocks 4A, 4B, and 4C is collected from the operation history of the operation recording unit 24 set outside the digital LSi2 from the recording / collection bus 26. The operation history storage information collected by the circuit 28 includes block, start-up time, completion time, frequency setting, and setting time for each logical block 4A, 4B, 4C. In the operation history collection example of FIG. 7, the operation history storage example of FIG. 6 is arranged. Within the set time, the logical block 4A is time C, the logical block 4B is time B, F, and the logical block 4C is time A at the start time. D at the completion time, the logical block 4A is time I, the logical block 4B is time E, H, the logical block 4C is time C, G, and the frequency setting is the frequency at the start time C of the logical block 4A. f1, frequency f1 at time B (startup time) of logic block 4B, frequency f2 at time F (startup time) of logic block 4B, frequency f1 at time A (startup time) of logic block 4C, time D of logic block 4C In (start-up time), the frequency is f2.

  Therefore, based on the operation control specifications of the logical blocks 4A, 4B, and 4C, the operation recording collection time is set by the operation recording unit 24 from outside the digital LSi2. The digital LSi2 is operated, and the transition diagram (graph) shown in FIG. 5 is obtained based on the transition of the current consumption within the set time. Simultaneously with the measurement of current consumption, the operation histories shown in FIG. 6 are stored in the operation history storage blocks 20A, 20B, and 20C in the logical blocks 4A, 4B, and 4C. After completion of current consumption measurement within the set time, the operation history of each of the logic blocks 4A, 4B, 4C is collected from the digital LSi2 by the operation history collection circuit 28, and the result shown in FIG. 7 is obtained. As described above, by comparing the current consumption simulation result of each of the logic blocks 4A, 4B, and 4C with the operation history of each of the logic blocks 4A, 4B, and 4C with respect to the transition of the current consumption, It is easily confirmed whether or not the transition matches the control specifications of the logic blocks 4A, 4B, and 4C, and the validity of the current value can be confirmed and evaluated.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 8 shows an example of a digital LSi evaluation apparatus.

  The digital LSi evaluation apparatus 50 is provided with an evaluation board 52. The evaluation board 52 is equipped with, for example, a digital LSi2 as an integrated circuit to be evaluated, and stores as a peripheral circuit of the digital LSi2. A device 54, a power supply unit 56, an operation recording unit 24, a current probe 58, an analog LSi 60, a high frequency unit (RF) 62, and the like are mounted. The current probe 58 is installed at an arbitrary current detection point capable of detecting the consumption current of the digital LSi2. In this case, for example, a W-CDMA digital baseband chip (Digital Baseband Chip) of LSi for W-CDMA communication terminal apparatus is used for the digital LSi2. The storage device 54 is configured by a flash memory or SDRAM (Synchronous Dynamic Random-Access Memory), and is used for storing a program for operating the digital LSi2. The power supply unit 56 is configured by a DC-DC converter, and a low voltage power supply 64 is connected between the VDD terminal and the GND terminal. The low voltage applied from the low voltage power supply 64 is converted into an optimum DC voltage by the DC-DC converter of the power supply unit 56 and then applied to the power supply terminal (Power Pin) 66 of the digital LSi2. In this case, a current detection point is set on the power supply line 68 between the power supply terminal 66 and the power supply unit 56, a current probe 58 is connected to this current detection point, and the operating current detected by the current probe 58 is a current probe amplifier. The current value is converted into a voltage value. The voltage value corresponding to the operating current is added to the oscilloscope 72 constituting the voltmeter, and the value is measured. The oscilloscope 72 is connected to the trigger terminal 74 of the digital LSi2, and a single trigger set is executed in order to take a timing for measuring a current value.

  The operation recording unit 24 stores the operation record data extracted from the operation history storage blocks 20A, 20B, and 20C (FIG. 1) of the digital LSi2. Data stored in the operation recording unit 24 is added to the PC 34 via the ICE device 32. As described above, the PC 34 constitutes a current consumption evaluation unit of the digital LSi2.

  Further, the PC 80 is connected to the JTAGI / F terminal 76 of the digital LSi 2 via the ICE device 78. A radio simulator 82 is connected to the digital LSi 2 via analog LSi 60 and RF 62, and a PC 86 is connected to the radio simulator 82 by a radio wave 84 or the like.

  Next, the configuration of the digital LSi2 will be described with reference to FIGS. 9 shows the configuration of the digital LSi2 before installation of the operation history storage blocks 20A, 20B, and 20C and the block activation control circuit 6, and FIG. 10 shows the digital LSi2 after installation of the operation history storage blocks 20A, 20B, and 20C. .

  The digital LSi2 includes a logic block 4A including a wireless data receiver 90, a logic block 4B including a demodulator control DSP 92, and a logic block 4C including a CPU 94, as well as a peripheral unit 98 such as a decoder 96 and a USB (Universal Serial Bus). A clock generator 100, a power save controller 102, a global timer 104, and the like are mounted. The output clock of the clock generator 100 is controlled by the power save controller 102.

  The logical block 4A (wireless data reception unit 90) includes a clock controller 106, a DSP-I / F 108, a despreading unit 110, a demodulation unit 112, and the like corresponding to the clock control block 10. Clock control of the clock controller 106 is possible by DSP control by the DSP-I / F 108. The decoding unit 94 includes a BUS-I / F 114 and the like.

  The logical block 4B (demodulation unit control DSP 92) includes a clock controller 116 corresponding to the internal clock generation circuit 12, a functional unit 118 such as a PC address counter, an instruction RAM 120, a BUS-I / F 122, and the like. By the program control by the clock controller 116, the frequency of the clock signal can be reduced, and the frequency control such as 1/2 or 1/4 of the fundamental frequency can be executed.

  The logic block 4C (CPU 94) includes a CPUCORE 124, an instruction RAM 126, a clock generator 128 corresponding to the internal clock generation circuit 16, a clock controller 130 corresponding to the operation clock selection circuit 18, a BUS-I / F 132, and the like. Further, the peripheral part 98 such as a USB includes a BUS-I / F 134 and the like. The output clock of the clock controller 130 can be gear-down by program control, and frequency control such as 1/2 or 1/4 of the fundamental frequency is executed.

  In addition, TCXO 136, ABBLSi 138, a storage device 54, an ICE device 78, a driver IC 140, a PC 142, and the like are installed in the peripheral portion of the digital LSi2 as a configuration for operation confirmation.

  In this digital LSi2, the radio data receiving unit 90 corresponds to the logical block 4A, the demodulating unit control DSP 92 corresponds to the logical block 4B, and the CPU 94 corresponds to the logical block 4C, as apparent from comparison with the digital LSi2 described above. is there. Therefore, in this digital LSi2, as shown in FIG. 10, the wireless data receiver 90 has the operation history storage block 20A described above, the demodulator control DSP 92 has an operation history storage block 20B, and the CPU 94 has an operation history storage block. 20C is installed, and a timer circuit 22 is connected to each operation history storage block 20A, 20B, 20C. Each operation history storage block 20A, 20B, 20C is connected to an operation recording unit 24 via a recording / collecting bus 26. The history data stored in the operation recording unit 24 is stored in the PC 34 via the ICE device 32. Is taken in.

  Next, a consumption current analysis method and a consumption current analysis program for an integrated circuit according to the present invention will be described with reference to FIG. FIG. 11 shows the processing procedure of the consumption current analysis method or consumption current analysis program of the digital LSi according to the second embodiment.

  For current consumption analysis, the current probe 58 is connected to the measurement point (step S1). In the evaluation board 52 shown in FIG. 8, the measurement probe of the current probe 58 is connected to the power supply line 68 between the power supply unit 56 and the digital LSi2. Power is supplied to the evaluation system (step S2), and program selection for operating the digital LSi2 on the PC 80 side is executed (step S3). This program is transmitted to the digital LSi2 through the ICE device 78 and downloaded to the storage device 54 connected to the digital LSi2 (step S4).

  A single trigger set is executed from the digital LSi2 to the oscilloscope 72 (step S5), a program start command issued from the PC 80 is transmitted to the digital LSi2 through the ICE device 78, and the program is executed (step S6). Through such processing, the measurement result is acquired in the operation recording unit 24 (step S7), and such acquisition of the measurement result is executed for each program. Corresponding to the program selection in step S3, an expected current value is calculated from the PC 34 by executing the current simulation program (step S8) (step S9).

  Then, the measurement result for each program obtained in step S7 and the expected current value obtained in step S9 are compared and verified (step S10), and the evaluation result is obtained. The comparison result is displayed on the display unit 46 (FIG. 2) of the PC 34.

  By the way, in the operation history storage blocks 20A, 20B, and 20C installed in the digital LSi2, the transition of current consumption is stored as operation history data for each operation of the program. In the current simulation, each current consumption value of each logic block 4A, 4B, 4C and its accumulated current consumption value are calculated.

  With reference to such a result, the operation record contents stored in the operation history storage blocks 20A, 20B, and 20C, and the actual measured current consumption value or the accumulated current consumption value within the recording period obtained by the current simulation are obtained. By comparing each other on the time axis, it is possible to analyze the accumulated current consumption in the logic circuit of the digital LSi2, to improve its efficiency and to determine its validity.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 12 shows a specific configuration example of the operation history storage blocks 20A, 20B, and 20C and the operation recording unit 24 mounted on the digital LSi2 or the digital LSi2. In FIG. 12, the same parts as those of FIG.

  The operation history storage blocks 20A, 20B, and 20C are different in the installed logic blocks 4A, 4B, and 4C, but the configurations are the same. Therefore, the configuration of the operation history storage block 20A will be described.

  Regarding the input / output of the operation history storage block 20A, the master clock signal MCK, the start enable signal SE, the frequency setting signal FS, and the timer value signal TS are added from the logic block 4A side of the digital LSi2, and the write control signal WC and the read address signal RA. The read control signal RC is applied from the operation recording unit 24, and the operation history data ARD is output from the operation history storage block 20A to the operation recording unit 24.

  The operation history storage block 20A is provided with first and second RAMs 150 and 152 for storing the operation history of the logic block 4A, as well as an address value register 154, an address counter 156, a control register 158, and a change point detection circuit. 160, a RAM control circuit 162, a RAM read control circuit 164, and the like are provided. The RAMs 150 and 152 and the address value register 154 receive an output representing an address value from the address counter 156. The address counter 156 receives the master clock signal MCK and counts the master clock. The address counter 156 receives the address reset signal from the control register 158, resets the count value, and receives the output of the change point detection circuit 160.

  A start enable signal SE and a frequency setting signal FS are added to the RAM 150 and the change point detection circuit 160, and in this embodiment, the change point detection circuit 160 installed in the operation history storage block 20A has the frequency of the clock signal. Is determined from the frequency division number, and the change point of the start enable signal SE and the frequency setting signal FS is detected. This detection signal is applied to the RAM control circuit 162. The RAM control circuit 162 controls the RAMs 150 and 152. The write control signal WC and the read address signal RA output from the operation recording unit 24 are added to the control register 158 and used for address reset of the address counter 156.

  The operation history data stored in the RAMs 150 and 152 is output through the RAM read control circuit 164 based on the read address signal RA and the read control signal RC from the operation recording unit 24. The read control signal of the RAM read control circuit 164 is: It is added to the RAMs 150 and 152 and the address value register 154. That is, an address value is specified by the read address signal RA from the operation recording unit 24, and the operation history data ARD read from the RAM 150 is added to the operation recording unit 24 by the read control signal RC.

  The configuration of the operation history storage block 20A is the same for the other operation history storage blocks 20B and 20C. The operation recording unit 24 is provided with a processor 166 and a register control unit 168, and the processor 166 executes control such as data writing and reading, and address designation. The register control unit 168 adds the write control signal WC, the read address signal RA, and the read control signal RC described above to the operation history storage blocks 20A, 20B, and 20C in accordance with an instruction from the processor 166, and this operation history storage block 20A. , 20B, and 20C, the operation history data ARD is fetched. The operation history data ARD stored in the operation recording unit 24 is used as evaluation data and added to the PC 34 through the ICE device 32.

  The frequency setting signal, start enable, and operation history storage information stored in each operation history storage block 20A, 20B, 20C will be described. In this embodiment, the frequency setting signal FS has its address as shown in FIG. The clock stop and different clock signal frequencies are set with the value, and the start enable signal SE is set with the contents of the start enable together with the address value, for example, as shown in FIG. 14, and the operation history storage information is shown in FIG. As shown, it is composed of a timer value, a frequency, and a start enable that are set together with the address value.

  According to such a configuration, the circuit for recording and holding the supply start time and the supply completion time of the supply / stop control for each clock signal of each logic block 4A, 4B, 4C multiple times, and the control contents RAMs 150 and 152, a control register 158, an address counter 156, and the like are provided as circuits capable of arbitrarily setting a recording period, and RAM read control is performed as a circuit for outputting a value holding a recorded content to the outside of the digital LSi2. A circuit 164 is installed.

  Then, as shown in the digital LSi2 (for example, FIG. 9), the frequency of the clock signal supplied to the logic blocks 4A, 4B, and 4C can be changed by a frequency divider circuit (for example, the clock controllers 106, 116, and 130). Therefore, the change point detection circuit 160 is installed as a circuit that determines the frequency of the clock signal used in the logic blocks 4A, 4B, and 4C by the set value of the frequency division number (clock selection information, frequency setting signal). A RAM 150 is provided as a circuit for holding the recorded contents. With such a configuration, the operating frequency information is stored in the operation history storage blocks 20A, 20B, and 20C, and the information can be used for evaluation of current consumption.

  Based on such operation history information, the operation content of the digital LSi 2 can be confirmed, and the operation content based on the operation history information is used for evaluating the measured value of the current consumption, enabling highly reliable evaluation. Become.

  Next, technical matters are extracted from the embodiments of the integrated circuit, the current consumption analysis method and the current consumption analysis program described above, and the technical significance, modifications, and other technical extension items are described below. Are listed.

  (1) As described above, for the current consumption evaluation of digital LSi, a complicated control content aiming at low power consumption, a method for analyzing the measurement result of current consumption based on the control, an analysis program, and an integrated circuit are provided. Is.

  (2) In the above embodiment, in the measurement and analysis of the current consumption of the digital LSi that is an example of the integrated circuit, simulation is performed with each operation pattern of each of the logic blocks 4A, 4B, and 4C, and an expected current value is created. It is necessary to keep it. In addition, the current consumption of the digital LSi2 is dominated by the proportion of cells (clock buffer, etc.) having a large drive capability in order to increase the circuit scale and the operating frequency, and the clocks of the logical blocks 4A, 4B, 4C. It is the simplest and most common to reduce current consumption by stopping supply.

  (3) Therefore, in the above-described embodiment, each logical block 4A, 4B, 4C of the digital LSi2 for the purpose of reducing power consumption mounted on the W-CDMA terminal is converted into a single or a plurality of fixed-cycle clock signals. A logic circuit that operates and can control supply / stop for each clock used in each of the logic blocks 4A, 4B, and 4C is configured. As an example, as described above, the timer circuit 22 and each logic block are configured. A circuit for recording and holding the supply start time and the supply completion time of the supply / stop control for each clock of 4A, 4B, and 4C, and a period for recording the control contents can be arbitrarily set. Digital LSi2 added to each logic block of the operation history storage blocks 20A, 20B, and 20C is configured as a circuit for outputting a value holding the recorded contents to the outside of the LSi. Has been.

  (4) Also, as shown in the digital LSi2 (FIG. 9), the frequency of the clock signal supplied to the logic blocks 4A, 4B, and 4C is changed by a frequency divider or the like (for example, the clock controllers 106, 116, and 130). If possible, the change point detection circuit 160 is a circuit that determines the frequency of the clock signal used in the logic blocks 4A, 4B, and 4C based on the set value of the frequency division number (clock selection information, frequency setting signal). The operation history storage blocks 20A, 20B, and 20C having the RAM 150 as a circuit for holding the recorded contents are added to the digital LSi2. In the first embodiment, the operation history storage blocks 20A, 20B, and 20C constitute a determination unit that determines the frequency of the clock signal based on the set value of the frequency division number. In the third embodiment, the change point detection circuit 160 and the like. However, the determination unit may be configured using the functions of the operation clock selection circuits 14 and 18 shown in the first embodiment.

  (5) In the above embodiment, in the digital LSi2, the logic blocks 4A, 4B, and 4C are composed of logic circuits. However, for example, the logic blocks 4A, 4B, and 4C may be composed of memories, and the memories are capable of inhibit control. As described above, the timer circuit 22 and the operation history storage blocks 20A, 20B, and 20C are provided for the functional circuit (logic circuit) including the memory capable of controlling the inhibit signal of each memory, and each operation history storage block 20A is provided. , 20B and 20C can arbitrarily set a circuit for recording and holding the control inhibit start time and the inhibit completion time for each inhibit signal of each memory multiple times, and a period for recording the control contents. Digital circuit having a circuit for outputting recorded values stored outside the digital LSi to each memory. You may comprise as LLSi.

  (6) In the above embodiment, as described above, as an example of an integrated circuit including a functional circuit that operates by a single or a plurality of clock signals having different frequencies, low power consumption mounted in a W-CDMA terminal is reduced. The intended digital LSi is assumed. In this W-CDMA baseband LSi, the operating conditions for power saving are complicatedly controlled by hardware and firmware, and multiple functional blocks inside the digital LSi2 are multiplexed in time series according to the wireless communication protocol. Is going. Here, the operating conditions indicate clock ON / OFF control, clock frequency change, memory inhibit, and the like, and are elements that greatly affect power consumption. Therefore, in this W-CDMA baseband LSi power consumption monitor, operation history storage blocks 20A, 20B, and 20C are mounted in the digital LSi2 as circuits corresponding to the respective functional blocks (logic blocks 4A, 4B, and 4C) of the digital LSi2. is doing. Each of the operation history storage blocks 20A, 20B, and 20C includes an operation condition in a specified time zone, that is, a storage unit that stores a history of clock control, operation frequency, and memory control, a setting unit that arbitrarily sets a time zone specification, and the like. I have.

  (7) In the above embodiment, the digital LSi2 is exemplified as an example of an integrated circuit equipped with a functional circuit that operates by a single or a plurality of clock signals having different frequencies. Any integrated circuit including functional circuits that operate with a plurality of clock signals may be used, and the present invention is not limited to digital LSi for the purpose of reducing power consumption mounted in the W-CDMA terminal described above.

  (8) As described in the above embodiment, when the logic blocks 4A, 4B, and 4C are set for the digital LSi2 as an integrated circuit and the operation history storage blocks 20A, 20B, and 20C are incorporated, the operation is performed. The validity of the current consumption value of the digital LSi2 can be determined relatively easily by providing the recorded data to an external evaluation device or the like based on the recorded contents.

  (9) As described in the above embodiment, the reliability of the consumption current value of the actually measured digital LSi2 can be easily improved. That is, it is only necessary to monitor the control state of the clock signal as the operation history of each logic block 4A, 4B, 4C. It can be ignored. In digital LSi such as a portable terminal, much effort is required to estimate the call time, standby time, etc. from the transition of the actually measured current value, and to take a logical support, according to the present invention. , Can easily take back the performance.

  (10) The operation history of each logical block 4A, 4B, 4C contributes to the improvement of the operation quality of the control system of the logical blocks 4A, 4B, 4C. When control is performed using firmware, if the present invention is applied to timing verification with hardware and its evaluation, effects such as verification and shortening of the evaluation time can be obtained.

  (11) If the area for storing the operation history is expanded in the operation history storage blocks 20A, 20B, and 20C, measurement in a very long time, for example, several hours is possible. The operation history storage blocks 20A, 20B, and 20C can suppress current consumption except during evaluation by supplying a clock signal from the outside. Furthermore, the current consumption can be logically monitored by reading out information at every certain period (for example, intermittent period).

  Next, technical ideas extracted from the embodiments of the integrated circuit, the consumption current analysis method and the consumption current analysis program of the present invention described above are listed as appendices according to the description format of the claims. The technical idea according to the present invention can be grasped by various levels and variations from a superordinate concept to a subordinate concept, and the present invention is not limited to the following supplementary notes.

(Supplementary Note 1) An integrated circuit on which a functional circuit that operates by a single or a plurality of clock signals having different frequencies is mounted,
A plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently;
A recording unit for recording the operation content based on the clock signal for each functional block,
An integrated circuit comprising:

  (Supplementary note 2) The integrated circuit according to supplementary note 1, wherein the recording unit has a period for recording the operation content.

  (Additional remark 3) The integrated circuit of Additional remark 1 characterized by including the determination part which determines the frequency of the said clock signal by the setting value of a frequency division number, and makes the said recording part record the operating frequency information of the said functional block.

(Additional remark 4) It is the consumption current analysis method of the integrated circuit by which the functional circuit which operate | moves with the single or several clock signal from which a frequency differs, Comprising:
A process of recording a current value based on the clock signal for each of a plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently;
Processing to obtain the current value of the functional block by simulation;
A process of comparing the current value obtained by the simulation with the current value obtained by the operation of the functional block;
A method for analyzing current consumption of an integrated circuit, comprising: analyzing the current consumption of the integrated circuit.

(Additional remark 5) It is the consumption current analysis program of the integrated circuit by which the functional circuit which operate | moves with the single or several clock signal from which a frequency differs, Comprising:
Recording a current value based on the clock signal for each of a plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently;
Obtaining a current value of the functional block by simulation;
Comparing the current value obtained by the simulation with the current value obtained by the operation of the functional block;
A computer-executable current consumption analysis program for analyzing the current consumption of the integrated circuit.

  (Additional remark 6) The integrated circuit of Additional remark 1 provided with the timer circuit which provides time information to the said recording part.

  (Additional remark 7) The said recording part is set for every said functional block, and while setting supply time for every said clock signal, it was set as the structure which can set recording time, The additional description 1 characterized by the above-mentioned. Integrated circuit.

  (Supplementary Note 8) The function block can change the frequency of the clock signal according to the frequency division number, and the recording unit determines the frequency of the clock signal based on the frequency division number and stores the frequency information of the function block. The integrated circuit according to appendix 1, wherein the integrated circuit is configured as described above.

  (Additional remark 9) The said recording part is provided with the holding circuit which counts the clock signal supplied to the said functional block, and hold | maintains the count value, The integrated circuit of Additional remark 1 characterized by the above-mentioned.

(Supplementary Note 10) An integrated circuit on which a functional circuit that operates with a single or a plurality of clock signals having different frequencies is mounted,
A plurality of memories set in the functional circuit and capable of starting and stopping the clock signal independently;
A recording unit for recording the operation content based on the clock signal for each memory;
An integrated circuit comprising:

As described above, the most preferred embodiment of the present invention has been described. However, the present invention is not limited to the above description, and is described in the claims or disclosed in the detailed description of the invention. It goes without saying that various modifications and changes can be made by those skilled in the art based on the gist of the invention, and such modifications and changes are included in the scope of the present invention.

The present invention relates to evaluation of current consumption of an integrated circuit such as a digital LSi, and is an integrated circuit equipped with a functional circuit that operates by a single or a plurality of clock signals having different frequencies, and independently activates a clock signal and A plurality of functional blocks that can be stopped are set, and each functional block is provided with a recording unit that records the operation content based on the clock signal, and history information is taken out of the integrated circuit from this recording unit, and evaluation information such as current consumption Therefore, it is useful because it can improve the evaluation accuracy and contribute to the provision of a highly reliable integrated circuit.

1 is a block diagram showing an integrated circuit according to a first embodiment of the present invention. It is a block diagram which shows the outline | summary of a structure of a personal computer. It is a figure which shows the operation control specification of a logic block. It is a figure which shows the electric current simulation result of a logic block. It is a figure which shows the transition of the consumption current of digital LSi. It is a figure which shows the example of storage of the operation | movement history of a logical block. It is a figure which shows the collection example of the operation | movement history of a logic block. It is a figure which shows the outline | summary of the digital LSi evaluation apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the basic composition of digital LSi which concerns on 2nd Embodiment. It is a block diagram which shows the structure of digital LSi which concerns on 2nd Embodiment. It is a flowchart which shows the processing procedure of the consumption current analysis method and consumption current analysis program of digital LSi which concern on 2nd Embodiment. It is a block diagram which shows the structural example of the operation | movement history storage block and operation | movement recording part which concern on 3rd Embodiment. It is a figure which shows the address and content of a frequency setting signal. It is a figure which shows the address and content of a starting enable signal. It is a figure which shows the operation | movement log storage information of a logical block.

Explanation of symbols

2 Digital LSi
4A, 4B, 4C logic block (functional block)
20A, 20B, 20C Operation history storage block (recording unit)
24 Operation recording unit 34 PC
50 Digital LSi Evaluation Device 160 Change Point Detection Circuit (Judgment Unit)

Claims (5)

An integrated circuit on which a functional circuit that operates by a single or a plurality of clock signals having different frequencies is mounted,
A plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently;
A recording unit for recording the operation content based on the clock signal for each functional block,
An integrated circuit comprising:   The integrated circuit according to claim 1, wherein a period for recording the operation content is set in the recording unit.   The integrated circuit according to claim 1, further comprising a determination unit that determines a frequency of the clock signal based on a set value of a frequency division number, and causes the recording unit to record operating frequency information of the functional block. A method for analyzing current consumption of an integrated circuit equipped with a functional circuit that operates by a single or a plurality of clock signals having different frequencies,
A process of recording a current value based on the clock signal for each of a plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently;
Processing to obtain the current value of the functional block by simulation;
A process of comparing the current value obtained by the simulation with the current value obtained by the operation of the functional block;
A method for analyzing current consumption of an integrated circuit, comprising: analyzing the current consumption of the integrated circuit. A current consumption analysis program for an integrated circuit equipped with a functional circuit that operates by a single or a plurality of clock signals having different frequencies,
Recording a current value based on the clock signal for each of a plurality of functional blocks set in the functional circuit and capable of starting and stopping the clock signal independently;
Obtaining a current value of the functional block by simulation;
Comparing the current value obtained by the simulation with the current value obtained by the operation of the functional block;
A computer-executable current consumption analysis program for analyzing the current consumption of the integrated circuit.

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