JP2006060381A - Phase-locked loop circuit and information reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of improving frequency comparison precision and realizing stable and high-speed frequency lead-in, and an information reproducing device. <P>SOLUTION: The PLL circuit is provided with a frequency comparator 25 that removes a 2T pattern which has not been removed by a hysteresis comparator 24 by periodically measuring pulses in synchronism with three-phase clocks CLKA, CLKB, and CLKC by a VCO23, and then outputs an UP signal UP or down signal DOWN based upon a detection result to a charge pump circuit 26 when a hysteresis signal HYC by the hysteresis comparator 24 is taken in synchronously with the three-phase clocks CLKA, CLKB, and CLKC by the VCO 23 and from which phase to which phase the edge of hysteresis of an input data signal is changed is thereafter observed in synchronism with, for example, the 1st-phase clock CLKA to detect whether a frequency is high or low as a frequency error. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a phase-locked loop (PLL) applied to an RF signal processing system such as an optical disk device, and an information reproducing apparatus including the phase-locked loop (PLL).

  In general, in an RF signal processing system of a digital recording / reproducing apparatus such as an optical disk, a PLL circuit that obtains an appropriate clock by comparing phase and frequency is used for recording and reproducing data.

As a frequency comparison method in an optical disk PLL circuit, for example, a method of extracting a wobble signal on a disk and locking it to this frequency to synchronize with the rotational speed of the disk is used.
However, this method cannot be used, for example, in the case of a disc having no wobble signal (as an example, a Blu-ray disc ROM, hereinafter referred to as BDROM).

  A method of extracting a frame synchronization signal periodically recorded for each recording frame and locking to this signal without using a wobble signal is also used (see, for example, Patent Document 1).

As a method for extracting a frequency error from a random data pattern, there is a method for monitoring a phase transition of a data edge based on a multiphase clock based on a voltage controlled oscillator (VCO) or a multiphase clock of a ring VCO. It is known (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 11-232795 Japanese Patent Laid-Open No. 11-308097

  However, in the case of the method described in Patent Document 1, the phase frequency comparison period becomes longer depending on the frame period (in the case of BDROM, 1932T period), so the time until frame sync detection is established is also included. There is a disadvantage that it takes time to pull in, and is not suitable for high-speed frequency pulling.

In the method described in Patent Document 2, when applied to a high-density optical disk, the quality of the input data edge is poor due to an analog signal equalization error, disk perturbation, noise, and the like. There are disadvantages that false detections occur frequently and stable frequency pull-in cannot be performed.
Also, with this method, the frequency detection gain is not proportional to the frequency error, and if the error increases to some extent, the gain decreases, so such erroneous detection with a large initial frequency error increases the pull-in time. Alternatively, the frequency may diverge out of the pulling range.
In addition, the frequency error must be within the phase pull-in range when switching to the phase mode, but if the convergence value is not stable due to false detection of the frequency loop, the phase pull-in cannot be performed and the data cannot be read. There is sex.
In order to ensure the stability of the frequency loop, the loop gain may be lowered, but in this case, the time required for pulling in increases.

In addition, as a method for comparing frequencies in the data synchronizer PLL of the RF signal of the optical disc, a method using all user data is adopted.
However, when all user data is used, the shortest pattern of user data has a smaller amplitude due to the frequency characteristics of the recording / playback system. It will change.
For this reason, among the 2T to 8T data patterns, the result of performing the 2T period measurement may be an incorrect value for the data reproduction speed.
Since the appearance frequency of the shortest pattern is higher than that of other patterns, the influence on the frequency comparator output due to the period change is great.
For this reason, if the degree of interference changes due to the parameter setting of the equalizer in the previous stage of the PLL circuit, its variation, or the recording density of the disk, the 2T period changes, and the frequency comparator is affected. The capture range is greatly affected, and in some cases, the desired capture range may not be ensured.
In addition, since the inter-waveform interference has a different degree of interference depending on the pattern before and after the 2T pattern, the frequency comparator may be affected by the recording pattern, and the PLL pull-in operation may become unstable at a specific recording pattern portion. .

  The present invention has been made in view of such circumstances, and an object thereof is to provide a PLL circuit and an information reproducing apparatus capable of improving frequency comparison accuracy and realizing stable and high-speed frequency acquisition. It is in.

  In order to achieve the above object, a phase locked loop according to a first aspect of the present invention includes an oscillation circuit that oscillates at a frequency according to a control signal and outputs a clock having a predetermined frequency, and a clock and an input signal generated by the oscillation circuit. A phase comparison circuit that detects a phase difference and outputs phase difference data; a feedback circuit that generates the control signal based on the phase difference data and the feedback signal of the phase comparison circuit and supplies the control signal to the oscillation circuit; A frequency comparison unit that compares the signal obtained by removing only the shortest pattern from the input signal including the pattern and the frequency of the clock of the oscillation circuit and outputs a signal corresponding to the frequency error to the feedback circuit is provided.

  Preferably, the frequency comparison unit includes a hysteresis comparator, removes the shortest pattern having a small amplitude from the input signal through the hysteresis comparator, and compares the output pulse after the removal with the frequency of the clock of the oscillation circuit.

  Preferably, the frequency comparison unit includes a comparator, measures an edge period of an output pulse obtained from the input signal through the comparator, and stops output of the frequency comparison or comparison result in the case of the shortest pattern. .

  Preferably, the comparator is a hysteresis comparator that removes the shortest pattern having a small amplitude of the input signal.

  Preferably, the plurality of patterns include 2T to 8T data patterns, and the frequency comparison unit removes only the 2T pattern which is the shortest pattern among the 2T to 8T data patterns.

  A phase locked loop circuit according to a second aspect of the present invention includes an oscillation circuit that oscillates at a frequency according to a control signal and outputs a multiphase clock having different phases, and one of the multiphase clocks generated by the oscillation circuit. A phase comparison circuit that detects a phase difference between the input signal and output the phase difference data, and a feedback circuit that generates the control signal based on the phase difference data and the feedback signal of the phase comparison circuit and supplies the control signal to the oscillation circuit And a hysteresis comparator that removes the shortest pattern having a small amplitude of the input signal from an input signal including a plurality of patterns, and based on the output pulse of the hysteresis comparator and the multiphase clock of the oscillation circuit, the output pulse and the clock Detects frequency error, outputs a signal according to the frequency error, measures the edge period of the output pulse, and makes the shortest pattern Case, and a frequency comparator for stopping the output of the frequency comparison or comparison result.

  According to a third aspect of the present invention, there is provided an information reproducing circuit for sampling a signal read from a recording medium based on a clock, converting the signal into a digital signal, and reproducing the digital signal. A phase synchronization circuit, the phase synchronization circuit oscillating at a frequency according to a control signal and outputting a clock having a predetermined frequency, and detecting a phase difference between the clock by the oscillation circuit and the input signal; A phase comparison circuit that outputs phase difference data; a feedback circuit that generates the control signal based on the phase difference data of the phase comparison circuit and a feedback signal; and supplies the control signal to the oscillation circuit; and an input signal including a plurality of patterns. The signal from which only the pattern is removed is compared with the frequency of the clock of the oscillation circuit, and a signal corresponding to the frequency error is output to the feedback circuit. A frequency comparing unit that, the.

  A fourth aspect of the present invention is an information reproducing circuit that samples a sine wave signal read from a recording medium based on a clock, converts it into a digital signal and reproduces it, and the sampling phase of the clock matches the correct state A phase synchronization circuit for oscillating, wherein the phase synchronization circuit oscillates at a frequency corresponding to a control signal and outputs a multiphase clock having different phases, and a multiphase clock of the oscillation circuit A phase comparison circuit that detects a phase difference between one clock and an input signal and outputs phase difference data, and generates the control signal based on the phase difference data of the phase comparison circuit and a feedback signal, and supplies the control signal to the oscillation circuit Feedback circuit and hysteresis comparator that removes the shortest pattern with small amplitude of the input signal from the input signal containing multiple patterns Based on the output pulse of the hysteresis comparator and the multiphase clock of the oscillation circuit, the frequency error between the output pulse and the clock is detected, a signal corresponding to the frequency error is output, and the edge period of the output pulse is measured. In the case of the shortest pattern, a frequency comparator that stops frequency comparison or output of the comparison result is included.

  Preferably, the input signal of the hysteresis comparator is a reproduction RF signal of an equalizer output, and the reproduction RF signal is partial response equalized.

According to the present invention, the clock of the oscillation circuit is supplied to the phase comparison circuit and the frequency comparison unit.
In the frequency comparison unit, for example, only the shortest pattern is removed from the input signal including a plurality of patterns such as 2T to 8T. Then, the signal from which the shortest pattern is removed is compared with the frequency of the clock of the oscillation circuit, and a signal corresponding to the frequency error is output to the feedback circuit.
In the phase comparison circuit, the phase difference between the clock and the input signal by the oscillation circuit is detected, and the phase difference data is output to the feedback circuit.
Then, a control signal is generated based on the phase difference data of the phase comparison circuit and the feedback signal, and the oscillation frequency of the oscillation circuit is controlled.

According to the present invention, by removing the shortest pattern, which is greatly deteriorated due to noise and intersymbol interference, and comparing the frequencies, the equalization error of the equalizer, the recording pattern, the aberration of the optical pickup, the disc skew and the recording density are used. Therefore, accurate frequency comparison is possible.
As a result, the frequency pull-in operation of the PLL circuit is stable, and a desired capture range can be ensured.
As a result, the playability of the high density optical disk device can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a system configuration diagram showing an embodiment of an RF signal processing system of an optical disc apparatus employing a PLL circuit (phase synchronization circuit) according to the present invention.

  As shown in FIG. 1, the optical disk apparatus 10 includes an optical disk 11 as a recording medium, an optical head 12, a preamplifier 13, an AGC (Auto Gain Control) circuit 14, an analog equalizer 15, an analog-digital converter (ADC) 16, and an FIR filter. 17, Viterbi decoder 18, decoder (ECC, interface (I / F) 19, encoder 20, laser driver 21, phase comparator 22, VCO 23, hysteresis comparator 24, frequency comparator 25, charge pump circuit 26, and loop filter 27.

Among these components, the phase comparator 22, the VCO 23, the hysteresis comparator 24, the frequency comparator 25, the charge pump circuit 26, and the loop filter 27 constitute the PLL circuit 30 of the present invention. The charge pump circuit 26 and the loop filter 27 constitute a feedback circuit of the present invention. The hysteresis comparator 24 and the frequency comparator 25 constitute a frequency comparison unit.
Hereinafter, the specific functions of the components of the PLL circuit will be mainly described.

In the optical disc apparatus 10, the reproduction signal output from the optical head 12 and amplified by the preamplifier 13 is adjusted in amplitude by the AGC circuit 14 and input to the analog equalizer circuit 15.
The reproduction signal equalized by the analog equalizer 15 and from which high frequency noise has been removed is input to the ADC 16 and the hysteresis comparator 24.
The output of the ADC 16 is input to the phase comparator 22 of the PLL circuit, and is controlled so that the sampling phase of the ADC 15 is matched by controlling the VCO 23 in the PLL circuit 40 as will be described later.
Further, the output of the ADC 15 is input to the FIR filter 17 and further equalized with high accuracy, and then input to the Viterbi decoder 18 where it is decoded and error-corrected, and then output as NRZ data.
The NRZ data is encoded by the encoder 20, and the laser of the optical head 12 is driven and controlled by the laser driver 21 based on the result.

  Hereinafter, the PLL circuit will be specifically described.

  The phase comparator 22 compares the phase of the digital signal from the ADC 15 with the phase of the output clock (A) of the VCO 23 and outputs the phase error data S22 to the loop filter 27.

The VCO 23 has a three-stage ring configuration of inverters 231 to 233, and the oscillation frequency is controlled by a control signal S27 obtained by integrating the phase error data S22 by the loop filter 27.
The VCO 23 outputs three-phase clocks A, B, and C that divide one cycle of CLK into three as shown in FIGS. 2C, 2D, and 2E, as shown in FIGS. These three-phase clocks CLKA, CLKB, and CLKC are supplied to the frequency comparator 25.
The first phase clock (output clock of the inverter 233) of the VCO 23 is supplied to the ADC 16, the FIR filter 17, the Viterbi decoder 18, and the phase comparator 22.

  The hysteresis comparator 24 receives, for example, a sinusoidal RF reproduction signal as shown in FIG. 2A from the analog equalizer 15, and the level changes according to the hysteresis point as shown in FIG. 2B. The signal HYS is output to the frequency comparator 25.

Although it is necessary to match the sampling phase of the ADC 16 to the correct state by the PLL circuit, it is difficult to pull in the phase by the phase detector when the difference between the input signal frequency and the clock frequency is large (over about 3%). Therefore, first, it is necessary to draw a frequency shift by the frequency loop.
The frequency comparator 25 is arranged at the first stage of this frequency loop.

The frequency comparator 25 takes in the hysteresis signal HYC by the hysteresis comparator 24 in synchronization with the three-phase clocks CLKA, CLKB, and CLKC by the VCO 23, and thereafter, for example, in synchronization with the first phase clock A, the hysteresis edge of the input data signal By observing which phase changes from which phase to which phase, whether the frequency is high or low is detected as a frequency error, and the up signal UP or the down signal DOWN is output to the charge pump circuit 27.
The frequency comparator 25 receives the output pulse HYC of the hysteresis comparator 24 and uses it to detect a frequency error (UP or DOWN). However, as will be described below, the frequency comparator 25 cannot remove it. The 2T pattern is removed by measuring the pulse period in synchronization with the three-phase clocks CLKA, CLKB, and CLKC by the VCO 23.

  Thus, the frequency comparator 25 measures the edge period of the input analog signal using the VCO clock. In the present embodiment, as the input signal, an output pulse (hysteresis signal HYS) of the hysteresis comparator 24 is used instead of using an analog signal zero-cross comparator output.

In the case of a Blu-ray disc, 2T to 8T exist as user data patterns. However, the 2T of the shortest pattern has a smaller amplitude due to the frequency characteristics of the recording / reproducing system. The influence is great, and the period changes due to interference. Therefore, before being input to the frequency comparator 25, the 2T pattern having a low period reliability is removed using the difference in amplitude.
In a high-density recording device such as a Blu-ray disc, a partial response equalizer and a maximum likelihood decoding device (equal to characteristics approximate to the frequency characteristics of the recording / reproducing system) are used to compensate for the deteriorated identification S / N. PRML signal processing combined with a Viterbi decoder) is employed.

  FIG. 3 is a diagram showing an ideal eye pattern of a reproduction RF signal equalized to PR (1, 2, 1) in a Blu-ray disc adopting 1-7PP modulation having a shortest pattern of 2T. FIG. 4 is a diagram showing an actual eye pattern of a reproduction RF signal equalized to PR (1, 2, 1) in a Blu-ray disc adopting 1-7PP modulation having a shortest pattern of 2T. is there.

As shown in FIG. 3, the reproduction response RF signal that has been subjected to partial response equalization has an amplitude of 2RT, which is the shortest pattern, which is significantly smaller than the amplitude of a pattern of 3T or more, so that the hysteresis level of the comparator is set appropriately. It can be removed by setting the value.
Here, the partial response class is not limited to PR (1,2,1). The shortest pattern is not limited to 2T, and 3T modulation represented by DVD EFMpuls may be used.
However, as shown by the eye pattern in FIG. 4, in the actual machine waveform, there is intersymbol interference due to noise and equalization error. Therefore, 2T cannot be completely removed only by the hysteresis of the comparator.

The output pulse HYS of the hysteresis comparator 24 is input to the frequency comparator 25 of the PLL 30 and used to detect the direction of frequency error (UP or DOWN).
At this time, the 2T pattern that could not be removed by the hysteresis comparator 24 is removed by measuring the pulse period using the VCO clock.

When removing a 2T pattern by period measurement, it is difficult to remove only 2T because the distribution of the 3T pattern and the distribution of the 2T pattern overlap.
For this reason, when trying to remove 2T by periodic measurement alone, especially when the 2T distribution is moved to the 3T side due to a change in the 2T period, the distribution of the 3T pattern becomes asymmetric due to the remaining 2T component. Therefore, the symmetry of frequency comparison may be deteriorated.
On the other hand, in 2T removal by the hysteresis comparator 24, 2T and 3T distribution symmetry can be ensured, and the 2T distribution can be removed to some extent.
Therefore, 2T can be accurately removed by using these two methods together.

  FIG. 5 is a diagram illustrating a basic operation image of the frequency comparator according to the present embodiment. FIG. 6 is a diagram showing the comparison logic of the frequency comparator according to the present embodiment.

As shown in FIG. 5, one clock CLK section is divided into three by the first phase clock CLKA, the second phase clock CLKB, and the third phase clock CLKC, which are three phase clocks, and each phase section is divided into A, B, and C. To do.
At this time, the frequency error (direction) is detected from the phase transition of the current edge Yn and the next edge Yn + 1 of the hysteresis of the input data signal as follows.

If the transition of the edge is forward (A → B → C) for each phase A, B, C in the clock CLK1 period, the input signal frequency is considered to be lower than the VCO frequency, so the down signal DOWN Is output.
If the edge transition is in the reverse direction (C → B → A), the frequency of the input data signal is considered to be higher than the VCO frequency, and therefore the up signal UP is output.
If there is no edge phase transition, no error is detected, so nothing is output.

Specifically, as shown in FIG. 6, when the edge Yn is the phase A and the next edge Yn + 1 is the phase A, the frequency comparator 25 has no phase transition of the edge and cannot detect an error. Neither the up signal UP nor the down signal DOWN is output.
When the edge Yn is the phase A and the next edge Yn + 1 is the phase B, the frequency of the input data signal is considered to be lower than the VCO frequency, so the down signal DOWN is output.
When the edge Yn is the phase A and the next edge Yn + 1 is the phase C, the up signal UP is output because the frequency of the input data signal is considered to be higher than the VCO frequency.
When the edge Yn is the phase B and the next edge Yn + 1 is the phase A, the frequency of the input data signal is considered to be higher than the VCO frequency, so the up signal UP is output.
When the edge Yn is the phase B and the next edge Yn + 1 is the phase B, there is no phase transition of the edge and the error cannot be detected, so neither the up signal UP nor the down signal DOWN is output.
When the edge Yn is the phase B and the next edge Yn + 1 is the phase C, the frequency of the input data signal is considered to be lower than the VCO frequency, so the down signal DOWN is output.
When the edge Yn is the phase C and the next edge Yn + 1 is the phase A, the frequency of the input data signal is considered to be lower than the VCO frequency, so the down signal DOWN is output.
When the edge Yn is the phase C and the next edge Yn + 1 is the phase B, the up signal UP is output because the frequency of the input data signal is considered to be higher than the VCO frequency.
When the edge Yn is the phase C and the next edge Yn + 1 is the phase C, there is no phase transition of the edge and the error cannot be detected, so neither the up signal UP nor the down signal DOWN is output.

  FIG. 7 is a circuit diagram showing an example of a logic circuit of a frequency comparator that enables the detection operation of FIG.

  7 includes D-type flip-flops 201 to 218, exclusive OR (EXOR) gates 219 to 221, a two-input AND gate 222 including a negative input, and a three-input AND gate 223, 3 including a negative input. Input OR gates 224 to 226, 2-input NOR gate 227, switch circuits 228 to 230, 3-input AND gate 231 including negative input, 3-input AND gates 232 to 235, 4-input AND gate 236 including negative input, and first Buffers 237 and 238 for delaying the phase clock CLKA are provided.

The flip-flops 201 to 203 are arranged in parallel with the input HYCIN of the hysteresis signal HYC. The flip-flop 201 latches the hysteresis signal HYC in synchronization with the first phase clock CLKA, the flip-flop 202 latches the hysteresis signal HYC in synchronization with the second phase clock CLKB, and the flip-flop 203 receives the third phase clock CLKC. Synchronously, the hysteresis signal HYC is latched.
That is, the flip-flops 201 to 203 are arranged at the input stage of the frequency comparator 25 and latch the hysteresis signal HYC by the hysteresis comparator 24 in synchronization with the three-phase clocks CLKA, CLKB, and CLKC of the VCO 23.
2F to 2H show the Q outputs of the flip-flops 201 to 203 as A0, B0, and C0, respectively.
Note that the flip-flops 204 to 218 after the first stage input / output data in synchronization with the first phase clock CLKA.

The D input of the flip-flop 204 is connected to the Q output of the first flip-flop 201, the D input of the flip-flop 205 is connected to the Q output of the first flip-flop 202, and the D input of the flip-flop 206 is the first flip-flop 203. Connected to the Q output.
The flip-flops 204 to 206 latch the outputs of the flip-flops 201 to 203 in synchronization with the first phase clock CLKA via the buffer 237, respectively.
2 (I) to (K) show the Q outputs of the flip-flops 204 to 206 as A1, B1, and C1, respectively.

The EXOR 219 takes the exclusive OR of the output A1 of the flip-flop 204 and the output B1 of the flip-flop 205, and outputs the result as the H input of the switch 228, the negative input of the AND gate 222, the first negative input of the AND gate 223, And to the first input of the OR gate 224.
The EXOR 220 takes the exclusive OR of the output B1 of the flip-flop 205 and the output C1 of the flip-flop 206, and outputs the result as the positive input of the AND gate 222, the second negative input of the AND gate 223, and the first of the OR gate 224. Supply to 2 inputs.
The EXOR 221 performs an exclusive OR operation between the output B1 of the flip-flop 206 and the output A0 of the first-stage flip-flop 201, and supplies the result to the positive input of the AND gate 223 and the third input of the OR gate 224.
These three EXORs 219 to 221 are provided to obtain the current clock, and take out one of the clocks CLKA, CLKB, and CLKC.
2 (L) to (N) show the outputs of EXORs 218 to 220 as A2, B2, and C2, respectively.
One of the outputs A2, B2, and C2 of the EXORs 219 to 222 becomes high level when there is hysteresis. In this example, the output C2 of the EXOR 221 is at a high level.

The output of the AND gate 222 is supplied to the H input of the switch circuit 229, and the output of the AND gate 23 is supplied to the H input of the switch circuit 230.
The OR gate 224 calculates the logical sum of the outputs A2, B2, and C2 of the EXORs 219 to 221 and outputs them as switch signals SW to the switch circuits 228 to 230 and the D input of the flip-flop 213.

When the switch signal SW is at a high level, the switch circuits 228 to 230 select the H input on the assumption that a hysteresis point has been detected, and output it to the D inputs of the corresponding flip-flops 207 to 209.
When the switch signal SW is at a low level, the switch circuits 228 to 230 select the L input on the assumption that the hysteresis point is not detected, and input the Q outputs of the corresponding flip-flops 207 to 209 to the D input. To form a loop.
FIG. 2O shows the switch signal SW that is the output of the OR gate 224.

As described above, the flip-flops 207 to 209 capture the outputs of the corresponding switch circuits 228 to 230 in synchronization with the first phase clock CLKA via the buffers 237 and 238.
While the hysteresis is not detected, the flip-flops 207 to 209 continue to latch the previously latched data by the loop formed by the switch circuits 228 to 230 in synchronization with the first phase clock CLKA, and the hysteresis is detected. In this case, the data at the time of detection is latched in synchronization with the first phase clock CLKA through the switch circuits 229-230.
The Q output of the flip-flop 207 is supplied to the L input of the switch circuit 228, the D input of the next-stage flip-flop 210, the first input of the AND gate 233, and the third input of the AND gate 236.
The Q output of the flip-flop 208 is supplied to the L input of the switch circuit 229, the D input of the next-stage flip-flop 211, the third input of the AND gate 232, and the second input of the AND gate 235.
The Q output of the flip-flop 209 is supplied to the L input of the switch circuit 230, the D input of the next-stage flip-flop 212, the third input of the AND gate 231, and the third input of the AND gate 234.
2 (U) to (W) show the Q outputs of the flip-flops 207 to 209 as A3, B3, and C3, respectively.

The flip-flops 210 to 212 latch the outputs of the flip-flops 207 to 209 in synchronization with the first phase clock CLKA via the buffers 237 and 238, respectively.
The output of the flip-flop 210 is supplied to the first input of the AND gate 231 and the first input of the AND gate 232.
The output of the flip-flop 211 is supplied to the second input of the AND gate 233 and the first input of the AND gate 234.
The output of flip-flop 212 is supplied to a first input of AND gate 235 and a second input of AND gate 236.
2 (X) to (Z) show the Q outputs of the flip-flops 210 to 212 as A4, B4, and C4, respectively.

The flip-flop 213 latches the output signal SW of the OR gate 224 in synchronization with the first phase clock CLKA via the buffers 237 and 238.
The Q output of the flip-flop 213 is supplied to the D input of the flip-flop 214 at the next stage.
The flip-flop 214 latches the output of the flip-flop 213 in synchronization with the first phase clock CLKA via the buffers 237 and 238.
The Q output of the flip-flop 214 is supplied to the D input of the next-stage flip-flop 215, the first input of the NOR gate 227, and the second input (negative input) of the AND gate.
The flip-flop 215 latches the output of the flip-flop 214 in synchronization with the first phase clock CLKA via the buffers 237 and 238.
The Q output of the flip-flop 215 is supplied to the D input of the next-stage flip-flop 216 and the second input of the NOR gate 227.
The flip-flop 216 latches the output of the flip-flop 215 in synchronization with the first phase clock CLKA via the buffers 237 and 238.
The Q output of the flip-flop 216 is supplied to the fourth input (negative input) of the AND gate 236.
The flip-flops 214 to 216 are enabled by an enable signal ENB. 2 (Q) to (S) show the Q outputs of the flip-flops 213 to 216 as P0, P1, P2 and P3, respectively.

The output of the NOR gate 227 is supplied to the third input of the AND gate 232, the third input of the AND gate 233, the second input of the AND gate 234, the third input of the AND gate 235, and the first input of the AND gate 236. The
FIG. 2 (T) shows the output of the NOR gate 227 as P4.

  Since the flip-flops 213 to 216 and the NOR gate 227 basically mask the frequency comparison result by the 2T pattern (and 1T generated by noise and other factors) as a logic operation, one clock of the current data edge is used. Alternatively, when a data edge exists two clocks before, it is determined that it is 2T or less, and the output is masked.

Based on the logic of FIG. 6, the AND gate 231 determines that the frequency of the input data signal is higher than the VCO frequency when the edge Yn is in phase A and the next edge Yn + 1 is in phase C. Is supplied to the first input of the OR gate 225.
Based on the logic of FIG. 6, the AND gate 232 determines that the frequency of the input data signal is lower than the VCO frequency when the previous edge Yn is phase A and the next edge Yn + 1 is phase B. A high level signal is supplied to the first input of the OR gate 226 to output the signal DOWN.
When the edge Yn is phase A and the next edge Yn + 1 is phase A, the AND gates 231 and 232 cannot detect an error because there is no phase transition of the edge, so that the up signal UP and the down signal DOWN are not output. The low level signals are output to the gates 225 and 226, respectively.

Based on the logic of FIG. 6, the AND gate 233 determines that the frequency of the input data signal is higher than the VCO frequency when the previous edge Yn is phase B and the next edge Yn + 1 is phase A. In order to output the signal UP, a high level signal is supplied to the second input of the OR gate 225.
Based on the logic of FIG. 6, the AND gate 234 determines that the frequency of the input data signal is lower than the VCO frequency when the previous edge Yn is phase B and the next edge Yn + 1 is phase C. In order to output the signal DOWN, a high level signal is supplied to the second input of the OR gate 226.
When the edge Yn is phase B and the next edge Yn + 1 is phase B, the AND gates 233 and 234 do not output an up signal UP or a down signal DOWN because there is no phase transition of the edge and error detection is not possible. The low level signals are output to the gates 225 and 226, respectively.

Based on the logic of FIG. 6, the AND gate 235 determines that the frequency of the input data signal is higher than the VCO frequency when the previous edge Yn is phase C and the next edge Yn + 1 is phase B. A high level signal is supplied to the third input of the OR gate 225 to output the signal UP.
Based on the logic of FIG. 6, the AND gate 236 determines that the frequency of the input data signal is lower than the VCO frequency when the previous edge Yn is phase C and the next edge Yn + 1 is phase A. In order to output the signal DOWN, a high level signal is supplied to the third input of the OR gate 226.
When the edge Yn is phase C and the next edge Yn + 1 is phase C, the AND gates 235 and 236 do not output an up signal UP or a down signal DOWN because there is no phase transition of the edge and error detection is not possible. The low level signals are output to the gates 225 and 226, respectively.

The OR gate 225 calculates the logical sum of the output signals of the AND gates 231, 233 and 235 and supplies it to the D input of the flip-flop 217 in the output stage of the up signal UP.
The OR gate 226 calculates the logical sum of the output signals of the AND gates 232, 234, and 236 and supplies it to the D input of the flip-flop 218 at the output stage of the down signal DWM.
2 (Γ) and (Δ) show the outputs of the OR gates 225 and 226 as U0 and D0, respectively.

The flip-flop 217 latches the output U0 that takes the high level or low level of the OR gate 225 in synchronization with the first phase clock CLKA via the buffers 237 and 238, and outputs the up signal UP from the Q output to the charge pump circuit 26. Output to.
The flip-flop 218 latches the output D0 that takes the high level or low level of the OR gate 226 in synchronization with the first phase clock CLKA via the buffers 237 and 238, and outputs the down signal DOWN from the Q output to the charge pump circuit 26. Output to.
2 (Π) and (Σ) show the up signal UP and the down signal DOWN which are the outputs of the flip-flops 217 and 218, respectively.

The first phase clock CLKA supplied to the flip-flops 217 and 218 is, for example, as the first phase clock CLK2 after being frequency-divided by a frequency divider (not shown) (eg, frequency division by 2), for example, the up signal UP and the down signal DOWN. Can also be configured to latch and output.
FIG. 2 (Υ) shows this clock CLK2.

  In the frequency comparator 25 of FIG. 7, data indicating in which phase the previous hysteresis is detected is set in the flip-flops 210 to 212, and the current (next) hysteresis is set in the flip-flops 207 to 209. Since the data indicating in which phase is detected is set, information on the detection phase of the previous edge Yn and information on the detection phase of the next edge Yn + 1 are obtained.

  The flip-flops 213 to 216 provided in the present embodiment function as a 2T removal logic system in the frequency comparator 25.

  FIG. 8 is a diagram for explaining a 2T determination method based on pulse edge period measurement using a three-phase clock.

A CLK section is divided into three by CLKA, CLKB, and CLKC, which are three-phase clocks, and A, B, and C are defined as each phase section.
At this time, period measurement is performed with an accuracy three times that of the clock of the VCO 23 depending on where the current edge and the next edge of the input data pulse are in each phase and how many VCO clocks exist between the two edges. .
Note that the measurement clock does not have to be three-phase, and may be multi-phased to four or more phases in order to increase the resolution.
Further, the hysteresis level of the hysteresis comparator 24 is adjustable and can be set to an optimum value.

The logic operation basically masks the frequency comparison result based on the 2T pattern (and 1T generated by noise and other factors), so that the data edge exists one or two clocks before the current data edge. Is configured to mask the output by judging that it is 2T or less. However, the following pattern exists as an exception.
(1) 3T pattern starting from A and ending C after 2 clocks,
(2) A 2T pattern starting from C and ending at A after 3 clocks.

As for (1), since the 3T pattern is also removed as it is, the transition from A to C is masked only when a data edge exists one clock before.
As for (2), since a 2T pattern is left behind, the transition from C to A is masked by the presence of data edges up to three clocks before.

  As described above, by using the hysteresis comparator 24 and the pattern period measurement in combination, the 2T pattern can be removed with high accuracy, and as a result, malfunction of the frequency comparator 25 can be prevented.

  In the frequency comparator 25 according to the present embodiment, it is impossible to detect hysteresis twice within one cycle of the first phase clock CLKA because of data characteristics. The up signal UP and the down signal DOWN are not output and ignored, assuming that data based on noise or the like is taken in.

For example, in the normal operation, when the previous edge Yn is phase A and the next edge Yn + 1 is phase B, the output A4 of the flip-flop 210 and the output B3 of the flip-flop 208 are at a high level, and Since the output of the NOR gate 227 should also be at a high level, the AND gate 232 assumes that the frequency of the input data signal is lower than the VCO frequency and outputs a high level signal to output the down signal DOWN. This is supplied to the OR gate 226.
However, when the output of the NOR gate 227 is at a low level due to noise or the like, the output of the AND gate 232 is masked and held at a low level, and the output of the down signal DOWN is suppressed.

Similarly, in the normal operation, when the previous edge Yn is phase B and the next edge Yn + 1 is phase A, the output A3 of the flip-flop 207 and the output B4 of the flip-flop 211 are at a high level. In addition, since the output of the NOR gate 227 should also be at a high level, the AND gate 233 assumes that the frequency of the input data signal is higher than the VCO frequency and outputs a high level signal to output the up signal UP. Is supplied to the OR gate 225.
However, when the output of the NOR gate 227 is at a low level due to noise or the like, the output of the AND gate 233 is masked and held at a low level, and the output of the up signal UP is suppressed.

Similarly, in the normal operation, when the previous edge Yn is phase B and the next edge Yn + 1 is phase C, the output C3 of the flip-flop 209 and the output B4 of the flip-flop 211 are at a high level. Since the output of the NOR gate 227 should also be at a high level, the AND gate 234 assumes that the frequency of the input data signal is lower than the VCO frequency and outputs a high level signal to output the down signal DOWN. Is supplied to the OR gate 226.
However, when the output of the NOR gate 227 is low level due to noise or the like, the output of the AND gate 234 is masked and held at the low level, and the output of the down signal DOWN is suppressed.

Similarly, in the normal operation, when the previous edge Yn is the phase C and the next edge Yn + 1 is the phase B, the output B3 of the flip-flop 208 and the output C4 of the flip-flop 212 are at the high level. In addition, since the output of one gate 227 should also be at a high level, in the AND gate 235, the frequency of the input data signal is assumed to be higher than the VCO frequency, so that the up signal UP is output. A signal is supplied to the OR gate 225.
However, when the output of the NOR gate 227 is at a low level due to noise or the like, the output of the AND gate 235 is masked and held at the low level, and the output of the up signal UP is suppressed.

Similarly, in the normal operation, when the previous edge Yn is the phase C and the next edge Yn + 1 is the phase A, the output A3 of the flip-flop 207 and the output C4 of the flip-flop 212 are at the high level. Since the output of the NOR gate 227 should also be at a high level, the AND gate 236 assumes that the frequency of the input data signal is lower than the VCO frequency and outputs a high level signal to output the down signal DOWN. Is supplied to the OR gate 226.
However, when the output of the NOR gate 227 is low level due to noise or the like, the output of the AND gate 236 is masked and held at the low level, and the output of the down signal DOWN is suppressed.

  Next, the operation of the circuit of FIG. 1 will be described.

The reproduction signal output from the optical head 12 and amplified by the preamplifier 13 is adjusted in amplitude by the AGC circuit 14 and input to the analog equalizer circuit 15.
The reproduction signal equalized by the analog equalizer 15 and from which high frequency noise has been removed is input to the ADC 16 and the hysteresis comparator 24.

  At this time, it is necessary to match the sampling phase of the ADC 16 to the correct state by the PLL circuit 30. However, when the difference between the input signal frequency and the clock frequency is large (in excess of about 3%), the phase acquisition by the phase detector is not performed. Since it is difficult, the frequency shift is first drawn by the frequency loop.

  The output of the hysteresis comparator 24 is input to the frequency comparator 25 of the PLL circuit 30 and used for detecting the direction of frequency error (UP or DOWN).

In the frequency comparator 25, the hysteresis signal HYC is taken in by the hysteresis comparator 24 in synchronization with the three-phase clocks CLKA, CLKB, CLKC by the VCO 23, and thereafter, for example, the hysteresis of the input data signal is synchronized with the first phase clock A. By observing from which phase the phase has changed to which phase, whether the frequency is high or low is detected as a frequency error, and the up signal UP or the down signal DOWN is output to the charge pump circuit 27.
At this time, in the frequency comparator 25, the output pulse HYC of the hysteresis comparator 24 is input and used to detect the frequency error (UP or DOWN). However, the 2T pattern that cannot be removed by the hysteresis comparator 24 is It is removed by measuring the pulse period in synchronization with the three-phase clocks CLKA, CLKB, and CLKC by the VCO 23.

The up signal UP or the down signal DOWN output from the frequency comparator 25 is converted into a current by a frequency loop charge pump circuit 26 and integrated into a loop filter 27.
The oscillation frequency of the VCO 23 is controlled by the output control signal S27 of the loop filter 27, and operates so as to match the frequency of the input data signal.
The VCO 23 has a three-stage ring configuration, and the output from each stage is a three-phase clock CLKA, CLKB, CLKC that divides one cycle of CLK into three. The three-phase clocks CLKA, CLKB, and CLKC are input to the frequency comparator 25, and the frequency is detected by comparing with the hysteresis signal HYC output from the hysteresis comparator 24.

  The above is the operation in the frequency mode, and when the input data signal and the oscillation frequency of the VCO 23 substantially coincide with each other by the operation of the frequency loop, the PLL circuit 30 is switched to the phase lock mode.

The output of the ADC 16 is input to the phase comparison circuit 22 of the PLL circuit 30. The phase error data S22 is integrated by the loop filter 27, and the sampling phase of the ADC 16 is matched by controlling the VCO 23.
The output of the ADC 16 is input to the FIR filter 17 and equalized with higher accuracy, and then input to the Viterbi decoder 18, decoded and error-corrected, and then output as NRZ data.

  As described above, according to the present embodiment, the hysteresis signal HYC is acquired by the hysteresis comparator 24 in synchronization with the three-phase clocks CLKA, CLKB, and CLKC by the VCO 23, and thereafter, for example, in synchronization with the first phase clock CLKA, A 2T pattern that cannot be removed by the hysteresis comparator 24 when detecting whether the frequency is high or low by observing from which phase the hysteresis edge of the input data signal has changed to which phase. The frequency comparison is performed by measuring the period of the pulse in synchronization with the three-phase clocks CLKA, CLKB, and CLKC by the VCO 23 and thereby outputting the up signal UP or the down signal DOWN to the charge pump circuit 26 based on the detection result. Has vessel 25 And a, it is possible to obtain the following effects.

That is, according to the present invention, the equalization error of the equalizer, the recording pattern, the aberration of the optical pickup, the disc skew or the recording density is obtained by removing the shortest pattern that is greatly deteriorated due to noise or intersymbol interference and comparing the frequencies. Regardless of this, accurate frequency comparison is possible.
As a result, the frequency pull-in operation of the PLL circuit is stable, and a desired capture range can be ensured.
As a result, the playability of the high density optical disk device can be improved.

1 is a system configuration diagram showing an embodiment of an RF signal processing system of an optical disc apparatus employing a PLL circuit according to the present invention. 3 is a timing chart showing waveforms of respective portions of an input data signal, a hysteresis signal, a three-phase clock, and a frequency comparator in the PLL circuit according to the present embodiment. It is a figure which shows the ideal eye pattern of the reproduction | regeneration RF signal equalized to PR (1,2,1) in the Blu-ray disc which employ | adopted 1-7PP modulation whose shortest pattern is 2T. FIG. 5 is a diagram showing an actual eye pattern of a reproduction RF signal equalized to PR (1, 2, 1) in a Blu-ray disc adopting 1-7PP modulation with a shortest pattern of 2T. It is a figure which shows the operation | movement image of the frequency comparator which concerns on this embodiment. It is a figure which shows the comparison logic of the frequency comparator which concerns on this embodiment. FIG. 4 is a circuit diagram illustrating an example of a logic circuit of a frequency comparator that enables the detection operation of FIG. 3. It is a figure for demonstrating the 2T determination method by pulse edge period measurement.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Optical disk, 11 ... Optical disk, 12 ... Optical head, 13 ... Preamplifier, 14 ... AGC circuit, 15 ... Analog equalizer, 16, Analog-digital converter (ADC), 17 ... FIR filter, 18 ... Viterbi decoder, 19 ... Decoder (ECC, interface (I / F), 20 ... encoder, 21 ... laser driver, 22 ... phase comparator, 23 ... VCO, 24 ... hysteresis comparator, 25 ... frequency comparator, 26 ... charge pump circuit, 27 ... loop filter 30 ... PLL circuit.

Claims (18)

An oscillation circuit that oscillates at a frequency according to a control signal and outputs a clock of a predetermined frequency;
A phase comparison circuit that detects a phase difference between the clock and the input signal by the oscillation circuit and outputs phase difference data;
A feedback circuit that generates the control signal based on phase difference data and a feedback signal of the phase comparison circuit and supplies the control signal to the oscillation circuit;
A phase synchronization circuit comprising: a frequency comparison unit that compares a signal obtained by removing only the shortest pattern from an input signal including a plurality of patterns with a frequency of a clock of the oscillation circuit and outputs a signal corresponding to a frequency error to the feedback circuit. 2. The phase according to claim 1, wherein the frequency comparison unit includes a hysteresis comparator, removes the shortest pattern having a small amplitude from the input signal through the hysteresis comparator, and compares the output pulse after the removal with the frequency of the clock of the oscillation circuit. Synchronous circuit. The frequency comparison unit includes a comparator, measures an edge period of an output pulse obtained from the input signal through the comparator, and stops output of a frequency comparison or comparison result in the case of the shortest pattern. Phase synchronization circuit. The phase synchronization circuit according to claim 3, wherein the comparator is a hysteresis comparator that removes a shortest pattern having a small amplitude of the input signal. The plurality of patterns include 2T to 8T data patterns,
The phase synchronization circuit according to claim 1, wherein the frequency comparison unit removes only the 2T pattern which is the shortest pattern among the 2T to 8T data patterns. The plurality of patterns include 2T to 8T data patterns,
The phase synchronization circuit according to claim 2, wherein the frequency comparison unit removes only the 2T pattern which is the shortest pattern from the 2T to 8T data patterns. An oscillation circuit that oscillates at a frequency according to the control signal and outputs a multiphase clock having different phases;
A phase comparison circuit that detects a phase difference between one of the multiphase clocks by the oscillation circuit and an input signal, and outputs phase difference data;
A feedback circuit that generates the control signal based on phase difference data and a feedback signal of the phase comparison circuit and supplies the control signal to the oscillation circuit;
A hysteresis comparator that removes the shortest pattern with a small amplitude of the input signal from an input signal including a plurality of patterns;
Based on the output pulse of the hysteresis comparator and the multi-phase clock of the oscillation circuit, the frequency error between the output pulse and the clock is detected, a signal corresponding to the frequency error is output, the edge period of the output pulse is measured, In the case of the shortest pattern, a phase synchronization circuit having a frequency comparator that stops frequency comparison or comparison result output. The plurality of patterns include 2T to 8T data patterns,
The phase synchronization circuit according to claim 7, wherein the frequency comparison unit removes only the 2T pattern which is the shortest pattern from the 2T to 8T data patterns. An information reproducing circuit that samples a signal read from a recording medium based on a clock, converts the signal into a digital signal, and reproduces the signal.
Having a phase synchronization circuit for matching the sampling phase by the clock to the correct state;
The phase synchronization circuit is
An oscillation circuit that oscillates at a frequency according to a control signal and outputs a clock of a predetermined frequency;
A phase comparison circuit that detects a phase difference between the clock and the input signal by the oscillation circuit and outputs phase difference data;
A feedback circuit that generates the control signal based on phase difference data and a feedback signal of the phase comparison circuit and supplies the control signal to the oscillation circuit;
An information reproducing apparatus comprising: a frequency comparison unit that compares a signal obtained by removing only the shortest pattern from an input signal including a plurality of patterns with a frequency of a clock of the oscillation circuit and outputs a signal corresponding to a frequency error to the feedback circuit . 10. The information according to claim 9, wherein the frequency comparison unit includes a hysteresis comparator, removes the shortest pattern having a small amplitude from the input signal through the hysteresis comparator, and compares the output pulse after the removal with the frequency of the clock of the oscillation circuit. Playback device. 10. The frequency comparison unit includes a comparator, measures an edge period of an output pulse obtained from the input signal through the comparator, and stops output of the frequency comparison or comparison result in the case of the shortest pattern. Information playback device. The information reproducing apparatus according to claim 11, wherein the comparator is a hysteresis comparator that removes a shortest pattern having a small amplitude of the input signal. The plurality of patterns include 2T to 8T data patterns,
The information reproducing apparatus according to claim 9, wherein the frequency comparison unit removes only the 2T pattern that is the shortest pattern among the 2T to 8T data patterns. The plurality of patterns include 2T to 8T data patterns,
The information reproducing apparatus according to claim 10, wherein the frequency comparison unit removes only the 2T pattern that is the shortest pattern from the 2T to 8T data patterns. The information reproducing apparatus according to claim 9, wherein the input signal of the hysteresis comparator is a reproduction RF signal output from an equalizer, and the reproduction RF signal is subjected to partial response equalization. An information reproducing circuit that samples a sinusoidal signal read from a recording medium based on a clock, converts the signal into a digital signal, and reproduces the digital signal.
Having a phase synchronization circuit for matching the sampling phase by the clock to the correct state;
The phase synchronization circuit is
An oscillation circuit that oscillates at a frequency according to the control signal and outputs a multiphase clock having different phases;
A phase comparison circuit that detects a phase difference between one of the multiphase clocks by the oscillation circuit and an input signal, and outputs phase difference data;
A feedback circuit that generates the control signal based on phase difference data and a feedback signal of the phase comparison circuit and supplies the control signal to the oscillation circuit;
A hysteresis comparator that removes the shortest pattern with a small amplitude of the input signal from an input signal including a plurality of patterns;
Based on the output pulse of the hysteresis comparator and the multi-phase clock of the oscillation circuit, the frequency error between the output pulse and the clock is detected, a signal corresponding to the frequency error is output, the edge period of the output pulse is measured, A frequency comparator that stops frequency comparison or output of comparison results in the case of the shortest pattern. The plurality of patterns include 2T to 8T data patterns,
The information reproducing apparatus according to claim 16, wherein the frequency comparison unit removes only the 2T pattern which is the shortest pattern from the 2T to 8T data patterns. The information reproducing apparatus according to claim 16, wherein an input signal of the hysteresis comparator is a reproduction RF signal output from an equalizer, and the reproduction RF signal is partial response equalized.

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