JP2006059420A - Sram memory cell and semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To collectively write data of a memory cell without increasing its area. <P>SOLUTION: An SRAM memory cell has a first inverter constituted of of a first N type MOS transistor 102 and a second P type MOS transistor 103, a second inverter constituted of a third N type MOS transistor 104 and a fourth P type MOS transistor 105, a fifth transistor 106 which is connected to the output of the first inverter, and a sixth transistor 107 which is connected to the output of the second inverter. In the SRAM memory cell, a latch circuit is constituted by the first and second inverters, the sources of the second transistor 103 and the fourth transistor 105 are connected to a common power supply line, the sources of the first transistor 102 and the third transistor 104 are connected to first and second terminals 108 and 109, respectively, and by controlling the first terminal 108 or the second terminal 109, the data held by the latch circuit can be set to an arbitrary state. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an SRAM memory cell and a semiconductor memory device that simplify initialization of retained data by devising the wiring of a memory cell.

  In a conventional semiconductor memory device, there is a technique for writing data in memory cells in a batch in order to set initial data of an SRAM and to shorten a data write time during a test.

Among them, there are many memory cells to which a transistor is added and a batch data write mode is provided. There is also a method of controlling the power supply circuit of the two inverters of the latch circuit (see, for example, Patent Document 1). FIG. 4 is a layout diagram of a conventional memory cell, and FIG. 5 is a layout diagram of the conventional memory cell. 4 and 5, 401 is a memory cell, 402 is an N-type MOS transistor of an inverter that constitutes a latch, 403 is a P-type MOS transistor of an inverter that constitutes a latch, and 404 is an N-type MOS transistor of an inverter that constitutes a latch. 405, a P-type MOS transistor of an inverter that constitutes a latch, 406, an N-type MOS transistor that exchanges data between the latch data and the bit line, and 407, an N-type MOS that exchanges data between the latch data and the bit line. Transistors 408 and 409 are power supply terminals, 410 and 411 are latch nodes, 412 and 413 are bit lines, and 414 is a word line.
JP 2003-187579 A

  As described above, the area of the semiconductor memory device having the collective data write mode with the addition of transistors is increased correspondingly. Further, in the method of controlling the power supply circuits of the two inverters of the latch circuit (FIG. 4), when laying out using the current mainstream horizontal memory cells, two middle power supply lines (408, 409) as shown in FIG. ) It is necessary to prepare, resulting in an increase in area.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an SRAM memory cell and a semiconductor memory device capable of collectively writing memory cell data without increasing the area.

  To achieve the above object, an SRAM memory cell according to claim 1 of the present invention includes a first inverter composed of a first N-type MOS transistor and a second P-type MOS transistor, and a third inverter. A second inverter composed of an N-type MOS transistor and a fourth P-type MOS transistor, a fifth transistor connected to the output of the first inverter, and an output of the second inverter A latch circuit is formed by the first and second inverters, and the sources of the second transistor and the fourth transistor are connected to a common power supply line, and And the source of the third transistor are respectively connected to the first and second terminals, and the latch circuit is controlled by controlling the first or second terminal. The retained data can be set to any state.

  The SRAM memory cell according to claim 2 is the SRAM memory cell according to claim 1, wherein the first transistor and the fifth transistor share a diffusion layer and are arranged in a vertical direction, respectively, and the second transistor is A straight gate wiring is shared with the first transistor in parallel with the first transistor, and the third transistor and the sixth transistor are respectively arranged in the vertical direction with a diffusion layer in common. The fourth transistor shares a straight gate wiring and is arranged in parallel with the third transistor, and the third transistor is arranged with the first transistor of the second transistor. The fourth transistor is arranged in a point-symmetrical position with respect to the first transistor with the point A on the opposite side as the origin, and the fourth transistor has the point A as the origin. The sixth transistor is disposed at a point-symmetrical position with respect to the second transistor, and the sixth transistor is disposed at a point-symmetrical position with respect to the fifth transistor with the point A as an origin. The diffusion layer that is not shared with the transistor No. 5 is not connected to the diffusion layer that is not shared with the sixth transistor of the third transistor through the diffusion layer or the wiring.

  According to a third aspect of the present invention, there is provided a semiconductor memory device comprising the SRAM memory cell according to the first aspect, comprising a wiring for applying a substrate potential, the wiring being connected to the first terminal or the second terminal. Not.

  According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising: adjacent first and second SRAM memory cells configured using the SRAM memory cell according to the first aspect; and a fifth transistor of the first SRAM memory cell. In contrast, the first bit line for inputting / outputting data and the first bit bar line for inputting / outputting data to / from the sixth transistor and the fifth transistor of the second SRAM memory cell receive data. And a second bit line for inputting / outputting data and a second bit bar line for inputting / outputting data to / from the sixth transistor, and the bit lines constituting the first bit line and the first bit bar line The pair, the bit line pair constituting the second bit line and the second bit bar are mirror-arranged.

  According to the SRAM memory cell of the first aspect of the present invention, the first and second inverters constitute a latch circuit, and the sources of the second transistor and the fourth transistor are connected to a common power supply line, The sources of the first transistor and the third transistor are connected to the first and second terminals, respectively, and the data held in the latch circuit can be set to an arbitrary state by controlling the first or second terminal. By controlling the two inverters of the latch circuit by the first or second terminal with one power supply wiring, the data in the memory cells can be collectively written without increasing the area. As described above, the retention data can be easily initialized by devising the wiring of the memory cell.

  According to a second aspect of the present invention, in the SRAM memory cell of the first aspect, the first transistor and the fifth transistor are respectively arranged in the vertical direction while sharing a diffusion layer in the SRAM memory cell of the first aspect. Transistors are arranged in parallel beside the first transistor, sharing a straight gate wiring with the first transistor, and the third transistor and the sixth transistor are arranged in the vertical direction, sharing a diffusion layer. The fourth transistor shares a straight gate wiring and is arranged in parallel next to the third transistor. The third transistor is the one in which the first transistor of the second transistor is arranged. The fourth transistor is arranged in a point-symmetrical position with respect to the first transistor with the point A on the opposite side as the origin, and the fourth transistor is The sixth transistor is arranged at a point-symmetrical position with the fifth transistor with the point A as the origin, and the diffusion layer which is not shared with the fifth transistor of the first transistor is arranged at the symmetrical position. A layout in which the third diffusion layer that is not shared with the sixth transistor is not connected to the diffusion layer through a diffusion layer, a wiring, or the like is preferable.

  According to a third aspect of the present invention, there is provided a semiconductor memory device comprising the SRAM memory cell according to the first aspect, comprising a wiring for applying a substrate potential, wherein the wiring is a first terminal or a second wiring. It is preferable that the terminal is not connected. This is because when high data is input from the first or second terminal, the substrate potential of the first or third transistor needs to be set to a low level.

  According to a fourth aspect of the semiconductor memory device of the present invention, the adjacent first and second SRAM memory cells configured using the SRAM memory cell according to the first aspect, and the first SRAM memory cell of the first SRAM memory cell. A first bit line for inputting / outputting data to / from the fifth transistor, a first bit bar line for inputting / outputting data to / from the sixth transistor, and a fifth bit of the second SRAM memory cell A second bit line for inputting / outputting data and a second bit bar line for inputting / outputting data to / from the sixth transistor, and constitutes a first bit line and a first bit bar line. The bit line pair, the second bit line, and the bit line pair constituting the second bit bar are preferably mirror-arranged. Since the bit line pairs are mirror-arranged, high-level or low-level data can be written easily and in a short time by controlling the terminals in which the first or second terminals are bundled.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of an SRAM memory cell according to an embodiment of the present invention, and FIG. 2 is a layout diagram thereof.

  As shown in FIGS. 1 and 2, the memory cell 101 includes a first inverter including a first N-type MOS transistor 102 and a second P-type MOS transistor 103, a third N-type MOS transistor 104, and a first N-type MOS transistor 104. A latch circuit is configured by a second inverter composed of four P-type MOS transistors 105, and the sources of the second transistor 103 and the fourth transistor 105 are set to a common high level (power supply wiring 201). Each latch node 110, 111 has fifth and sixth N-type MOS transistors 106, 107 for inputting / outputting data to / from the bit line pair (bit lines 112, 113). The fifth transistor 106 is connected to the output of the first inverter, and the sixth transistor 107 is connected to the output of the second inverter. Reference numeral 114 denotes a word line.

  Here, the source terminals of the first and third N-type MOS transistors 102 and 104 of the two inverter circuits are separated. The sources of the first transistor 102 and the third transistor 104 are connected to the first and second terminals 108 and 109, respectively, and the data held in the latch circuit is controlled by controlling the first or second terminals 108 and 109. Can be set to any state.

  The memory cell configured as described above will be described.

  Assume that the latch node 110 holds High and the latch node 110 holds Low. According to the present embodiment, when low data is input from the first terminal 108 and high data is input from the second terminal 109, the data in the latch can be easily rewritten. Further, as shown in FIG. 2, the layout is the same as that of a normal memory cell, and the practical effect is great without increasing the area.

  In the memory cell 101, the first transistor 102 and the fifth transistor 106 are arranged in the vertical direction, sharing a diffusion layer, and the second transistor 103 has a linear gate wiring with the first transistor 102. The third transistor 104 and the sixth transistor 107 are arranged in the vertical direction while sharing the diffusion layer, and the fourth transistor 105 is linearly arranged. A gate wiring is shared and arranged in parallel beside the third transistor 104, and the third transistor 104 is opposite to the second transistor 103 in which the first transistor 102 is arranged. The fourth transistor 105 is arranged at a point-symmetrical position with respect to the first transistor 102 with A as the origin, and the fourth transistor 105 has a second transistor with the point A as the origin. The sixth transistor 107 is arranged at a point-symmetrical position with respect to the fifth transistor 106 with the point A as the origin, and is shared with the fifth transistor 106 of the first transistor 102. A layout in which the non-diffusion layer is not connected to the diffusion layer that is not shared with the sixth transistor 107 of the third transistor 104 through a diffusion layer or a wiring is preferable.

  A second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a configuration diagram of a memory array configured using SRAM memory cells according to the embodiment of the present invention.

  As shown in FIG. 3, tap cells 301 for fixing the substrate potential are inserted in a 4 × 8 memory array. Further, the wiring 302 is connected to the tap cell 301 and applies a substrate potential, and the wiring 302 is not connected to the first terminal 108 or the second terminal 109. Adjacent memory cells 101 (first and second SRAM memory cells) are mirror-arranged including bit lines. That is, the first bit line and the first bit bar line of the first SRAM memory cell, the second bit line and the second bit bar line of the second SRAM memory cell, A bit line pair constituting the bit line and the first bit bar line, and a bit line pair constituting the second bit line and the second bit bar are mirror-arranged. BL0 to 3 are bit lines, and NBL0 to 3 are bit bar lines. The bit line inputs and outputs data to and from the fifth transistor, and the bit bar line inputs and outputs data to and from the sixth transistor. The first terminal 108 (or the second terminal 109) is shared with the adjacent memory cell 101.

  The memory array configured as described above will be described.

  When high data is input from the first terminal 108 or the second terminal 109, the substrate potential of the N-type MOS transistor must be at a low level. Therefore, it is desirable that the wiring connected to the tap cell 301 be fixed at a low level by the terminal 302 different from the first terminal 108 or the second terminal 109.

  The first and second terminals 108 and 109 are preferably shared with adjacent memory cells in terms of area. At this time, since the bit line pairs are mirror-arranged, by controlling the terminal 303 or 304 in which the first terminal 108 or the second terminal 109 is bundled, the entire High or Low data can be easily and in a short time. The practical effect is great.

  The SRAM memory and the semiconductor memory device according to the present invention have an effect that the retained data can be easily initialized by devising the wiring of the memory cell, and are useful as an SRAM.

1 is a configuration diagram of an SRAM memory cell according to an embodiment of the present invention. FIG. 2 is a layout diagram of FIG. 1. It is a block diagram of the memory array comprised using the SRAM memory cell of embodiment of this invention. It is a block diagram of the SRAM memory cell of a prior art example. FIG. 5 is a layout diagram of FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Memory cell 102 N-type MOS transistor of the inverter constituting the latch 103 P-type MOS transistor of the inverter constituting the latch 104 N-type MOS transistor of the inverter constituting the latch 105 P-type MOS transistor of the inverter constituting the latch 106 Latch data N-type MOS transistor for exchanging data with the bit line 107 N-type MOS transistor for exchanging data with the latch data and bit line 108 terminal 109 terminal 110 latch node 111 latch node 112 bit line 113 bit line 114 word line 201 power supply wiring 301 tap cell 302 power supply line for applying potential to tap cell 303 data line of terminal 108 304 data line of terminal 109 401 memory cell 402 latch N-type MOS transistor of the inverter 403 P-type MOS transistor of the inverter constituting the latch 404 N-type MOS transistor of the inverter constituting the latch 405 P-type MOS transistor of the inverter constituting the latch 406 Latch data and bit line data N-type MOS transistor 407 that exchanges data between the latch data and bit line 408 Power-supply terminal 409 Power-supply terminal 410 Latch node 411 Latch node 412 Bit line 413 Bit line 414 Word line

Claims (4)

A first inverter composed of a first N-type MOS transistor and a second P-type MOS transistor;
A second inverter composed of a third N-type MOS transistor and a fourth P-type MOS transistor;
A fifth transistor connected to the output of the first inverter;
A sixth transistor connected to the output of the second inverter;
The first and second inverters constitute a latch circuit,
The sources of the second transistor and the fourth transistor are connected to a common power line,
The sources of the first transistor and the third transistor are connected to first and second terminals, respectively.
An SRAM memory cell characterized in that data held in the latch circuit can be set to an arbitrary state by controlling the first or second terminal. The first transistor and the fifth transistor are respectively arranged in a vertical direction sharing a diffusion layer;
The second transistor is arranged in parallel beside the first transistor, sharing a linear gate wiring with the first transistor;
The third transistor and the sixth transistor share a diffusion layer and are arranged in the vertical direction,
The fourth transistor is arranged in parallel beside the third transistor, sharing a straight gate wiring;
The third transistor is arranged in a point-symmetrical position with respect to the first transistor with the point A as the origin on the opposite side of the second transistor where the first transistor is arranged,
The fourth transistor is disposed at a point-symmetrical position with respect to the second transistor with the point A as an origin,
The sixth transistor is arranged at a point-symmetrical position with respect to the fifth transistor with the point A as an origin,
The diffusion layer that is not shared with the fifth transistor of the first transistor is not connected to the diffusion layer that is not shared with the sixth transistor of the third transistor through a diffusion layer or a wiring. 2. The SRAM memory cell according to claim 1, which is configured as described above.   2. A semiconductor memory device comprising the SRAM memory cell according to claim 1, wherein said semiconductor memory device has a wiring for applying a substrate potential, and said wiring is not connected to a first terminal or a second terminal. . Adjacent first and second SRAM memory cells configured using the SRAM memory cell of claim 1;
A first bit line for inputting / outputting data to / from a fifth transistor of the first SRAM memory cell and a first bit bar line for inputting / outputting data to / from a sixth transistor;
A second bit line for inputting / outputting data to / from a fifth transistor of the second SRAM memory cell and a second bit bar line for inputting / outputting data to / from the sixth transistor;
The bit line pair constituting the first bit line and the first bit bar line and the bit line pair constituting the second bit line and the second bit bar are mirror-arranged. Semiconductor memory device.

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