JP2006054288A - Semiconductor-device manufacturing method, semiconductor device, bump manufacturing method, and bump transcribing substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor-device manufacturing method, a semiconductor device, a bump manufacturing method, and a bump transcribing substrate wherein the productivity of the semiconductor device can be improved by shortening the necessary time for forming bumps. <P>SOLUTION: In the semiconductor-device manufacturing method, there are opposed to each other a plurality of pads 13a and a plurality of bumps 20. The plurality of pads 13a are formed above a semiconductor substrate 1 and in a single layer. The plurality of bumps 20 are so disposed previously on a bump transcribing substrate 30 as to oppose them respectively to the plurality of pads 13a. By approximating to each other the bump transcribing substrate 30 and the semiconductor substrate 1, the plurality of bumps 20 are pressed on the plurality of pads 13a. By separating from each other the bump transcribing substrate 30 and the semiconductor substrate 1, the plurality of bumps 20 are transcribed on the plurality of pads 13a. The bump transcribing substrate 30 may have a buffer film 31. The adhesiveness of the buffer film 31 to the bumps 20 is preferably made lower than the adhesiveness of the bumps 20 to the pads 13a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing method, a semiconductor device, a bump manufacturing method, and a bump transfer substrate. In particular, the present invention relates to a semiconductor device manufacturing method, a semiconductor device, a bump manufacturing method, and a bump transfer substrate capable of increasing productivity and reducing a defect rate. The present invention also relates to a semiconductor device manufacturing method, a semiconductor device, a bump manufacturing method, and a bump transfer substrate in which bumps are stably bonded to a functional substrate such as COG (Chip On Glass) and COF (Chip On Film). Also relevant.

7A to 7D are cross-sectional views for explaining a conventional method for manufacturing a semiconductor device. This method is a method of directly forming bumps on a pad.
First, as shown in FIG. 7A, an Al alloy wiring 102 and an Al alloy pad 102a are formed on the insulating film 101. Next, a passivation film 103 is formed on the insulating film 101, the Al alloy wiring 102, and the Al alloy pad 102a, and an opening 103a located on the Al alloy pad 102a is formed in the passivation film 103.

  Next, a TiW film 104 as a barrier film is formed on the entire surface including the inside of the opening 103 a, and an Au film 105 as an adhesion metal film is further formed on the TiW film 104. Next, a photoresist film is applied on the Au film 105, this photoresist film is exposed to light, and then developed. As a result, a resist pattern 106 having an opening 106 a is formed on the Au film 105. The opening 106 a is located above the opening 103 a of the passivation film 103. Further, the shape of the opening 106a tends to be inversely tapered due to the nature of the photolithography technique.

  Next, as shown in FIG. 7B, electrolytic plating is performed using the Au film 105 as an electrode. As a result, Au precipitates and grows on the Au film 105 exposed in the opening 106a, and a gold bump 107 is formed. Since the shape of the opening 106a is a reverse taper, the shape of the gold bump 107 is a reverse taper.

Next, as shown in FIG. 7C, after removing the resist pattern 106, etching is performed using the gold bump 107 as a mask. As a result, the exposed portions of the Au film 105 and the TiW film 104 are removed (see Patent Document 1).
JP 2000-188304 A (FIGS. 2 to 7)

The most time-consuming process in forming the bump is a process of depositing metal. In the conventional method described above, bumps are formed by depositing metal directly on the pad. For this reason, it was difficult to separate the process of depositing the bumps and shorten the time required to form the bumps.
In addition, when there is an abnormality in the formed bump, it is difficult to remove the bump from the pad, so that the semiconductor device is a defective product.

  In addition, as described above, when a resist pattern is formed by exposing a photoresist film with light, the opening of the resist pattern tends to have an inversely tapered shape. When the opening has a reverse taper shape, the bump also has a reverse taper shape. In this case, if the bump is bonded to a functional substrate such as COG (Chip On Glass) and COF (Chip On Film), the bonding surface between the functional substrate and the bump becomes larger than the bonding surface between the bump and the pad. Sometimes it was not possible to join.

  The present invention has been made in consideration of the above-described circumstances, and the object thereof is a method for manufacturing a semiconductor device, which can increase productivity by reducing the time required for forming bumps, A semiconductor device, a bump manufacturing method, and a bump transfer substrate are provided. It is another object of the present invention to provide a semiconductor device manufacturing method, a semiconductor device, a bump manufacturing method, and a bump transfer substrate capable of reducing a defect rate. Another object of the present invention is to provide a semiconductor device manufacturing method, a semiconductor device, a bump manufacturing method, and a bump transfer substrate that facilitate bonding of functional substrates such as COG and COF and bumps.

In order to solve the above problems, a semiconductor device manufacturing method according to the present invention includes a plurality of pads formed on the same layer above a semiconductor substrate, and bump transfer so as to have a positional relationship corresponding to each of the plurality of pads. A step of opposing a plurality of bumps formed on the substrate for use;
Bringing the bump transfer substrate and the semiconductor substrate close to each other and pressing the plurality of bumps against the plurality of pads;
Transferring the plurality of bumps onto the plurality of pads by separating the bump transfer substrate and the semiconductor substrate from each other;
It comprises.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductive barrier film on each of a plurality of pads formed above and on the same layer of a semiconductor substrate,
A plurality of bumps formed on a bump transfer substrate so as to have a positional relationship corresponding to each of the plurality of pads, and the plurality of pads facing each other;
Bringing the bump transfer substrate and the semiconductor substrate close to each other and pressing the plurality of bumps against the plurality of barrier films;
Transferring the plurality of bumps onto the plurality of barrier films by separating the bump transfer substrate and the semiconductor substrate from each other;
It comprises.

  According to these methods for manufacturing a semiconductor device, bumps can be formed on the bump transfer substrate in parallel with or prior to the step of forming pads on the semiconductor substrate. For this reason, it is possible to shorten the time required to form the bumps on the pads and increase the productivity of the semiconductor device.

  Each of the plurality of bumps has a reverse taper shape on the bump transfer substrate, and after being transferred onto each of the plurality of pads or each of the barrier films, a forward taper shape is formed on the pads or the barrier films. You may make it become. In this case, when the bump is bonded to a functional substrate such as COG and COF, the bonding surface between the functional substrate and the bump is smaller than the bonding surface between the bump and the pad or the barrier film. Therefore, the bump can be stably bonded to the functional substrate.

  A buffer film positioned between the plurality of bumps and the bump transfer substrate of the bump transfer substrate may be provided. The buffer film preferably has lower adhesion to the bump than adhesion between the bump and the pad, or adhesion between the bump and the barrier film. In this case, since the bumps and the bump transfer substrate are easily peeled off, the bumps are easily transferred from the bump transfer substrate onto the pad. When the bump is a gold bump and the pad is made of an Al alloy, the buffer film is an indium oxide film, for example.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of bumps on a bump transfer substrate so as to have a positional relationship corresponding to a plurality of pads formed above the semiconductor substrate.
Inspecting the plurality of bumps, and rejecting the bump transfer substrate having the abnormal bumps;
Bringing the bump transfer substrate and the semiconductor substrate that have passed the inspection closer together, and pressing the plurality of bumps against the plurality of pads;
Transferring the plurality of bumps onto the plurality of pads by separating the bump transfer substrate and the semiconductor substrate from each other;
It comprises.

  According to this method of manufacturing a semiconductor device, when the bump does not meet the standard, the bump transfer substrate having the bump can be removed from the process before the bump is transferred onto the pad. Therefore, the defect rate of the semiconductor device can be reduced.

  In the step of pressing the plurality of bumps against the plurality of pads or barrier films, it is preferable to heat at least one of the plurality of pads or barrier films and the plurality of bumps. In this case, since the bump and the pad or the bump and the barrier film are easily alloyed, the transfer from the bump transfer substrate onto the pad is facilitated.

A semiconductor device according to the present invention includes a pad provided above a semiconductor substrate;
And a bump provided on the pad and having a forward tapered shape.
According to this semiconductor device, the step of pressing and bonding the bump to a functional substrate such as COG or COF can be stably performed.

Another semiconductor device according to the present invention is provided above a semiconductor substrate, a plurality of pads located in the same layer,
A plurality of bumps provided on each of the plurality of pads;
The plurality of bumps are previously formed on a bump transfer substrate and then transferred onto each of the plurality of pads.

The bump manufacturing method according to the present invention includes a step of forming a conductive film on a bump forming substrate,
Forming an insulating mask film on the conductive film;
Forming a plurality of openings in the mask film having the same positional relationship as a plurality of pads formed above the semiconductor substrate;
Forming a bump in each of the plurality of openings by performing electroplating using the conductive film as an electrode;
It comprises.

Another bump manufacturing method according to the present invention includes a step of forming an insulating mask film on a bump forming substrate having at least a surface layer having conductivity,
Forming a plurality of openings in the mask film having the same positional relationship as a plurality of pads formed above the semiconductor substrate;
Forming a bump in each of the plurality of openings on the bump forming substrate by performing electroplating using the surface layer as an electrode; and
It comprises.

Another bump manufacturing method according to the present invention includes a step of forming a mask film on a bump forming substrate,
Forming a plurality of openings in the mask film having the same positional relationship as a plurality of pads formed above the semiconductor substrate;
Forming a bump in each of the plurality of openings by plating using the mask film as a mask;
It comprises.

  In the bump manufacturing method described above, when the mask film is a photoresist film, the step of forming the plurality of openings in the mask film may be a process of exposing the photoresist film with light and then developing it. .

  In the step of forming the mask film, the side surface of the opening is preferably reverse tapered. In this way, a reverse taper-shaped bump is formed. When the bump is transferred onto the pad of the semiconductor device, it becomes a forward tapered shape. For this reason, the process of pressing and bonding the bump on the semiconductor device to the functional substrate can be performed stably.

  Further, when the mask film is a photoresist film, the step of forming the plurality of openings in the mask film may be a process of exposing the photoresist film with an electron beam and then developing.

The bump transfer substrate according to the present invention includes a substrate,
A plurality of bumps formed on the substrate;
The plurality of bumps are arranged in advance at positions corresponding to the plurality of pads to which the plurality of bumps are to be transferred.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1, 2, and 3 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. In the present embodiment, a plurality of gold bumps are formed in advance on a glass substrate, and the glass substrate is pressed against a silicon substrate on which a semiconductor device is formed, whereby the plurality of gold bumps on the glass substrate are converted into a semiconductor. Transfer is performed collectively on a plurality of pads of the apparatus.

  First, as shown in FIG. 1A, an element isolation film 2 is formed on a silicon substrate 1. The element isolation film 2 may be formed by the LOCOS method as shown in this figure, but may be embedded in the silicon substrate 1 by the STI (Shallow Trench Isolation) method. Next, the silicon substrate 1 is thermally oxidized. Thereby, a gate oxide film 3 is formed on the surface of the silicon substrate 1 located between the element isolation films 2. Next, a polysilicon film is formed on the entire surface including the gate oxide film 3, and this polysilicon film is patterned. Thereby, a gate electrode 4 is formed on the gate oxide film 3.

Next, impurity ions are implanted into the silicon substrate 1 using the gate electrode 4 and the element isolation film 2 as a mask. Thereby, low concentration impurity regions 6a and 6b are formed in the silicon substrate 1 positioned between the element isolation films 2. Next, a silicon oxide film is formed on the entire surface including on the gate electrode 4, and this silicon oxide film is etched back. Thereby, a sidewall 5 is formed on the sidewall of the gate electrode 4. Next, impurity ions are implanted into the silicon substrate 1 using the gate electrode 4, the sidewall 5 and the element isolation film 2 as a mask. As a result, impurity regions 7 a and 7 b serving as a source and a drain are formed in the silicon substrate 1 positioned between the element isolation films 2.
In this way, a transistor is formed on the silicon substrate 1. Note that although only one transistor is illustrated in FIG. 1A, a plurality of transistors are actually formed.

  Next, a first interlayer insulating film 8 containing silicon oxide as a main component is formed on the entire surface including the top of the transistor by a CVD method. Next, a photoresist film (not shown) is applied on the first interlayer insulating film 8, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the first interlayer insulating film 8. Next, the first interlayer insulating film 8 is etched using this resist pattern as a mask. Thus, a contact hole 8a located on the gate electrode 4 and contact holes (not shown) located on the impurity regions 7a and 7b are formed in the first interlayer insulating film 8. Note that only one contact hole 8a is illustrated in FIG. 1A, but in reality, the contact hole 8a is formed over each of the gate electrodes 4 included in the plurality of transistors. At this time, contact holes (not shown) are also formed on the impurity regions 7a and 7b. Thereafter, the resist pattern is removed.

  Next, after a TiN film (not shown) serving as a barrier film is formed by sputtering in each contact hole and on the first interlayer insulating film 8, a tungsten (W) film is formed by CVD. Next, the tungsten film and the TiN film located on the first interlayer insulating film 8 are removed by CMP polishing or etch back. Thereby, the W plug 9 is buried in the contact hole 8a. Also, W plugs (not shown) are buried in the contact holes on the impurity regions 7a and 7b. Although only one W plug 9 is shown in FIG. 1A, in reality, the W plug 9 is formed on each of the gate electrodes 4 included in a plurality of transistors.

  Next, an Al alloy film is formed on the first interlayer insulating film 8 by a sputtering method. Next, a photoresist film (not shown) is applied on the Al alloy film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. Thereby, an Al alloy wiring 10 connected to the W plug 9 is formed on the first interlayer insulating film 8. At this time, Al alloy wirings (not shown) are also formed on the first interlayer insulating film 8, and these Al alloy wirings are connected to the impurity regions 7a and 7b through W plugs. Although only one Al alloy wiring 10 is shown in FIG. 1A, in reality, an Al alloy wiring 10 is formed for each of the plurality of W plugs 9. Thereafter, the resist pattern is removed.

  Next, a second interlayer insulating film 11 mainly composed of silicon oxide is formed on the first interlayer insulating film 8 and the Al alloy wiring by a CVD method. Next, a photoresist film (not shown) is applied on the second interlayer insulating film 11, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the second interlayer insulating film 11. Next, the second interlayer insulating film 11 is etched using this resist pattern as a mask. As a result, a via hole 11 a located on the Al alloy wiring 10 is formed in the second interlayer insulating film 11. At this time, a via hole (not shown) is also formed on an Al alloy wiring (not shown). Although only one via hole 11a is shown in FIG. 1A, actually, the via hole 11a is formed on each of the plurality of Al alloy wirings 10. Thereafter, the resist pattern is removed.

  Next, after a TiN film (not shown) serving as a barrier film is formed by sputtering in each of the via holes and on the second interlayer insulating film 11, a tungsten (W) film is formed by CVD. Next, the tungsten film and the TiN film located on the second interlayer insulating film 11 are removed by CMP polishing or etch back. As a result, the W plug 12 is buried in the via hole 11a. A W plug (not shown) is also embedded in a via hole (not shown). Although only one W plug 12 is shown in FIG. 1A, actually, the W plug 12 is buried in each of the plurality of via holes 11a.

  Next, an Al alloy film is formed on the second interlayer insulating film 11 by a sputtering method. Next, a photoresist film (not shown) is applied on the Al alloy film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. As a result, on the second interlayer insulating film 11, an Al alloy wiring 13 connected to each of the plurality of W plugs 12 and an Al alloy pad 13 a located at each end of the Al alloy wiring 13 are formed. At this time, an Al alloy wiring (not shown) and an Al alloy pad (not shown) connected to a W plug (not shown) are also formed at the same time. Thereafter, the resist pattern is removed.

  Next, a passivation film 14 made of a silicon nitride film is formed on the entire surface including the plurality of Al alloy wirings 13 and the Al alloy pads 13a. Next, a photoresist film (not shown) is applied on the passivation film 14, and this photoresist film is exposed using a reticle (not shown) and then developed. Thereby, a resist pattern is formed on the passivation film 14. Next, the passivation film 14 is etched using this resist pattern as a mask. Thereby, in the passivation film 14, the opening part 14a located on each of several Al alloy pad 13a is formed. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 1B, a barrier film 15 is formed on the entire surface including the Al alloy pad 13a and the passivation film 14 exposed in the opening 14a. The barrier film 15 is a laminated film in which a Pt film and a Ti film are laminated in this order, or a TiW film. Next, a photoresist film is applied on the barrier film 15, and the photoresist film is exposed and developed. As a result, a resist pattern is formed on the barrier film 15. Next, the barrier film 15 is etched using this resist pattern as a mask. Thereby, the barrier film 15 is removed except in and around the opening 14a.
In this way, a semiconductor device is formed on the silicon substrate 1.

A plurality of gold bumps are formed on the glass substrate (bump transfer substrate, bump forming substrate) in accordance with the following steps in parallel or in advance of the above-described manufacturing of the semiconductor device.
First, as shown in FIG. 2A, a conductive film 31 is formed over a glass substrate 30 by, for example, a sputtering method. The conductive film 31 is preferably made of a material that is less likely to adhere to gold than Al or a material that is less likely to be alloyed with gold, such as an indium oxide film, W, or Ag.

  Next, a resist film is applied on the conductive film 31. The thickness of the resist film is, for example, 20 μm or more and 30 μm or less. Next, the resist film is exposed using, for example, an electron beam and then developed. Thereby, a resist pattern 50 is formed on the conductive film 31. The resist pattern 50 has a plurality of openings 50a. The arrangement pattern of the openings 50a is the arrangement pattern of the openings 14a (shown in FIG. 1) of the passivation film 14 (shown in FIG. 1), that is, an Al alloy pad. This is the same as the arrangement pattern 13a (shown in FIG. 1). The size of the opening 50a is slightly larger than the size of the opening 14a. Further, the sidewall of the opening 50 a is substantially perpendicular to the conductive film 31.

  Next, as shown in FIG. 2B, gold is electroplated using the conductive film 31 as an electrode. Thereby, gold is deposited and grows on the conductive film 31 exposed in the opening 50a, and the gold bump 20 is formed. The height of the gold bump is, for example, 20 μm or more and 30 μm or less. Since the side wall of the opening 50 a is substantially vertical, the side wall of the gold bump 20 is also substantially perpendicular to the bottom surface of the gold bump 20.

  Next, as shown in FIG. 2C, the resist pattern 50 is removed. In this way, a plurality of gold bumps 20 are formed on the glass substrate 30. The arrangement pattern of the gold bumps 20 is the arrangement pattern of the openings 14a of the passivation film 14, that is, the arrangement pattern of the Al alloy pads 13a. Is the same. The horizontal cross-sectional area of the gold bump 20 is slightly larger than the horizontal cross-sectional area of the opening 14a.

Next, the outer shape inspection of the gold bump 20 is performed. For example, the external inspection is performed by picking up a plurality of gold bumps 20 as samples. When the external shape of any of the gold bumps 20 does not satisfy the standard, the glass substrate 30 is determined to be unacceptable and is removed from the production line. Then, the gold bumps 20 are removed from the glass substrate 30, a resist pattern 50 is formed on the conductive film 31 again, and the gold bumps 20 are recreated.
When the shape of all the sampled gold bumps 20 satisfies the standard, it is determined that the glass substrate 30 is acceptable.

  When the semiconductor device is formed on the silicon substrate 1 according to the process shown in each drawing of FIG. 1, and when the plurality of gold bumps 20 are formed on the glass substrate 30 according to the process shown in each drawing of FIG. The processing shown in each diagram of FIG. 3 is performed.

  First, as shown in FIG. 3A, the silicon substrate 1 is placed on the heating stage 60. Further, the glass substrate 30 that has passed the inspection is fixed on a stage 62 with a heating mechanism. At least one of the heating stage 60 and the stage 62 can be moved in the horizontal plane and in the vertical direction. First, each of the plurality of gold bumps 20 on the glass substrate 30 is moved by moving one of the stages in the horizontal plane. The plurality of Al alloy pads 13a located above the silicon substrate 1 are opposed to each other.

  Next, as shown in FIG. 3B, the stage 62 is directed toward the silicon substrate 1 while heating the silicon substrate 1 and the Al alloy pad 13 a thereabove, and the glass substrate 30 and the gold bumps 20 thereon. Move. It is preferable that the heating temperature of each of the silicon substrate 1 and the glass substrate 30 is 200 ° C. or more and 450 ° C. or less. Thereby, each of the plurality of gold bumps 20 is embedded in the opening 14a and is formed on the Al alloy pad 13a. It is pressed by the barrier film 15 located. Since the horizontal cross-sectional area of the gold bump 20 is slightly larger than the horizontal cross-sectional area of the opening 14a, the gold bump 20 is densely embedded in the opening 14a.

  Since the silicon substrate 1 is heated, a portion of the gold bump 20 that is pressed against the barrier film 15 is alloyed with the barrier film 15. The amount of alloying is preferably set to a minimum amount necessary for the gold bump 20 to be stably fixed on the barrier film 15. Further, since the glass substrate 30 is also heated, the gold bump 20 and the conductive film 31 are easily peeled off.

  Next, as shown in FIG. 3C, the stage 62 is moved in a direction away from the silicon substrate 1. As a result, the plurality of gold bumps 20 are peeled off from the conductive film 31 and transferred from the glass substrate 30 onto each of the Al alloy pads 13a. At this time, the upper surface of the gold bump 20 has high flatness. Note that the gold bumps 20 are formed on the glass substrate 30 and the conductive film 31 after the transfer by performing the process described with reference to FIG. 2 again.

As described above, according to the first embodiment, a plurality of gold bumps 20 are formed on the glass substrate 30 in parallel with or prior to the formation of the semiconductor device on the silicon substrate 1 and the same as the Al alloy pad 13a of the semiconductor device. It is formed in a positional relationship. Then, the plurality of gold bumps 20 on the glass substrate 30 are pressed toward the Al alloy pad 13a of the semiconductor device, and then the glass substrate 30 is separated from the semiconductor device, whereby the gold bump 20 is placed on the Al alloy pad 13a. Transcription. In this way, in the step of forming the gold bump 20 on the Al alloy pad 13a, the step of depositing and growing the gold bump 20 is separated. In addition, since a plurality of gold bumps are transferred together, the time required for transfer is short. Further, it is not necessary to move the silicon substrate 1 out of the clean room at the time of bump formation.
Therefore, the time required to form the gold bump 20 on the Al alloy pad 13a can be shortened, and the productivity of the semiconductor device can be increased.

  Further, when the gold bump 20 formed on the glass substrate 30 does not satisfy the standard, the glass substrate 30 having the gold bump 20 is removed from the process before the gold bump 20 is transferred onto the Al alloy pad 13a. be able to. Therefore, the defect rate of the semiconductor device can be reduced. Further, the glass substrate 30 and the conductive film 31 can be reused, and the glass substrate 30 and the conductive film 31 can be shared regardless of the type of semiconductor device to be manufactured. Therefore, the manufacturing cost of the gold bump 20 can be suppressed.

  In this embodiment, the barrier film 15 is formed on the Al alloy pad 13a and the gold bump 20 is transferred thereon. However, when the operating temperature of the semiconductor device is low, the barrier film 15 is formed on the Al alloy pad 13a. It may not be formed. In this case, the gold bump 20 is directly bonded to the Al alloy pad 13a at the time of transfer. For this reason, even if the heating temperature of the silicon substrate 1 and the glass substrate 30 is lowered from the above-described range (for example, 200 ° C. or more and 450 ° C. or less), the bonding surface between the gold bump 20 and the Al alloy pad 13a is alloyed.

  4, 5, and 6 are cross-sectional views for explaining a semiconductor device manufacturing method according to the second embodiment of the present invention. In the present embodiment, the method for forming the opening 50a of the resist pattern 50 on the glass substrate 30 is different from that in the first embodiment, and as a result, the shape of the gold bump 20 is different from that in the first embodiment. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 4A, a conductive film 31 is formed on a glass substrate 30, and a photoresist film is further applied thereon. Next, the photoresist film is exposed to light and then developed. Thereby, a resist pattern 50 having a plurality of openings 50 a is formed on the conductive film 31. At this time, by adjusting the exposure and development conditions or selecting the type of the photoresist film, the opening 50a has an inversely tapered shape. The arrangement pattern of the openings 50a is the same as the arrangement pattern of the openings 14a included in the passivation film 14, that is, the arrangement pattern of the Al alloy pads 13a.

  For the exposure when the resist pattern 50 is formed, the reticle used when exposing the passivation film 14 can be used. In this way, the number of reticles can be reduced. Note that the size of the upper surface of the opening 50a is slightly larger than that of the opening 14a, but this can be realized by adjusting, for example, conditions for exposure.

  Further, a reticle dedicated to this process may be used for exposure when forming the resist pattern 50. In this case, the entire surface of the photoresist film may be exposed at once using a single reticle, or the entire surface of the photoresist film may be exposed by performing multiple exposures using the same reticle while shifting the exposure area. You may expose.

  Next, as shown in FIG. 4B, gold is electroplated using the conductive film 31 as an electrode. Thereby, the gold bump 20 is formed in the opening 50a. In addition, since the opening part 50a is reverse taper shape, the gold bump 20 also becomes reverse taper shape.

Next, as shown in FIG. 4C, the resist pattern 50 is removed. In this way, a plurality of gold bumps 20 are formed on the glass substrate 30. The arrangement pattern of the gold bumps 20 is the arrangement pattern of the openings 14a of the passivation film 14 as in the first embodiment. That is, it is the same as the arrangement pattern of the Al alloy pad 13a. Further, the area of the upper surface of the gold bump 20 is slightly larger than the horizontal sectional area of the opening 14a.
Next, the gold bump 20 is inspected as in the first embodiment.

  Further, in parallel with the process shown in FIG. 4, the semiconductor device is formed on the silicon substrate 1 by performing the process shown in each drawing of FIG. 1 in the first embodiment. Then, the processing shown in each drawing of FIG. 5 is performed.

  First, as shown in FIG. 5A, the silicon substrate 1 is placed on the heating stage 60, and the glass substrate 30 is fixed on the stage 62. Next, each of the plurality of gold bumps 20 formed on the glass substrate 30 is opposed to the plurality of Al alloy pads 13 a formed above the silicon substrate 1.

  Next, although not shown, the stage 62 is moved toward the silicon substrate 1 while heating the silicon substrate 1 and the glass substrate 30 respectively. Thereby, each of the plurality of gold bumps 20 is pressed against the barrier film 15 located on the Al alloy pad 13 a and alloyed with the barrier film 15. Further, since the glass substrate 30 is also heated, the gold bump 20 and the conductive film 31 are easily peeled off.

  Next, as shown in FIG. 5B, the stage 62 is moved away from the silicon substrate 1. Thereby, the plurality of gold bumps 20 on the glass substrate 30 are transferred onto each of the Al alloy pads 13a. The plurality of gold bumps 20 have a forward tapered shape.

  Next, as shown in FIG. 6, the upper surface of the gold bump 20 is bonded to the wiring 41 on the functional substrate 40 such as COG and COF. At this time, the bonding surface between the wiring 41 and the gold bump 20 is smaller than the bonding surface between the gold bump 20 and the barrier film 15. Therefore, the gold bump 20 can be stably bonded to the functional substrate 40.

  As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. Further, when the gold bump 20 is formed on the glass substrate 30, the gold bump 20 can be easily formed into a reverse taper shape. Therefore, the gold bump 20 after being transferred onto the Al alloy pad 13 a is forward tapered. It can be shaped. Therefore, the gold bump 20 can be stably bonded to the functional substrate 40.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, when the gold bump 20 is transferred from the glass substrate 320 to the Al alloy pad 13a, ultrasonic waves may be additionally applied to the bonding surface between the gold bump 20 and the barrier film 15 (or the Al alloy pad 13a). . In this case, the gold bump 20 and the Al alloy pad 13a are easily alloyed, and the heating temperature can be lowered.

  Further, a substrate made of a conductive material may be used as a substrate for forming the gold bump. In this case, the material of the substrate is preferably a material that is difficult to alloy with gold. The material of the bump may be other than gold (for example, solder). Moreover, in the said embodiment, although the gold bump was formed by electrolytic plating, you may form a gold bump by electroless plating.

(A) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment, (B) is sectional drawing for demonstrating the next process of (A). (A) is sectional drawing for demonstrating the method to form the gold bump for transcription | transfer, (B) is sectional drawing for demonstrating the next process of (A), (C) is following (B). Sectional drawing for demonstrating this process. 2A is a cross-sectional view for explaining a method of transferring the gold bump shown in FIG. 2 to the semiconductor device shown in FIG. 1, and FIG. 2B is a cross-sectional view for explaining the next step of FIG. (C) is sectional drawing for demonstrating the next process of (B). (A) is sectional drawing for demonstrating the method to form the gold bump for transfer which concerns on 2nd Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C ) Is a cross-sectional view for explaining the next step of (B). 4A is a cross-sectional view for explaining a method of transferring the gold bump shown in FIG. 4 to the semiconductor device shown in FIG. 1, and FIG. 4B is a cross-sectional view for explaining the next step of FIG. . Sectional drawing for demonstrating the next process of FIG. 5 (B). (A) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device, (B) is sectional drawing for demonstrating the next process of (A).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation film, 3 ... Gate oxide film, 4 ... Gate electrode, 5 ... Side wall, 6a, 6b ... Low concentration impurity region, 7a, 7b ... Impurity region, 8 ... 1st interlayer insulation Film, 8a ... Contact hole, 9, 12 ... W plug, 10, 13, 102 ... Al alloy wiring, 11 ... Second interlayer insulating film, 11a ... Via hole, 13a, 102a ... Al alloy pad, 14, 103 ... Passivation Films, 14a, 50a, 103a, 106a ... openings, 15 ... barrier films, 20, 107 ... gold bumps, 30 ... glass substrates, 31 ... conductive films, 40 ... functional substrates, 50, 106 ... resist patterns, 60 ... heating Stage 62 ... Stage 101 ... Insulating film 102 ... Al alloy wiring 104 ... TiW film 105 ... Au film

Claims (16)

A step of opposing a plurality of pads formed on the same layer above the semiconductor substrate and a plurality of bumps formed on the bump transfer substrate so as to have a positional relationship corresponding to each of the plurality of pads;
Bringing the bump transfer substrate and the semiconductor substrate close to each other and pressing the plurality of bumps against the plurality of pads;
Transferring the plurality of bumps onto the plurality of pads by separating the bump transfer substrate and the semiconductor substrate from each other;
A method for manufacturing a semiconductor device comprising: Forming a conductive barrier film on each of a plurality of pads formed on the same layer above the semiconductor substrate;
A plurality of bumps formed on a bump transfer substrate so as to have a positional relationship corresponding to each of the plurality of pads, and the plurality of pads facing each other;
Bringing the bump transfer substrate and the semiconductor substrate close to each other and pressing the plurality of bumps against the plurality of barrier films;
Transferring the plurality of bumps onto the plurality of barrier films by separating the bump transfer substrate and the semiconductor substrate from each other;
A method for manufacturing a semiconductor device comprising: Each of the plurality of bumps is
3. A reverse taper shape on the bump transfer substrate, and a forward taper shape on the pad or barrier film after being transferred onto each of the plurality of pads or the barrier film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The bump transfer substrate has a buffer film positioned between the bumps and the bump transfer substrate,
4. The buffer film according to claim 1, wherein an adhesiveness between the buffer film and the bump is lower than an adhesiveness between the bump and the pad or an adhesiveness between the bump and the barrier film. Semiconductor device manufacturing method. The bump is a gold bump,
The pad is made of an Al alloy,
The method of manufacturing a semiconductor device according to claim 4, wherein the buffer film is an indium oxide film. Forming a plurality of bumps on the bump transfer substrate so as to have a positional relationship corresponding to the plurality of pads formed above the semiconductor substrate;
Inspecting the plurality of bumps, and rejecting the bump transfer substrate having the abnormal bumps;
Bringing the bump transfer substrate and the semiconductor substrate that have passed the inspection closer together, and pressing the plurality of bumps against the plurality of pads;
Transferring the plurality of bumps onto the plurality of pads by separating the bump transfer substrate and the semiconductor substrate from each other;
A method for manufacturing a semiconductor device comprising:   The step of pressing the plurality of bumps against the plurality of pads or barrier films heats at least one of the plurality of pads or barrier films and the plurality of bumps. A method for manufacturing a semiconductor device. A pad provided above the semiconductor substrate;
A semiconductor device comprising a bump provided on the pad and having a forward taper shape. A plurality of pads provided above the semiconductor substrate and positioned in the same layer;
A plurality of bumps provided on each of the plurality of pads;
And the plurality of bumps are previously formed on a bump transfer substrate and then transferred onto each of the plurality of pads. Forming a conductive film on the bump forming substrate;
Forming an insulating mask film on the conductive film;
Forming a plurality of openings in the mask film having the same positional relationship as a plurality of pads formed above the semiconductor substrate;
Forming a bump in each of the plurality of openings by performing electroplating using the conductive film as an electrode;
A bump manufacturing method comprising: Forming an insulating mask film on a bump forming substrate having at least a conductive surface layer; and
Forming a plurality of openings in the mask film having the same positional relationship as a plurality of pads formed above the semiconductor substrate;
Forming a bump in each of the plurality of openings on the bump forming substrate by performing electroplating using the surface layer as an electrode; and
A bump manufacturing method comprising: Forming a mask film on the bump forming substrate;
Forming a plurality of openings in the mask film having the same positional relationship as a plurality of pads formed above the semiconductor substrate;
Forming a bump in each of the plurality of openings by plating using the mask film as a mask;
A bump manufacturing method comprising: The mask film is a photoresist film,
The bump manufacturing method according to any one of claims 10 to 12, wherein the step of forming the plurality of openings in the mask film is a step of exposing the photoresist film with light and then developing the photoresist film.   14. The bump manufacturing method according to claim 10, wherein, in the step of forming the plurality of openings in the mask film, a side surface of the opening is inversely tapered. The mask film is a resist film,
The bump manufacturing method according to claim 10, wherein the step of forming the plurality of openings in the mask film is a step of exposing the resist film with an electron beam and then developing the resist film. A substrate,
A plurality of bumps formed on the substrate;
The bump transfer substrate, wherein the plurality of bumps are arranged in advance at positions corresponding to a plurality of pads to which the plurality of bumps are to be transferred.

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