JP2006054231A - Manufacturing method of substrate for group 3 nitride semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent stress caused by a difference in a thermal coefficient of expansion in each layer inside a substrate for a semiconductor element in an operating temperature of the semiconductor element. <P>SOLUTION: An assist layer 2 made of a silicon single crystal that is a material having a thermal coefficient of expansion K2 that is smaller than that K4 of a group 3 nitride semiconductor is formed at least at one of main surfaces 1A, 1B of a sapphire original substrate 1 in a temperature within the allowable operating temperature range of a semiconductor element, and thus a substrate having the assist layer is manufactured. Then a compound semiconductor layer 4 that is at least one group 3 nitride semiconductor layer is grown on the main surface of the sapphire original substrate 1 or on the surface of the assist layer, thus manufacturing the substrate for a group 3 nitride semiconductor element. Since the substrate having the assist layer and the compound semiconductor layer 4 have the same thermal coefficient of expansion, no stress caused by the difference in the thermal coefficient of expansion is generated between both of them. No stress caused by the difference in the thermal coefficient of expansion is generated also between the sapphire original substrate 1 and the assist layer 2 since the assist layer 2 is formed at room temperature. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a substrate for a group III nitride semiconductor device suitable for use in manufacturing a blue / ultraviolet light emitting / receiving device or the like.

  A semiconductor element including a group III nitride semiconductor typified by GaN has a large band gap of about 3.4 eV at room temperature and is chemically stable. Therefore, it is applied to blue and ultraviolet light receiving and emitting devices. Yes.

A semiconductor device substrate for manufacturing a semiconductor device including a Group 3 nitride semiconductor is manufactured by epitaxially growing a Group 3 nitride semiconductor layer on an original substrate by MOCVD or MBE. The original substrate is desirably a single crystal plate of a group 3 nitride semiconductor, but it is difficult to manufacture a single crystal plate of a group 3 nitride semiconductor. An original substrate made of a single crystal of α-Al ₂ O ₃ is used instead of a single crystal plate of a group 3 nitride semiconductor.

  However, it is known that when a semiconductor element substrate is manufactured by epitaxially growing a group III nitride semiconductor such as GaN on an original substrate made of sapphire, the obtained semiconductor element substrate is warped. This is because the thermal expansion coefficient of sapphire is larger than the thermal expansion coefficient of the group 3 nitride semiconductor, so that, for example, the group 3 nitride semiconductor layer is grown on the sapphire base substrate at a high temperature of about 1000 ° C. This is because the sapphire base substrate contracts more than the group 3 nitride semiconductor when cooled.

  In order to solve the warp problem described above, Al is first deposited as an adhesive layer on both surfaces of the original sapphire substrate, and a thin plate of Si single crystal is laminated on each surface of the deposited Al adhesive layer under heating at 800 ° C. A method of manufacturing a semiconductor device substrate by growing a compound semiconductor layer such as GaN on the Si single crystal plate is proposed (for example, see Patent Document 1).

  The reason why a substrate with less warpage can be obtained by manufacturing the substrate in this manner is based on the following principle. Since the thermal expansion coefficient of Si single crystal is smaller than that of Group III nitride semiconductors such as GaN, the composite original substrate formed by combining sapphire and two Si single crystal plates has a thermal expansion coefficient of sapphire as a whole. It behaves as a substrate having a thermal expansion coefficient intermediate between that of Si and the single crystal of Si. On the other hand, since the thermal expansion coefficient of the group 3 compound semiconductor has an intermediate thermal expansion coefficient between sapphire and Si single crystal, the difference in thermal expansion coefficient between the group 3 compound semiconductor and the composite base substrate is small. Become. Moreover, by making the thicknesses of the two Si single crystal plates the same, the stress applied to the sapphire base substrate is caused by the difference in thermal expansion coefficient between the Si single crystal and sapphire, and the stress applied to the pair of surfaces of the sapphire base substrate And the warpage of the composite original substrate itself can be reduced.

Further details can be explained as follows. The thermal expansion coefficient of sapphire is α ₁ , the thermal expansion coefficient of Si single crystal is α ₂ , the thermal expansion coefficient of composite substrate is α ₃ , the elastic modulus of sapphire is E ₁ , the elastic modulus of Si single crystal is E ₂ , and sapphire The thickness of the original substrate is t ₁ , and the total thickness of the two Si single crystal plates is t _{2. For} simplicity, the shape of the plate in which sapphire and two Si single crystal plates are combined is rectangular. Suppose that the width is d and the length is L. The stress applied in the length direction of the sapphire base substrate at a temperature different from the temperature at which the sapphire base substrate and the Si single crystal plate are bonded by T ° C. is a unit length with a length change of L (α ₃ −α ₁ ) T. Since the stress per strike is the product E ₁ dt ₁ of the elastic modulus and the cross-sectional area (ignoring minute changes in d), it becomes L (α ₃ −α ₁ ) TE ₁ dt ₁ . On the other hand, the stress applied to the two Si single crystal plates is similarly L (α ₂ −α ₃ ) TE ₂ dt ₂ . Since these two stresses are equal, the following equation (1) is established.
L (α ₃ −α ₁ ) TE ₁ dt ₁ = L (α ₂ −α ₃ ) TE ₂ dt ₂ (1)
Here, by dividing both sides by LTd, (α ₃ −α ₁ ) E ₁ t ₁ = (α ₂ −α ₃ ) E ₂ t ₂ (2)
And obtaining α ₃ ,
α ₃ = (α ₁ E ₁ t ₁ + α ₂ E ₂ t ₂ ) / (E ₁ t ₁ + E ₂ t ₂ ) (3)
It becomes.

When the material is fixed to sapphire and Si single crystal, for example, when t ₁ is increased and t ₂ is decreased, α ₃ approaches α _1, and when t ₁ is decreased and t ₂ is increased, α ₃ approaches α ₂ . Therefore, by adjusting t ₁ and t ₂ , the thermal expansion coefficient α ₃ of the composite base substrate can be matched with the thermal expansion coefficient of the group III compound semiconductor such as GaN between α ₁ and α _2. . By combining the thermal expansion coefficients in this manner, a semiconductor element substrate in which warpage due to the difference in thermal expansion between the sapphire base substrate and the group 3 compound semiconductor hardly occurs can be obtained.
JP 2002-124473 A

  If the group 3 compound semiconductor device substrate is manufactured using the composite base substrate in the prior art described above, the warp of the semiconductor device substrate can be greatly reduced as compared with the case where the sapphire base substrate is used. However, since the conventional composite original substrate is produced by bonding a sapphire base substrate and a Si single crystal plate under heating at 600 ° C., a semiconductor element using a substrate for a semiconductor element using this composite original substrate When this is manufactured, the following problems occur. That is, in the temperature range of −20 to 120 ° C. in which a semiconductor element is normally used, the inside of the substrate, which is a constituent element of the semiconductor element, is in a temperature state sufficiently lower than 600 ° C. Therefore, sapphire and Si single crystal Stress caused by the difference in thermal expansion between the substrate and the inside of the substrate is applied. As a result, there has been a problem that the semiconductor element is rapidly deteriorated with time, and defective products are easily generated due to internal cracks in the semiconductor element.

  An object of the present invention is to provide a method for manufacturing a substrate for a group III nitride semiconductor device that can solve the above-described problems in the prior art.

  An object of the present invention is to provide a method for manufacturing a substrate for a group III nitride semiconductor device that can solve the problem of warpage in the substrate.

  An object of the present invention is to provide a method for manufacturing a group III nitride semiconductor device substrate capable of obtaining a semiconductor device substrate with a low stress applied to the inside of the substrate within an allowable operating temperature range of the semiconductor device.

  In order to solve the above-mentioned problems, the present inventors diligently studied a manufacturing method for obtaining a compound semiconductor element substrate having a low internal stress. As a result, an auxiliary layer made of a material having a thermal expansion coefficient smaller than that of the group 3 nitride semiconductor is formed on at least one main surface of the sapphire base substrate at a temperature within the allowable operating temperature range of the semiconductor element. Thus, when a group III nitride semiconductor layer is grown on the main surface of the sapphire base substrate or the surface of the auxiliary layer to form a semiconductor device substrate after the formation, the semiconductor device substrate has less warpage and the semiconductor It has been found that the stress applied to the inside of the substrate during use of the element can be kept small, and has led to the present invention.

  According to invention of Claim 1, in the manufacturing method of the board | substrate for group 3 nitride semiconductor elements used in order to manufacture a semiconductor element, the thermal expansion coefficient of the group 3 nitride semiconductor is provided on at least one main surface of the sapphire base substrate. After forming an auxiliary layer made of a material having a smaller coefficient of thermal expansion at a temperature within the allowable operating temperature range of the semiconductor element, at least one group III nitride is formed on the main surface of the sapphire base substrate or the surface of the auxiliary layer. A method for manufacturing a substrate for a group III nitride semiconductor device is proposed, characterized in that an oxide semiconductor layer is grown.

  According to the second aspect of the present invention, there is proposed a method for manufacturing a substrate for a group III nitride semiconductor device, wherein the auxiliary layer is a silicon single crystal layer.

  According to the invention of claim 3, in the invention of claim 1 or 2, there is proposed a method for manufacturing a substrate for a group III nitride semiconductor device, wherein at least one of the group III nitride semiconductor layers is a GaN layer.

  According to the present invention, within the operating temperature range allowed for the semiconductor element, stress caused by the difference in the thermal expansion coefficient of the material does not occur inside, and macro defects such as cracks and pits are generated on the sapphire base substrate and Occurrence in the compound semiconductor layer can be effectively suppressed.

  Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an embodiment of a method for manufacturing a substrate for a group III nitride semiconductor device according to the present invention. Here, an embodiment in which the sapphire base substrate 1 is a substrate crystal and a group III nitride semiconductor layer is formed on the sapphire base substrate 1 by vapor phase growth will be described.

  First, a sapphire base substrate 1 is prepared (FIG. 1A). The sapphire base substrate 1 is a sapphire plate having a required thickness of about 300 to 500 μm, and its plane orientation is the (0001) plane, but it may be replaced with an equivalent plane. The main surfaces 1A and 1B that are both surfaces of the sapphire base substrate 1 are preferably mirror surfaces, and the thickness of the sapphire base substrate 1 is preferably as uniform as possible.

  Next, as shown in FIG.1 (b), the auxiliary | assistant layer 2 is vapor-deposited by the thickness of 250-410 micrometers at room temperature on one main surface 1A among the two main surfaces 1A and 1B of the sapphire base substrate 1. As the material of the auxiliary layer, a material whose thermal expansion coefficient K2 is smaller than the thermal expansion coefficient K1 of the sapphire base substrate 1 is selected. Here, a silicon single crystal is selected as the material of the auxiliary layer 2. Since the auxiliary layer 2 is deposited on the main surface 1A of the sapphire base substrate 1 at room temperature, even when the auxiliary layer 2 is formed on the sapphire base substrate 1, the sapphire base substrate 1 is in contact with the auxiliary layer 2 at room temperature. No stress due to the difference in thermal expansion is applied between them, and the sapphire base substrate 1 in the state shown in FIG. 1 (b) remains substantially free of warpage.

  As for the warpage of the substrate, when the curvature is 0.05 / m or less, there is no particular problem in semiconductor manufacturing. Therefore, when the warpage is within this range, there is substantially no warpage. is there.

  Next, the sapphire base substrate 1 in the state shown in FIG. 1B is set in a reaction furnace of a vapor phase growth apparatus (not shown), and an AlN high-temperature buffer layer is first formed on the auxiliary layer 2 under a required growth temperature. 3 is grown and formed as a thin film layer having a thickness of 0.1 μm (FIG. 1C). Here, since the substrate obtained mainly from the sapphire base substrate 1 rises in temperature to a growth temperature considerably higher than room temperature, the thermal expansion coefficient K1 and the auxiliary layer of the sapphire base substrate 1 are used in the process shown in FIG. Warpage occurs due to the difference between the thermal expansion coefficient K2 of 2. Since K1> K2, the warping direction is the direction in which the auxiliary layer 2 is pulled.

  Further, as shown in FIG. 1D, a compound semiconductor layer 4 made of a required group 3 nitride semiconductor is formed on the AlN high-temperature buffer layer 3 as a thin film layer to a desired thickness by the vapor phase growth method. Even if it is formed, the required substrate for a group III nitride semiconductor device can be obtained. Since the compound semiconductor layer 4 is formed on the AlN high-temperature buffer layer 3, lattice matching is achieved between them, and the compound semiconductor layer 4 can be formed with good crystallinity and surface specularity.

  Here, the AlN high-temperature buffer layer 3 is formed using a high growth temperature of about 1000 ° C. which is substantially the same as the growth temperature of the compound semiconductor layer 4. Therefore, each growth of the AlN high-temperature buffer layer 3 and the compound semiconductor layer 4 is performed at substantially the same high temperature, so that switching of the temperature is unnecessary and only the switching of the source gas is required, thereby simplifying the manufacturing process. Can be planned. Here, the film thickness of the AlN high-temperature buffer layer 3 is usually about 0.1 μm, and the film thickness of the compound semiconductor layer 4 is usually about 3 μm.

  When the thermal expansion coefficient of the group 3 nitride semiconductor that is a material forming the compound semiconductor layer 4 is K4, the relationship of K2 <K4 <K1 is established. Here, the thermal expansion coefficient of the sapphire base substrate 1 on which the auxiliary layer 2 is formed (hereinafter sometimes simply referred to as a substrate with an auxiliary layer) has a value between K1 and K2, and the thickness of the sapphire base substrate 1 By adjusting the thickness of the auxiliary layer 2 as appropriate, the coefficient of thermal expansion of the substrate with the auxiliary layer can be made to coincide with K4. Then, after the compound semiconductor layer 4 is grown, when the temperature of the sapphire base substrate 1 is lowered from the growth temperature and returned to room temperature, the substrate with an auxiliary layer and the compound semiconductor layer 4 have the same thermal expansion coefficient, and thus the thermal expansion. Stress due to the difference does not occur between the two, and the auxiliary layer 2 is formed at room temperature, so the stress due to the difference in thermal expansion is also present between the sapphire base substrate 1 and the auxiliary layer 2. Does not occur.

  The AlN high-temperature buffer layer 3 and the compound semiconductor layer 4 can be formed using a MOVPE growth furnace or a hydride vapor phase growth furnace including known processes. That is, it can be performed by supplying ammonia and introducing a required metal raw material diluted with hydrogen gas. For example, the AlN high-temperature buffer layer 3 is formed by growing an AlN layer by introducing ammonia and trimethylaluminum into the reaction furnace, and the compound semiconductor layer 4 is formed by introducing ammonia and trimethylgallium into the reaction furnace. Layers can be grown and formed. A known technique can be used for the growth process itself and the film thickness control.

  Since the auxiliary layer 2 is formed on the main surface 2A of the sapphire base substrate 1 at room temperature, the stress acting on the sapphire base substrate 1 and the auxiliary layer 2 due to the difference in thermal expansion between the sapphire base substrate 1 and the auxiliary layer 2 is normal temperature. Is almost zero. Strictly speaking, the temperature becomes 0 at the temperature when the auxiliary layer 2 is formed on the sapphire base substrate 1. In the above embodiment, the case where the auxiliary layer 2 is formed on the main surface 2A of the sapphire base substrate 1 at room temperature has been described. However, the formation temperature is not limited to this room temperature, and may be a temperature within an allowable operating temperature range of the semiconductor element, for example, a temperature range of about −20 to 120 ° C., preferably a temperature of 20 to 60 ° C. The temperature is within the range.

  As can be seen from the above description, the method for manufacturing a substrate for a group 3 nitride semiconductor device according to the present invention has a thermal expansion smaller than the thermal expansion coefficient of the group 3 nitride semiconductor on at least one main surface 2A of the sapphire base substrate 1. The auxiliary layer 2 made of a material having a coefficient is formed at a temperature within the allowable operating temperature range of the semiconductor element to form a substrate with an auxiliary layer.

Examples of the material having a thermal expansion coefficient smaller than that of the group 3 nitride semiconductor include Si single crystal, AlN single crystal, and Si ₃ N ₄ single crystal. It is preferable because it is easy to do.

  In order to form the auxiliary layer 2 at room temperature or a temperature close thereto, or at a temperature within the allowable operating temperature range of the semiconductor element, a vapor deposition method can be used. Vapor deposition can be performed on the conditions normally performed using the apparatus normally used industrially. However, the temperature of the sapphire base substrate 1 during the formation of the auxiliary layer 2 must be maintained at a required temperature state such as room temperature.

  After forming the auxiliary layer 2, the compound semiconductor layer necessary for manufacturing the substrate for the group III nitride semiconductor device is formed on either the main surface 1B of the sapphire base substrate 1 where the auxiliary layer is not formed or the surface of the auxiliary layer 2. 4 is grown to obtain a substrate for a group 3 nitride semiconductor device. The growth of the compound semiconductor layer 4 is usually performed by heating to a temperature of 500 ° C. or more and 1200 ° C. or less. At this time, stress due to the difference in thermal expansion between the sapphire base substrate 1 and the auxiliary layer 2 acts on the substrate with the auxiliary layer, but when the growth of the compound semiconductor layer 4 is finished and the whole is cooled to room temperature, the sapphire base substrate 1 And the stress caused by the difference in thermal expansion between the auxiliary layer 2 are eliminated.

The difference in thermal expansion between the sapphire base substrate on which the auxiliary layer is formed and the group 3 nitride semiconductor layer is examined as follows. In general, the thermal expansion coefficient of the entire substrate with an auxiliary layer in which an auxiliary layer made of a material having a thermal expansion coefficient smaller than that of the group 3 nitride semiconductor is formed on at least one main surface of the sapphire base substrate is α _K. The auxiliary layer made of a material having a thermal expansion coefficient smaller than that of the group 3 nitride semiconductor is α _A , the auxiliary layer thickness is t _A , and the elastic modulus is E _A. Assuming that the thermal expansion coefficient, thickness, and elastic modulus are α ₁ , t ₁ , and E ₁ , respectively,
α _K = (α ₁ E ₁ t ₁ + α _A E _A t _A ) / (E ₁ t ₁ + E _A t _A ) (4)
Holds.

That is, α _K can be adjusted by changing the thickness of the material having a thermal expansion coefficient smaller than that of the group 3 nitride semiconductor and the thickness of the auxiliary layer, and manufacture of the substrate for the group 3 nitride semiconductor element. The thermal expansion coefficient α _N (here, α _A <α _N <α ₁ ) of the group 3 nitride semiconductor used in the above can be approached.

  As described above, in the manufacturing method according to the present invention, by forming the auxiliary layer at a temperature within the allowable operating temperature range of the semiconductor element, the thermal expansion coefficient of the sapphire base substrate and the auxiliary layer is generated inside the semiconductor element substrate. The stress due to the difference can be substantially eliminated at the normal use temperature of the semiconductor element. By adjusting the material of the auxiliary layer, the thickness of the auxiliary layer, and the thickness of the sapphire base substrate, the thermal expansion coefficient difference between the substrate with the auxiliary layer and the group 3 nitride semiconductor layer is generated inside the group 3 nitride semiconductor device substrate. Since the stress caused by the above can be substantially eliminated at the normal operating temperature of the semiconductor element, the substrate for a group III nitride semiconductor element manufactured by the manufacturing method of the present invention is a semiconductor manufactured using the same. At a temperature at which the element is normally used, there is substantially no stress inside, and thus there is no warpage of the semiconductor element substrate.

  FIG. 2 is a process diagram for explaining another embodiment of the present invention. In this embodiment, first, as in the embodiment shown in FIG. 1, a sapphire base substrate 11 is prepared (FIG. 2A), and silicon is formed on one main surface 11B of the sapphire base substrate 11 from silicon. The auxiliary layer 12 is deposited to a required thickness at room temperature (FIG. 2B). Thereafter, the substrate on which the auxiliary layer 12 is formed on the sapphire base substrate 11 is put in a reaction furnace (not shown), and the temperature of the sapphire base substrate 11 is raised to a required growth temperature. After forming the GaN low-temperature buffer layer 13 on the main surface 11A, GaN is grown on the GaN low-temperature buffer layer 13 to form the compound semiconductor layer 14. The film forming process itself of the GaN low-temperature buffer layer 13 and the compound semiconductor layer 14 is the same as that in the embodiment shown in FIG.

  Here again, the relationship of K12 <K14 <K11 is established among the thermal expansion coefficient K11 of the sapphire base substrate 11, the thermal expansion coefficient K12 of the auxiliary layer 12, and the thermal expansion coefficient K14 of the compound semiconductor layer 14. The material is chosen. Therefore, as in the case of the embodiment shown in FIG. 1, the sapphire base substrate and the auxiliary layer for the same reason as raising the substrate with the auxiliary layer 12 having the auxiliary layer 12 formed on the sapphire base substrate 11 to the growth temperature. During this period, stress is generated due to the difference in thermal expansion between the two, and warpage occurs.

  In this state, the compound semiconductor layer 14 is grown via the GaN low temperature buffer layer 13. Here, as in the case of the embodiment shown in FIG. 1, the coefficient of thermal expansion of the substrate with the auxiliary layer is made to coincide with K14 by appropriately adjusting the thickness of the sapphire base substrate and the thickness of the auxiliary layer. Can do. Then, after the compound semiconductor layer 14 is grown, when the temperature of the sapphire base substrate 11 falls from the growth temperature and returns to room temperature (FIG. 2D), the substrate with auxiliary layer and the compound semiconductor layer have the same thermal expansion coefficient. Therefore, stress due to the difference in thermal expansion does not occur between the two, and the auxiliary layer is formed at room temperature, so that the difference in thermal expansion is also present between the sapphire base substrate 11 and the auxiliary layer 12. There is no stress caused by this.

  FIG. 3 is a process diagram for explaining still another embodiment of the present invention. In the case of this embodiment, a sapphire base substrate 21 is prepared (FIG. 3A), and auxiliary layers 22A and 22B made of silicon single crystal are respectively formed on a pair of main surfaces 21A and 21B of the prepared sapphire base substrate 21. Is deposited at room temperature (FIG. 3B). Each material of the auxiliary layers 22A and 22B is a silicon single crystal, and is formed to a required thickness by the same method as described with reference to FIG. Then, an AlN high-temperature buffer layer 23 is formed on the auxiliary layer 22A (FIG. 3C), and further, GaN, which is a required group III nitride semiconductor, is grown on the AlN high-temperature buffer layer 23 to obtain a compound semiconductor. The layer 24 is formed (FIG. 3D). The processes shown in FIGS. 3C and 3D are the same as the processes in FIGS. 1C and 1D, and the magnitude relationship of the thermal expansion coefficient of each layer is the same as that in the embodiment of FIG. It is.

  The example shown in FIG. 3 differs from the embodiment shown in FIG. 1 in that an auxiliary layer 22B is also provided on the main surface 21B of the sapphire base substrate 21. In the embodiment shown in FIG. 3, the auxiliary layers 22A and 22B provided on the principal surfaces 21A and 21B of the sapphire base substrate 21 are formed to have the same thickness, so that the sapphire base is formed to form the compound semiconductor layer 24. Even if the substrate 21 is heated to a high temperature of 1000 ° C. or higher, the elongation in both is offset, and stress due to the thermal expansion difference between the two is generated between the sapphire base substrate 21 and the auxiliary layers 22A and 22B. The AlN high temperature buffer layer 23 and the compound semiconductor layer 24 can be formed in a state where the original substrate 21 does not warp and the sapphire original substrate 21 is not warped.

  In the case of the embodiment shown in FIG. 3, as in the case of the embodiment shown in FIG. 1, by appropriately adjusting the thickness of the sapphire base substrate 21 and the thickness of the auxiliary layers 22A and 22B, The coefficient of thermal expansion of the substrate with an auxiliary layer can be matched with the coefficient of thermal expansion of the compound semiconductor layer 24. Then, after the compound semiconductor layer 24 is grown, when the temperature of the sapphire base substrate 21 is lowered from the growth temperature and returned to room temperature, the auxiliary layer-attached substrate and the compound semiconductor layer 24 have the same thermal expansion coefficient. In addition, since the stress caused by the two is not generated between the two, and the auxiliary layers 22A and 22B are formed at room temperature, the thermal expansion difference is also generated between the sapphire base substrate 21 and the auxiliary layers 22A and 22B. The stress resulting from this is still not generated.

The manufacturing process figure of the board | substrate for semiconductor elements for describing embodiment of this invention. The manufacturing process figure of the board | substrate for semiconductor elements for demonstrating other embodiment of this invention. The manufacturing process figure of the board | substrate for semiconductor elements for demonstrating other embodiment of this invention.

Explanation of symbols

1, 11, 21 Sapphire base substrate 1A, 11A, 21A, 1B, 11B, 21B Main surface 2, 12, 22A, 22B Auxiliary layer 3, 23 AlN high temperature buffer layer 13 GaN low temperature buffer layer 4, 14, 24 Compound semiconductor layer

Claims (3)

  In a method for manufacturing a substrate for a group III nitride semiconductor device used for manufacturing a semiconductor device, at least one main surface of a sapphire base substrate is made of a material having a thermal expansion coefficient smaller than that of the group III nitride semiconductor. And forming an auxiliary layer at a temperature within an allowable operating temperature range of the semiconductor element, and then growing at least one group III nitride semiconductor layer on the main surface of the sapphire base substrate or the surface of the auxiliary layer. The manufacturing method of the board | substrate for 3 group nitride semiconductor elements made into.   2. The method for manufacturing a substrate for a group III nitride semiconductor device according to claim 1, wherein the auxiliary layer is a silicon single crystal layer.   The method for manufacturing a substrate for a group III nitride semiconductor device according to claim 1 or 2, wherein at least one of the group III nitride semiconductor layers is a GaN layer.

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